Sample records for wafer manufacturing process

  1. Developing quartz wafer mold manufacturing process for patterned media

    NASA Astrophysics Data System (ADS)

    Chiba, Tsuyoshi; Fukuda, Masaharu; Ishikawa, Mikio; Itoh, Kimio; Kurihara, Masaaki; Hoga, Morihisa

    2009-04-01

    Recently, patterned media have gained attention as a possible candidate for use in the next generation of hard disk drives (HDD). Feature sizes on media are predicted to be 20-25 nm half pitch (hp) for discrete-track media in 2010. One method of fabricating such a fine pattern is by using a nanoimprint. The imprint mold for the patterned media is created from a 150-millimeter, rounded, quartz wafer. The purpose of the process introduced here was to construct a quartz wafer mold and to fabricate line and space (LS) patterns at 24 nmhp for DTM. Additionally, we attempted to achieve a dense hole (HOLE) pattern at 12.5 nmhp for BPM for use in 2012. The manufacturing process of molds for patterned media is almost the same as that for semiconductors, with the exception of the dry-etching process. A 150-millimeter quartz wafer was etched on a special tray made from carving a 6025 substrate, by using the photo-mask tool. We also optimized the quartz etching conditions. As a result, 24 nmhp LS and HOLE patterns were manufactured on the quartz wafer. In conclusion, the quartz wafer mold manufacturing process was established. It is suggested that the etching condition should be further optimized to achieve a higher resolution of HOLE patterns.

  2. Reticle variation influence on manufacturing line and wafer device performance

    NASA Astrophysics Data System (ADS)

    Nistler, John L.; Spurlock, Kyle

    1994-01-01

    Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

  3. 1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Lorenz, Adam

    For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10more » billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).« less

  4. Contamination-Free Manufacturing: Tool Component Qualification, Verification and Correlation with Wafers

    NASA Astrophysics Data System (ADS)

    Tan, Samantha H.; Chen, Ning; Liu, Shi; Wang, Kefei

    2003-09-01

    As part of the semiconductor industry "contamination-free manufacturing" effort, significant emphasis has been placed on reducing potential sources of contamination from process equipment and process equipment components. Process tools contain process chambers and components that are exposed to the process environment or process chemistry and in some cases are in direct contact with production wafers. Any contamination from these sources must be controlled or eliminated in order to maintain high process yields, device performance, and device reliability. This paper discusses new nondestructive analytical methods for quantitative measurement of the cleanliness of metal, quartz, polysilicon and ceramic components that are used in process equipment tools. The goal of these new procedures is to measure the effectiveness of cleaning procedures and to verify whether a tool component part is sufficiently clean for installation and subsequent routine use in the manufacturing line. These procedures provide a reliable "qualification method" for tool component certification and also provide a routine quality control method for reliable operation of cleaning facilities. Cost advantages to wafer manufacturing include higher yields due to improved process cleanliness and elimination of yield loss and downtime resulting from the installation of "bad" components in process tools. We also discuss a representative example of wafer contamination having been linked to a specific process tool component.

  5. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  6. Silicon Chemical Vapor Deposition Process Using a Half-Inch Silicon Wafer for Minimal Manufacturing System

    NASA Astrophysics Data System (ADS)

    Li, Ning; Habuka, Hitoshi; Ikeda, Shin-ichi; Hara, Shiro

    A chemical vapor deposition reactor for producing thin silicon films was designed and developed for achieving a new electronic device production system, the Minimal Manufacturing, using a half-inch wafer. This system requires a rapid process by a small footprint reactor. This was designed and verified by employing the technical issues, such as (i) vertical gas flow, (ii) thermal operation using a highly concentrated infrared flux, and (iii) reactor cleaning by chlorine trifluoride gas. The combination of (i) and (ii) could achieve a low heating power and a fast cooling designed by the heat balance of the small wafer placed at a position outside of the reflector. The cleaning process could be rapid by (iii). The heating step could be skipped because chlorine trifluoride gas was reactive at any temperature higher than room temperature.

  7. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Johnston, S.; Yan, F.; Zaunbracher, K.

    2011-07-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finishedmore » cell performance.« less

  8. Microeconomics of process control in semiconductor manufacturing

    NASA Astrophysics Data System (ADS)

    Monahan, Kevin M.

    2003-06-01

    Process window control enables accelerated design-rule shrinks for both logic and memory manufacturers, but simple microeconomic models that directly link the effects of process window control to maximum profitability are rare. In this work, we derive these links using a simplified model for the maximum rate of profit generated by the semiconductor manufacturing process. We show that the ability of process window control to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process variation at the lot, wafer, x-wafer, x-field, and x-chip levels. We conclude that x-wafer and x-field CD control strategies will be critical enablers of density, performance and optimum profitability at the 90 and 65nm technology nodes. These analyses correlate well with actual factory data and often identify millions of dollars in potential incremental revenue and cost savings. As an example, we show that a scatterometry-based CD Process Window Monitor is an economically justified, enabling technology for the 65nm node.

  9. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  10. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  11. Patterned wafer geometry grouping for improved overlay control

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Han, Sangjun; Woo, Jaeson; Park, Junbeom; Song, Changrock; Anis, Fatima; Vukkadala, Pradeep; Jeon, Sanghuck; Choi, DongSub; Huang, Kevin; Heo, Hoyoung; Smith, Mark D.; Robinson, John C.

    2017-03-01

    Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

  12. A Knowledge Database on Thermal Control in Manufacturing Processes

    NASA Astrophysics Data System (ADS)

    Hirasawa, Shigeki; Satoh, Isao

    A prototype version of a knowledge database on thermal control in manufacturing processes, specifically, molding, semiconductor manufacturing, and micro-scale manufacturing has been developed. The knowledge database has search functions for technical data, evaluated benchmark data, academic papers, and patents. The database also displays trends and future roadmaps for research topics. It has quick-calculation functions for basic design. This paper summarizes present research topics and future research on thermal control in manufacturing engineering to collate the information to the knowledge database. In the molding process, the initial mold and melt temperatures are very important parameters. In addition, thermal control is related to many semiconductor processes, and the main parameter is temperature variation in wafers. Accurate in-situ temperature measurment of wafers is important. And many technologies are being developed to manufacture micro-structures. Accordingly, the knowledge database will help further advance these technologies.

  13. The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line

    NASA Astrophysics Data System (ADS)

    Lee, Jeffrey; McGarvey, Steve

    2013-04-01

    The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the

  14. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  15. Effect of wafer geometry on lithography chucking processes

    NASA Astrophysics Data System (ADS)

    Turner, Kevin T.; Sinha, Jaydeep K.

    2015-03-01

    Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

  16. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  17. Low cost back contact heterojunction solar cells on thin c-Si wafers. integrating laser and thin film processing for improved manufacturability

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Hegedus, Steven S.

    2015-09-08

    An interdigitated back contact (IBC) Si wafer solar cell with deposited a-Si heterojunction (HJ) emitter and contacts is considered the ultimate single junction Si solar cell design. This was confirmed in 2014 by both Panasonic and Sharp Solar producing IBC-HJ cells breaking the previous record Si solar cell efficiency of 25%. But manufacturability at low cost is a concern for the complex IBC-HJ device structure. In this research program, our goals were to addressed the broad industry need for a high-efficiency c-Si cell that overcomes the dominant module cost barriers by 1) developing thin Si wafers synthesized by innovative, kerflessmore » techniques; 2) integrating laser-based processing into most aspects of solar cell fabrication, ensuring high speed and low thermal budgets ; 3) developing an all back contact cell structure compatible with thin wafers using a simplified, low-temperature fabrication process; and 4) designing the contact patterning to enable simplified module assembly. There were a number of significant achievements from this 3 year program. Regarding the front surface, we developed and applied new method to characterize critical interface recombination parameters including interface defect density Dit and hole and electron capture cross-section for use as input for 2D simulation of the IBC cell to guide design and loss analysis. We optimized the antireflection and passivation properties of the front surface texture and a-Si/a-SiN/a-SiC stack depositions to obtain a very low (< 6 mA/cm2) front surface optical losses (reflection and absorption) while maintaining excellent surface passivation (SRV<5 cm/s). We worked with kerfless wafer manufacturers to apply defect-engineering techniques to improve bulk minority-carrier lifetime of thin kerfless wafers by both reducing initial impurities during growth and developing post-growth gettering techniques. This led insights about the kinetics of nickel, chromium, and dislocations in PV-grade silicon and

  18. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  19. High throughput wafer defect monitor for integrated metrology applications in photolithography

    NASA Astrophysics Data System (ADS)

    Rao, Nagaraja; Kinney, Patrick; Gupta, Anand

    2008-03-01

    The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

  20. Strategy For Yield Control And Enhancement In VLSI Wafer Manufacturing

    NASA Astrophysics Data System (ADS)

    Neilson, B.; Rickey, D.; Bane, R. P.

    1988-01-01

    In most fully utilized integrated circuit (IC) production facilities, profit is very closely linked with yield. In even the most controlled manufacturing environments, defects due to foreign material are a still major contributor to yield loss. Ideally, an IC manufacturer will have ample engineering resources to address any problem that arises. In the real world, staffing limitations require that some tasks must be left undone and potential benefits left unrealized. Therefore, it is important to prioritize problems in a manner that will give the maximum benefit to the manufacturer. When offered a smorgasbord of problems to solve, most people (engineers included) will start with what is most interesting or the most comfortable to work on. By providing a system that accurately predicts the impact of a wide variety of defect types, a rational method of prioritizing engineering effort can be made. To that effect, a program was developed to determine and rank the major yield detractors in a mixed analog/digital FET manufacturing line. The two classical methods of determining yield detractors are chip failure analysis and defect monitoring on drop in test die. Both of these methods have short comings: 1) Chip failure analysis is painstaking and very time consuming. As a result, the sample size is very small. 2) Drop in test die are usually designed for device parametric analysis rather than defect analysis. To provide enough wafer real estate to do meaningful defect analysis would render the wafer worthless for production. To avoid these problems, a defect monitor was designed that provided enough area to detect defects at the same rate or better than the NMOS product die whose yield was to be optimized. The defect monitor was comprehensive and electrically testable using such equipment as the Prometrix LM25 and other digital testers. This enabled the quick accumulation of data which could be handled statistically and mapped individually. By scaling the defect densities

  1. Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

    NASA Astrophysics Data System (ADS)

    Turner, K. T.; Spearing, S. M.

    2002-12-01

    Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

  2. From magic to technology: materials integration by wafer bonding

    NASA Astrophysics Data System (ADS)

    Dragoi, Viorel

    2006-02-01

    Wafer bonding became in the last decade a very powerful technology for MEMS/MOEMS manufacturing. Being able to offer a solution to overcome some problems of the standard processes used for materials integration (e.g. epitaxy, thin films deposition), wafer bonding is nowadays considered an important item in the MEMS engineer toolbox. Different principles governing the wafer bonding processes will be reviewed in this paper. Various types of applications will be presented as examples.

  3. Wafer-shape metrics based foundry lithography

    NASA Astrophysics Data System (ADS)

    Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

    2017-03-01

    As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

  4. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2008-10-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  5. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  6. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-03-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  7. Wafer-level colinearity monitoring for TFH applications

    NASA Astrophysics Data System (ADS)

    Moore, Patrick; Newman, Gary; Abreau, Kelly J.

    2000-06-01

    Advances in thin film head (TFH) designs continue to outpace those in the IC industry. The transition to giant magneto resistive (GMR) designs is underway along with the push toward areal densities in the 20 Gbit/inch2 regime and beyond. This comes at a time when the popularity of the low-cost personal computer (PC) is extremely high, and PC prices are continuing to fall. Consequently, TFH manufacturers are forced to deal with pricing pressure in addition to technological demands. New methods of monitoring and improving yield are required along with advanced head designs. TFH manufacturing is a two-step process. The first is a wafer-level process consisting of manufacturing devices on substrates using processes similar to those in the IC industry. The second half is a slider-level process where wafers are diced into 'rowbars' containing many heads. Each rowbar is then lapped to obtain the desired performance from each head. Variation in the placement of specific layers of each device on the bar, known as a colinearity error, causes a change in device performance and directly impacts yield. The photolithography tool and process contribute to colinearity errors. These components include stepper lens distortion errors, stepper stage errors, reticle fabrication errors, and CD uniformity errors. Currently, colinearity is only very roughly estimated during wafer-level TFH production. An absolute metrology tool, such as a Nikon XY, could be used to quantify colinearity with improved accuracy, but this technique is impractical since TFH manufacturers typically do not have this type of equipment at the production site. More importantly, this measurement technique does not provide the rapid feedback needed in a high-volume production facility. Consequently, the wafer-fab must rely on resistivity-based measurements from slider-fab to quantify colinearity errors. The feedback of this data may require several weeks, making it useless as a process diagnostic. This study examines

  8. Wafer hot spot identification through advanced photomask characterization techniques

    NASA Astrophysics Data System (ADS)

    Choi, Yohan; Green, Michael; McMurran, Jeff; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

    2016-10-01

    As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that the classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced characterization methods in order to optimize the mask process to meet the wafer lithographer's needs. These advanced characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled wafer performance.

  9. Study of temperature distributions in wafer exposure process

    NASA Astrophysics Data System (ADS)

    Lin, Zone-Ching; Wu, Wen-Jang

    During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

  10. Quantitative phase measurement for wafer-level optics

    NASA Astrophysics Data System (ADS)

    Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

    2015-07-01

    Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

  11. Post exposure bake unit equipped with wafer-shape compensation technology

    NASA Astrophysics Data System (ADS)

    Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

    2007-03-01

    In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

  12. Warpage Measurement of Thin Wafers by Reflectometry

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

  13. Within-wafer CD variation induced by wafer shape

    NASA Astrophysics Data System (ADS)

    Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

    2016-03-01

    In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer

  14. Laser wafering for silicon solar.

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurfacemore » damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.« less

  15. Intentional defect array wafers: their practical use in semiconductor control and monitoring systems

    NASA Astrophysics Data System (ADS)

    Emami, Iraj; McIntyre, Michael; Retersdorf, Michael

    2003-07-01

    In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.

  16. Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

    NASA Astrophysics Data System (ADS)

    Chen, Po-Ying

    2008-12-01

    Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

  17. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  18. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

  19. Interferometric thickness calibration of 300 mm silicon wafers

    NASA Astrophysics Data System (ADS)

    Wang, Quandou; Griesmann, Ulf; Polvani, Robert

    2005-12-01

    The "Improved Infrared Interferometer" (IR 3) at the National Institute of Standards and Technology (NIST) is a phase-measuring interferometer, operating at a wavelength of 1550 nm, which is being developed for measuring the thickness and thickness variation of low-doped silicon wafers with diameters up to 300 mm. The purpose of the interferometer is to produce calibrated silicon wafers, with a certified measurement uncertainty, which can be used as reference wafers by wafer manufacturers and metrology tool manufacturers. We give an overview of the design of the interferometer and discuss its application to wafer thickness measurements. The conversion of optical thickness, as measured by the interferometer, to the wafer thickness requires knowledge of the refractive index of the material of the wafer. We describe a method for measuring the refractive index which is then used to establish absolute thickness and thickness variation maps for the wafer.

  20. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  1. Silicon crystals: Process for manufacturing wafer-like silicon crystals with a columnar structure

    NASA Technical Reports Server (NTRS)

    Authier, B.

    1978-01-01

    Wafer-like crystals suitable for making solar cells are formed by pouring molten Si containing suitable dopants into a mold of the desired shape and allowing it to solidify in a temperature gradient, whereby the large surface of the melt in contact with the mold is kept at less than 200 D and the free surface is kept at a temperature of 200-1000 D higher, but below the melting point of Si. The mold can also be made in the form of a slit, whereby the 2 sides of the mold are kept at different temperatures. A mold was milled in the surface of a cylindrical graphite block 200 mm in diameter. The granite block was induction heated and the bottom of the mold was cooled by means of a water-cooled Cu plate, so that the surface of the mold in contact with one of the largest surfaces of the melt was held at approximately 800 D. The free surface of the melt was subjected to thermal radiation from a graphite plate located 2 mm from the surface and heated to 1500 D. The Si crystal formed after slow cooling to room temperature had a columnar structure and was cut with a diamond saw into wafers approximately 500 mm thick. Solar cells prepared from these wafers had efficiencies of 10 to 11%.

  2. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  3. Optical surface analysis: a new technique for the inspection and metrology of optoelectronic films and wafers

    NASA Astrophysics Data System (ADS)

    Bechtler, Laurie; Velidandla, Vamsi

    2003-04-01

    In response to demand for higher volumes and greater product capability, integrated optoelectronic device processing is rapidly increasing in complexity, benefiting from techniques developed for conventional silicon integrated circuit processing. The needs for high product yield and low manufacturing cost are also similar to the silicon wafer processing industry. This paper discusses the design and use of an automated inspection instrument called the Optical Surface Analyzer (OSA) to evaluate two critical production issues in optoelectronic device manufacturing: (1) film thickness uniformity, and (2) defectivity at various process steps. The OSA measurement instrument is better suited to photonics process development than most equipment developed for conventional silicon wafer processing in two important ways: it can handle both transparent and opaque substrates (unlike most inspection and metrology tools), and it is a full-wafer inspection method that captures defects and film variations over the entire substrate surface (unlike most film thickness measurement tools). Measurement examples will be provided in the paper for a variety of films and substrates used for optoelectronics manufacturing.

  4. Overview of several applications of chemical downstream etching (CDE) for IC manufacturing: advantages and drawbacks versus WET processes

    NASA Astrophysics Data System (ADS)

    de Buttet, Côme; Prevost, Emilie; Campo, Alain; Garnier, Philippe; Zoll, Stephane; Vallier, Laurent; Cunge, Gilles; Maury, Patrick; Massin, Thomas; Chhun, Sonarith

    2017-03-01

    Today the IC manufacturing faces lots of problematics linked to the continuous down scaling of printed structures. Some of those issues are related to wet processing, which are often used in the IC manufacturing flow for wafer cleaning, material etching and surface preparation. In the current work we summarize the limitations for the next nodes of wet processing such as metallic contaminations, wafer charging, corrosion and pattern collapse. As a replacement, we promoted the isotropic chemical dry etching (CDE) which is supposed to fix all the above drawbacks. Etching steps of SI3N4 layers were evaluated in order to prove the interest of such technique.

  5. Advances in process overlay on 300-mm wafers

    NASA Astrophysics Data System (ADS)

    Staecker, Jens; Arendt, Stefanie; Schumacher, Karl; Mos, Evert C.; van Haren, Richard J. F.; van der Schaar, Maurits; Edart, Remi; Demmerle, Wolfgang; Tolsma, Hoite

    2002-07-01

    Overlay budgets are getting tighter within 300 mm volume production and as a consequence the process effects on alignment and off-line metrology becomes more important. In a short loop experiment, with cleared reference marks in each image field, the isolated effect of processing was measured with a sub-nanometer accuracy. The examined processes are Shallow Trench Isolation (STI), Tungsten-Chemical Mechanical Processing (W-CMP) and resist spinning. The alignment measurements were done on an ASML TWINSCANT scanner and the off-line metrology measurements on a KLA Tencor. Mark type and mark position dependency of the process effects are analyzed. The mean plus 3 (sigma) of the maximum overlay after correcting batch average wafer parameters is used as an overlay performance indicator (OPI). 3 (sigma) residuals to the wafer-model are used as an indicator of the noise that is added by the process. The results are in agreement with existing knowledge of process effects on 200 mm wafers. The W-CMP process introduces an additional wafer rotation and scaling that is similar for alignment marks and metrology targets. The effects depend on the mark type; in general they get less severe for higher spatial frequencies. For a 7th order alignment mark, the OPI measured about 12 nm and the added noise about 12 nm. For the examined metrology targets the OPI is about 20 nm with an added noise of about 90 nm. Two different types of alignment marks were tested in the STI process, i.e., zero layer marks and marks that were exposed together with the STI product. The overlay contribution due to processing on both types of alignment marks is very low (smaller than 5 nm OPI) and independent on mark type. Some flyers are observed fot the zero layer marks. The flyers can be explained by the residues of oxide and nitride that is left behind in the spaces of the alignment marks. Resist spinning is examined on single layer resist and resist with an organic Bottom Anti-Reflective Coating (BARC

  6. Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

    NASA Astrophysics Data System (ADS)

    Syed, Ahmed Rashid

    Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

  7. Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

    NASA Astrophysics Data System (ADS)

    Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

    2018-03-01

    The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

  8. Computational Modeling in Plasma Processing for 300 mm Wafers

    NASA Technical Reports Server (NTRS)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  9. Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Johnston, S.; Yan, F.; Dorn, D.

    2012-06-01

    Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect bandmore » images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.« less

  10. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-07

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  11. Edge printability: techniques used to evaluate and improve extreme wafer edge printability

    NASA Astrophysics Data System (ADS)

    Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

    2004-05-01

    The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

  12. Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

    NASA Astrophysics Data System (ADS)

    Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

    2001-11-01

    The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

  13. Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

    NASA Astrophysics Data System (ADS)

    Matsuoka, Yoichi; Seki, Junichi; Nakayama, Takahiro; Nakagawa, Kazuki; Azuma, Hisanobu; Yamamoto, Kiyohito; Sato, Chiaki; Sakai, Fumio; Takabayashi, Yukio; Aghili, Ali; Mizuno, Makoto; Choi, Jin; Jones, Chris E.

    2016-10-01

    Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. On the mask side, a new replication tool, the FPA-1100 NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control, resolution and image placement accuracy. In this paper we discuss the progress made in both feature resolution and in meeting the image placement specification for replica masks.

  14. Propagation of resist heating mask error to wafer level

    NASA Astrophysics Data System (ADS)

    Babin, S. V.; Karklin, Linard

    2006-10-01

    As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the

  15. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  16. A front-end wafer-level microsystem packaging technique with micro-cap array

    NASA Astrophysics Data System (ADS)

    Chiang, Yuh-Min

    2002-09-01

    The back-end packaging process is the remaining challenge for the micromachining industry to commercialize microsystem technology (MST) devices at low cost. This dissertation presents a novel wafer level protection technique as a final step of the front-end fabrication process for MSTs. It facilitates improved manufacturing throughput and automation in package assembly, wafer level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized micro-cap array, which consists of an assortment of small caps micro-molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments during packaging. The micro-cap array is first constructed by a micromachining process with micro-molding technique, then sealed to the device wafer at wafer level. Epoxy-based wafer-level micro cap array has been successfully fabricated and showed good compatibility with conventional back-end packaging processes. An adhesive transfer technique was demonstrated to seal the micro cap array with a MEMS device wafer. No damage or gross leak was observed while wafer dicing or later during a gross leak test. Applications of the micro cap array are demonstrated on MEMS, microactuators fabricated using CRONOS MUMPS process. Depending on the application needs, the micro-molded cap can be designed and modified to facilitate additional component functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. Successful fabrication of a micro cap array comprised with microlenses can provide active functions as well as passive protection. An optical tweezer array could be one possibility for applications of a micro cap with microlenses. The micro cap itself could serve as micro well for DNA or bacteria amplification as well.

  17. Thermo-acousto-photonics for noncontact temperature measurement in silicon wafer processing

    NASA Astrophysics Data System (ADS)

    Suh, Chii-Der S.; Rabroker, G. Andrew; Chona, Ravinder; Burger, Christian P.

    1999-10-01

    A non-contact thermometry technique has been developed to characterize the thermal state of silicon wafers during rapid thermal processing. Information on thermal variations is obtained from the dispersion relations of the propagating waveguide mode excited in wafers using a non-contact, broadband optical system referred to as Thermal Acousto- Photonics for Non-Destructive Evaluation. Variations of thermo-mechanical properties in silicon wafers are correlated to temperature changes by performing simultaneous time-frequency analyses on Lamb waveforms acquired with a fiber-tip interferometer sensor. Experimental Lamb wave data collected for cases ranging from room temperature to 400 degrees C is presented. The results show that the temporal progressions of all spectral elements found in the fundamental antisymmetric mode are strong functions of temperature. This particular attribute is exploited to achieve a thermal resolution superior to the +/- 5 degrees C attainable through current pyrometric techniques. By analyzing the temperature-dependent group velocity of a specific frequency component over the temperature range considered and then comparing the results to an analytical model developed for silicon wafers undergoing annealing, excellent agreement was obtained. Presented results demonstrate the feasibility of applying laser-induced stress waves as a temperature diagnostic during rapid thermal processing.

  18. A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

    NASA Astrophysics Data System (ADS)

    Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

    2013-03-01

    The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

  19. Method for wafer edge profile extraction using optical images obtained in edge defect inspection process

    NASA Astrophysics Data System (ADS)

    Okamoto, Hiroaki; Sakaguchi, Naoshi; Hayano, Fuminori

    2010-03-01

    It is becoming increasingly important to monitor wafer edge profiles in the immersion lithography era. A Nikon edge defect inspection tool acquires the circumferential optical images of the wafer edge during its inspection process. Nikon's unique illumination system and optics make it possible to then convert the brightness data of the captured images to quantifiable edge profile information. During this process the wafer's outer shape is also calculated. Test results show that even newly shipped bare wafers may not have a constant shape over 360 degree. In some cases repeated deformations with 90 degree pitch are observed.

  20. Novel wafer stepper with violet LED light source

    NASA Astrophysics Data System (ADS)

    Ting, Yung-Chiang; Shy, Shyi-Long

    2014-03-01

    Novel wafer stepper by using contact or proximity printing will be developed, using violet LED light source to replace Hg Arc. lamp or laser. Mirror, filter and condenser lens for Hg Arc. Lamp or laser and reduction lens for projection printing can be discarded. Reliability and manufacturing cost of wafer stepper can be improved. Exposure result by using IP3600 resist and wafer stepper with violet LED light source (wave-length 360nm to 410 nm) will be obtained. This novel wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist with sub-micron to 100 micron thickness.

  1. Sensor-based atomic layer deposition for rapid process learning and enhanced manufacturability

    NASA Astrophysics Data System (ADS)

    Lei, Wei

    In the search for sensor based atomic layer deposition (ALD) process to accelerate process learning and enhance manufacturability, we have explored new reactor designs and applied in-situ process sensing to W and HfO 2 ALD processes. A novel wafer scale ALD reactor, which features fast gas switching, good process sensing compatibility and significant similarity to the real manufacturing environment, is constructed. The reactor has a unique movable reactor cap design that allows two possible operation modes: (1) steady-state flow with alternating gas species; or (2) fill-and-pump-out cycling of each gas, accelerating the pump-out by lifting the cap to employ the large chamber volume as ballast. Downstream quadrupole mass spectrometry (QMS) sampling is applied for in-situ process sensing of tungsten ALD process. The QMS reveals essential surface reaction dynamics through real-time signals associated with byproduct generation as well as precursor introduction and depletion for each ALD half cycle, which are then used for process learning and optimization. More subtle interactions such as imperfect surface saturation and reactant dose interaction are also directly observed by QMS, indicating that ALD process is more complicated than the suggested layer-by-layer growth. By integrating in real-time the byproduct QMS signals over each exposure and plotting it against process cycle number, the deposition kinetics on the wafer is directly measured. For continuous ALD runs, the total integrated byproduct QMS signal in each ALD run is also linear to ALD film thickness, and therefore can be used for ALD film thickness metrology. The in-situ process sensing is also applied to HfO2 ALD process that is carried out in a furnace type ALD reactor. Precursor dose end-point control is applied to precisely control the precursor dose in each half cycle. Multiple process sensors, including quartz crystal microbalance (QCM) and QMS are used to provide real time process information. The

  2. Influence of Si wafer thinning processes on (sub)surface defects

    NASA Astrophysics Data System (ADS)

    Inoue, Fumihiro; Jourdain, Anne; Peng, Lan; Phommahaxay, Alain; De Vos, Joeri; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik; Beyne, Eric; Uedono, Akira

    2017-05-01

    Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5 μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 μm. For the case of Si thinning towards 5 μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5-2 μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in between grinding and dry etch it is possible to significantly reduce not only the roughness, but also the remaining vacancies at the subsurface. The surface of grinding + CMP + dry etching gives an equivalent mono vacancy result as to that of grinding + CMP. This combination of thinning processes allows development of extremely thin 3D integration devices with minimal roughness and vacancy surface.

  3. Wafer level reliability testing: An idea whose time has come

    NASA Technical Reports Server (NTRS)

    Trapp, O. D.

    1987-01-01

    Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

  4. Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

    NASA Astrophysics Data System (ADS)

    Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

    2018-04-01

    In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

  5. Model-Based Infrared Metrology for Advanced Technology Nodes and 300 mm Wafer Processing

    NASA Astrophysics Data System (ADS)

    Rosenthal, Peter A.; Duran, Carlos; Tower, Josh; Mazurenko, Alex; Mantz, Ulrich; Weidner, Peter; Kasic, Alexander

    2005-09-01

    The use of infrared spectroscopy for production semiconductor process monitoring has evolved recently from primarily unpatterned, i.e. blanket test wafer measurements in a limited historical application space of blanket epitaxial, BPSG, and FSG layers to new applications involving patterned product wafer measurements, and new measurement capabilities. Over the last several years, the semiconductor industry has adopted a new set of materials associated with copper/low-k interconnects, and new structures incorporating exotic materials including silicon germanium, SOI substrates and high aspect ratio trenches. The new device architectures and more chemically sophisticated materials have raised new process control and metrology challenges that are not addressed by current measurement technology. To address the challenges we have developed a new infrared metrology tool designed for emerging semiconductor production processes, in a package compatible with modern production and R&D environments. The tool incorporates recent advances in reflectance instrumentation including highly accurate signal processing, optimized reflectometry optics, and model-based calibration and analysis algorithms. To meet the production requirements of the modern automated fab, the measurement hardware has been integrated with a fully automated 300 mm platform incorporating front opening unified pod (FOUP) interfaces, automated pattern recognition and high throughput ultra clean robotics. The tool employs a suite of automated dispersion-model analysis algorithms capable of extracting a variety of layer properties from measured spectra. The new tool provides excellent measurement precision, tool matching, and a platform for deploying many new production and development applications. In this paper we will explore the use of model based infrared analysis as a tool for characterizing novel bottle capacitor structures employed in high density dynamic random access memory (DRAM) chips. We will explore

  6. Using the surface charge profiler for in-line monitoring of doping concentration in silicon epitaxial wafer manufacturing

    NASA Astrophysics Data System (ADS)

    Tower, Joshua P.; Kamieniecki, Emil; Nguyen, M. C.; Danel, Adrien

    1999-08-01

    The Surface Charge Profiler (SCP) has been introduced for monitoring and development of silicon epitaxial processes. The SCP measures the near-surface doping concentration and offers advantages that lead to yield enhancement in several ways. First, non-destructive measurement technology enables in-line process monitoring, eliminating the need to sacrifice production wafers for resistivity measurements. Additionally, the full-wafer mapping capability helps in development of improved epitaxial growth processes and early detection of reactor problems. As examples, we present the use of SCP to study the effects of susceptor degradation in barrel reactors and to study autodoping for development of improved dopant uniformity.

  7. Clean solutions to the incoming wafer quality impact on lithography process yield limits in a dynamic copper/low-k research and development environment

    NASA Astrophysics Data System (ADS)

    Lysaght, Patrick S.; Ybarra, Israel; Sax, Harry; Gupta, Gaurav; West, Michael; Doros, Theodore G.; Beach, James V.; Mello, Jim

    2000-06-01

    The continued growth of the semiconductor manufacturing industry has been due, in large part, to improved lithographic resolution and overlay across increasingly larger chip areas. Optical lithography continues to be the mainstream technology for the industry with extensions of optical lithography being employed to support 180 nm product and process development. While the industry momentum is behind optical extensions to 130 nm, the key challenge will be maintaining an adequate and affordable process latitude (depth of focus/exposure window) necessary for 10% post-etch critical dimension (CD) control. If the full potential of optical lithography is to be exploited, the current lithographic systems can not be compromised by incoming wafer quality. Impurity specifications of novel Low-k dielectric materials, plating solutions, chemical-mechanical planarization (CMP) slurries, and chemical vapor deposition (CVD) precursors are not well understood and more stringent control measures will be required to meet defect density targets as identified in the National Technology Roadmap for Semiconductors (NTRS). This paper identifies several specific poor quality wafer issues that have been effectively addressed as a result of the introduction of a set of flexible and reliable wafer back surface clean processes developed on the SEZ Spin-Processor 203 configured for processing of 200 mm diameter wafers. Patterned wafers have been back surface etched by means of a novel spin process contamination elimination (SpCE) technique with the wafer suspended by a dynamic nitrogen (N2) flow, device side down, via the Bernoulli effect. Figure 1 illustrates the wafer-chuck orientation within the process chamber during back side etch processing. This paper addresses a number of direct and immediate benefits to the MicraScan IIITM deep-ultraviolet (DUV) step-and-scan system at SEMATECH. These enhancements have resulted from the resolution of three significant problems: (1) back surface

  8. Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

    NASA Astrophysics Data System (ADS)

    Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

    2017-08-01

    Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

  9. Overlay Tolerances For VLSI Using Wafer Steppers

    NASA Astrophysics Data System (ADS)

    Levinson, Harry J.; Rice, Rory

    1988-01-01

    In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his

  10. Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

    NASA Astrophysics Data System (ADS)

    Kubair, D. V.; Spearing, S. M.

    2006-03-01

    Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

  11. Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

    NASA Astrophysics Data System (ADS)

    Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

    2018-04-01

    Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

  12. Big data driven cycle time parallel prediction for production planning in wafer manufacturing

    NASA Astrophysics Data System (ADS)

    Wang, Junliang; Yang, Jungang; Zhang, Jie; Wang, Xiaoxi; Zhang, Wenjun Chris

    2018-07-01

    Cycle time forecasting (CTF) is one of the most crucial issues for production planning to keep high delivery reliability in semiconductor wafer fabrication systems (SWFS). This paper proposes a novel data-intensive cycle time (CT) prediction system with parallel computing to rapidly forecast the CT of wafer lots with large datasets. First, a density peak based radial basis function network (DP-RBFN) is designed to forecast the CT with the diverse and agglomerative CT data. Second, the network learning method based on a clustering technique is proposed to determine the density peak. Third, a parallel computing approach for network training is proposed in order to speed up the training process with large scaled CT data. Finally, an experiment with respect to SWFS is presented, which demonstrates that the proposed CTF system can not only speed up the training process of the model but also outperform the radial basis function network, the back-propagation-network and multivariate regression methodology based CTF methods in terms of the mean absolute deviation and standard deviation.

  13. Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

    PubMed

    Logan, Andrew; Yeow, John T W

    2009-05-01

    We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

  14. Wafer plane inspection with soft resist thresholding

    NASA Astrophysics Data System (ADS)

    Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

    2008-10-01

    Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

  15. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    NASA Astrophysics Data System (ADS)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

    2016-08-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

  16. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    NASA Technical Reports Server (NTRS)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; hide

    2016-01-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN(sub x)) materials and microwave structures, and the resulting performance improvements.

  17. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  18. Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

    PubMed

    Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

    2011-04-21

    A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

  19. Resolving critical dimension drift over time in plasma etching through virtual metrology based wafer-to-wafer control

    NASA Astrophysics Data System (ADS)

    Lee, Ho Ki; Baek, Kye Hyun; Shin, Kyoungsub

    2017-06-01

    As semiconductor devices are scaled down to sub-20 nm, process window of plasma etching gets extremely small so that process drift or shift becomes more significant. This study addresses one of typical process drift issues caused by consumable parts erosion over time and provides feasible solution by using virtual metrology (VM) based wafer-to-wafer control. Since erosion of a shower head has center-to-edge area dependency, critical dimensions (CDs) at the wafer center and edge area get reversed over time. That CD trend is successfully estimated on a wafer-to-wafer basis by a partial least square (PLS) model which combines variables from optical emission spectroscopy (OES), VI-probe and equipment state gauges. R 2 of the PLS model reaches 0.89 and its prediction performance is confirmed in a mass production line. As a result, the model can be exploited as a VM for wafer-to-wafer control. With the VM, advanced process control (APC) strategy is implemented to solve the CD drift. Three σ of CD across wafer is improved from the range (1.3-2.9 nm) to the range (0.79-1.7 nm). Hopefully, results introduced in this paper will contribute to accelerating implementation of VM based APC strategy in semiconductor industry.

  20. Free-world microelectronic manufacturing equipment

    NASA Astrophysics Data System (ADS)

    Kilby, J. S.; Arnold, W. H.; Booth, W. T.; Cunningham, J. A.; Hutcheson, J. D.; Owen, R. W.; Runyan, W. R.; McKenney, Barbara L.; McGrain, Moira; Taub, Renee G.

    1988-12-01

    Equipment is examined and evaluated for the manufacture of microelectronic integrated circuit devices and sources for that equipment within the Free World. Equipment suitable for the following are examined: single-crystal silicon slice manufacturing and processing; required lithographic processes; wafer processing; device packaging; and test of digital integrated circuits. Availability of the equipment is also discussed, now and in the near future. Very adequate equipment for most stages of the integrated circuit manufacturing process is available from several sources, in different countries, although the best and most widely used versions of most manufacturing equipment are made in the United States or Japan. There is also an active market in used equipment, suitable for manufacture of capable integrated circuits with performance somewhat short of the present state of the art.

  1. Wave-front propagation of rinsing flows on rotating semiconductor wafers

    NASA Astrophysics Data System (ADS)

    Frostad, John M.; Ylitalo, Andy; Walls, Daniel J.; Mui, David S. L.; Fuller, Gerald G.

    2016-11-01

    The semiconductor manufacturing industry is migrating to a cleaning technology that involves dispersing cleaning solutions onto a rotating wafer, similar to spin-coating. Advantages include a more continuous overall fabrication process, lower particle level, no cross contamination from the back side of a wafer, and less usage of harsh chemicals for a lower environmental impact. Rapid rotation of the wafer during rinsing can be more effective, but centrifugal forces can pull spiral-like ribbons of liquid radially outward from the advancing wave-front where particles can build up, causing higher instances of device failure at these locations. A better understanding of the rinsing flow is essential for reducing yield losses while taking advantage of the benefits of rotation. In the present work, high-speed video and image processing are used to study the dynamics of the advancing wave-front from an impinging jet on a rotating substrate. The flow-rate and rotation-speed are varied for substrates coated with a thin layer of a second liquid that has a different surface tension than the jet liquid. The difference in surface tension of the two fluids gives rise to Marangoni stresses at the interface that have a significant impact on the rinsing process, despite the extremely short time-scales involved.

  2. A thermal microprobe fabricated with wafer-stage processing

    NASA Astrophysics Data System (ADS)

    Zhang, Yongxia; Zhang, Yanwei; Blaser, Juliana; Sriram, T. S.; Enver, Ahsan; Marcus, R. B.

    1998-05-01

    A thermal microprobe has been designed and built for high resolution temperature sensing. The thermal sensor is a thin-film thermocouple junction at the tip of an atomic force microprobe (AFM) silicon probe needle. Only wafer-stage processing steps are used for the fabrication. For high resolution temperature sensing it is essential that the junction be confined to a short distance at the AFM tip. This confinement is achieved by a controlled photoresist coating process. Experiment prototypes have been made with an Au/Pd junction confined to within 0.5 μm of the tip, with the two metals separated elsewhere by a thin insulating oxide layer. Processing begins with double-polished, n-type, 4 in. diameter, 300-μm-thick silicon wafers. Atomically sharp probe tips are formed by a combination of dry and wet chemical etching, and oxidation sharpening. The metal layers are sputtering deposited and the cantilevers are released by a combination of KOH and dry etching. A resistively heated calibration device was made for temperature calibration of the thermal microprobe over the temperature range 25-110 °C. Over this range the thermal outputs of two microprobes are 4.5 and 5.6 μV/K and is linear. Thermal and topographical images are also obtained from a heated tungsten thin film fuse.

  3. The uses of Man-Made diamond in wafering applications

    NASA Technical Reports Server (NTRS)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  4. Six Sigma-based approach to optimise the diffusion process of crystalline silicon solar cell manufacturing

    NASA Astrophysics Data System (ADS)

    Prasad, A. Guru; Saravanan, S.; Gijo, E. V.; Dasari, Sreenivasa Murty; Tatachar, Raghu; Suratkar, Prakash

    2016-02-01

    Silicon-based photovoltaics (PV) plays the dominant role in the history of PV due to the continuous process and technology improvement in silicon solar cells and its manufacturing flow. In general, silicon solar cell process uses either p-type- or n-type-doped silicon as the starting material. Currently, most of the PV industries use p-type, boron-doped silicon wafer as the starting material. In this work too, the boron-doped wafers were considered as the starting material to create pn junction and phosphorus was used as n-type doping material. Industries use either phosphorous oxy chloride (POCl3) or ortho phosphoric acid (H3PO4) as the precursor for doping phosphorous. While the industries use POCl3 as the precursor, the throughput is lesser than that of the industries' use of H3PO4 due to the manufacturing limitations of the POCl3-based equipments. Hence, in order to achieve the operational excellence in POCl3-based equipments, business strategies such as the Six Sigma methodology have to be adapted. This paper describes the application of Six Sigma Define-Measure-Analyze-Improve-Control methodology for throughput improvement of the phosphorus doping process. The optimised recipe has been implemented in the production and it is running successfully. As a result of this project, an effective gain of 0.9 MW was reported per annum.

  5. A novel patterning control strategy based on real-time fingerprint recognition and adaptive wafer level scanner optimization

    NASA Astrophysics Data System (ADS)

    Cekli, Hakki Ergun; Nije, Jelle; Ypma, Alexander; Bastani, Vahid; Sonntag, Dag; Niesing, Henk; Zhang, Linmiao; Ullah, Zakir; Subramony, Venky; Somasundaram, Ravin; Susanto, William; Matsunobu, Masazumi; Johnson, Jeff; Tabery, Cyrus; Lin, Chenxi; Zou, Yi

    2018-03-01

    In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a `fingerprint', on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching <3nm, requiring the allowable budget for process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel `computational process control strategy' which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each

  6. Development of parametric material, energy, and emission inventories for wafer fabrication in the semiconductor industry.

    PubMed

    Murphy, Cynthia F; Kenig, George A; Allen, David T; Laurent, Jean-Philippe; Dyer, David E

    2003-12-01

    Currently available data suggest that most of the energy and material consumption related to the production of an integrated circuit is due to the wafer fabrication process. The complexity of wafer manufacturing, requiring hundreds of steps that vary from product to product and from facility to facility and which change every few years, has discouraged the development of material, energy, and emission inventory modules for the purpose of insertion into life cycle assessments. To address this difficulty, a flexible, process-based system for estimating material requirements, energy requirements, and emissions in wafer fabrication has been developed. The method accounts for mass and energy use atthe unit operation level. Parametric unit operation modules have been developed that can be used to predict changes in inventory as the result of changes in product design, equipment selection, or process flow. A case study of the application of the modules is given for energy consumption, but a similar methodology can be used for materials, individually or aggregated.

  7. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    NASA Astrophysics Data System (ADS)

    Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

    2016-02-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

  8. Process Performance of Optima XEx Single Wafer High Energy Implanter

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Kim, J. H.; Yoon, Jongyoon; Kondratenko, S.

    2011-01-07

    To meet the process requirements for well formation in future CMOS memory production, high energy implanters require more robust angle, dose, and energy control while maintaining high productivity. The Optima XEx high energy implanter meets these requirements by integrating a traditional LINAC beamline with a robust single wafer handling system. To achieve beam angle control, Optima XEx can control both the horizontal and vertical beam angles to within 0.1 degrees using advanced beam angle measurement and correction. Accurate energy calibration and energy trim functions accelerate process matching by eliminating energy calibration errors. The large volume process chamber and UDC (upstreammore » dose control) using faraday cups outside of the process chamber precisely control implant dose regardless of any chamber pressure increase due to PR (photoresist) outgassing. An optimized RF LINAC accelerator improves reliability and enables singly charged phosphorus and boron energies up to 1200 keV and 1500 keV respectively with higher beam currents. A new single wafer endstation combined with increased beam performance leads to overall increased productivity. We report on the advanced performance of Optima XEx observed during tool installation and volume production at an advanced memory fab.« less

  9. Thinning of PLZT ceramic wafers for sensor integration

    NASA Astrophysics Data System (ADS)

    Jin, Na; Liu, Weiguo

    2010-08-01

    Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

  10. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    NASA Astrophysics Data System (ADS)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  11. High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Antoniadis, H.

    Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink highmore » efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.« less

  12. Automatic vision-based grain optimization and analysis of multi-crystalline solar wafers using hierarchical region growing

    NASA Astrophysics Data System (ADS)

    Fan, Shu-Kai S.; Tsai, Du-Ming; Chuang, Wei-Che

    2017-04-01

    Solar power has become an attractive alternative source of energy. The multi-crystalline solar cell has been widely accepted in the market because it has a relatively low manufacturing cost. Multi-crystalline solar wafers with larger grain sizes and fewer grain boundaries are higher quality and convert energy more efficiently than mono-crystalline solar cells. In this article, a new image processing method is proposed for assessing the wafer quality. An adaptive segmentation algorithm based on region growing is developed to separate the closed regions of individual grains. Using the proposed method, the shape and size of each grain in the wafer image can be precisely evaluated. Two measures of average grain size are taken from the literature and modified to estimate the average grain size. The resulting average grain size estimate dictates the quality of the crystalline solar wafers and can be considered a viable quantitative indicator of conversion efficiency.

  13. Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

    NASA Astrophysics Data System (ADS)

    Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

    2018-07-01

    This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

  14. The establishment of a production-ready manufacturing process utilizing thin silicon substrates for solar cells

    NASA Technical Reports Server (NTRS)

    Pryor, R. A.

    1980-01-01

    Three inch diameter Czochralski silicon substrates sliced directly to 5 mil, 8 mil, and 27 mil thicknesses with wire saw techniques were procured. Processing sequences incorporating either diffusion or ion implantation technologies were employed to produce n+p or n+pp+ solar cell structures. These cells were evaluated for performance, ease of fabrication, and cost effectiveness. It was determined that the use of 7 mil or even 4 mil wafers would provide near term cost reductions for solar cell manufacturers.

  15. Impedance-based structural health monitoring of additive manufactured structures with embedded piezoelectric wafers

    NASA Astrophysics Data System (ADS)

    Scheyer, Austin G.; Anton, Steven R.

    2017-04-01

    Embedding sensors within additive manufactured (AM) structures gives the ability to develop smart structures that are capable of monitoring the mechanical health of a system. AM provides an opportunity to embed sensors within a structure during the manufacturing process. One major limitation of AM technology is the ability to verify the geometric and material properties of fabricated structures. Over the past several years, the electromechanical impedance (EMI) method for structural health monitoring (SHM) has been proven to be an effective method for sensing damage in structurers. The EMI method utilizes the coupling between the electrical and mechanical properties of a piezoelectric transducer to detect a change in the dynamic response of a structure. A piezoelectric device, usually a lead zirconate titanate (PZT) ceramic wafer, is bonded to a structure and the electrical impedance is measured across as range of frequencies. A change in the electrical impedance is directly correlated to changes made to the mechanical condition of the structure. In this work, the EMI method is employed on piezoelectric transducers embedded inside AM parts to evaluate the feasibility of performing SHM on parts fabricated using additive manufacturing. The fused deposition modeling (FDM) method is used to print specimens for this feasibility study. The specimens are printed from polylactic acid (PLA) in the shape of a beam with an embedded monolithic piezoelectric ceramic disc. The specimen is mounted as a cantilever while impedance measurements are taken using an HP 4194A impedance analyzer. Both destructive and nondestructive damage is simulated in the specimens by adding an end mass and drilling a hole near the free end of the cantilever, respectively. The Root Mean Square Deviation (RMSD) method is utilized as a metric for quantifying damage to the system. In an effort to determine a threshold for RMSD, the values are calculated for the variation associated with taking multiple

  16. Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

    NASA Astrophysics Data System (ADS)

    Kubis, Michael; Wise, Rich; Reijnen, Liesbeth; Viatkina, Katja; Jaenen, Patrick; Luca, Melisa; Mernier, Guillaume; Chahine, Charlotte; Hellin, David; Kam, Benjamin; Sobieski, Daniel; Vertommen, Johan; Mulkens, Jan; Dusa, Mircea; Dixit, Girish; Shamma, Nader; Leray, Philippe

    2016-03-01

    With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

  17. Wafer-Level Vacuum Packaging of Smart Sensors.

    PubMed

    Hilton, Allan; Temple, Dorota S

    2016-10-31

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  18. Wafer-Level Vacuum Packaging of Smart Sensors

    PubMed Central

    Hilton, Allan; Temple, Dorota S.

    2016-01-01

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology. PMID:27809249

  19. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  20. Planning for the semiconductor manufacturer of the future

    NASA Technical Reports Server (NTRS)

    Fargher, Hugh E.; Smith, Richard A.

    1992-01-01

    Texas Instruments (TI) is currently contracted by the Air Force Wright Laboratory and the Defense Advanced Research Projects Agency (DARPA) to develop the next generation flexible semiconductor wafer fabrication system called Microelectronics Manufacturing Science & Technology (MMST). Several revolutionary concepts are being pioneered on MMST, including the following: new single-wafer rapid thermal processes, in-situ sensors, cluster equipment, and advanced Computer Integrated Manufacturing (CIM) software. The objective of the project is to develop a manufacturing system capable of achieving an order of magnitude improvement in almost all aspects of wafer fabrication. TI was awarded the contract in Oct., 1988, and will complete development with a fabrication facility demonstration in April, 1993. An important part of MMST is development of the CIM environment responsible for coordinating all parts of the system. The CIM architecture being developed is based on a distributed object oriented framework made of several cooperating subsystems. The software subsystems include the following: process control for dynamic control of factory processes; modular processing system for controlling the processing equipment; generic equipment model which provides an interface between processing equipment and the rest of the factory; specification system which maintains factory documents and product specifications; simulator for modelling the factory for analysis purposes; scheduler for scheduling work on the factory floor; and the planner for planning and monitoring of orders within the factory. This paper first outlines the division of responsibility between the planner, scheduler, and simulator subsystems. It then describes the approach to incremental planning and the way in which uncertainty is modelled within the plan representation. Finally, current status and initial results are described.

  1. Computational metrology: enabling full-lot high-density fingerprint information without adding wafer metrology budget, and driving improved monitoring and process control

    NASA Astrophysics Data System (ADS)

    Kim, Hyun-Sok; Hyun, Min-Sung; Ju, Jae-Wuk; Kim, Young-Sik; Lambregts, Cees; van Rhee, Peter; Kim, Johan; McNamara, Elliott; Tel, Wim; Böcker, Paul; Oh, Nang-Lyeom; Lee, Jun-Hyung

    2018-03-01

    Computational metrology has been proposed as the way forward to resolve the need for increased metrology density, resulting from extending correction capabilities, without adding actual metrology budget. By exploiting TWINSCAN based metrology information, dense overlay fingerprints for every wafer can be computed. This extended metrology dataset enables new use cases, such as monitoring and control based on fingerprints for every wafer of the lot. This paper gives a detailed description, discusses the accuracy of the fingerprints computed, and will show results obtained in a DRAM HVM manufacturing environment. Also an outlook for improvements and extensions will be shared.

  2. Controllable laser thermal cleavage of sapphire wafers

    NASA Astrophysics Data System (ADS)

    Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

    2018-03-01

    Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

  3. Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

    NASA Astrophysics Data System (ADS)

    Mieda, Eiko; Maeda, Tatsuro; Miyata, Noriyuki; Yasuda, Tetsuji; Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki; Aoki, Takeshi; Yamamoto, Taketsugu; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko; Ogawa, Arito; Kikuchi, Toshiyuki; Kunii, Yasuo

    2015-03-01

    We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

  4. Forming electrical interconnections through semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Anthony, T. R.

    1981-01-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  5. Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

    2018-03-01

    It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

  6. Fabrication of spherical microlens array by combining lapping on silicon wafer and rapid surface molding

    NASA Astrophysics Data System (ADS)

    Liu, Xiaohua; Zhou, Tianfeng; Zhang, Lin; Zhou, Wenchen; Yu, Jianfeng; Lee, L. James; Yi, Allen Y.

    2018-07-01

    Silicon is a promising mold material for compression molding because of its properties of hardness and abrasion resistance. Silicon wafers with carbide-bonded graphene coating and micro-patterns were evaluated as molds for the fabrication of microlens arrays. This study presents an efficient but flexible manufacturing method for microlens arrays that combines a lapping method and a rapid molding procedure. Unlike conventional processes for microstructures on silicon wafers, such as diamond machining and photolithography, this research demonstrates a unique approach by employing precision steel balls and diamond slurries to create microlenses with accurate geometry. The feasibility of this method was demonstrated by the fabrication of several microlens arrays with different aperture sizes and pitches on silicon molds. The geometrical accuracy and surface roughness of the microlens arrays were measured using an optical profiler. The measurement results indicated good agreement with the optical profile of the design. The silicon molds were then used to copy the microstructures onto polymer substrates. The uniformity and quality of the samples molded through rapid surface molding were also assessed and statistically quantified. To further evaluate the optical functionality of the molded microlens arrays, the focal lengths of the microlens arrays were measured using a simple optical setup. The measurements showed that the microlens arrays molded in this research were compatible with conventional manufacturing methods. This research demonstrated an alternative low-cost and efficient method for microstructure fabrication on silicon wafers, together with the follow-up optical molding processes.

  7. Relation between film character and wafer alignment: critical alignment issues on HV device for VLSI manufacturing

    NASA Astrophysics Data System (ADS)

    Lo, Yi-Chuan; Lee, Chih-Hsiung; Lin, Hsun-Peng; Peng, Chiou-Shian

    1998-06-01

    Several continuous splits for wafer alignment target topography conditions to improve epitaxy film alignment were applied. The alignment evaluation among former layer pad oxide thickness (250 angstrom - 500 angstrom), drive oxide thickness (6000 angstrom - 10000 angstrom), nitride film thickness (600 angstrom - 1500 angstrom), initial oxide etch (fully wet etch, fully dry etch and dry plus wet etch) will be split to this experiment. Also various epitaxy deposition recipe such as: epitaxy source (SiHCl2 or SiCHCl3) and growth rate (1.3 micrometer/min approximately 2.0 micrometer/min) will be used to optimize the process window for alignment issue. All the reflectance signal and cross section photography of alignment target during NIKON stepper alignment process will be examined. Experimental results show epitaxy recipe plays an important role to wafer alignment. Low growth rate with good performance conformity epitaxy lead to alignment target avoid washout, pattern shift and distortion. All the results (signal monitor and film character) combined with NIKON's stepper standard laser scanning alignment system will be discussed in this paper.

  8. Wafer-level vacuum/hermetic packaging technologies for MEMS

    NASA Astrophysics Data System (ADS)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  9. Multiproject wafers: not just for million-dollar mask sets

    NASA Astrophysics Data System (ADS)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

  10. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  11. Lasers in energy device manufacturing

    NASA Astrophysics Data System (ADS)

    Ostendorf, A.; Schoonderbeek, A.

    2008-02-01

    Global warming is a current topic all over the world. CO II emissions must be lowered to stop the already started climate change. Developing regenerative energy sources, like photovoltaics and fuel cells contributes to the solution of this problem. Innovative technologies and strategies need to be competitive with conventional energy sources. During the last years, the photovoltaic solar cell industry has experienced enormous growth. However, for solar cells to be competitive on the longer term, both an increase in efficiency as well as reduction in costs is necessary. An effective method to reduce costs of silicon solar cells is reducing the wafer thickness, because silicon makes up a large part of production costs. Consequently, contact free laser processing has a large advantage, because of the decrease in waste materials due to broken wafers as caused by other manufacturing processes. Additionally, many novel high efficiency solar cell concepts are only economically feasible with laser technology, e.g. for scribing silicon thin-film solar cells. This paper describes laser hole drilling, structuring and texturing of silicon wafer based solar cells and describes thin film solar cell scribing. Furthermore, different types of lasers are discussed with respect to processing quality and time.

  12. Interactions of double patterning technology with wafer processing, OPC and design flows

    NASA Astrophysics Data System (ADS)

    Lucas, Kevin; Cork, Chris; Miloslavsky, Alex; Luk-Pat, Gerry; Barnes, Levi; Hapli, John; Lewellen, John; Rollins, Greg; Wiaux, Vincent; Verhaegen, Staf

    2008-03-01

    Double patterning technology (DPT) is one of the main options for printing logic devices with half-pitch less than 45nm; and flash and DRAM memory devices with half-pitch less than 40nm. DPT methods decompose the original design intent into two individual masking layers which are each patterned using single exposures and existing 193nm lithography tools. The results of the individual patterning layers combine to re-create the design intent pattern on the wafer. In this paper we study interactions of DPT with lithography, masks synthesis and physical design flows. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step which will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons where required; and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals such as: reduce circuit area; minimize rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure symmetric wafer results; and create uniform wafer density for the individual patterning layers.

  13. George E. Pake Prize: A Few Challenges in the Evolution of Semiconductor Device/Manufacturing Technology

    NASA Astrophysics Data System (ADS)

    Doering, Robert

    In the early 1980s, the semiconductor industry faced the related challenges of ``scaling through the one-micron barrier'' and converting single-level-metal NMOS integrated circuits to multi-level-metal CMOS. Multiple advances in lithography technology and device materials/process integration led the way toward the deep-sub-micron transistors and interconnects that characterize today's electronic chips. In the 1990s, CMOS scaling advanced at an accelerated pace enabled by rapid advances in many aspects of optical lithography. However, the industry also needed to continue the progress in manufacturing on ever-larger silicon wafers to maintain economy-of-scale trends. Simultaneously, the increasing complexity and absolute-precision requirements of manufacturing compounded the necessity for new processes, tools, and control methodologies. This talk presents a personal perspective on some of the approaches that addressed the aforementioned challenges. In particular, early work on integrating silicides, lightly-doped-drain FETs, shallow recessed isolation, and double-level metal will be discussed. In addition, some pioneering efforts in deep-UV lithography and single-wafer processing will be covered. The latter will be mainly based on results from the MMST Program - a 100 M +, 5-year R&D effort, funded by DARPA, the U.S. Air Force, and Texas Instruments, that developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration of sub-3-day cycle time for manufacturing 350-nm CMOS integrated circuits in 1993. This was principally enabled by the development of: (1) 100% single-wafer processing, including rapid-thermal processing (RTP), and (2) computer-integrated-manufacturing (CIM), including real-time, in-situ process control.

  14. Evaluation of the Technical Feasibility and Effective Cost of Various Wafer Thicknesses for the Manufacture of Solar Cells

    NASA Technical Reports Server (NTRS)

    1979-01-01

    Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.

  15. Evaluation of the technical feasibility and effective cost of various wafer thicknesses for the manufacture of solar cells

    NASA Technical Reports Server (NTRS)

    1978-01-01

    Three wafering demonstration runs were completed on the Yasunaga wire saw. Wafer thickness/taper uniformity is excellent. Many small problems were encountered with Yasunaga accessories, slowing the effort. A wafer characterization cycle was defined and will be initiated during the next period.

  16. A novel approach: high resolution inspection with wafer plane defect detection

    NASA Astrophysics Data System (ADS)

    Hess, Carl; Wihl, Mark; Shi, Rui-fang; Xiong, Yalin; Pang, Song

    2008-05-01

    High Resolution reticle inspection is well-established as a proven, effective, and efficient means of detecting yield-limiting mask defects as well as defects which are not immediately yield-limiting yet can enable manufacturing process improvements. Historically, RAPID products have enabled detection of both classes of these defects. The newly-developed Wafer Plane Inspection (WPI) detector technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. Wafer Plane Inspection accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. This has the effect of reducing sensitivity to non-printing defects while enabling higher sensitivity focused in high MEEF areas where small reticle defects still yield significant printing defects on wafers. WPI is a new inspection mode that has been developed by KLA-Tencor and is currently under test with multiple customers. It employs the same transmitted and reflected-light high-resolution images as the industry-standard high-resolution inspections, but with much more sophisticated processing involved. A rigorous mask pattern recovery algorithm is used to convert the transmitted and reflected light images into a modeled representation of the reticle. Lithographic modeling of the scanner is then used to generate an aerial image of the mask. This is followed by resist modeling to determine the exposure of the photoresist. The defect detectors are then applied on this photoresist plane so that only printing defects are detected. Note that no hardware modifications to the inspection system are required to enable this detector. The same tool will be able to perform both our standard High Resolution inspections and the Wafer Plane Inspection detector. This approach has several important features. The ability to ignore non

  17. Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

    NASA Astrophysics Data System (ADS)

    Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

    2018-04-01

    Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

  18. Space station automation study: Automation requriements derived from space manufacturing concepts,volume 2

    NASA Technical Reports Server (NTRS)

    1984-01-01

    Automation reuirements were developed for two manufacturing concepts: (1) Gallium Arsenide Electroepitaxial Crystal Production and Wafer Manufacturing Facility, and (2) Gallium Arsenide VLSI Microelectronics Chip Processing Facility. A functional overview of the ultimate design concept incoporating the two manufacturing facilities on the space station are provided. The concepts were selected to facilitate an in-depth analysis of manufacturing automation requirements in the form of process mechanization, teleoperation and robotics, sensors, and artificial intelligence. While the cost-effectiveness of these facilities was not analyzed, both appear entirely feasible for the year 2000 timeframe.

  19. Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

    NASA Astrophysics Data System (ADS)

    Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

    2012-05-01

    In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

  20. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    DOEpatents

    Lin, YuPo J [Naperville, IL; Henry, Michael P [Batavia, IL; Snyder, Seth W [Lincolnwood, IL

    2011-07-12

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  1. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  2. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  3. Accomplishments in Photovoltaic Manufacturing R&D | Photovoltaic Research |

    Science.gov Websites

    made that significantly reduced the cost of solar modules while increasing their reliability and -area efficiency. Manufacturing Processes Half the cost of producing a solar module is incurred in wafer project partners marked significant progress in module cost reduction. A few notable examples follow

  4. Emission factors of air toxics from semiconductor manufacturing in Korea.

    PubMed

    Eom, Yun-Sung; Hong, Ji-Hyung; Lee, Suk-Jo; Lee, Eun-Jung; Cha, Jun-Seok; Lee, Dae-Gyun; Bang, Sun-Ae

    2006-11-01

    The development of local, accurate emission factors is very important for the estimation of reliable national emissions and air quality management. For that, this study is performed for pollutants released to the atmosphere with source-specific emission tests from the semiconductor manufacturing industry. The semiconductor manufacturing industry is one of the major sources of air toxics or hazardous air pollutants (HAPs); thus, understanding the emission characteristics of the emission source is a very important factor in the development of a control strategy. However, in Korea, there is a general lack of information available on air emissions from the semiconductor industry. The major emission sources of air toxics examined from the semiconductor manufacturing industry were wet chemical stations, coating applications, gaseous operations, photolithography, and miscellaneous devices in the wafer fabrication and semiconductor packaging processes. In this study, analyses of emission characteristics, and the estimations of emission data and factors for air toxics, such as acids, bases, heavy metals, and volatile organic compounds from the semiconductor manufacturing process have been performed. The concentration of hydrogen chloride from the packaging process was the highest among all of the processes. In addition, the emission factor of total volatile organic compounds (TVOCs) for the packaging process was higher than that of the wafer fabrication process. Emission factors estimated in this study were compared with those of Taiwan for evaluation, and they were found to be of similar level in the case of TVOCs and fluorine compounds.

  5. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  6. Continuous Manufacturing in Pharmaceutical Process Development and Manufacturing.

    PubMed

    Burcham, Christopher L; Florence, Alastair J; Johnson, Martin D

    2018-06-07

    The pharmaceutical industry has found new applications for the use of continuous processing for the manufacture of new therapies currently in development. The transformation has been encouraged by regulatory bodies as well as driven by cost reduction, decreased development cycles, access to new chemistries not practical in batch, improved safety, flexible manufacturing platforms, and improved product quality assurance. The transformation from batch to continuous manufacturing processing is the focus of this review. The review is limited to small, chemically synthesized organic molecules and encompasses the manufacture of both active pharmaceutical ingredients (APIs) and the subsequent drug product. Continuous drug product is currently used in approved processes. A few examples of production of APIs under current good manufacturing practice conditions using continuous processing steps have been published in the past five years, but they are lagging behind continuous drug product with respect to regulatory filings.

  7. A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

    PubMed

    Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

    2012-07-01

    We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

  8. Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

    NASA Astrophysics Data System (ADS)

    Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

    2016-11-01

    The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

  9. WaferOptics® mass volume production and reliability

    NASA Astrophysics Data System (ADS)

    Wolterink, E.; Demeyer, K.

    2010-05-01

    The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

  10. Wafer hot spot identification through advanced photomask characterization techniques: part 2

    NASA Astrophysics Data System (ADS)

    Choi, Yohan; Green, Michael; Cho, Young; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

    2017-03-01

    Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.

  11. Geometry-based across wafer process control in a dual damascene scenario

    NASA Astrophysics Data System (ADS)

    Krause, Gerd; Hofmann, Detlef; Habets, Boris; Buhl, Stefan; Gutsch, Manuela; Lopez-Gomez, Alberto; Thrun, Xaver

    2018-03-01

    Dual damascene is an established patterning process for back-end-of-line to generate copper interconnects and lines. One of the critical output parameters is the electrical resistance of the metal lines. In our 200 mm line, this is currently being controlled by a feed-forward control from the etch process to the final step in the CMP process. In this paper, we investigate the impact of alternative feed-forward control using a calibrated physical model that estimates the impact on electrical resistance of the metal lines* . This is done by simulation on a large set of wafers. Three different approaches are evaluated, one of which uses different feed-forward settings for different radial zones in the CMP process.

  12. X-ray topography as a process control tool in semiconductor and microcircuit manufacture

    NASA Technical Reports Server (NTRS)

    Parker, D. L.; Porter, W. A.

    1977-01-01

    A bent wafer camera, designed to identify crystal lattice defects in semiconductor materials, was investigated. The camera makes use of conventional X-ray topographs and an innovative slightly bent wafer which allows rays from the point source to strike all portions of the wafer simultaneously. In addition to being utilized in solving production process control problems, this camera design substantially reduces the cost per topograph.

  13. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  14. Solar cell circuit and method for manufacturing solar cells

    NASA Technical Reports Server (NTRS)

    Mardesich, Nick (Inventor)

    2010-01-01

    The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

  15. Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

    NASA Astrophysics Data System (ADS)

    Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

    2015-07-01

    Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

  16. Compensating measured intra-wafer ring oscillator stage delay with intra-wafer exposure dose corrections

    NASA Astrophysics Data System (ADS)

    Verhaegen, Staf; Nackaerts, Axel; Dusa, Mircea; Carpaij, Rene; Vandenberghe, Geert; Finders, Jo

    2006-03-01

    The purpose of this paper is to use measurements on real working devices to derive more information than typically measured by the classic line-width measurement techniques. The first part of the paper will discuss the principle of the measurements with a ring oscillator, a circuit used to measure the speed of elementary logic gates. These measurements contribute to the understanding of the exact timing dependencies in circuits, which is of utmost importance for the design and simulation of these circuits. When connecting an odd number of digital inverting stages in a ring, the circuit has no stable digital state but acts as an analog oscillator with the oscillation frequency dependent on the analog propagation delay of the signals through the stages. By varying some conditions during a litho step, the delay change caused by the process condition change can be measured very accurately. The response of the ring oscillator delay to exposure dose is measured and presented in this paper together with a comparison of measured line-width values of the poly gate lines. The second part of the paper will focus on improving the intra-wafer variation of the stage delay. A number of ring oscillators are put in a design at different slit and scan locations. 200mm wafers are processed with 48 full dies present. From the intra-wafer delay fingerprint and the dose sensitivity of the delay an intra-wafer dose correction, also called a dose recipe, is calculated. This dose recipe is used on the scanner to compensate for effects that are the root cause for the delay profile; including reticle and processing such as track, etch and annealing.

  17. Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response

    PubMed Central

    Brito, Nuno; Ferreira, Carlos; Alves, Filipe; Cabral, Jorge; Gaspar, João; Monteiro, João; Rocha, Luís

    2016-01-01

    The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr), quality factor (Q), and pull-in voltage (Vpi) within 1.5 s with repeatability better than 5 ppt (parts per thousand). A full-wafer with 420 devices under test (DUTs) has been evaluated detecting the faulty devices and providing important design specification feedback to the designers. PMID:27657087

  18. Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response.

    PubMed

    Brito, Nuno; Ferreira, Carlos; Alves, Filipe; Cabral, Jorge; Gaspar, João; Monteiro, João; Rocha, Luís

    2016-09-21

    The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr), quality factor (Q), and pull-in voltage (Vpi) within 1.5 s with repeatability better than 5 ppt (parts per thousand). A full-wafer with 420 devices under test (DUTs) has been evaluated detecting the faulty devices and providing important design specification feedback to the designers.

  19. Quality management of manufacturing process based on manufacturing execution system

    NASA Astrophysics Data System (ADS)

    Zhang, Jian; Jiang, Yang; Jiang, Weizhuo

    2017-04-01

    Quality control elements in manufacturing process are elaborated. And the approach of quality management of manufacturing process based on manufacturing execution system (MES) is discussed. The functions of MES for a microcircuit production line are introduced conclusively.

  20. Accelerating yield ramp through design and manufacturing collaboration

    NASA Astrophysics Data System (ADS)

    Sarma, Robin C.; Dai, Huixiong; Smayling, Michael C.; Duane, Michael P.

    2004-12-01

    Ramping an integrated circuit from first silicon bring-up to production yield levels is a challenge for all semiconductor products on the path to profitable market entry. Two approaches to accelerating yield ramp are presented. The first is the use of laser mask writers for fast throughput, high yield, and cost effective pattern transfer. The second is the use of electrical test to find a defect and identify the physical region to probe in failure analysis that is most likely to uncover the root cause. This provides feedback to the design team on modifications to make to the design to avoid the yield issue in a future tape-out revision. Additionally, the process parameter responsible for the root cause of the defect is forward annotated through the design, mask and wafer coordinate systems so it can be monitored in-line on subsequent lots of the manufacturing run. This results in an improved recipe for the manufacturing equipment to potentially prevent the recurrence of the defect and raise yield levels on the following material. The test diagnostics approach is enabled by the seamless traceability of a feature across the design, photomask and wafer, made possible by a common data model for design, mask pattern generation and wafer fabrication.

  1. Wafer-scale fabrication of polymer-based microdevices via injection molding and photolithographic micropatterning protocols.

    PubMed

    Lee, Dae-Sik; Yang, Haesik; Chung, Kwang-Hyo; Pyo, Hyeon-Bong

    2005-08-15

    Because of their broad applications in biomedical analysis, integrated, polymer-based microdevices incorporating micropatterned metallic and insulating layers are significant in contemporary research. In this study, micropatterns for temperature sensing and microelectrode sets for electroanalysis have been implemented on an injection-molded thin polymer membrane by employing conventional semiconductor processing techniques (i.e., standard photolithographic methods). Cyclic olefin copolymer (COC) is chosen as the polymer substrate because of its high chemical and thermal stability. A COC 5-in. wafer (1-mm thickness) is manufactured using an injection molding method, in which polymer membranes (approximately 130 microm thick and 3 mm x 6 mm in area) are implemented simultaneously in order to reduce local thermal mass around micropatterned heaters and temperature sensors. The highly polished surface (approximately 4 nm within 40 microm x 40 microm area) of the fabricated COC wafer as well as its good resistance to typical process chemicals makes it possible to use the standard photolithographic and etching protocols on the COC wafer. Gold micropatterns with a minimum 5-microm line width are fabricated for making microheaters, temperature sensors, and microelectrodes. An insulating layer of aluminum oxide (Al2O3) is prepared at a COC-endurable low temperature (approximately 120 degrees C) by using atomic layer deposition and micropatterning for the electrode contacts. The fabricated microdevice for heating and temperature sensing shows improved performance of thermal isolation, and microelectrodes display good electrochemical performances for electrochemical sensors. Thus, this novel 5-in. wafer-level microfabrication method is a simple and cost-effective protocol to prepare polymer substrate and demonstrates good potential for application to highly integrated and miniaturized biomedical devices.

  2. Guided ultrasonic wave beam skew in silicon wafers

    NASA Astrophysics Data System (ADS)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2018-04-01

    In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

  3. SEMICONDUCTOR TECHNOLOGY A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    NASA Astrophysics Data System (ADS)

    Baohong, Gao; Yuling, Liu; Chenwei, Wang; Yadong, Zhu; Shengli, Wang; Qiang, Zhou; Baimei, Tan

    2010-10-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection.

  4. I-line stepper based overlay evaluation method for wafer bonding applications

    NASA Astrophysics Data System (ADS)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2018-03-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

  5. Solid state laser applications in photovoltaics manufacturing

    NASA Astrophysics Data System (ADS)

    Dunsky, Corey; Colville, Finlay

    2008-02-01

    Photovoltaic energy conversion devices are on a rapidly accelerating growth path driven by increasing government and societal pressure to use renewable energy as part of an overall strategy to address global warming attributed to greenhouse gas emissions. Initially supported in several countries by generous tax subsidies, solar cell manufacturers are relentlessly pushing the performance/cost ratio of these devices in a quest to reach true cost parity with grid electricity. Clearly this eventual goal will result in further acceleration in the overall market growth. Silicon wafer based solar cells are currently the mainstay of solar end-user installations with a cost up to three times grid electricity. But next-generation technology in the form of thin-film devices promises streamlined, high-volume manufacturing and greatly reduced silicon consumption, resulting in dramatically lower per unit fabrication costs. Notwithstanding the modest conversion efficiency of thin-film devices compared to wafered silicon products (around 6-10% versus 15-20%), this cost reduction is driving existing and start-up solar manufacturers to switch to thin-film production. A key aspect of these devices is patterning large panels to create a monolithic array of series-interconnected cells to form a low current, high voltage module. This patterning is accomplished in three critical scribing processes called P1, P2, and P3. Lasers are the technology of choice for these processes, delivering the desired combination of high throughput and narrow, clean scribes. This paper examines these processes and discusses the optimization of industrial lasers to meet their specific needs.

  6. Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

    PubMed

    Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

    2014-01-09

    Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

  7. Applications of the silicon wafer direct-bonding technique to electron devices

    NASA Astrophysics Data System (ADS)

    Furukawa, K.; Nakagawa, A.

    1990-01-01

    A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

  8. Chelant Enhanced Solution Processing for Wafer Scale Synthesis of Transition Metal Dichalcogenide Thin Films.

    PubMed

    Ionescu, Robert; Campbell, Brennan; Wu, Ryan; Aytan, Ece; Patalano, Andrew; Ruiz, Isaac; Howell, Stephen W; McDonald, Anthony E; Beechem, Thomas E; Mkhoyan, K Andre; Ozkan, Mihrimah; Ozkan, Cengiz S

    2017-07-25

    It is of paramount importance to improve the control over large area growth of high quality molybdenum disulfide (MoS 2 ) and other types of 2D dichalcogenides. Such atomically thin materials have great potential for use in electronics, and are thought to make possible the first real applications of spintronics. Here in, a facile and reproducible method of producing wafer scale atomically thin MoS 2 layers has been developed using the incorporation of a chelating agent in a common organic solvent, dimethyl sulfoxide (DMSO). Previously, solution processing of a MoS 2 precursor, ammonium tetrathiomolybdate ((NH 4 ) 2 MoS 4 ), and subsequent thermolysis was used to produce large area MoS 2 layers. Our work here shows that the use of ethylenediaminetetraacetic acid (EDTA) in DMSO exerts superior control over wafer coverage and film thickness, and the results demonstrate that the chelating action and dispersing effect of EDTA is critical in growing uniform films. Raman spectroscopy, photoluminescence (PL), x-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectroscopy (FTIR), atomic force microscopy (AFM) and high-resolution scanning transmission electron microscopy (HR-STEM) indicate the formation of homogenous few layer MoS 2 films at the wafer scale, resulting from the novel chelant-in-solution method.

  9. 40 CFR Table I-16 to Subpart I of... - Default Emission Destruction or Removal Efficiency (DRE) Factors for Electronics Manufacturing

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... Manufacturing: Plasma Etch/Wafer Clean Process Type: CF4 75 CH3F 97 CHF3 97 CH2F2 97 C2F6 97 C3F8 97 C4F6 97 C4F8 97 C5F8 97 SF6 97 NF3 96 All other carbon-based plasma etch/wafer clean fluorinated GHG 60 Chamber...

  10. Realize multiple hermetic chamber pressures for system-on-chip process by using the capping wafer with diverse cavity depths

    NASA Astrophysics Data System (ADS)

    Cheng, Shyh-Wei; Weng, Jui-Chun; Liang, Kai-Chih; Sun, Yi-Chiang; Fang, Weileun

    2018-04-01

    Many mechanical and thermal characteristics, for example the air damping, of suspended micromachined structures are sensitive to the ambient pressure. Thus, micromachined devices such as the gyroscope and accelerometer have different ambient pressure requirements. Commercially available process platforms could be used to fabricate and integrate devices of various functions to reduce the chip size. However, it remains a challenge to offer different ambient pressures for micromachined devices after sealing them by wafer level capping (WLC). This study exploits the outgassing characteristics of the CMOS chip to fabricate chambers of various pressures after the WLC of the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform. The pressure of the sealed chamber can be modulated by the chamber volume after the outgassing. In other words, the pressure of hermetic sealed chambers can be easily and properly defined by the etching depth of the cavity on an Si capping wafer. In applications, devices sealed with different cavity depths are implemented using the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform to demonstrate the present approach. Measurements show the feasibility of this simple chamber pressure modulation approach on eight-inch wafers.

  11. Integrated manufacturing approach to attain benchmark team performance

    NASA Astrophysics Data System (ADS)

    Chen, Shau-Ron; Nguyen, Andrew; Naguib, Hussein

    1994-09-01

    A Self-Directed Work Team (SDWT) was developed to transfer a polyimide process module from the research laboratory to our wafer fab facility for applications in IC specialty devices. The SDWT implemented processes and tools based on the integration of five manufacturing strategies for continuous improvement. These were: Leadership Through Quality (LTQ), Total Productive Maintenance (TMP), Cycle Time Management (CTM), Activity-Based Costing (ABC), and Total Employee Involvement (TEI). Utilizing these management techniques simultaneously, the team achieved six sigma control of all critical parameters, increased Overall Equipment Effectiveness (OEE) from 20% to 90%, reduced cycle time by 95%, cut polyimide manufacturing cost by 70%, and improved its overall team member skill level by 33%.

  12. Optima XE Single Wafer High Energy Ion Implanter

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Satoh, Shu; Ferrara, Joseph; Bell, Edward

    2008-11-03

    The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowingmore » the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.« less

  13. High-NA optical CD metrology on small in-cell targets enabling improved higher order dose control and process control for logic

    NASA Astrophysics Data System (ADS)

    Cramer, Hugo; Mc Namara, Elliott; van Laarhoven, Rik; Jaganatharaja, Ram; de la Fuente, Isabel; Hsu, Sharon; Belletti, Filippo; Popadic, Milos; Tu, Ward; Huang, Wade

    2017-03-01

    The logic manufacturing process requires small in-device metrology targets to exploit the full dose correction potential of the modern scanners and process tools. A high-NA angular resolved scatterometer (YieldStar S-1250D) was modified to demonstrate the possibility of OCD measurements on 5x5µm2 targets. The results obtained on test wafers in a logic manufacturing environment, measured after litho and after core etch, showed a good correlation to larger reference targets and AEI to ADI intra-field CDU correlation, thereby demonstrating the feasibility of OCD on such small targets. The data was used to determine a reduction potential of 55% for the intra-field CD variation, using 145 points per field on a few inner fields, and 33% of the process induced across wafer CD variation using 16 points per field full wafer. In addition, the OCD measurements reveal valuable information on wafer-to-wafer layer height variations within a lot.

  14. Strategy optimization for mask rule check in wafer fab

    NASA Astrophysics Data System (ADS)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  15. Studying post-etching silicon crystal defects on 300mm wafer by automatic defect review AFM

    NASA Astrophysics Data System (ADS)

    Zandiatashbar, Ardavan; Taylor, Patrick A.; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

    2016-03-01

    Single crystal silicon wafers are the fundamental elements of semiconductor manufacturing industry. The wafers produced by Czochralski (CZ) process are very high quality single crystalline materials with known defects that are formed during the crystal growth or modified by further processing. While defects can be unfavorable for yield for some manufactured electrical devices, a group of defects like oxide precipitates can have both positive and negative impacts on the final device. The spatial distribution of these defects may be found by scattering techniques. However, due to limitations of scattering (i.e. light wavelength), many crystal defects are either poorly classified or not detected. Therefore a high throughput and accurate characterization of their shape and dimension is essential for reviewing the defects and proper classification. While scanning electron microscopy (SEM) can provide high resolution twodimensional images, atomic force microscopy (AFM) is essential for obtaining three-dimensional information of the defects of interest (DOI) as it is known to provide the highest vertical resolution among all techniques [1]. However AFM's low throughput, limited tip life, and laborious efforts for locating the DOI have been the limitations of this technique for defect review for 300 mm wafers. To address these limitations of AFM, automatic defect review AFM has been introduced recently [2], and is utilized in this work for studying DOI on 300 mm silicon wafer. In this work, we carefully etched a 300 mm silicon wafer with a gaseous acid in a reducing atmosphere at a temperature and for a sufficient duration to decorate and grow the crystal defects to a size capable of being detected as light scattering defects [3]. The etched defects form a shallow structure and their distribution and relative size are inspected by laser light scattering (LLS). However, several groups of defects couldn't be properly sized by the LLS due to the very shallow depth and low

  16. 450mm wafer patterning with jet and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  17. Cohesive zone model for direct silicon wafer bonding

    NASA Astrophysics Data System (ADS)

    Kubair, D. V.; Spearing, S. M.

    2007-05-01

    Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

  18. Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

    NASA Astrophysics Data System (ADS)

    Miki, N.; Spearing, S. M.

    2003-11-01

    Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

  19. Low-temperature magnetotransport in Si/SiGe heterostructures on 300 mm Si wafers

    NASA Astrophysics Data System (ADS)

    Scappucci, Giordano; Yeoh, L.; Sabbagh, D.; Sammak, A.; Boter, J.; Droulers, G.; Kalhor, N.; Brousse, D.; Veldhorst, M.; Vandersypen, L. M. K.; Thomas, N.; Roberts, J.; Pillarisetty, R.; Amin, P.; George, H. C.; Singh, K. J.; Clarke, J. S.

    Undoped Si/SiGe heterostructures are a promising material stack for the development of spin qubits in silicon. To deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. Electron mobility and valley splitting are two key electrical metrics of substrate quality relevant for qubits. Here we present low-temperature magnetotransport measurements of strained Si quantum wells with mobilities in excess of 100000 cm2/Vs fabricated on 300 mm wafers within the framework of advanced semiconductor manufacturing. These results are benchmarked against the results obtained in Si quantum wells deposited on 100 mm Si wafers in an academic research environment. To ensure rapid progress in quantum wells quality we have implemented fast feedback loops from materials growth, to heterostructure FET fabrication, and low temperature characterisation. On this topic we will present recent progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

  20. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  1. Worker exposure to methanol vapors during cleaning of semiconductor wafers in a manufacturing setting.

    PubMed

    Gaffney, Shannon; Moody, Emily; McKinley, Meg; Knutsen, Jeffrey; Madl, Amy; Paustenbach, Dennis

    2008-05-01

    An exposure simulation was conducted to characterize methanol exposure of workers who cleaned wafers in quality control departments within the semiconductor industry. Short-term (15 min) and long-term (2-4 hr) personal and area samples (at distances of 1 m and 3-6 m from the source) were collected during the 2-day simulation. On the first day, 45 mL of methanol were used per hour by a single worker washing wafers in a 102 m(3) room with a ventilation rate of about 10 air changes per hour (ACH). Virtually all methanol volatilized. To assess exposures under conditions associated with higher productivity, on the second day, two workers cleaned wafers simultaneously, together using methanol at over twice the rate of the first day (95 mL/hr). On this day, the ventilation rate was halved (5 ACH). Personal concentrations on the first day averaged 60 ppm (SD = 46 ppm) and ranged from 10-140 ppm. On the second day, personal concentrations for both workers averaged 118 ppm (SD = 50 ppm; range: 64-270 ppm). Area concentrations measured on the first day at 1 m from the source and throughout the balance of the room averaged 29 ppm (SD = 19 ppm; range: 4-83 ppm) and 18 ppm (SD = 12 ppm; range: 3-42 ppm), respectively. As expected, area concentrations measured on the second day were higher than the first and averaged 73 ppm (SD = 25 ppm; range: 27-140 ppm) at 1 meter and 48 ppm (SD = 13 ppm; range: 21-67 ppm) throughout the balance of the room. The results of this simulation suggest that the use of methanol to clean semiconductor wafers without the use of local exhaust ventilation and with relatively low room ventilation rates is unlikely to result in worker exposures exceeding the current ACGIH(R) threshold limit value of 200 ppm. This study also confirmed prior studies suggesting that when a relatively volatile chemical is located within arm's length (near field), breathing zone concentrations will be about two- to threefold greater than the room concentration when the air

  2. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  3. Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

    NASA Astrophysics Data System (ADS)

    Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

    2018-01-01

    Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

  4. Development of Pulsed Processes for the Manufacture of Solar Cells

    NASA Technical Reports Server (NTRS)

    1979-01-01

    The development status of the process based upon ion implantation for the introduction of junctions and back surface fields is described. A process sequence is presented employing ion implantation and pulse processing. Efforts to improve throughout and descrease process element costs for furnace annealing are described. Design studies for a modular 3,000 wafer per hour pulse processor are discussed.

  5. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

    1979-01-01

    A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

  6. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    NASA Astrophysics Data System (ADS)

    Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

    2014-08-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

  7. Material electronic quality specifications for polycrystalline silicon wafers

    NASA Astrophysics Data System (ADS)

    Kalejs, J. P.

    1994-06-01

    As the use of polycrystalline silicon wafers has expanded in the photovoltaic industry, the need grows for monitoring and qualification techniques for as-grown material that can be used to optimize crystal growth and help predict solar cell performance. Particular needs are for obtaining quantitative measures over full wafer areas of the effects of lifetime limiting defects and of the lifetime upgrading taking place during solar cell processing. We review here the approaches being pursued in programs under way to develop material quality specifications for thin Edge-defined Film-fed Growth (EFG) polycrystalline silicon as-grown wafers. These studies involve collaborations between Mobil Solar, and NREL and university-based laboratories.

  8. Manufacturability of the X Architecture at the 90-nm technology node

    NASA Astrophysics Data System (ADS)

    Smayling, Michael C.; Sarma, Robin C.; Nagata, Toshiyuki; Arora, Narain; Duane, Michael P.; Oemardani, Shiany; Shah, Santosh

    2004-05-01

    In this paper, we discuss the results from a test chip that demonstrate the manufacturability and integration-worthiness of the X Architecture at the 90-nm technology node. We discuss how a collaborative effort between the design and chip making communities used the current generation of mask, lithography, wafer processing, inspection and metrology equipment to create 45 degree wires in typical metal pitches for the upper layers on a 90-nm device in a production environment. Cadence Design Systems created the test structure design and chip validation tools for the project. Canon"s KrF ES3 and ArF AS2 scanners were used for the lithography. Applied Materials used its interconnect fabrication technologies to produce the multilayer copper, low-k interconnect on 300-mm wafers. The results were confirmed for critical dimension and defect levels using Applied Materials" wafer inspection and metrology systems.

  9. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  10. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, Gary S.

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  11. Mechanics of wafer bonding: Effect of clamping

    NASA Astrophysics Data System (ADS)

    Turner, K. T.; Thouless, M. D.; Spearing, S. M.

    2004-01-01

    A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

  12. Robust wafer identification recognition based on asterisk-shape filter and high-low score comparison method.

    PubMed

    Hsu, Wei-Chih; Yu, Tsan-Ying; Chen, Kuan-Liang

    2009-12-10

    Wafer identifications (wafer ID) can be used to identify wafers from each other so that wafer processing can be traced easily. Wafer ID recognition is one of the problems of optical character recognition. The process to recognize wafer IDs is similar to that used in recognizing car license-plate characters. However, due to some unique characteristics, such as the irregular space between two characters and the unsuccessive strokes of wafer ID, it will not get a good result to recognize wafer ID by directly utilizing the approaches used in car license-plate character recognition. Wafer ID scratches are engraved by a laser scribe almost along the following four fixed directions: horizontal, vertical, plus 45 degrees , and minus 45 degrees orientations. The closer to the center line of a wafer ID scratch, the higher the gray level will be. These and other characteristics increase the difficulty to recognize the wafer ID. In this paper a wafer ID recognition scheme based on an asterisk-shape filter and a high-low score comparison method is proposed to cope with the serious influence of uneven luminance and make recognition more efficiently. Our proposed approach consists of some processing stages. Especially in the final recognition stage, a template-matching method combined with stroke analysis is used as a recognizing scheme. This is because wafer IDs are composed of Semiconductor Equipment and Materials International (SEMI) standard Arabic numbers and English alphabets, and thus the template ID images are easy to obtain. Furthermore, compared with the approach that requires prior training, such as a support vector machine, which often needs a large amount of training image samples, no prior training is required for our approach. The testing results show that our proposed scheme can efficiently and correctly segment out and recognize the wafer ID with high performance.

  13. Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

    PubMed

    Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

    2017-10-01

    Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

  14. Manufacturing Process Simulation of Large-Scale Cryotanks

    NASA Technical Reports Server (NTRS)

    Babai, Majid; Phillips, Steven; Griffin, Brian; Munafo, Paul M. (Technical Monitor)

    2002-01-01

    NASA's Space Launch Initiative (SLI) is an effort to research and develop the technologies needed to build a second-generation reusable launch vehicle. It is required that this new launch vehicle be 100 times safer and 10 times cheaper to operate than current launch vehicles. Part of the SLI includes the development of reusable composite and metallic cryotanks. The size of these reusable tanks is far greater than anything ever developed and exceeds the design limits of current manufacturing tools. Several design and manufacturing approaches have been formulated, but many factors must be weighed during the selection process. Among these factors are tooling reachability, cycle times, feasibility, and facility impacts. The manufacturing process simulation capabilities available at NASA's Marshall Space Flight Center have played a key role in down selecting between the various manufacturing approaches. By creating 3-D manufacturing process simulations, the varying approaches can be analyzed in a virtual world before any hardware or infrastructure is built. This analysis can detect and eliminate costly flaws in the various manufacturing approaches. The simulations check for collisions between devices, verify that design limits on joints are not exceeded, and provide cycle times which aid in the development of an optimized process flow. In addition, new ideas and concerns are often raised after seeing the visual representation of a manufacturing process flow. The output of the manufacturing process simulations allows for cost and safety comparisons to be performed between the various manufacturing approaches. This output helps determine which manufacturing process options reach the safety and cost goals of the SLI.

  15. Wafer edge overlay control solution for N7 and beyond

    NASA Astrophysics Data System (ADS)

    van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

    2018-03-01

    Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

  16. Surface etching technologies for monocrystalline silicon wafer solar cells

    NASA Astrophysics Data System (ADS)

    Tang, Muzhi

    With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

  17. Research and Development Advances Impacting Diminishing Manufacturing Sources and Material Shortages Management

    DTIC Science & Technology

    2016-06-01

    commercially available in 2 to 3 years. The fabs that fabricate today’s ICs service high-volume customers. Manufacturing the small volumes needed by DOD...is simply not cost effective and is disruptive to the process flow. There are smaller specialty fabs that focus on smaller orders and process smaller...process wafers with leading-edge technology, these fabs would have to invest in the same tools as the high-volume fabs —a prohibitive expense. Multi

  18. Automated defect spatial signature analysis for semiconductor manufacturing process

    DOEpatents

    Tobin, Jr., Kenneth W.; Gleason, Shaun S.; Karnowski, Thomas P.; Sari-Sarraf, Hamed

    1999-01-01

    An apparatus and method for performing automated defect spatial signature alysis on a data set representing defect coordinates and wafer processing information includes categorizing data from the data set into a plurality of high level categories, classifying the categorized data contained in each high level category into user-labeled signature events, and correlating the categorized, classified signature events to a present or incipient anomalous process condition.

  19. A Process Management System for Networked Manufacturing

    NASA Astrophysics Data System (ADS)

    Liu, Tingting; Wang, Huifen; Liu, Linyan

    With the development of computer, communication and network, networked manufacturing has become one of the main manufacturing paradigms in the 21st century. Under the networked manufacturing environment, there exist a large number of cooperative tasks susceptible to alterations, conflicts caused by resources and problems of cost and quality. This increases the complexity of administration. Process management is a technology used to design, enact, control, and analyze networked manufacturing processes. It supports efficient execution, effective management, conflict resolution, cost containment and quality control. In this paper we propose an integrated process management system for networked manufacturing. Requirements of process management are analyzed and architecture of the system is presented. And a process model considering process cost and quality is developed. Finally a case study is provided to explain how the system runs efficiently.

  20. Characterizing SOI Wafers By Use Of AOTF-PHI

    NASA Technical Reports Server (NTRS)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  1. Investigation of radiation hardened SOI wafer fabricated by ion-cut technique

    NASA Astrophysics Data System (ADS)

    Chang, Yongwei; Wei, Xing; Zhu, Lei; Su, Xin; Gao, Nan; Dong, Yemin

    2018-07-01

    Total ionizing dose (TID) effect on Silicon-on-Insulator (SOI) wafers due to inherent buried oxide (BOX) is a significant concern as it leads to the degradation of electrical properties of SOI-based devices and circuits, even failures of the systems associated with them. This paper reports the radiation hardening implementation of SOI wafer fabricated by ion-cut technique integrated with low-energy Si+ implantation. The electrical properties and radiation response of pseudo-MOS transistors are analyzed. The results demonstrate that the hardening process can significantly improve the TID tolerance of SOI wafers by generating Si nanocrystals (Si-NCs) within the BOX. The presence of Si-NCs created through Si+ implantation is evidenced by high-resolution transmission electron microscopy (HR-TEM). Under the pass gate (PG) irradiation bias, the anti-radiation properties of H-gate SOI nMOSFETs suggest that the radiation hardened SOI wafers with optimized Si implantation dose can perform effectively in a radiation environment. The radiation hardening process provides an excellent way to reinforce the TID tolerance of SOI wafers.

  2. Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

    PubMed

    Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

    2012-03-01

    Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

  3. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    NASA Astrophysics Data System (ADS)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  4. Non-contact defect diagnostics in Cz-Si wafers using resonance ultrasonic vibrations

    NASA Astrophysics Data System (ADS)

    Belyaev, A.; Kochelap, V. A.; Tarasov, I.; Ostapenko, S.

    2001-01-01

    A new resonance effect of generation of sub-harmonic acoustic vibrations was applied to characterize defects in as-grown and processed Cz-Si wafers. Ultrasonic vibrations were generated into standard 8″ wafers using an external ultrasonic transducer and their amplitude recorded in a non-contact mode using a scanning acoustic probe. By tuning the frequency, f, of the transducer we observed generation of intense sub-harmonic acoustic mode ("whistle" or w-mode) with f/2 frequency. The characteristics of the w-mode-amplitude dependence, frequency scans, spatial distribution allow a clear distinction versus harmonic vibrations of the same wafer. The origin of sub-harmonic vibrations observed on 8″ Cz-Si wafers is attributed to a parametric resonance of flexural vibrations in thin silicon circular plates. We present evidence that "whistle" effect shows a strong dependence on the wafer's growth and processing history and can be used for quality assurance purposes.

  5. Advanced FTIR technology for the chemical characterization of product wafers

    NASA Astrophysics Data System (ADS)

    Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

    2001-01-01

    Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers.

  6. Reduction of wafer-edge overlay errors using advanced correction models, optimized for minimal metrology requirements

    NASA Astrophysics Data System (ADS)

    Kim, Min-Suk; Won, Hwa-Yeon; Jeong, Jong-Mun; Böcker, Paul; Vergaij-Huizer, Lydia; Kupers, Michiel; Jovanović, Milenko; Sochal, Inez; Ryan, Kevin; Sun, Kyu-Tae; Lim, Young-Wan; Byun, Jin-Moo; Kim, Gwang-Gon; Suh, Jung-Joon

    2016-03-01

    In order to optimize yield in DRAM semiconductor manufacturing for 2x nodes and beyond, the (processing induced) overlay fingerprint towards the edge of the wafer needs to be reduced. Traditionally, this is achieved by acquiring denser overlay metrology at the edge of the wafer, to feed field-by-field corrections. Although field-by-field corrections can be effective in reducing localized overlay errors, the requirement for dense metrology to determine the corrections can become a limiting factor due to a significant increase of metrology time and cost. In this study, a more cost-effective solution has been found in extending the regular correction model with an edge-specific component. This new overlay correction model can be driven by an optimized, sparser sampling especially at the wafer edge area, and also allows for a reduction of noise propagation. Lithography correction potential has been maximized, with significantly less metrology needs. Evaluations have been performed, demonstrating the benefit of edge models in terms of on-product overlay performance, as well as cell based overlay performance based on metrology-to-cell matching improvements. Performance can be increased compared to POR modeling and sampling, which can contribute to (overlay based) yield improvement. Based on advanced modeling including edge components, metrology requirements have been optimized, enabling integrated metrology which drives down overall metrology fab footprint and lithography cycle time.

  7. Disc resonator gyroscope fabrication process requiring no bonding alignment

    NASA Technical Reports Server (NTRS)

    Shcheglov, Kirill V. (Inventor)

    2010-01-01

    A method of fabricating a resonant vibratory sensor, such as a disc resonator gyro. A silicon baseplate wafer for a disc resonator gyro is provided with one or more locating marks. The disc resonator gyro is fabricated by bonding a blank resonator wafer, such as an SOI wafer, to the fabricated baseplate, and fabricating the resonator structure according to a pattern based at least in part upon the location of the at least one locating mark of the fabricated baseplate. MEMS-based processing is used for the fabrication processing. In some embodiments, the locating mark is visualized using optical and/or infrared viewing methods. A disc resonator gyroscope manufactured according to these methods is described.

  8. Mask manufacturing of advanced technology designs using multi-beam lithography (Part 1)

    NASA Astrophysics Data System (ADS)

    Green, Michael; Ham, Young; Dillon, Brian; Kasprowicz, Bryan; Hur, Ik Boum; Park, Joong Hee; Choi, Yohan; McMurran, Jeff; Kamberian, Henry; Chalom, Daniel; Klikovits, Jan; Jurkovic, Michal; Hudek, Peter

    2016-10-01

    As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask manufacturers. Techniques including advanced Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the new challenges are continued shrinking Sub-Resolution Assist Features (SRAFs), curvilinear SRAFs, and other complex mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible solutions to these coming challenges. In this paper, we study one such process, characterizing mask manufacturing capability of 10nm and below structures with particular focus on minimum resolution and pattern fidelity.

  9. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  10. A 45° saw-dicing process applied to a glass substrate for wafer-level optical splitter fabrication for optical coherence tomography

    NASA Astrophysics Data System (ADS)

    Maciel, M. J.; Costa, C. G.; Silva, M. F.; Gonçalves, S. B.; Peixoto, A. C.; Ribeiro, A. Fernando; Wolffenbuttel, R. F.; Correia, J. H.

    2016-08-01

    This paper reports on the development of a technology for the wafer-level fabrication of an optical Michelson interferometer, which is an essential component in a micro opto-electromechanical system (MOEMS) for a miniaturized optical coherence tomography (OCT) system. The MOEMS consists on a titanium dioxide/silicon dioxide dielectric beam splitter and chromium/gold micro-mirrors. These optical components are deposited on 45° tilted surfaces to allow the horizontal/vertical separation of the incident beam in the final micro-integrated system. The fabrication process consists of 45° saw dicing of a glass substrate and the subsequent deposition of dielectric multilayers and metal layers. The 45° saw dicing is fully characterized in this paper, which also includes an analysis of the roughness. The optimum process results in surfaces with a roughness of 19.76 nm (rms). The actual saw dicing process for a high-quality final surface results as a compromise between the dicing blade’s grit size (#1200) and the cutting speed (0.3 mm s-1). The proposed wafer-level fabrication allows rapid and low-cost processing, high compactness and the possibility of wafer-level alignment/assembly with other optical micro components for OCT integrated imaging.

  11. Manufacturing Process Simulation of Large-Scale Cryotanks

    NASA Technical Reports Server (NTRS)

    Babai, Majid; Phillips, Steven; Griffin, Brian

    2003-01-01

    NASA's Space Launch Initiative (SLI) is an effort to research and develop the technologies needed to build a second-generation reusable launch vehicle. It is required that this new launch vehicle be 100 times safer and 10 times cheaper to operate than current launch vehicles. Part of the SLI includes the development of reusable composite and metallic cryotanks. The size of these reusable tanks is far greater than anything ever developed and exceeds the design limits of current manufacturing tools. Several design and manufacturing approaches have been formulated, but many factors must be weighed during the selection process. Among these factors are tooling reachability, cycle times, feasibility, and facility impacts. The manufacturing process simulation capabilities available at NASA.s Marshall Space Flight Center have played a key role in down selecting between the various manufacturing approaches. By creating 3-D manufacturing process simulations, the varying approaches can be analyzed in a virtual world before any hardware or infrastructure is built. This analysis can detect and eliminate costly flaws in the various manufacturing approaches. The simulations check for collisions between devices, verify that design limits on joints are not exceeded, and provide cycle times which aide in the development of an optimized process flow. In addition, new ideas and concerns are often raised after seeing the visual representation of a manufacturing process flow. The output of the manufacturing process simulations allows for cost and safety comparisons to be performed between the various manufacturing approaches. This output helps determine which manufacturing process options reach the safety and cost goals of the SLI. As part of the SLI, The Boeing Company was awarded a basic period contract to research and propose options for both a metallic and a composite cryotank. Boeing then entered into a task agreement with the Marshall Space Flight Center to provide manufacturing

  12. Advanced manufacturing rules check (MRC) for fully automated assessment of complex reticle designs

    NASA Astrophysics Data System (ADS)

    Gladhill, R.; Aguilar, D.; Buck, P. D.; Dawkins, D.; Nolke, S.; Riddick, J.; Straub, J. A.

    2005-11-01

    Advanced electronic design automation (EDA) tools, with their simulation, modeling, design rule checking, and optical proximity correction capabilities, have facilitated the improvement of first pass wafer yields. While the data produced by these tools may have been processed for optimal wafer manufacturing, it is possible for the same data to be far from ideal for photomask manufacturing, particularly at lithography and inspection stages, resulting in production delays and increased costs. The same EDA tools used to produce the data can be used to detect potential problems for photomask manufacturing in the data. A production implementation of automated photomask manufacturing rule checking (MRC) is presented and discussed for various photomask lithography and inspection lines. This paper will focus on identifying data which may cause production delays at the mask inspection stage. It will be shown how photomask MRC can be used to discover data related problems prior to inspection, separating jobs which are likely to have problems at inspection from those which are not. Photomask MRC can also be used to identify geometries requiring adjustment of inspection parameters for optimal inspection, and to assist with any special handling or change of routing requirements. With this foreknowledge, steps can be taken to avoid production delays that increase manufacturing costs. Finally, the data flow implemented for MRC can be used as a platform for other photomask data preparation tasks.

  13. Current manufacturing processes of drug-eluting sutures.

    PubMed

    Champeau, Mathilde; Thomassin, Jean-Michel; Tassaing, Thierry; Jérôme, Christine

    2017-11-01

    Drug-eluting sutures represent the next generation of surgical sutures since they fulfill their mechanical functions but also deliver the drug in their vicinity after implantation. These implants are produced by a variety of manufacturing processes. Drug-eluting sutures represent the next generation of surgical sutures since they fulfill their mechanical functions but also deliver the drug in their vicinity after implantation. These implants are produced by a variety of manufacturing processes. Two general approaches can be followed: (i) the ones that add the API into the material during the manufacturing process of the suture and (ii) the ones that load the API to an already manufactured suture. Areas covered: This review provides an overview of the current manufacturing processes for drug-eluting suture production and discusses their benefits and drawbacks depending on the type of drugs. The mechanical properties and the drug delivery profile of drug-eluting sutures are highlighted since these implants must fulfill both criteria. Expert opinion: For limited drug contents, melt extrusion and electrospinning are the emerging processes since the drug is added during the suture manufacture process. Advantageously, the drug release profile can be tuned by controlling the processing parameters specific to each process and the composition of the drug-containing polymer. If high drug content is targeted, the coating or grafting of a drug layer on a pre-manufactured suture allows for preservation of the tensile strength requirements of the suture.

  14. New getter configuration at wafer level for assuring long term stability of MEMs

    NASA Astrophysics Data System (ADS)

    Moraja, Marco; Amiotti, Marco; Kullberg, Richard C.

    2003-01-01

    The evolution from ceramic packages to wafer to wafer hermetic sealing poses tremendous technical challenges to integrate a proper getter inside the MEMs to assure a long term stability and reliability of the devices. The state of the art solution to integrate a getter inside the MEMs of the last generation consists in patterning the getter material with a specific geometry onto the Si cap wafer. The practical implementation of this solution consists in a 4" or 6" Si wafers with grooves or particular incisures, where the getter material is placed in form of a thick film. The typical thickness of these thick films is in the range of few microns, depending on the gas load to be handled during the lifetime of the device. The structure of the thick getter film is highly porous in order to improve sorption performances, but at the same time there are no loose particles thanks to a proprietary manufacturing method. The getter thick film is composed of a Zr special alloy with a proper composition to optimize the sorption performances. The getter thick film can be placed selectively into grooves without affecting the lateral regions, surrounding the grooves where the hermetic sealing is performed.

  15. CD and defect improvement challenges for immersion processes

    NASA Astrophysics Data System (ADS)

    Ehara, Keisuke; Ema, Tatsuhiko; Yamasaki, Toshinari; Nakagawa, Seiji; Ishitani, Seiji; Morita, Akihiko; Kim, Jeonghun; Kanaoka, Masashi; Yasuda, Shuichi; Asai, Masaya

    2009-03-01

    The intention of this study is to develop an immersion lithography process using advanced track solutions to achieve world class critical dimension (CD) and defectivity performance in a state of the art manufacturing facility. This study looks at three important topics for immersion lithography: defectivity, CD control, and wafer backside contamination. The topic of defectivity is addressed through optimization of coat, develop, and rinse processes as well as implementation of soak steps and bevel cleaning as part of a comprehensive defect solution. Develop and rinse processing techniques are especially important in the effort to achieve a zero defect solution. Improved CD control is achieved using a biased hot plate (BHP) equipped with an electrostatic chuck. This electrostatic chuck BHP (eBHP) is not only able to operate at a very uniform temperature, but it also allows the user to bias the post exposure bake (PEB) temperature profile to compensate for systematic within-wafer (WiW) CD non-uniformities. Optimized CD results, pre and post etch, are presented for production wafers. Wafer backside particles can cause focus spots on an individual wafer or migrate to the exposure tool's wafer stage and cause problems for a multitude of wafers. A basic evaluation of the cleaning efficiency of a backside scrubber unit located on the track was performed as a precursor to a future study examining the impact of wafer backside condition on scanner focus errors as well as defectivity in an immersion scanner.

  16. Massively parallel E-beam inspection: enabling next-generation patterned defect inspection for wafer and mask manufacturing

    NASA Astrophysics Data System (ADS)

    Malloy, Matt; Thiel, Brad; Bunday, Benjamin D.; Wurm, Stefan; Mukhtar, Maseeh; Quoi, Kathy; Kemen, Thomas; Zeidler, Dirk; Eberle, Anna Lena; Garbowski, Tomasz; Dellemann, Gregor; Peters, Jan Hendrik

    2015-03-01

    SEMATECH aims to identify and enable disruptive technologies to meet the ever-increasing demands of semiconductor high volume manufacturing (HVM). As such, a program was initiated in 2012 focused on high-speed e-beam defect inspection as a complement, and eventual successor, to bright field optical patterned defect inspection [1]. The primary goal is to enable a new technology to overcome the key gaps that are limiting modern day inspection in the fab; primarily, throughput and sensitivity to detect ultra-small critical defects. The program specifically targets revolutionary solutions based on massively parallel e-beam technologies, as opposed to incremental improvements to existing e-beam and optical inspection platforms. Wafer inspection is the primary target, but attention is also being paid to next generation mask inspection. During the first phase of the multi-year program multiple technologies were reviewed, a down-selection was made to the top candidates, and evaluations began on proof of concept systems. A champion technology has been selected and as of late 2014 the program has begun to move into the core technology maturation phase in order to enable eventual commercialization of an HVM system. Performance data from early proof of concept systems will be shown along with roadmaps to achieving HVM performance. SEMATECH's vision for moving from early-stage development to commercialization will be shown, including plans for development with industry leading technology providers.

  17. Development of a plan for automating integrated circuit processing

    NASA Technical Reports Server (NTRS)

    1971-01-01

    The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

  18. Automotive Manufacturing Processes. Volume II - Manufacturing Processes for Passive Restraint Systems

    DOT National Transportation Integrated Search

    1981-02-01

    Extensive material substitution and resizing of the domestic automotive fleet, as well as the introduction of new technologies, will require major changes in the techniques and equipment used in the various manufacturing processes employed in the pro...

  19. Wafer characteristics via reflectometry

    DOEpatents

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  20. Epitaxial gallium arsenide wafers

    NASA Technical Reports Server (NTRS)

    Black, J. F.; Robinson, L. B.

    1971-01-01

    The preparation of GaAs epitaxial layers by a vapor transport process using AsCl3, Ga and H2 was pursued to provide epitaxial wafers suitable for the fabrication of transferred electron oscillators and amplifiers operating in the subcritical region. Both n-n(+) structures, and n(++)-n-n(+) sandwich structures were grown using n(+) (Si-doped) GaAs substrates. Process variables such as the input AsCl3 concentration, gallium temperature, and substrate temperature and temperature gradient and their effects on properties are presented and discussed.

  1. Mask manufacturing of advanced technology designs using multi-beam lithography (part 2)

    NASA Astrophysics Data System (ADS)

    Green, Michael; Ham, Young; Dillon, Brian; Kasprowicz, Bryan; Hur, Ik Boum; Park, Joong Hee; Choi, Yohan; McMurran, Jeff; Kamberian, Henry; Chalom, Daniel; Klikovits, Jan; Jurkovic, Michal; Hudek, Peter

    2016-09-01

    As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask manufacturers. Techniques including advanced optical proximity correction (OPC) and Inverse Lithography Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the new challenges are continued shrinking sub-resolution assist features (SRAFs), curvilinear SRAFs, and other complex mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible solutions to these coming challenges. In this paper, Part 2 of our study, we further characterize an MBMW process for 10nm and below logic node mask manufacturing including advanced pattern analysis and write time demonstration.

  2. Wafer scale oblique angle plasma etching

    DOEpatents

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  3. Encapsulation Processing and Manufacturing Yield Analysis

    NASA Technical Reports Server (NTRS)

    Willis, P. B.

    1984-01-01

    The development of encapsulation processing and a manufacturing productivity analysis for photovoltaic cells are discussed. The goals were: (1) to understand the relationships between both formulation variables and process variables; (2) to define conditions required for optimum performance; (3) to predict manufacturing yield; and (4) to provide documentation to industry.

  4. Encapsulation processing and manufacturing yield analysis

    NASA Astrophysics Data System (ADS)

    Willis, P. B.

    1984-10-01

    The development of encapsulation processing and a manufacturing productivity analysis for photovoltaic cells are discussed. The goals were: (1) to understand the relationships between both formulation variables and process variables; (2) to define conditions required for optimum performance; (3) to predict manufacturing yield; and (4) to provide documentation to industry.

  5. A two layer hermetic-like coating process for on-wafer encapsulation of GaAs MMIC`s

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Kaleta, T.; Varmazis, C.; Carney, J.P.

    1995-12-31

    The authors have developed a low-cost, manufacturable, 2-layer coating process for on-wafer encapsulation of GaAs MMICs. This packaging approach takes advantage of the low dielectric permittivity of polymers such as Benzocyclobutene (BCB) and the sealing properties of ceramics such as SiC to provide both mechanical protection to MMICs during handling and also hermetic-like equivalence to moisture with predictable changes in the electrical performance of the coated MMICs. The effects of coatings on FET parameters, spiral inductors and a two stage X-Band LNA have been investigated. Results on FETs indicate that the internode capacitances Cgs and Cgd exhibited the same incrementalmore » change of 0.035 pF/mm (3 and 25 % increase respectively), while Cds changed by 0.051 pF/mm (27% increase) with very minimal changes in the other FET parameters. The only observed change in spiral inductors was a 112% increase in Cp from 0.006 pF to 0.013 pF. The LNA exhibited a 1 GHz shift in frequency response from 7 to 11 GHz to 6 to 11 GHz with no substantial changes in gain and noise figure. Preliminary reliability investigations on coated devices did not show any failures after 150 hours in autoclave (120C, 100% humidity).« less

  6. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Powell, J. Anthony (Inventor)

    1991-01-01

    This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  7. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

    1992-01-01

    A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  8. Particle detection for patterned wafers of 100nm design rule by evanescent light illumination: analysis of evanescent light scattering using Finite-Difference Time-Domain (FDTD) method

    NASA Astrophysics Data System (ADS)

    Yoshioka, Toshie; Miyoshi, Takashi; Takaya, Yasuhiro

    2005-12-01

    To realize high productivity and reliability of the semiconductor, patterned wafers inspection technology to maintain high yield becomes essential in modern semiconductor manufacturing processes. As circuit feature is scaled below 100nm, the conventional imaging and light scattering methods are impossible to apply to the patterned wafers inspection technique, because of diffraction limit and lower S/N ratio. So, we propose a new particle detection method using annular evanescent light illumination. In this method, a converging annular light used as a light source is incident on a micro-hemispherical lens. When the converging angle is larger than critical angle, annular evanescent light is generated under the bottom surface of the hemispherical lens. Evanescent light is localized near by the bottom surface and decays exponentially away from the bottom surface. So, the evanescent light selectively illuminates the particles on the patterned wafer surface, because it can't illuminate the patterned wafer surface. The proposed method evaluates particles on a patterned wafer surface by detecting scattered evanescent light distribution from particles. To analyze the fundamental characteristics of the proposed method, the computer simulation was performed using FDTD method. The simulation results show that the proposed method is effective for detecting 100nm size particle on patterned wafer of 100nm lines and spaces, particularly under the condition that the evanescent light illumination with p-polarization and parallel incident to the line orientation. Finally, the experiment results suggest that 220nm size particle on patterned wafer of about 200nm lines and spaces can be detected.

  9. Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

    PubMed

    Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

    2015-11-01

    Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. Copyright © 2015 Elsevier B.V. All rights reserved.

  10. Carbon dioxide capture using resin-wafer electrodeionization

    DOEpatents

    Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

    2015-09-08

    The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

  11. Process in manufacturing high efficiency AlGaAs/GaAs solar cells by MO-CVD

    NASA Technical Reports Server (NTRS)

    Yeh, Y. C. M.; Chang, K. I.; Tandon, J.

    1984-01-01

    Manufacturing technology for mass producing high efficiency GaAs solar cells is discussed. A progress using a high throughput MO-CVD reactor to produce high efficiency GaAs solar cells is discussed. Thickness and doping concentration uniformity of metal oxide chemical vapor deposition (MO-CVD) GaAs and AlGaAs layer growth are discussed. In addition, new tooling designs are given which increase the throughput of solar cell processing. To date, 2cm x 2cm AlGaAs/GaAs solar cells with efficiency up to 16.5% were produced. In order to meet throughput goals for mass producing GaAs solar cells, a large MO-CVD system (Cambridge Instrument Model MR-200) with a susceptor which was initially capable of processing 20 wafers (up to 75 mm diameter) during a single growth run was installed. In the MR-200, the sequencing of the gases and the heating power are controlled by a microprocessor-based programmable control console. Hence, operator errors can be reduced, leading to a more reproducible production sequence.

  12. Boosting Manufacturing through Modular Chemical Process Intensification

    ScienceCinema

    None

    2018-06-12

    Manufacturing USA's Rapid Advancement in Process Intensification Deployment Institute will focus on developing breakthrough technologies to boost domestic energy productivity and energy efficiency by 20 percent in five years through manufacturing processes.

  13. Boosting Manufacturing through Modular Chemical Process Intensification

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    None

    2016-12-09

    Manufacturing USA's Rapid Advancement in Process Intensification Deployment Institute will focus on developing breakthrough technologies to boost domestic energy productivity and energy efficiency by 20 percent in five years through manufacturing processes.

  14. A new approach to measure the temperature in rapid thermal processing

    NASA Astrophysics Data System (ADS)

    Yan, Jiang

    This dissertation has presented the research work about a new method to measure the temperatures for the silicon wafer. The new technology is mainly for the rapid thermal processing (RTP) system. RTP is a promising technology in semiconductor manufacturing especially for the devices with minimum feature size less than 0.5 μm. The technique to measure the temperatures of the silicon wafer accurately is the key factor to apply the RTP technology to more critical processes in the manufacturing. Two methods which are mostly used nowadays, thermocouples and pyrometer, all have the limitation to be applied in the RTP. This is the motivation to study the new method using acoustic waves for the temperature measurement. The test system was designed and built up for the study of the acoustic method. The whole system mainly includes the transducer unit, circuit hardware, control software, the computer, and the chamber. The acoustic wave was generated by the PZT-5H transducer. The wave travels through the quartz rod into the silicon wafer. After traveling a certain distances in the wafer, the acoustic waves could be received by other transducers. By measuring the travel time and with the travel distance, the velocity of the acoustic wave traveling in the silicon wafer can be calculated. Because there is a relationship between the velocity and the temperature: the velocities of the acoustic waves traveling in the silicon wafer decrease as the temperatures of the wafer increase, the temperature of the wafer can be finally obtained. The thermocouples were used to check the measurement accuracy of the acoustic method. The temperature mapping across the 8″ silicon wafer was obtained with four transducer sensor unit. The temperatures of the wafer were measured using acoustic method at both static and dynamic status. The main purpose of the tests is to know the measurement accuracy for the new method. The goal of the research work regarding to the accuracy is <=+/-3°C. The

  15. Process tool monitoring and matching using interferometry technique

    NASA Astrophysics Data System (ADS)

    Anberg, Doug; Owen, David M.; Mileham, Jeffrey; Lee, Byoung-Ho; Bouche, Eric

    2016-03-01

    The semiconductor industry makes dramatic device technology changes over short time periods. As the semiconductor industry advances towards to the 10 nm device node, more precise management and control of processing tools has become a significant manufacturing challenge. Some processes require multiple tool sets and some tools have multiple chambers for mass production. Tool and chamber matching has become a critical consideration for meeting today's manufacturing requirements. Additionally, process tools and chamber conditions have to be monitored to ensure uniform process performance across the tool and chamber fleet. There are many parameters for managing and monitoring tools and chambers. Particle defect monitoring is a well-known and established example where defect inspection tools can directly detect particles on the wafer surface. However, leading edge processes are driving the need to also monitor invisible defects, i.e. stress, contamination, etc., because some device failures cannot be directly correlated with traditional visualized defect maps or other known sources. Some failure maps show the same signatures as stress or contamination maps, which implies correlation to device performance or yield. In this paper we present process tool monitoring and matching using an interferometry technique. There are many types of interferometry techniques used for various process monitoring applications. We use a Coherent Gradient Sensing (CGS) interferometer which is self-referencing and enables high throughput measurements. Using this technique, we can quickly measure the topography of an entire wafer surface and obtain stress and displacement data from the topography measurement. For improved tool and chamber matching and reduced device failure, wafer stress measurements can be implemented as a regular tool or chamber monitoring test for either unpatterned or patterned wafers as a good criteria for improved process stability.

  16. Methane production using resin-wafer electrodeionization

    DOEpatents

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  17. Enhanced capture rate for haze defects in production wafer inspection

    NASA Astrophysics Data System (ADS)

    Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

    2010-03-01

    Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure

  18. ILT based defect simulation of inspection images accurately predicts mask defect printability on wafer

    NASA Astrophysics Data System (ADS)

    Deep, Prakash; Paninjath, Sankaranarayanan; Pereira, Mark; Buck, Peter

    2016-05-01

    At advanced technology nodes mask complexity has been increased because of large-scale use of resolution enhancement technologies (RET) which includes Optical Proximity Correction (OPC), Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO). The number of defects detected during inspection of such mask increased drastically and differentiation of critical and non-critical defects are more challenging, complex and time consuming. Because of significant defectivity of EUVL masks and non-availability of actinic inspection, it is important and also challenging to predict the criticality of defects for printability on wafer. This is one of the significant barriers for the adoption of EUVL for semiconductor manufacturing. Techniques to decide criticality of defects from images captured using non actinic inspection images is desired till actinic inspection is not available. High resolution inspection of photomask images detects many defects which are used for process and mask qualification. Repairing all defects is not practical and probably not required, however it's imperative to know which defects are severe enough to impact wafer before repair. Additionally, wafer printability check is always desired after repairing a defect. AIMSTM review is the industry standard for this, however doing AIMSTM review for all defects is expensive and very time consuming. Fast, accurate and an economical mechanism is desired which can predict defect printability on wafer accurately and quickly from images captured using high resolution inspection machine. Predicting defect printability from such images is challenging due to the fact that the high resolution images do not correlate with actual mask contours. The challenge is increased due to use of different optical condition during inspection other than actual scanner condition, and defects found in such images do not have correlation with actual impact on wafer. Our automated defect simulation tool predicts

  19. Optimal mask characterization by Surrogate Wafer Print (SWaP) method

    NASA Astrophysics Data System (ADS)

    Kimmel, Kurt R.; Hoellein, Ingo; Peters, Jan Hendrick; Ackmann, Paul; Connolly, Brid; West, Craig

    2008-10-01

    Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask relative to the specifications is done completely by the mask maker. As the challenges of low-k1 imaging continue to grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers' continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore, improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent and compelling. The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images, rather than the mask's physical attributes, as a technically superior and lower-cost method to characterize a mask. The idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for traditional mask inspections and measurements represents the ultimate method to characterize a mask's performance, which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab mask qualification to validate defect and dimensional performance. In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of SWaP for the characterization of defects as an alternative to traditional mask inspection [1]. It showed that this concept is not only feasible, but, in some cases, desirable. This paper expands on last year's work at AMTC to assess the full implementation of SWaP as an

  20. 21 CFR 1005.25 - Service of process on manufacturers.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Service of process on manufacturers. 1005.25....25 Service of process on manufacturers. (a) Every manufacturer of electronic products, prior to... United States as the manufacturer's agent upon whom service of all processes, notices, orders, decisions...

  1. SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

    NASA Astrophysics Data System (ADS)

    Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

    2016-10-01

    Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and

  2. Implementation of activity-based costing (ABC) to drive cost reduction efforts in a semiconductor manufacturing operation

    NASA Astrophysics Data System (ADS)

    Naguib, Hussein; Bol, Igor I.; Lora, J.; Chowdhry, R.

    1994-09-01

    This paper presents a case study on the implementation of ABC to calculate the cost per wafer and to drive cost reduction efforts for a new IC product line. The cost reduction activities were conducted through the efforts of 11 cross-functional teams which included members of the finance, purchasing, technology development, process engineering, equipment engineering, production control, and facility groups. The activities of these cross functional teams were coordinated by a cost council. It will be shown that these activities have resulted in a 57% reduction in the wafer manufacturing cost of the new product line. Factors contributed to successful implementation of an ABC management system are discussed.

  3. The future of automation for high-volume wafer fabrication and ASIC manufacturing

    NASA Astrophysics Data System (ADS)

    Hughes, Randall A.; Shott, John D.

    1986-12-01

    A framework is given to analyze the future trends in semiconductor manufacturing automation systems, focusing specifically on the needs of ASIC (application-specific integrated circuit) or custom integrated circuit manufacturing. Advances in technologies such as gate arrays and standard cells now make it significantly easier to obtain system cost and performance advantages by integrating nonstandard functions on silicon. ASICs are attractive to U.S. manufacturers because they place a premium on sophisticated design tools, familiarity with customer needs and applications, and fast turn-around fabrication. These are areas where U.S. manufacturers believe they have an advantage and, consequently, will not suffer from the severe price/manufacturing competition encountered in conventional high-volume semiconductor products. Previously, automation was often considered viable only for high-volume manufacturing, but automation becomes a necessity in the new ASIC environment.

  4. Reducing bottom anti-reflective coating (BARC) defects: optimizing and decoupling the filtration and dispense process

    NASA Astrophysics Data System (ADS)

    Brakensiek, Nickolas L.; Martin, Gary; Simmons, Sean; Batchelder, Traci

    2006-03-01

    Semiconductor device manufacturing is one of the cleanest manufacturing operations that can be found in the world today. It has to be that way; a particle on a wafer today can kill an entire device, which raises the costs, and therefore reduces the profits, of the manufacturing company in two ways: it must produce extra wafers to make up for the lost die, and it has less product to sell. In today's state-of-the-art fab, everything is filtered to the lowest pore size available. This practice is fairly easy for gases because a gas molecule is very small compared to the pore size of the filter. Filtering liquids, especially photochemicals such as photoresists and BARCs, can be much harder because the molecules that form the polymers used to manufacture the photochemicals are approaching the filter pore size. As a result, filters may plug up, filtration rates may drop, pressure drops across the filter may increase, or a filter may degrade. These conditions can then cause polymer shearing, microbubble formation, gel particle formation, and BARC chemical changes to occur before the BARC reaches the wafer. To investigate these possible interactions, an Entegris(R) IntelliGen(R) pump was installed on a TEL Mk8 TM track to see if the filtration process would have an effect on the BARC chemistry and coating defects. Various BARC chemicals such as DUV112 and DUV42P were pumped through various filter media having a variety of pore sizes at different filtration rates to investigate the interaction between the dispense process and the filtration process. The IntelliGen2 pump has the capability to filter the BARC independent of the dispense process. By using a designed experiment to look at various parameters such as dispense rate, filtration rate, and dispense volume, the effects of the complete pump system can be learned, and appropriate conditions can be applied to yield the cleanest BARC coating process. Results indicate that filtration rate and filter pore size play a

  5. Design process optimization, virtual prototyping of manufacturing, and foundry-portable DFM (Invited Paper)

    NASA Astrophysics Data System (ADS)

    Hogan, James; Progler, Christopher; Chatila, Ahmad; Bruggeman, Bert; Heins, Mitchell; Pack, Robert; Boksha, Victor

    2005-05-01

    We consider modern design for manufacturing (DFM) as a manifestation of IC industry re-integration and intensive cost management dynamics. In that regard DFM is somewhat different from so-called design for yield (DFY) which essentially focuses on productivity (yield) management (that is not to say that DFM and DFY do not have significant overlaps and interactions). We clearly see the shaping of a new "full-chip DFM" infrastructure on the background of the "back to basics" design-manufacturing re-integration dynamics. In the presented work we are focusing on required DFM-efficiencies in a "foundry-fabless" link. Concepts of "virtual prototyping of manufacturing", "design process optimization", and "foundry-portable DFM" models are explored. Both senior management of the industry and leading design groups finally realize the need for a radical change of design styles. Some of the DFM super-goals are to isolate designers from process details and to make designs foundry portable. It requires qualification of designs at different foundries. In their turn, foundries specified and are implementing a set of DFM rules: "action-required", "recommended", and "guidelines" while asking designers to provide netlist and testing information. Also, we observe strong signs of innovation coming back to the mask industry. Powerful solutions are emerging and shaping up toward mask-centered IP as a business. While it seems that pure-play foundries have found their place for now in the "IDM+" model (supporting manufacturing capacity of IDMs) it is not obvious how sustainable the model is. Wafer as a production unit is not sufficient anymore; foundries are being asked by large customers to price products in terms of good die. It brings back the notion of the old ASIC business model where the foundry is responsible for dealing with both random and systematic yield issues for a given design. One scenario of future development would be that some of the leading foundries might eventually

  6. NASA's In-Space Manufacturing Project: Materials and Manufacturing Process Development Update

    NASA Technical Reports Server (NTRS)

    Prater, Tracie; Bean, Quincy; Werkheiser, Niki; Ledbetter, Frank

    2017-01-01

    The mission of NASA's In-Space Manufacturing (ISM) project is to identify, design, and implement on-demand, sustainable manufacturing solutions for fabrication, maintenance and repair during exploration missions. ISM has undertaken a phased strategy of incrementally increasing manufacturing capabilities to achieve this goal. The ISM project began with the development of the first 3D printer for the International Space Station. To date, the printer has completed two phases of flight operations. Results from phase I specimens indicated some differences in material properties between ground-processed and ISS-processed specimens, but results of follow-on analyses of these parts and a ground-based study with an equivalent printer strongly indicate that this variability is likely attributable to differences in manufacturing process settings between the ground and flight prints rather than microgravity effects on the fused deposition modeling (FDM) process. Analysis of phase II specimens from the 3D Printing in Zero G tech demo, which shed further light on the sources of material variability, will be presented. The ISM project has also developed a materials characterization plan for the Additive Manufacturing Facility, the follow-on commercial multimaterial 3D printing facility developed for ISS by Made in Space. This work will yield a suite of characteristic property values that can inform use of AMF by space system designers. Other project activities include development of an integrated 3D printer and recycler, known as the Refabricator, by Tethers Unlimited, which will be operational on ISS in 2018. The project also recently issued a broad area announcement for a multimaterial fabrication laboratory, which may include in-space manufacturing capabilities for metals, electronics, and polymeric materials, to be deployed on ISS in the 2022 timeframe.

  7. Microeconomics of yield learning and process control in semiconductor manufacturing

    NASA Astrophysics Data System (ADS)

    Monahan, Kevin M.

    2003-06-01

    Simple microeconomic models that directly link yield learning to profitability in semiconductor manufacturing have been rare or non-existent. In this work, we review such a model and provide links to inspection capability and cost. Using a small number of input parameters, we explain current yield management practices in 200mm factories. The model is then used to extrapolate requirements for 300mm factories, including the impact of technology transitions to 130nm design rules and below. We show that the dramatic increase in value per wafer at the 300mm transition becomes a driver for increasing metrology and inspection capability and sampling. These analyses correlate well wtih actual factory data and often identify millions of dollars in potential cost savings. We demonstrate this using the example of grating-based overlay metrology for the 65nm node.

  8. Dissolution of Oxygen Precipitate Nuclei in n-Type CZ-Si Wafers to Improve Their Material Quality: Experimental Results

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Sopori, Bhushan; Basnyat, Prakash; Devayajanam, Srinivas

    2017-01-01

    We present experimental results which show that oxygen-related precipitate nuclei (OPN) present in p-doped, n-type, Czochralski wafers can be dissolved using a flash-annealing process, yielding very high quality wafers for high-efficiency solar cells. Flash annealing consists of heating a wafer in an optical furnace to temperature between 1150 and 1250 degrees C for a short time. This process produces a large increase in the minority carrier lifetime (MCLT) and homogenizes each wafer. We have tested wafers from different axial locations of two ingots. All wafers reach nearly the same high value of MCLT. The OPN dissolution is confirmed by oxygenmore » analysis using Fourier transform infrared spectra and injection-level dependence of MCLT.« less

  9. ROI on yield data analysis systems through a business process management strategy

    NASA Astrophysics Data System (ADS)

    Rehani, Manu; Strader, Nathan; Hanson, Jeff

    2005-05-01

    The overriding motivation for yield engineering is profitability. This is achieved through application of yield management. The first application is to continually reduce waste in the form of yield loss. New products, new technologies and the dynamic state of the process and equipment keep introducing new ways to cause yield loss. In response, the yield management efforts have to continually come up with new solutions to minimize it. The second application of yield engineering is to aid in accurate product pricing. This is achieved through predicting future results of the yield engineering effort. The more accurate the yield prediction, the more accurate the wafer start volume, the more accurate the wafer pricing. Another aspect of yield prediction pertains to gauging the impact of a yield problem and predicting how long that will last. The ability to predict such impacts again feeds into wafer start calculations and wafer pricing. The question then is that if the stakes on yield management are so high why is it that most yield management efforts are run like science and engineering projects and less like manufacturing? In the eighties manufacturing put the theory of constraints1 into practice and put a premium on stability and predictability in manufacturing activities, why can't the same be done for yield management activities? This line of introspection led us to define and implement a business process to manage the yield engineering activities. We analyzed the best known methods (BKM) and deployed a workflow tool to make them the standard operating procedure (SOP) for yield managment. We present a case study in deploying a Business Process Management solution for Semiconductor Yield Engineering in a high-mix ASIC environment. We will present a description of the situation prior to deployment, a window into the development process and a valuation of the benefits.

  10. National Manufacturing Strategy: Is a National Manufacturing Strategy Essential to National Security?

    DTIC Science & Technology

    2011-05-01

    cycle found nearly a quarter of all homeowners owning more than their home was worth. 11 Both Paul Volcker and Warren Buffet arrived at similar...November 15, 2010; Warren Buffet , Testimony, Financial Crisis Inquiry Commission, June 2, 2010; “Subprime Mortgage Crisis,” http://en.wikipedia.org...overseas manufacturing. Case Study: Semiconductor Wafer Industry. The history of the semiconductor industry is an instructive account . It begins with

  11. Etching Selectivity of Cr, Fe and Ni Masks on Si & SiO2 Wafers

    NASA Astrophysics Data System (ADS)

    Garcia, Jorge; Lowndes, Douglas H.

    2000-10-01

    During this Summer 2000 I joined the Semiconductors and Thin Films group led by Dr. Douglas H. Lowndes at Oak Ridge National Laboratory’s Solid State Division. Our objective was to evaluate the selectivity that Trifluoromethane (CHF3), and Sulfur Hexafluoride (SF6) plasmas have for Si, SiO2 wafers and the Ni, Cr, and Fe masks; being this etching selectivity the ratio of the etching rates of the plasmas for each of the materials. We made use of Silicon and Silicon Dioxide-coated wafers that have Fe, Cr or Ni masks. In the semiconductor field, metal layers are often used as masks to protect layers underneath during processing steps; when these wafers are taken to the dry etching process, both the wafer and the mask layers’ thickness are reduced.

  12. Temperature Dependent Electrical Properties of PZT Wafer

    NASA Astrophysics Data System (ADS)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  13. Porous solid ion exchange wafer for immobilizing biomolecules

    DOEpatents

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  14. Manufacturing process applications team (MATeam)

    NASA Technical Reports Server (NTRS)

    Bangs, E. R.; Meyer, J. D.

    1978-01-01

    Activities of the manufacturing applications team (MATeam) in effecting widespread transfer of NASA technology to aid in the solution of manufacturing problems in the industrial sector are described. During the program's first year of operation, 450 companies, industry associations, and government agencies were contacted, 150 manufacturing problems were documented, and 20 potential technology transfers were identified. Although none of the technology transfers has been commercialized and put in use, several are in the applications engineering phase, and others are in the early stages of implementation. The technology transfer process is described and guidelines used for the preparation of problems statements are included.

  15. Automated manufacturing process for DEAP stack-actuators

    NASA Astrophysics Data System (ADS)

    Tepel, Dominik; Hoffstadt, Thorben; Maas, Jürgen

    2014-03-01

    Dielectric elastomers (DE) are thin polymer films belonging to the class of electroactive polymers (EAP), which are coated with compliant and conductive electrodes on each side. Due to the influence of an electrical field, dielectric elastomers perform a large amount of deformation. In this contribution a manufacturing process of automated fabricated stack-actuators based on dielectric electroactive polymers (DEAP) are presented. First of all the specific design of the considered stack-actuator is explained and afterwards the development, construction and realization of an automated manufacturing process is presented in detail. By applying this automated process, stack-actuators with reproducible and homogeneous properties can be manufactured. Finally, first DEAP actuator modules fabricated by the mentioned process are validated experimentally.

  16. Energetic additive manufacturing process with feed wire

    DOEpatents

    Harwell, Lane D.; Griffith, Michelle L.; Greene, Donald L.; Pressly, Gary A.

    2000-11-07

    A process for additive manufacture by energetic wire deposition is described. A source wire is fed into a energy beam generated melt-pool on a growth surface as the melt-pool moves over the growth surface. This process enables the rapid prototyping and manufacture of fully dense, near-net shape components, as well as cladding and welding processes. Alloys, graded materials, and other inhomogeneous materials can be grown using this process.

  17. Contacting graphene in a 200 mm wafer silicon technology environment

    NASA Astrophysics Data System (ADS)

    Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

    2018-06-01

    Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

  18. Manufacturing Process Selection of Composite Bicycle’s Crank Arm using Analytical Hierarchy Process (AHP)

    NASA Astrophysics Data System (ADS)

    Luqman, M.; Rosli, M. U.; Khor, C. Y.; Zambree, Shayfull; Jahidi, H.

    2018-03-01

    Crank arm is one of the important parts in a bicycle that is an expensive product due to the high cost of material and production process. This research is aimed to investigate the potential type of manufacturing process to fabricate composite bicycle crank arm and to describe an approach based on analytical hierarchy process (AHP) that assists decision makers or manufacturing engineers in determining the most suitable process to be employed in manufacturing of composite bicycle crank arm at the early stage of the product development process to reduce the production cost. There are four types of processes were considered, namely resin transfer molding (RTM), compression molding (CM), vacuum bag molding and filament winding (FW). The analysis ranks these four types of process for its suitability in the manufacturing of bicycle crank arm based on five main selection factors and 10 sub factors. Determining the right manufacturing process was performed based on AHP process steps. Consistency test was performed to make sure the judgements are consistent during the comparison. The results indicated that the compression molding was the most appropriate manufacturing process because it has the highest value (33.6%) among the other manufacturing processes.

  19. Wafer level reliability for high-performance VLSI design

    NASA Technical Reports Server (NTRS)

    Root, Bryan J.; Seefeldt, James D.

    1987-01-01

    As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

  20. 31 CFR 500.412 - Process vs. manufacture.

    Code of Federal Regulations, 2010 CFR

    2010-07-01

    ... 31 Money and Finance: Treasury 3 2010-07-01 2010-07-01 false Process vs. manufacture. 500.412... OF FOREIGN ASSETS CONTROL, DEPARTMENT OF THE TREASURY FOREIGN ASSETS CONTROL REGULATIONS Interpretations § 500.412 Process vs. manufacture. A commodity subject to § 500.204 remains subject howsoever it...

  1. Control wafer bow of InGaP on 200 mm Si by strain engineering

    NASA Astrophysics Data System (ADS)

    Wang, Bing; Bao, Shuyu; Made, Riko I.; Lee, Kwang Hong; Wang, Cong; Eng Kian Lee, Kenneth; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-12-01

    When epitaxially growing III-V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III-V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III-V semiconductors on large size Si substrates.

  2. Towards automatic planning for manufacturing generative processes

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    CALTON,TERRI L.

    2000-05-24

    Generative process planning describes methods process engineers use to modify manufacturing/process plans after designs are complete. A completed design may be the result from the introduction of a new product based on an old design, an assembly upgrade, or modified product designs used for a family of similar products. An engineer designs an assembly and then creates plans capturing manufacturing processes, including assembly sequences, component joining methods, part costs, labor costs, etc. When new products originate as a result of an upgrade, component geometry may change, and/or additional components and subassemblies may be added to or are omitted from themore » original design. As a result process engineers are forced to create new plans. This is further complicated by the fact that the process engineer is forced to manually generate these plans for each product upgrade. To generate new assembly plans for product upgrades, engineers must manually re-specify the manufacturing plan selection criteria and re-run the planners. To remedy this problem, special-purpose assembly planning algorithms have been developed to automatically recognize design modifications and automatically apply previously defined manufacturing plan selection criteria and constraints.« less

  3. Nanoscale x-ray imaging of circuit features without wafer etching

    NASA Astrophysics Data System (ADS)

    Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S. G.; Peterka, Tom; Levi, Anthony J. F.; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

    2017-03-01

    Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20-40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300 -μ m -thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240 -μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.

  4. Nanoscale x-ray imaging of circuit features without wafer etching.

    PubMed

    Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S G; Peterka, Tom; Levi, Anthony J F; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

    2017-03-01

    Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules, ideally in a non-destructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions, or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits, with past work delivering 20-40 nm resolution on thinned ICs. We describe a simple model for estimating the required exposure, and use it to estimate the future potential for this technique. Here we show for the first time that this approach can be used to image circuit detail through an unprocessed 300 μ m thick silicon wafer, with sub-20 nm detail clearly resolved after mechanical polishing to 240 μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire non-etched ICs to be imaged to 10 nm resolution or better while maintaining their ability to function in electrical tests.

  5. Nanoscale x-ray imaging of circuit features without wafer etching

    DOE PAGES

    Deng, Junjing; Hong, Young Pyo; Chen, Si; ...

    2017-03-24

    Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses hasmore » not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20–40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300-μm-thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240-μm thickness was used to eliminate image contrast caused by Si wafer surface scratches. Here, by using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.« less

  6. Characterization of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  7. Autonomous Agents for Dynamic Process Planning in the Flexible Manufacturing System

    NASA Astrophysics Data System (ADS)

    Nik Nejad, Hossein Tehrani; Sugimura, Nobuhiro; Iwamura, Koji; Tanimizu, Yoshitaka

    Rapid changes of market demands and pressures of competition require manufacturers to maintain highly flexible manufacturing systems to cope with a complex manufacturing environment. This paper deals with development of an agent-based architecture of dynamic systems for incremental process planning in the manufacturing systems. In consideration of alternative manufacturing processes and machine tools, the process plans and the schedules of the manufacturing resources are generated incrementally and dynamically. A negotiation protocol is discussed, in this paper, to generate suitable process plans for the target products real-timely and dynamically, based on the alternative manufacturing processes. The alternative manufacturing processes are presented by the process plan networks discussed in the previous paper, and the suitable process plans are searched and generated to cope with both the dynamic changes of the product specifications and the disturbances of the manufacturing resources. We initiatively combine the heuristic search algorithms of the process plan networks with the negotiation protocols, in order to generate suitable process plans in the dynamic manufacturing environment.

  8. A risk-based auditing process for pharmaceutical manufacturers.

    PubMed

    Vargo, Susan; Dana, Bob; Rangavajhula, Vijaya; Rönninger, Stephan

    2014-01-01

    The purpose of this article is to share ideas on developing a risk-based model for the scheduling of audits (both internal and external). Audits are a key element of a manufacturer's quality system and provide an independent means of evaluating the manufacturer's or the supplier/vendor's compliance status. Suggestions for risk-based scheduling approaches are discussed in the article. Pharmaceutical manufacturers are required to establish and implement a quality system. The quality system is an organizational structure defining responsibilities, procedures, processes, and resources that the manufacturer has established to ensure quality throughout the manufacturing process. Audits are a component of the manufacturer's quality system and provide a systematic and an independent means of evaluating the manufacturer's overall quality system and compliance status. Audits are performed at defined intervals for a specified duration. The intention of the audit process is to focus on key areas within the quality system and may not cover all relevant areas during each audit. In this article, the authors provide suggestions for risk-based scheduling approaches to aid pharmaceutical manufacturers in identifying the key focus areas for an audit.

  9. A manufacturable process integration approach for graphene devices

    NASA Astrophysics Data System (ADS)

    Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

    2013-06-01

    In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

  10. Throughput increase by adjustment of the BARC drying time with coat track process

    NASA Astrophysics Data System (ADS)

    Brakensiek, Nickolas L.; Long, Ryan

    2005-05-01

    Throughput of a coater module within the coater track is related to the solvent evaporation rate from the material that is being coated. Evaporation rate is controlled by the spin dynamics of the wafer and airflow dynamics over the wafer. Balancing these effects is the key to achieving very uniform coatings across a flat unpatterned wafer. As today"s coat tracks are being pushed to higher throughputs to match the scanner, the coat module throughput must be increased as well. For chemical manufacturers the evaporation rate of the material depends on the solvent used. One measure of relative evaporation rates is to compare flash points of a solvent. The lower the flash point, the quicker the solvent will evaporate. It is possible to formulate products with these volatile solvents although at a price. Shipping and manufacturing a more flammable product increase chances of fire, thereby increasing insurance premiums. Also, the end user of these chemicals will have to take extra precautions in the fab and in storage of these more flammable chemicals. An alternative coat process is possible which would allow higher throughput in a distinct coat module without sacrificing safety. A tradeoff is required for this process, that being a more complicated coat process and a higher viscosity chemical. The coat process uses the fact that evaporation rate depends on the spin dynamics of the wafer by utilizing a series of spin speeds that first would set the thickness of the material followed by a high spin speed to remove the residual solvent. This new process can yield a throughput of over 150 wafers per hour (wph) given two coat modules. The thickness uniformity of less than 2 nm (3 sigma) is still excellent, while drying times are shorter than 10 seconds to achieve the 150 wph throughput targets.

  11. High frequency guided wave propagation in monocrystalline silicon wafers

    NASA Astrophysics Data System (ADS)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2017-04-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

  12. P/N InP solar cells on Ge wafers

    NASA Technical Reports Server (NTRS)

    Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

    1994-01-01

    Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented

  13. 15 CFR 400.33 - Restrictions on manufacturing and processing activity.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ...-TRADE ZONES BOARD Manufacturing and Processing Activity-Reviews § 400.33 Restrictions on manufacturing and processing activity. (a) In general. In approving manufacturing or processing activity for a zone... 15 Commerce and Foreign Trade 2 2010-01-01 2010-01-01 false Restrictions on manufacturing and...

  14. Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

    NASA Astrophysics Data System (ADS)

    Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

    2015-02-01

    The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

  15. Analysis and evaluation in the production process and equipment area of the low-cost solar array project

    NASA Technical Reports Server (NTRS)

    Goldman, H.; Wolf, M.

    1979-01-01

    The energy consumed in manufacturing silicon solar cell modules was calculated for the current process, as well as for 1982 and 1986 projected processes. In addition, energy payback times for the above three sequences are shown. The module manufacturing energy was partitioned two ways. In one way, the silicon reduction, silicon purification, sheet formation, cell fabrication, and encapsulation energies were found. In addition, the facility, equipment, processing material and direct material lost-in-process energies were appropriated in junction formation processes and full module manufacturing sequences. A brief methodology accounting for the energy of silicon wafers lost-in-processing during cell manufacturing is described.

  16. Comparison of line shortening assessed by aerial image and wafer measurements

    NASA Astrophysics Data System (ADS)

    Ziegler, Wolfram; Pforr, Rainer; Thiele, Joerg; Maurer, Wilhelm

    1997-02-01

    Increasing number of patterns per area and decreasing linewidth demand enhancement technologies for optical lithography. OPC, the correction of systematic non-linearity in the pattern transfer process by correction of design data is one possibility to tighten process control and to increase the lifetime of existing lithographic equipment. The two most prominent proximity effects to be corrected by OPC are CD variation and line shortening. Line shortening measured on a wafer is up to 2 times larger than full resist simulation results. Therefore, the influence of mask geometry to line shortening is a key item to parameterize lithography. The following paper discusses the effect of adding small serifs to line ends with 0.25 micrometer ground-rule design. For reticles produced on an ALTA 3000 with standard wet etch process, the corner rounding on them mask can be reduced by adding serifs of a certain size. The corner rounding was measured and the effect on line shortening on the wafer is determined. This was investigated by resist measurements on wafer, aerial image plus resist simulation and aerial image measurements on the AIMS microscope.

  17. An all-silicon single-wafer micro-g accelerometer with a combined surface and bulk micromachining process

    NASA Technical Reports Server (NTRS)

    Yazdi, N.; Najafi, K.

    2000-01-01

    This paper reports an all-silicon fully symmetrical z-axis micro-g accelerometer that is fabricated on a single-silicon wafer using a combined surface and bulk fabrication process. The microaccelerometer has high device sensitivity, low noise, and low/controllable damping that are the key factors for attaining micro g and sub-micro g resolution in capacitive accelerometers. The microfabrication process produces a large proof mass by using the whole wafer thickness and a large sense capacitance by utilizing a thin sacrificial layer. The sense/feedback electrodes are formed by a deposited 2-3 microns polysilicon film with embedded 25-35 microns-thick vertical stiffeners. These electrodes, while thin, are made very stiff by the thick embedded stiffeners so that force rebalancing of the proof mass becomes possible. The polysilicon electrodes are patterned to create damping holes. The microaccelerometers are batch-fabricated, packaged, and tested successfully. A device with a 2-mm x 1-mm proof mass and a full bridge support has a measured sensitivity of 2 pF/g. The measured sensitivity of a 4-mm x 1-mm accelerometer with a cantilever support is 19.4 pF/g. The calculated noise floor of these devices at atmosphere are 0.23 micro g/sqrt(Hz) and 0.16 micro g/sqrt(Hz), respectively.

  18. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y.; James, Ralph B.

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  19. Silicon wafer temperature monitoring using all-fiber laser ultrasonics

    NASA Astrophysics Data System (ADS)

    Alcoz, Jorge J.; Duffer, Charles E.

    1998-03-01

    Laser-ultrasonics is a very attractive technique for in-line process control in the semiconductor industry as it is compatible with the clean room environment and offers the capability to inspect parts at high-temperature. We describe measurements of the velocity of laser-generated Lamb waves in silicon wafers as a function of temperature using fiber- optic laser delivery and all-fiber interferometric sensing. Fundamental anti-symmetric Lamb-wave modes were generated in 5 inches < 111 > silicon wafers using a Nd:YAG laser coupled to a large-core multimode fiber. Generation was also performed using an array of sources created with a diffraction grating. For detection a compact fiber-optic sensor was used which is well suited for industrial environments as it is compact, rugged, stable, and low-cost. The wafers were heated up to 1000 degrees C and the temperature correlated with ultrasonic velocity measurements.

  20. Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

    NASA Astrophysics Data System (ADS)

    Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

    2005-01-01

    Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

  1. Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

    NASA Astrophysics Data System (ADS)

    Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

    2004-12-01

    Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

  2. Cleaning Process Development for Metallic Additively Manufactured Parts

    NASA Technical Reports Server (NTRS)

    Tramel, Terri L.; Welker, Roger; Lowery, Niki; Mitchell, Mark

    2014-01-01

    Additive Manufacturing of metallic components for aerospace applications offers many advantages over traditional manufacturing techniques. As a new technology, many aspects of its widespread utilization remain open to investigation. Among these are the cleaning processes that can be used for post finishing of parts and measurements to verify effectiveness of the cleaning processes. Many cleaning and drying processes and measurement methods that have been used for parts manufactured using conventional techniques are candidates that may be considered for cleaning and verification of additively manufactured parts. Among these are vapor degreasing, ultrasonic immersion and spray cleaning, followed by hot air drying, vacuum baking and solvent displacement drying. Differences in porosity, density, and surface finish of additively manufactured versus conventionally manufactured parts may introduce new considerations in the selection of cleaning and drying processes or the method used to verify their effectiveness. This presentation will review the relative strengths and weaknesses of different candidate cleaning and drying processes as they may apply to additively manufactured metal parts for aerospace applications. An ultrasonic cleaning technique for exploring the cleanability of parts will be presented along with an example using additively manufactured Inconel 718 test specimens to illustrate its use. The data analysis shows that this ultrasonic cleaning approach results in a well-behaved ultrasonic cleaning/extraction behavior. That is, it does not show signs of accelerated cavitation erosion of the base material, which was later confirmed by neutron imaging. In addition, the analysis indicated that complete cleaning would be achieved by ultrasonic immersion cleaning at approximately 5 minutes, which was verified by subsequent cleaning of additional parts.

  3. InP-based photonic integrated circuit platform on SiC wafer.

    PubMed

    Takenaka, Mitsuru; Takagi, Shinichi

    2017-11-27

    We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

  4. Improving scanner wafer alignment performance by target optimization

    NASA Astrophysics Data System (ADS)

    Leray, Philippe; Jehoul, Christiane; Socha, Robert; Menchtchikov, Boris; Raghunathan, Sudhar; Kent, Eric; Schoonewelle, Hielke; Tinnemans, Patrick; Tuffy, Paul; Belen, Jun; Wise, Rich

    2016-03-01

    In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML's Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

  5. New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

    NASA Astrophysics Data System (ADS)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2017-06-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

  6. Continuous Flow in Labour-Intensive Manufacturing Process

    NASA Astrophysics Data System (ADS)

    Pacheco Eng., Jhonny; Carbajal MSc., Eduardo; Stoll-Ing., Cesar, Dr.

    2017-06-01

    A continuous-flow manufacturing represents the peak of standard production, and usually it means high production in a strict line production. Furthermore, low-tech industry demands high labour-intensive, in this context the efficient of the line production is tied at the job shop organization. Labour-intensive manufacturing processes are a common characteristic for developing countries. This research aims to propose a methodology for production planning in order to fulfilment a variable monthly production quota. The main idea is to use a clock as orchestra director in order to synchronize the rate time (takt time) of customer demand with the manufacturing time. In this way, the study is able to propose a stark reduction of stock in process, over-processing, and unnecessary variability.

  7. Printing Processes Used to Manufacture Photovoltaic Solar Cells

    ERIC Educational Resources Information Center

    Rardin, Tina E.; Xu, Renmei

    2011-01-01

    There is a growing need for renewable energy sources, and solar power is a good option in many instances. Photovoltaic solar panels are now being manufactured via various methods, and different printing processes are being incorporated into the manufacturing process. Screen printing has been used most prevalently in the printing process to make…

  8. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R.

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  9. Noncontact sheet resistance measurement technique for wafer inspection

    NASA Astrophysics Data System (ADS)

    Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

    1995-12-01

    A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

  10. Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

    2018-06-01

    We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

  11. Process for the homoepitaxial growth of single-crystal silicon carbide films on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Powell, J. Anthony (Inventor)

    1993-01-01

    The invention is a method for growing homoepitaxial films of SiC on low tilt angle vicinal (0001) SiC wafers. The invention proposes and teaches a new theoretical model for the homoepitaxial growth of SiC films on (0001) SiC substrates. The inventive method consists of preparing the growth surface of SiC wafers slightly off-axis (from less the 0.1 to 6 deg) from the (0001) plane, subjecting the growth surface to a suitable etch, and then growing the homoepitaxial film using conventional SiC growth techniques.

  12. Molded, wafer level optics for long wave infra-red applications

    NASA Astrophysics Data System (ADS)

    Franks, John

    2016-05-01

    For many years, the Thermal Imaging market has been driven by the high volume consumer market. The first signs of this came with the launch of night vision systems for cars, first by Cadillac and Honda and then, more successfully by BMW, Daimler and Audi. For the first time, simple thermal imaging systems were being manufactured at the rate of more than 10,000 units a year. This step change in volumes enabled a step change in system costs, with thermal imaging moving into the consumer's price range. Today we see that the consumer awareness and the consumer market continues to increase with the launch of a number of consumer focused smart phone add-ons. This has brought a further step change in system costs, with the possibility to turn your mobile phone into a thermal imager for under $250. As the detector technology has matured, the pixel pitches have dropped from 50μm in 2002 to 12 μm or even 10μm in today's detectors. This dramatic shrinkage in size has had an equally dramatic effect on the optics required to produce the image on the detector. A moderate field of view that would have required a focal length of 40mm in 2002 now requires a focal length of 8mm. For wide field of view applications and small detector formats, focal lengths in the range 1mm to 5mm are becoming common. For lenses, the quantity manufactured, quality and costs will require a new approach to high volume Infra-Red (IR) manufacturing to meet customer expectations. This, taken with the SwaP-C requirements and the emerging requirement for very small lenses driven by the new detectors, suggests that wafer scale optics are part of the solution. Umicore can now present initial results from an intensive research and development program to mold and coat wafer level optics, using its chalcogenide glass, GASIR®.

  13. Engineering Controlled Spalling in (100)-Oriented GaAs for Wafer Reuse

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Sweet, Cassi A.; McNeely, Joshua E.; Gorman, Brian

    Controlled spalling offers a way to cleave thin, single-crystal films or devices from wafers, particularly if the fracture planes in the material are oriented parallel to the wafer surface. Unfortunately, misalignment between the favored fracture planes and the wafer surface preferred for photovoltaic growth in (100)-oriented GaAs produces a highly faceted surface when subject to controlled spalling. This highly faceted cleavage surface is problematic in several ways: (1) it can result in large variations of spall depth due to unstable crack propagation; (2) it may introduce defects into the device zone or underlying substrate; and (3) it consumes many micronsmore » of material outside of the device zone. We present the ways in which we have engineered controlled spalling for (100)-oriented GaAs to minimize these effects. We expand the operational window for controlled spalling to avoid spontaneous spalling, find no evidence of dislocation activity in the spalled film or the parent wafer, and reduce facet height and facet height irregularity. Resolving these issues provides a viable path forward for reducing III-V device cost through the controlled spalling of (100)-oriented GaAs devices and subsequent wafer reuse when these processes are combined with a high-throughput growth method such as Hydride Vapor Phase Epitaxy.« less

  14. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  15. Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

    NASA Technical Reports Server (NTRS)

    Okojie, Robert S. (Inventor)

    2002-01-01

    A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

  16. Feed-forward alignment correction for advanced overlay process control using a standalone alignment station "Litho Booster"

    NASA Astrophysics Data System (ADS)

    Yahiro, Takehisa; Sawamura, Junpei; Dosho, Tomonori; Shiba, Yuji; Ando, Satoshi; Ishikawa, Jun; Morita, Masahiro; Shibazaki, Yuichi

    2018-03-01

    One of the main components of an On-Product Overlay (OPO) error budget is the process induced wafer error. This necessitates wafer-to-wafer correction in order to optimize overlay accuracy. This paper introduces the Litho Booster (LB), standalone alignment station as a solution to improving OPO. LB can execute high speed alignment measurements without throughput (THP) loss. LB can be installed in any lithography process control loop as a metrology tool, and is then able to provide feed-forward (FF) corrections to the scanners. In this paper, the detailed LB design is described and basic LB performance and OPO improvement is demonstrated. Litho Booster's extendibility and applicability as a solution for next generation manufacturing accuracy and productivity challenges are also outlined

  17. An Overview of Cloud Implementation in the Manufacturing Process Life Cycle

    NASA Astrophysics Data System (ADS)

    Kassim, Noordiana; Yusof, Yusri; Hakim Mohamad, Mahmod Abd; Omar, Abdul Halim; Roslan, Rosfuzah; Aryanie Bahrudin, Ida; Ali, Mohd Hatta Mohamed

    2017-08-01

    The advancement of information and communication technology (ICT) has changed the structure and functions of various sectors and it has also started to play a significant role in modern manufacturing in terms of computerized machining and cloud manufacturing. It is important for industries to keep up with the current trend of ICT for them to be able survive and be competitive. Cloud manufacturing is an approach that wanted to realize a real-world manufacturing processes that will apply the basic concept from the field of Cloud computing to the manufacturing domain called Cloud-based manufacturing (CBM) or cloud manufacturing (CM). Cloud manufacturing has been recognized as a new paradigm for manufacturing businesses. In cloud manufacturing, manufacturing companies need to support flexible and scalable business processes in the shop floor as well as the software itself. This paper provides an insight or overview on the implementation of cloud manufacturing in the modern manufacturing processes and at the same times analyses the requirements needed regarding process enactment for Cloud manufacturing and at the same time proposing a STEP-NC concept that can function as a tool to support the cloud manufacturing concept.

  18. Using an extractive Fourier transform infrared spectrometer for improving cleanroom air quality in a semiconductor manufacturing plant.

    PubMed

    Li, Shou-Nan; Chang, Chin-Ta; Shih, Hui-Ya; Tang, Andy; Li, Alen; Chen, Yin-Yung

    2003-01-01

    A mobile extractive Fourier transform infrared (FTIR) spectrometer was successfully used to locate, identify, and quantify the "odor" sources inside the cleanroom of a semiconductor manufacturing plant. It was found that ozone (O(3)) gas with a peak concentration of 120 ppm was unexpectedly releasing from a headspace of a drain for transporting used ozonized water and that silicon tetrafluoride (SiF(4)) with a peak concentration of 3 ppm was off-gassed from silicon wafers after dry-etching processing. When the sources of the odors was pinpointed by the FTIR, engineering control measures were applied. For O(3) control, a water-sealed pipeline was added to prevent the O(3) gas (emitting from the ozonized water) from entering the mixing unit. A ventilation system also was applied to the mixing unit in case of O(3) release. For SiF(4) mitigation, before the wafer-out chamber was opened, N(2) gas with a flow rate of 150 L/min was used for 100 sec to purge the wafer-out chamber, and a vacuum system was simultaneously activated to pump away the purging N(2). The effectiveness of the control measures was assured by using the FTIR. In addition, the FTIR was used to monitor the potential hazardous gas emissions during preventative maintenance of the semiconductor manufacturing equipment.

  19. Wafer-scale plasmonic and photonic crystal sensors

    NASA Astrophysics Data System (ADS)

    George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

    2015-08-01

    200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

  20. 21 CFR 201.122 - Drugs for processing, repacking, or manufacturing.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 21 Food and Drugs 4 2010-04-01 2010-04-01 false Drugs for processing, repacking, or manufacturing... for processing, repacking, or manufacturing. A drug in a bulk package, except tablets, capsules, or... manufacturing, processing, or repacking”; and if in substantially all dosage forms in which it may be dispensed...

  1. Big Data Analysis of Manufacturing Processes

    NASA Astrophysics Data System (ADS)

    Windmann, Stefan; Maier, Alexander; Niggemann, Oliver; Frey, Christian; Bernardi, Ansgar; Gu, Ying; Pfrommer, Holger; Steckel, Thilo; Krüger, Michael; Kraus, Robert

    2015-11-01

    The high complexity of manufacturing processes and the continuously growing amount of data lead to excessive demands on the users with respect to process monitoring, data analysis and fault detection. For these reasons, problems and faults are often detected too late, maintenance intervals are chosen too short and optimization potential for higher output and increased energy efficiency is not sufficiently used. A possibility to cope with these challenges is the development of self-learning assistance systems, which identify relevant relationships by observation of complex manufacturing processes so that failures, anomalies and need for optimization are automatically detected. The assistance system developed in the present work accomplishes data acquisition, process monitoring and anomaly detection in industrial and agricultural processes. The assistance system is evaluated in three application cases: Large distillation columns, agricultural harvesting processes and large-scale sorting plants. In this paper, the developed infrastructures for data acquisition in these application cases are described as well as the developed algorithms and initial evaluation results.

  2. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M.

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  3. Post Processing Methods used to Improve Surface Finish of Products which are Manufactured by Additive Manufacturing Technologies: A Review

    NASA Astrophysics Data System (ADS)

    Kumbhar, N. N.; Mulay, A. V.

    2016-08-01

    The Additive Manufacturing (AM) processes open the possibility to go directly from Computer-Aided Design (CAD) to a physical prototype. These prototypes are used as test models before it is finalized as well as sometimes as a final product. Additive Manufacturing has many advantages over the traditional process used to develop a product such as allowing early customer involvement in product development, complex shape generation and also save time as well as money. Additive manufacturing also possess some special challenges that are usually worth overcoming such as Poor Surface quality, Physical Properties and use of specific raw material for manufacturing. To improve the surface quality several attempts had been made by controlling various process parameters of Additive manufacturing and also applying different post processing techniques on components manufactured by Additive manufacturing. The main objective of this work is to document an extensive literature review in the general area of post processing techniques which are used in Additive manufacturing.

  4. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  5. Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

    NASA Astrophysics Data System (ADS)

    Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

    2017-02-01

    A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (~1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

  6. Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals.

    PubMed

    Carey, Benjamin J; Ou, Jian Zhen; Clark, Rhiannon M; Berean, Kyle J; Zavabeti, Ali; Chesman, Anthony S R; Russo, Salvy P; Lau, Desmond W M; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C; Dickey, Michael D; Kaner, Richard B; Daeneke, Torben; Kalantar-Zadeh, Kourosh

    2017-02-17

    A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

  7. Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

    PubMed Central

    Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kavehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

    2017-01-01

    A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes. PMID:28211538

  8. Mechanical Strength and Broadband Transparency Improvement of Glass Wafers via Surface Nanostructures.

    PubMed

    Kumar, Amarendra; Kashyap, Kunal; Hou, Max T; Yeh, J Andrew

    2016-06-17

    In this study, we mechanically strengthened a borosilicate glass wafer by doubling its bending strength and simultaneously enhancing its transparency using surface nanostructures for different applications including sensors, displays and panels. A fabrication method that combines dry and wet etching is used for surface nanostructure fabrication. Specifically, we improved the bending strength of plain borosilicate glass by 96% using these surface nanostructures on both sides. Besides bending strength improvement, a limited optical transmittance enhancement of 3% was also observed in the visible light wavelength region (400-800 nm). Both strength and transparency were improved by using surface nanostructures of 500 nm depth on both sides of the borosilicate glass without affecting its bulk properties or the glass manufacturing process. Moreover, we observed comparatively smaller fragments during the breaking of the nanostructured glass, which is indicative of strengthening. The range for the nanostructure depth is defined for different applications with which improvements of the strength and transparency of borosilicate glass substrate are obtained.

  9. Mechanical Strength and Broadband Transparency Improvement of Glass Wafers via Surface Nanostructures

    PubMed Central

    Kumar, Amarendra; Kashyap, Kunal; Hou, Max T.; Yeh, J. Andrew

    2016-01-01

    In this study, we mechanically strengthened a borosilicate glass wafer by doubling its bending strength and simultaneously enhancing its transparency using surface nanostructures for different applications including sensors, displays and panels. A fabrication method that combines dry and wet etching is used for surface nanostructure fabrication. Specifically, we improved the bending strength of plain borosilicate glass by 96% using these surface nanostructures on both sides. Besides bending strength improvement, a limited optical transmittance enhancement of 3% was also observed in the visible light wavelength region (400–800 nm). Both strength and transparency were improved by using surface nanostructures of 500 nm depth on both sides of the borosilicate glass without affecting its bulk properties or the glass manufacturing process. Moreover, we observed comparatively smaller fragments during the breaking of the nanostructured glass, which is indicative of strengthening. The range for the nanostructure depth is defined for different applications with which improvements of the strength and transparency of borosilicate glass substrate are obtained. PMID:27322276

  10. Wafer-level packaging with compression-controlled seal ring bonding

    DOEpatents

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  11. 30 GHz monolithic balanced mixers using an ion-implanted FET-compatible 3-inch GaAs wafer process technology

    NASA Technical Reports Server (NTRS)

    Bauhahn, P.; Contolatis, A.; Sokolov, V.; Chao, C.

    1986-01-01

    An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.

  12. Manufacturing of Smart Structures Using Fiber Placement Manufacturing Processes

    NASA Technical Reports Server (NTRS)

    Thomas, Matthew M.; Glowasky, Robert A.; McIlroy, Bruce E.; Story, Todd A.

    1996-01-01

    Smart structures research and development, with the ultimate aim of rapid commercial and military production of these structures, are at the forefront of the Synthesis and Processing of Intelligent Cost-Effective Structures (SPICES) program. As part of this ARPA-sponsored program, MDA-E is using fiber placement processes to manufacture integrated smart structure systems. These systems comprise advanced composite structures with embedded fiber optic sensors, shape memory alloys, piezoelectric actuators, and miniature accelerometers. Cost-effective approaches and solutions to smart material synthesis in the fiber-placement process, based upon integrated product development, are discussed herein.

  13. Increasing component functionality via multi-process additive manufacturing

    NASA Astrophysics Data System (ADS)

    Coronel, Jose L.; Fehr, Katherine H.; Kelly, Dominic D.; Espalin, David; Wicker, Ryan B.

    2017-05-01

    Additively manufactured components, although extensively customizable, are often limited in functionality. Multi-process additive manufacturing (AM) grants the ability to increase the functionality of components via subtractive manufacturing, wire embedding, foil embedding and pick and place. These processes are scalable to include several platforms ranging from desktop to large area printers. The Multi3D System is highlighted, possessing the capability to perform the above mentioned processes, all while transferring a fabricated component with a robotic arm. Work was conducted to fabricate a patent inspired, printed missile seeker. The seeker demonstrated the advantage of multi-process AM via introduction of the pick and place process. Wire embedding was also explored, with the successful interconnect of two layers of embedded wires in different planes. A final demonstration of a printed contour bracket, served to show the reduction of surface roughness on a printed part is 87.5% when subtractive manufacturing is implemented in tandem with AM. Functionality of the components on all the cases was improved. Results included optical components embedded within the printed housing, wires embedded with interconnection, and reduced surface roughness. These results highlight the improved functionality of components through multi-process AM, specifically through work conducted with the Multi3D System.

  14. Manufacturing Demonstration Facility: Roll-to-Roll Processing

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Datskos, Panos G; Joshi, Pooran C; List III, Frederick Alyious

    This Manufacturing Demonstration Facility (MDF)e roll-to-roll processing effort described in this report provided an excellent opportunity to investigate a number of advanced manufacturing approaches to achieve a path for low cost devices and sensors. Critical to this effort is the ability to deposit thin films at low temperatures using nanomaterials derived from nanofermentation. The overarching goal of this project was to develop roll-to-roll manufacturing processes of thin film deposition on low-cost flexible substrates for electronics and sensor applications. This project utilized ORNL s unique Pulse Thermal Processing (PTP) technologies coupled with non-vacuum low temperature deposition techniques, ORNL s clean roommore » facility, slot dye coating, drop casting, spin coating, screen printing and several other equipment including a Dimatix ink jet printer and a large-scale Kyocera ink jet printer. The roll-to-roll processing project had three main tasks: 1) develop and demonstrate zinc-Zn based opto-electronic sensors using low cost nanoparticulate structures manufactured in a related MDF Project using nanofermentation techniques, 2) evaluate the use of silver based conductive inks developed by project partner NovaCentrix for electronic device fabrication, and 3) demonstrate a suite of low cost printed sensors developed using non-vacuum deposition techniques which involved the integration of metal and semiconductor layers to establish a diverse sensor platform technology.« less

  15. Ramp Technology and Intelligent Processing in Small Manufacturing

    NASA Technical Reports Server (NTRS)

    Rentz, Richard E.

    1992-01-01

    To address the issues of excessive inventories and increasing procurement lead times, the Navy is actively pursuing flexible computer integrated manufacturing (FCIM) technologies, integrated by communication networks to respond rapidly to its requirements for parts. The Rapid Acquisition of Manufactured Parts (RAMP) program, initiated in 1986, is an integral part of this effort. The RAMP program's goal is to reduce the current average production lead times experienced by the Navy's inventory control points by a factor of 90 percent. The manufacturing engineering component of the RAMP architecture utilizes an intelligent processing technology built around a knowledge-based shell provided by ICAD, Inc. Rules and data bases in the software simulate an expert manufacturing planner's knowledge of shop processes and equipment. This expert system can use Product Data Exchange using STEP (PDES) data to determine what features the required part has, what material is required to manufacture it, what machines and tools are needed, and how the part should be held (fixtured) for machining, among other factors. The program's rule base then indicates, for example, how to make each feature, in what order to make it, and to which machines on the shop floor the part should be routed for processing. This information becomes part of the shop work order. The process planning function under RAMP greatly reduces the time and effort required to complete a process plan. Since the PDES file that drives the intelligent processing is 100 percent complete and accurate to start with, the potential for costly errors is greatly diminished.

  16. Ramp technology and intelligent processing in small manufacturing

    NASA Astrophysics Data System (ADS)

    Rentz, Richard E.

    1992-04-01

    To address the issues of excessive inventories and increasing procurement lead times, the Navy is actively pursuing flexible computer integrated manufacturing (FCIM) technologies, integrated by communication networks to respond rapidly to its requirements for parts. The Rapid Acquisition of Manufactured Parts (RAMP) program, initiated in 1986, is an integral part of this effort. The RAMP program's goal is to reduce the current average production lead times experienced by the Navy's inventory control points by a factor of 90 percent. The manufacturing engineering component of the RAMP architecture utilizes an intelligent processing technology built around a knowledge-based shell provided by ICAD, Inc. Rules and data bases in the software simulate an expert manufacturing planner's knowledge of shop processes and equipment. This expert system can use Product Data Exchange using STEP (PDES) data to determine what features the required part has, what material is required to manufacture it, what machines and tools are needed, and how the part should be held (fixtured) for machining, among other factors. The program's rule base then indicates, for example, how to make each feature, in what order to make it, and to which machines on the shop floor the part should be routed for processing. This information becomes part of the shop work order. The process planning function under RAMP greatly reduces the time and effort required to complete a process plan. Since the PDES file that drives the intelligent processing is 100 percent complete and accurate to start with, the potential for costly errors is greatly diminished.

  17. Thermodynamic analysis of resources used in manufacturing processes.

    PubMed

    Gutowski, Timothy G; Branham, Matthew S; Dahmus, Jeffrey B; Jones, Alissa J; Thiriez, Alexandre

    2009-03-01

    In this study we use a thermodynamic framework to characterize the material and energy resources used in manufacturing processes. The analysis and data span a wide range of processes from "conventional" processes such as machining, casting, and injection molding, to the so-called "advanced machining" processes such as electrical discharge machining and abrasive waterjet machining, and to the vapor-phase processes used in semiconductor and nanomaterials fabrication. In all, 20 processes are analyzed. The results show that the intensity of materials and energy used per unit of mass of material processed (measured either as specific energy or exergy) has increased by at least 6 orders of magnitude over the past several decades. The increase of material/energy intensity use has been primarily a consequence of the introduction of new manufacturing processes, rather than changes in traditional technologies. This phenomenon has been driven by the desire for precise small-scale devices and product features and enabled by stable and declining material and energy prices over this period. We illustrate the relevance of thermodynamics (including exergy analysis) for all processes in spite of the fact that long-lasting focus in manufacturing has been on product quality--not necessarily energy/material conversion efficiency. We promote the use of thermodynamics tools for analysis of manufacturing processes within the context of rapidly increasing relevance of sustainable human enterprises. We confirm that exergy analysis can be used to identify where resources are lost in these processes, which is the first step in proposing and/or redesigning new more efficient processes.

  18. Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell#

    PubMed Central

    Poghossian, Arshak; Schumacher, Kerstin; Kloock, Joachim P.; Rosenkranz, Christian; Schultze, Joachim W.; Müller-Veggian, Mattea; Schöning, Michael J.

    2006-01-01

    A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor) is realised by means of integration of a specifically designed capillary electrochemical micro-droplet cell into a commercial wafer prober-station. The developed system allows the identification and selection of “good” ISFETs at the earliest stage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. The developed system is also feasible for wafer-level characterisation of ISFETs in terms of sensitivity, hysteresis and response time. Additionally, the system might be also utilised for wafer-level testing of further electrochemical sensors.

  19. Controlling high-throughput manufacturing at the nano-scale

    NASA Astrophysics Data System (ADS)

    Cooper, Khershed P.

    2013-09-01

    Interest in nano-scale manufacturing research and development is growing. The reason is to accelerate the translation of discoveries and inventions of nanoscience and nanotechnology into products that would benefit industry, economy and society. Ongoing research in nanomanufacturing is focused primarily on developing novel nanofabrication techniques for a variety of applications—materials, energy, electronics, photonics, biomedical, etc. Our goal is to foster the development of high-throughput methods of fabricating nano-enabled products. Large-area parallel processing and highspeed continuous processing are high-throughput means for mass production. An example of large-area processing is step-and-repeat nanoimprinting, by which nanostructures are reproduced again and again over a large area, such as a 12 in wafer. Roll-to-roll processing is an example of continuous processing, by which it is possible to print and imprint multi-level nanostructures and nanodevices on a moving flexible substrate. The big pay-off is high-volume production and low unit cost. However, the anticipated cost benefits can only be realized if the increased production rate is accompanied by high yields of high quality products. To ensure product quality, we need to design and construct manufacturing systems such that the processes can be closely monitored and controlled. One approach is to bring cyber-physical systems (CPS) concepts to nanomanufacturing. CPS involves the control of a physical system such as manufacturing through modeling, computation, communication and control. Such a closely coupled system will involve in-situ metrology and closed-loop control of the physical processes guided by physics-based models and driven by appropriate instrumentation, sensing and actuation. This paper will discuss these ideas in the context of controlling high-throughput manufacturing at the nano-scale.

  20. Computational Process Modeling for Additive Manufacturing

    NASA Technical Reports Server (NTRS)

    Bagg, Stacey; Zhang, Wei

    2014-01-01

    Computational Process and Material Modeling of Powder Bed additive manufacturing of IN 718. Optimize material build parameters with reduced time and cost through modeling. Increase understanding of build properties. Increase reliability of builds. Decrease time to adoption of process for critical hardware. Potential to decrease post-build heat treatments. Conduct single-track and coupon builds at various build parameters. Record build parameter information and QM Meltpool data. Refine Applied Optimization powder bed AM process model using data. Report thermal modeling results. Conduct metallography of build samples. Calibrate STK models using metallography findings. Run STK models using AO thermal profiles and report STK modeling results. Validate modeling with additional build. Photodiode Intensity measurements highly linear with power input. Melt Pool Intensity highly correlated to Melt Pool Size. Melt Pool size and intensity increase with power. Applied Optimization will use data to develop powder bed additive manufacturing process model.

  1. Laser furnace and method for zone refining of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

    1988-01-01

    A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

  2. Resonance ultrasonic diagnostics of defects in full-size silicon wafers

    NASA Astrophysics Data System (ADS)

    Belyaev, A.; Ostapenko, S.

    2001-12-01

    A resonance acoustic effect was observed recently in full-size 200 mm Cz-Si wafers and applied to characterize as-grown and process-induced defects. Ultrasonic vibrations can be excited into wafers using an external ultrasonic transducer and their amplitude is recorded using a scanning air-coupled acoustic probe operated in a non-contact mode. By sweeping driving frequency, f, of the transducer, we observed an amplification of a specific acoustic mode referred to as ‘whistle’. In this paper, we performed theoretical modeling of the whistle which allowed in attributing this mode to resonant flexural vibrations in a thin circular plate. We calculated normal frequencies of the flexural vibrations of a circular plate of radius ρ in the case of the free edge. The model gives an excellent fit to experimental data with regard to whistle spatial distribution. The results of calculation allow the evaluation of resonance acoustic effect in wafers of different geometries employed in the industry.

  3. The Novel Preparation of P-N Junction Mesa Diodes by Silicon-Wafer Direct Bonding (SDB)

    NASA Astrophysics Data System (ADS)

    Yeh, Ching-Fa; Hwangleu, Shyang

    1992-05-01

    The key processes of silicon-wafer direct bonding (SDB), including hydrophilic surface formation and optimal two-step heat treatment, have been developed However, H2SO4/H2O2 solution being a strong oxidized acid solution, native oxide is found to have grown on the wafer surface as soon as a wafer is treated in this solution. In the case of a wafer further treated in diluted HF solution after hydrophilic surface formation, it is shown that the wafer surface can not only be cleaned of its native oxide but also remains hydrophilic, and can provide excellent voidless bonding. The N+/P and N/P combination junction mesa diodes fabricated on the wafers prepared by these novel SDB technologies are examined. The ideality factor n of the N/P mesa diode is 2.4˜2.8 for the voltage range 0.2˜0.3 V; hence, the lowering of the ideality factor n is evidently achieved. As for the N+/P mesa diode, the ideality factor n shows a value of 1.10˜1.30 for the voltage range 0.2˜0.6 V; the low value of n is attributed to an autodoping phenomenon which has caused the junction interface to form in the P-silicon bulk. However, the fact that the sustaining voltage of the N/P mesa diode showed a value greater than 520 V reveals the effectiveness of our novel SDB processes.

  4. Application of Contact Mode AFM to Manufacturing Processes

    NASA Astrophysics Data System (ADS)

    Giordano, Michael A.; Schmid, Steven R.

    A review of the application of contact mode atomic force microscopy (AFM) to manufacturing processes is presented. A brief introduction to common experimental techniques including hardness, scratch, and wear testing is presented, with a discussion of challenges in the extension of manufacturing scale investigations to the AFM. Differences between the macro- and nanoscales tests are discussed, including indentation size effects and their importance in the simulation of processes such as grinding. The basics of lubrication theory are presented and friction force microscopy is introduced as a method of investigating metal forming lubrication on the nano- and microscales that directly simulates tooling/workpiece asperity interactions. These concepts are followed by a discussion of their application to macroscale industrial manufacturing processes and direct correlations are made.

  5. SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

    NASA Astrophysics Data System (ADS)

    Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

    2010-05-01

    Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

  6. News: Good chemical manufacturing process criteria

    EPA Science Inventory

    This news column covers topics relating to manufacturing criteria, machine to machine technology, novel process windows, green chemistry indices, business resilience, immobilized enzymes, and Bt crops.

  7. UOE Pipe Manufacturing Process Simulation: Equipment Designing and Construction

    NASA Astrophysics Data System (ADS)

    Delistoian, Dmitri; Chirchor, Mihael

    2017-12-01

    UOE pipe manufacturing process influence directly on pipeline resilience and operation capacity. At present most spreaded pipe manufacturing method is UOE. This method is based on cold forming. After each technological step appears a certain stress and strain level. For pipe stress strain study is designed and constructed special equipment that simulate entire technological process.UOE pipe equipment is dedicated for manufacturing of longitudinally submerged arc welded DN 400 (16 inch) steel pipe.

  8. Advanced Manufacturing Processes in the Motor Vehicle Industry

    DOT National Transportation Integrated Search

    1983-05-01

    Advanced manufacturing processes, which include a range of automation and management techniques, are aiding U.S. motor vehicle manufacturers to reduce vehicle costs. This report discusses these techniques in general and their specific applications in...

  9. In-situ acoustic signature monitoring in additive manufacturing processes

    NASA Astrophysics Data System (ADS)

    Koester, Lucas W.; Taheri, Hossein; Bigelow, Timothy A.; Bond, Leonard J.; Faierson, Eric J.

    2018-04-01

    Additive manufacturing is a rapidly maturing process for the production of complex metallic, ceramic, polymeric, and composite components. The processes used are numerous, and with the complex geometries involved this can make quality control and standardization of the process and inspection difficult. Acoustic emission measurements have been used previously to monitor a number of processes including machining and welding. The authors have identified acoustic signature measurement as a potential means of monitoring metal additive manufacturing processes using process noise characteristics and those discrete acoustic emission events characteristic of defect growth, including cracks and delamination. Results of acoustic monitoring for a metal additive manufacturing process (directed energy deposition) are reported. The work investigated correlations between acoustic emissions and process noise with variations in machine state and deposition parameters, and provided proof of concept data that such correlations do exist.

  10. Improvements in Cz silicon PV module manufacturing

    NASA Astrophysics Data System (ADS)

    King, Richard R.; Mitchell, Kim W.; Jester, Theresa L.

    1997-02-01

    Work focused on reducing the cost per watt of Cz Si photovoltaic modules under Phase I of Siemens Solar Industries' DOE/NREL PVMaT 4A subcontract is described. Module cost components are analyzed and solutions to high-cost items are discussed in terms of specific module designs. The approaches of using larger cells and modules to reduce per-part processing cost, and of minimizing yield loss are particularly leveraging. Yield components for various parts of the fabrication process and various types of defects are shown, and measurements of the force required to break wafers throughout the cell fabrication sequence are given. The most significant type of yield loss is mechanical breakage. The implementation of statistical process control on key manufacturing processes at Siemens Solar Industries is described. Module configurations prototyped during Phase I of this project and scheduled to begin production in Phase II have a projected cost per watt reduction of 19%.

  11. Development of a Launch Vehicle Manufacturing Process. Chapter 4

    NASA Technical Reports Server (NTRS)

    Vickers, John; Munafo, Paul M. (Technical Monitor)

    2002-01-01

    One of the goals of this chapter is to provide sufficient information so that you can develop a manufacturing process for a potential launch vehicle. With the variety of manufacturing options available, you might ask how this can possibly be done in the span of a single chapter. Actually, it will be quite simple because a basic manufacturing process is nothing more than a set of logical steps that are iterated until they produce a desired product. Although these statements seem simple and logical, don't let this simplicity fool you. Manufacturing problems with launch vehicles and their subassemblies have been the primary cause of project failures because the vehicle concept delivered to the manufacturing floor could not be built as designed.

  12. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, Theodoer F.

    1995-01-01

    Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

  13. Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

    NASA Astrophysics Data System (ADS)

    Wang, Shing-Dar; Chen, Ting-Wei

    2018-06-01

    In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in <1 0 0> direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

  14. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  15. Nonterrestrial material processing and manufacturing of large space systems

    NASA Technical Reports Server (NTRS)

    Von Tiesenhausen, G.

    1979-01-01

    Nonterrestrial processing of materials and manufacturing of large space system components from preprocessed lunar materials at a manufacturing site in space is described. Lunar materials mined and preprocessed at the lunar resource complex will be flown to the space manufacturing facility (SMF), where together with supplementary terrestrial materials, they will be final processed and fabricated into space communication systems, solar cell blankets, radio frequency generators, and electrical equipment. Satellite Power System (SPS) material requirements and lunar material availability and utilization are detailed, and the SMF processing, refining, fabricating facilities, material flow and manpower requirements are described.

  16. Cost Models for MMC Manufacturing Processes

    NASA Technical Reports Server (NTRS)

    Elzey, Dana M.; Wadley, Haydn N. G.

    1996-01-01

    Processes for the manufacture of advanced metal matrix composites are rapidly approaching maturity in the research laboratory and there is growing interest in their transition to industrial production. However, research conducted to date has almost exclusively focused on overcoming the technical barriers to producing high-quality material and little attention has been given to the economical feasibility of these laboratory approaches and process cost issues. A quantitative cost modeling (QCM) approach was developed to address these issues. QCM are cost analysis tools based on predictive process models relating process conditions to the attributes of the final product. An important attribute, of the QCM approach is the ability to predict the sensitivity of material production costs to product quality and to quantitatively explore trade-offs between cost and quality. Applications of the cost models allow more efficient direction of future MMC process technology development and a more accurate assessment of MMC market potential. Cost models were developed for two state-of-the art metal matrix composite (MMC) manufacturing processes: tape casting and plasma spray deposition. Quality and Cost models are presented for both processes and the resulting predicted quality-cost curves are presented and discussed.

  17. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  18. Fabricating a Microcomputer on a Single Silicon Wafer

    NASA Technical Reports Server (NTRS)

    Evanchuk, V. L.

    1983-01-01

    Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

  19. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  20. Processing silicon microparticles recycled from wafer waste via Rapid Thermal Process for lithium-ion battery anode materials

    NASA Astrophysics Data System (ADS)

    Tan, Hui-Gee; Duh, Jenq-Gong

    2016-12-01

    A vast quantity of waste sludge is generated during the silicon wafers slicing process in semiconductor and photovoltaic industries. Turning the waste powder into high-value products is of strategic importance for industrial processes. The purified Si microparticles (Si-MP) are recycled by a simple and fast procedure, Rapid Thermal Process (RTP). A prominent anodic material of Si-MP/Carbon composite with porous structure is obtained via in-spaced carbonization of water-soluble binder sodium carboxymethyl cellulose during RTP. This strategy provides buffer space, which is constructed by carbon porous continuous conductive framework throughout the entire electrode, to resist local stress and intense volume variation. In addition, a sufficiently electrochemically stable solid-electrolyte interphase layer is accomplished with the coating of SiOx film and amorphous carbon on the surface of Si-MP. Under these circumstances, the enhanced electrodes achieve a first cycle efficiency of approximately 80% and a reversible charge capacity of 800 mAhg-1 over 100 cycles at 0.5 Ag-1 with good retention. Through a green and simple procedure, a remarkable Si-MP embedded carbon-matrix with porous structure is established to achieve commercially high performance Si-MP/C composite anodes and also to resolve the issues of waste disposal.

  1. Cost analysis of advanced turbine blade manufacturing processes

    NASA Technical Reports Server (NTRS)

    Barth, C. F.; Blake, D. E.; Stelson, T. S.

    1977-01-01

    A rigorous analysis was conducted to estimate relative manufacturing costs for high technology gas turbine blades prepared by three candidate materials process systems. The manufacturing costs for the same turbine blade configuration of directionally solidified eutectic alloy, an oxide dispersion strengthened superalloy, and a fiber reinforced superalloy were compared on a relative basis to the costs of the same blade currently in production utilizing the directional solidification process. An analytical process cost model was developed to quantitatively perform the cost comparisons. The impact of individual process yield factors on costs was also assessed as well as effects of process parameters, raw materials, labor rates and consumable items.

  2. Fabrication of wafer-scale nanopatterned sapphire substrate through phase separation lithography

    NASA Astrophysics Data System (ADS)

    Guo, Xu; Ni, Mengyang; Zhuang, Zhe; Dai, Jiangping; Wu, Feixiang; Cui, Yushuang; Yuan, Changsheng; Ge, Haixiong; Chen, Yanfeng

    2016-04-01

    A phase separation lithography (PSL) based on polymer blend provides an extremely simple, low-cost, and high-throughput way to fabricate wafer-scale disordered nanopatterns. This method was introduced to fabricate nanopatterned sapphire substrates (NPSSs) for GaN-based light-emitting diodes (LEDs). The PSL process only involved in spin-coating of polystyrene (PS)/polyethylene glycol (PEG) polymer blend on sapphire substrate and followed by a development with deionized water to remove PEG moiety. The PS nanoporous network was facilely obtained, and the structural parameters could be effectively tuned by controlling the PS/PEG weight ratio of the spin-coating solution. 2-in. wafer-scale NPSSs were conveniently achieved through the PS nanoporous network in combination with traditional nanofabrication methods, such as O2 reactive ion etching (RIE), e-beam evaporation deposition, liftoff, and chlorine-based RIE. In order to investigate the performance of such NPSSs, typical blue LEDs with emission wavelengths of ~450 nm were grown on the NPSS and a flat sapphire substrate (FSS) by metal-organic chemical vapor deposition, respectively. The integral photoluminescence (PL) intensity of the NPSS LED was enhanced by 32.3 % compared to that of the FSS-LED. The low relative standard deviation of 4.7 % for PL mappings of NPSS LED indicated the high uniformity of PL data across the whole 2-in. wafer. Extremely simple, low cost, and high throughput of the process and the ability to fabricate at the wafer scale make PSL a potential method for production of nanopatterned sapphire substrates.

  3. Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

    NASA Astrophysics Data System (ADS)

    Kim, Bong-Hwan; Kim, Jong-Bok

    2009-06-01

    We have developed a microfabrication process for high aspect ratio thick silicon wafer molds and electroplating using flipchip bonding with THB 151N negative photoresist (JSR micro). This fabrication technique includes large area and high thickness silicon wafer mold electroplating. The process consists of silicon deep reactive ion etching (RIE) of the silicon wafer mold, photoresist bonding between the silicon mold and the substrate, nickel electroplating and a silicon removal process. High thickness silicon wafer molds were made by deep RIE and flipchip bonding. In addition, nickel electroplating was developed. Dry film resist (ORDYL MP112, TOK) and thick negative-tone photoresist (THB 151N, JSR micro) were used as bonding materials. In order to measure the bonding strength, the surface energy was calculated using a blade test. The surface energy of the bonding wafers was found to be 0.36-25.49 J m-2 at 60-180 °C for the dry film resist and 0.4-1.9 J m-2 for THB 151N in the same temperature range. Even though ORDYL MP112 has a better value of surface energy than THB 151N, it has a critical disadvantage when it comes to removing residue after electroplating. The proposed process can be applied to high aspect ratio MEMS structures, such as air gap inductors or vertical MEMS probe tips.

  4. Key technologies for manufacturing and processing sheet materials: A global perspective

    NASA Astrophysics Data System (ADS)

    Demeri, Mahmoud Y.

    2001-02-01

    Modern industrial technologies continue to seek new materials and processes to produce products that meet design and functional requirements. Sheet materials made from ferrous and non-ferrous metals, laminates, composites, and reinforced plastics constitute a large percentage of today’s products, components, and systems. Major manufacturers of sheet products include automotive, aerospace, appliance, and food-packaging industries. The Second Global Symposium on Innovations in Materials Processing & Manufacturing: Sheet Materials is organized to provide a forum for presenting advances in sheet processing and manufacturing by worldwide researchers and engineers from industrial, research, and academic centers. The symposium, sponsored by the TMS Materials Processing & Manufacturing Division (MPMD), was planned for the 2001 TMS Annual Meeting, New Orleans, Louisiana, February 11 15, 2001. This article is a review of key papers submitted for publication in the concurrent volume. The selected papers present significant developments in the rapidly expanding areas of advanced sheet materials, innovative forming methods, industrial applications, primary and secondary processing, composite processing, and numerical modeling of manufacturing processes.

  5. Modelling deformation and fracture in confectionery wafers

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which wasmore » then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.« less

  6. Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers

    NASA Technical Reports Server (NTRS)

    Anthony, Thomas R. (Inventor)

    1983-01-01

    Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.

  7. Pulse plating of Pt on n-GaAs ( 1 0 0 ) wafer surfaces: Synchrotron induced photoelectron spectroscopy and XPS of wet fabrication processes

    NASA Astrophysics Data System (ADS)

    Ensling, D.; Hunger, R.; Kraft, D.; Mayer, Th.; Jaegermann, W.; Rodriguez-Girones, M.; Ichizli, V.; Hartnagel, H. L.

    2003-01-01

    Preparation steps of Pt/n-GaAs Schottky contacts as applied in the fabrication process of varactor diode arrays for THz applications are analysed by photoelectron spectroscopy. Pulsed cathodic deposition of Pt onto GaAs (1 0 0) wafer surfaces from acidic solution has been studied by core level photoelectron spectroscopy using different excitation energies. A laboratory AlKα source as well as synchrotron radiation of hν=130 and 645 eV at BESSY was used. Chemical analyses and semiquantitative estimates of layer thickness are given for the natural oxide of an untreated wafer surface, a surface conditioning NH 3 etching step, and stepwise pulse plating of Pt. The structural arrangement of the detected species and interface potentials are considered.

  8. Advanced excimer laser technologies enable green semiconductor manufacturing

    NASA Astrophysics Data System (ADS)

    Fukuda, Hitomi; Yoo, Youngsun; Minegishi, Yuji; Hisanaga, Naoto; Enami, Tatsuo

    2014-03-01

    "Green" has fast become an important and pervasive topic throughout many industries worldwide. Many companies, especially in the manufacturing industries, have taken steps to integrate green initiatives into their high-level corporate strategies. Governments have also been active in implementing various initiatives designed to increase corporate responsibility and accountability towards environmental issues. In the semiconductor manufacturing industry, there are growing concerns over future environmental impact as enormous fabs expand and new generation of equipments become larger and more powerful. To address these concerns, Gigaphoton has implemented various green initiatives for many years under the EcoPhoton™ program. The objective of this program is to drive innovations in technology and services that enable manufacturers to significantly reduce both the financial and environmental "green cost" of laser operations in high-volume manufacturing environment (HVM) - primarily focusing on electricity, gas and heat management costs. One example of such innovation is Gigaphoton's Injection-Lock system, which reduces electricity and gas utilization costs of the laser by up to 50%. Furthermore, to support the industry's transition from 300mm to the next generation 450mm wafers, technologies are being developed to create lasers that offer double the output power from 60W to 120W, but reducing electricity and gas consumption by another 50%. This means that the efficiency of lasers can be improve by up to 4 times in 450mm wafer production environments. Other future innovations include the introduction of totally Heliumfree Excimer lasers that utilize Nitrogen gas as its replacement for optical module purging. This paper discusses these and other innovations by Gigaphoton to enable green manufacturing.

  9. Automotive Manufacturing Processes. Volume III - Casting and Forging Processes

    DOT National Transportation Integrated Search

    1981-02-01

    Extensive material substitution and resizing of the domestic automotive fleet, as well as the introduction of new technologies, will require major changes in the techniques and equipment used in the various manufacturing processes employed in the pro...

  10. Nonterrestrial material processing and manufacturing of large space systems

    NASA Technical Reports Server (NTRS)

    Vontiesenhausen, G. F.

    1978-01-01

    An attempt is made to provide pertinent and readily usable information on the extraterrestrial processing of materials and manufacturing of components and elements of these planned large space systems from preprocessed lunar materials which are made available at a processing and manufacturing site in space. Required facilities, equipment, machinery, energy and manpower are defined.

  11. Controlling Wafer Contamination Using Automated On-Line Metrology during Wet Chemical Cleaning

    NASA Astrophysics Data System (ADS)

    Wang, Jason; Kingston, Skip; Han, Ye; Saini, Harmesh; McDonald, Robert; Mui, Rudy

    2003-09-01

    The capabilities of a trace contamination analyzer are discussed and demonstrated. This analytical tool utilizes an electrospray, time-of-flight mass spectrometer (ES-TOF-MS) for fully automated on-line monitoring of wafer cleaning solutions. The analyzer provides rich information on metallic, anionic, cationic, elemental, and organic species through its ability to provide harsh (elemental) and soft (molecular) ionization under both positive and negative modes. It is designed to meet semiconductor process control and yield management needs for the ever increasing complex new chemistries present in wafer fabrication.

  12. Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene

    DTIC Science & Technology

    2014-08-01

    Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene by Eugene Zakar, Wayne Churaman, Collin Becker, Bernard Rod, Luke...Laboratory Adelphi, MD 20783-1138 ARL-TR-7025 August 2014 Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene...Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6

  13. Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

    NASA Astrophysics Data System (ADS)

    Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

    2018-06-01

    Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

  14. Manufacturability improvements in EUV resist processing toward NXE:3300 processing

    NASA Astrophysics Data System (ADS)

    Kuwahara, Yuhei; Matsunaga, Koichi; Shimoaoki, Takeshi; Kawakami, Shinichiro; Nafus, Kathleen; Foubert, Philippe; Goethals, Anne-Marie; Shimura, Satoru

    2014-03-01

    As the design rule of semiconductor process gets finer, extreme ultraviolet lithography (EUVL) technology is aggressively studied as a process for 22nm half pitch and beyond. At present, the studies for EUV focus on manufacturability. It requires fine resolution, uniform, smooth patterns and low defectivity, not only after lithography but also after the etch process. In the first half of 2013, a CLEAN TRACKTM LITHIUS ProTMZ-EUV was installed at imec for POR development in preparation of the ASML NXE:3300. This next generation coating/developing system is equipped with state of the art defect reduction technology. This tool with advanced functions can achieve low defect levels. This paper reports on the progress towards manufacturing defectivity levels and latest optimizations towards the NXE:3300 POR for both lines/spaces and contact holes at imec.

  15. Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

    NASA Astrophysics Data System (ADS)

    Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

    2018-05-01

    A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

  16. Large-area copper indium diselenide (CIS) process, control and manufacturing

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Gillespie, T.J.; Lanning, B.R.; Marshall, C.H.

    1997-12-31

    Lockheed Martin Astronautics (LMA) has developed a large-area (30x30cm) sequential CIS manufacturing approach amenable to low-cost photovoltaics (PV) production. A prototype CIS manufacturing system has been designed and built with compositional uniformity (Cu/In ratio) verified within {+-}4 atomic percent over the 30x30cm area. CIS device efficiencies have been measured by the National Renewable Energy Laboratory (NREL) at 7% on a flexible non-sodium-containing substrate and 10% on a soda-lime-silica (SLS) glass substrate. Critical elements of the manufacturing capability include the CIS sequential process selection, uniform large-area material deposition, and in-situ process control. Details of the process and large-area manufacturing approach aremore » discussed and results presented.« less

  17. A fully wafer-level packaged RF MEMS switch with low actuation voltage using a piezoelectric actuator

    NASA Astrophysics Data System (ADS)

    Park, Jae-Hyoung; Lee, Hee-Chul; Park, Yong-Hee; Kim, Yong-Dae; Ji, Chang-Hyeon; Bu, Jonguk; Nam, Hyo-Jin

    2006-11-01

    In this paper, a fully wafer-level packaged RF MEMS switch has been demonstrated, which has low operation voltage, using a piezoelectric actuator. The piezoelectric actuator was designed to operate at low actuation voltage for application to advanced mobile handsets. The dc contact type RF switch was packaged using the wafer-level bonding process. The CPW transmission lines and piezoelectric actuators have been fabricated on separate wafers and assembled together by the wafer-level eutectic bonding process. A gold and tin composite was used for eutectic bonding at a low temperature of 300 °C. Via holes interconnecting the electrical contact pads through the wafer were filled completely with electroplated copper. The fully wafer-level packaged RF MEMS switch showed an insertion loss of 0.63 dB and an isolation of 26.4 dB at 5 GHz. The actuation voltage of the switch was 5 V. The resonant frequency of the piezoelectric actuator was 38.4 kHz and the spring constant of the actuator was calculated to be 9.6 N m-1. The size of the packaged SPST (single-pole single-through) switch was 1.2 mm × 1.2 mm including the packaging sealing rim. The effect of the proposed package structure on the RF performance was characterized with a device having CPW through lines and vertical feed lines excluding the RF switches. The measured packaging loss was 0.2 dB and the return loss was 33.6 dB at 5 GHz.

  18. Integrated Dynamic Process Planning and Scheduling in Flexible Manufacturing Systems via Autonomous Agents

    NASA Astrophysics Data System (ADS)

    Nejad, Hossein Tehrani Nik; Sugimura, Nobuhiro; Iwamura, Koji; Tanimizu, Yoshitaka

    Process planning and scheduling are important manufacturing planning activities which deal with resource utilization and time span of manufacturing operations. The process plans and the schedules generated in the planning phase shall be modified in the execution phase due to the disturbances in the manufacturing systems. This paper deals with a multi-agent architecture of an integrated and dynamic system for process planning and scheduling for multi jobs. A negotiation protocol is discussed, in this paper, to generate the process plans and the schedules of the manufacturing resources and the individual jobs, dynamically and incrementally, based on the alternative manufacturing processes. The alternative manufacturing processes are presented by the process plan networks discussed in the previous paper, and the suitable process plans and schedules are searched and generated to cope with both the dynamic status and the disturbances of the manufacturing systems. We initiatively combine the heuristic search algorithms of the process plan networks with the negotiation protocols, in order to generate suitable process plans and schedules in the dynamic manufacturing environment. A simulation software has been developed to carry out case studies, aimed at verifying the performance of the proposed multi-agent architecture.

  19. Design and manufacture of a lightweight piezo-composite curved actuator

    NASA Astrophysics Data System (ADS)

    Yoon, K. Joon; Shin, Seokjun; Park, Hoon C.; Goo, Nam Seo

    2002-02-01

    In this paper we are concerned with the design, manufacture and performance test of a lightweight piezo-composite curved actuator (called LIPCA) using a top carbon fiber composite layer with near-zero coefficient of thermal expansion (CTE), a middle PZT ceramic wafer, and a bottom glass/epoxy layer with a high CTE. The main point of the design for LIPCA is to replace the heavy metal layers of THUNDERTM by lightweight fiber reinforced plastic layers without losing the capabilities for generating high force and large displacement. It is possible to save up to about 40% of the weight if we replace the metallic backing material by the light fiber composite layer. We can also have design flexibility by selecting the fiber direction and the size of prepreg layers. In addition to the lightweight advantage and design flexibility, the proposed device can be manufactured without adhesive layers when we use an epoxy resin prepreg system. Glass/epoxy prepregs, a ceramic wafer with electrode surfaces, and a carbon prepreg were simply stacked and cured at an elevated temperature (177 °C) after following an autoclave bagging process. We found that the manufactured composite laminate device had a sufficient curvature after being detached from a flat mould. An analysis method using the classical lamination theory is presented to predict the curvature of LIPCA after curing at an elevated temperature. The predicted curvatures are in quite good agreement with the experimental values. In order to investigate the merits of LIPCA, performance tests of both LIPCA and THUNDERTM have been conducted under the same boundary conditions. From the experimental actuation tests, it was observed that the developed actuator could generate larger actuation displacement than THUNDERTM.

  20. CIMOSA process classification for business process mapping in non-manufacturing firms: A case study

    NASA Astrophysics Data System (ADS)

    Latiffianti, Effi; Siswanto, Nurhadi; Wiratno, Stefanus Eko; Saputra, Yudha Andrian

    2017-11-01

    A business process mapping is one important means to enable an enterprise to effectively manage the value chain. One of widely used approaches to classify business process for mapping purpose is Computer Integrated Manufacturing System Open Architecture (CIMOSA). CIMOSA was initially designed for Computer Integrated Manufacturing (CIM) system based enterprises. This paper aims to analyze the use of CIMOSA process classification for business process mapping in the firms that do not fall within the area of CIM. Three firms of different business area that have used CIMOSA process classification were observed: an airline firm, a marketing and trading firm for oil and gas products, and an industrial estate management firm. The result of the research has shown that CIMOSA can be used in non-manufacturing firms with some adjustment. The adjustment includes addition, reduction, or modification of some processes suggested by CIMOSA process classification as evidenced by the case studies.

  1. Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

    NASA Astrophysics Data System (ADS)

    Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

    2015-03-01

    A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

  2. Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

    PubMed Central

    Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

    2015-01-01

    A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing. PMID:25819285

  3. Automotive Manufacturing Processes. volume I - Overview

    DOT National Transportation Integrated Search

    1981-02-01

    Extensive material substitution and re-sizing of the domestic automotive fleet, as well as the introduction of new technologies, will require major changes in the techniques and equipment used in the various manufacturing processes employed in the pr...

  4. Automotive Manufacturing Processes. Volume I - Overview

    DOT National Transportation Integrated Search

    1981-02-01

    Extensive material substitution and re-sizing of the domestic automotive fleet, as well as the introduction of new technologies, will require major changes in the techniques and equipment used in the various manufacturing processes employed in the pr...

  5. Process for manufacturing multilayer capacitors

    DOEpatents

    Lauf, R.J.; Holcombe, C.E.; Dykes, N.L.

    1996-01-02

    The invention is directed to a method of manufacture of multilayer electrical components, especially capacitors, and components made by such a method. High capacitance dielectric materials and low cost metallizations layered with such dielectrics may be fabricated as multilayer electrical components by sintering the metallizations and the dielectrics during the fabrication process by application of microwave radiation. 4 figs.

  6. Process for manufacturing multilayer capacitors

    DOEpatents

    Lauf, Robert J.; Holcombe, Cressie E.; Dykes, Norman L.

    1996-01-01

    The invention is directed to a method of manufacture of multilayer electrical components, especially capacitors, and components made by such a method. High capacitance dielectric materials and low cost metallizations layered with such dielectrics may be fabricated as multilayer electrical components by sintering the metallizations and the dielectrics during the fabrication process by application of microwave radiation.

  7. Design for manufacturability production management activity report

    NASA Astrophysics Data System (ADS)

    Miyazaki, Norihiko; Sato, T.; Honma, M.; Yoshioka, N.; Hosono, K.; Onodera, T.; Itoh, H.; Suzuki, H.; Uga, T.; Kadota, K.; Iriki, N.

    2006-05-01

    Design For Manufacturability Production Management (DFM-PM) Subcommittee has been started in succession to Reticle Management Subcommittee (RMS) in Semiconductor Manufacturing Technology Committee for Japan (SMTCJ) from 2005. Our activity focuses on the SoC (System On Chip) Business, and it pursues the improvement of communication in manufacturing technique. The first theme of activity is the investigation and examination of the new trends about production (manufacturer) technology and related information, and proposals of business solution. The second theme is the standardization activity about manufacture technology and the cooperation with related semiconductors' organizations. And the third theme is holding workshop and support for promotion and spread of the standardization technology throughout semiconductor companies. We expand a range of scope from design technology to wafer pattern reliability and we will propose the competition domain, the collaboration area and the standardization technology on DFM. Furthermore, we will be able to make up a SoC business model as the 45nm node technology beyond manufacturing platform in cooperating with the design information and the production information by utilizing EDA technology.

  8. 21 CFR 801.122 - Medical devices for processing, repacking, or manufacturing.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ....122 Medical devices for processing, repacking, or manufacturing. A device intended for processing... act if its label bears the statement “Caution: For manufacturing, processing, or repacking”. ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Medical devices for processing, repacking, or...

  9. 78 FR 18234 - Service of Process on Manufacturers; Manufacturers Importing Electronic Products Into the United...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-03-26

    ... DEPARTMENT OF HEALTH AND HUMAN SERVICES Food and Drug Administration 21 CFR Part 1005 [Docket No. FDA-2007-N-0091; (formerly 2007N-0104)] Service of Process on Manufacturers; Manufacturers Importing Electronic Products Into the United States; Agent Designation; Change of Address AGENCY: Food and Drug...

  10. Numerical simulation of complex part manufactured by selective laser melting process

    NASA Astrophysics Data System (ADS)

    Van Belle, Laurent

    2017-10-01

    Selective Laser Melting (SLM) process belonging to the family of the Additive Manufacturing (AM) technologies, enable to build parts layer by layer, from metallic powder and a CAD model. Physical phenomena that occur in the process have the same issues as conventional welding. Thermal gradients generate significant residual stresses and distortions in the parts. Moreover, the large and complex parts to manufacturing, accentuate the undesirable effects. Therefore, it is essential for manufacturers to offer a better understanding of the process and to ensure production reliability of parts with high added value. This paper focuses on the simulation of manufacturing turbine by SLM process in order to calculate residual stresses and distortions. Numerical results will be presented.

  11. Characterization of wafer-level bonded hermetic packages using optical leak detection

    NASA Astrophysics Data System (ADS)

    Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

    2009-07-01

    For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

  12. Assessment of low-cost manufacturing process sequences. [photovoltaic solar arrays

    NASA Technical Reports Server (NTRS)

    Chamberlain, R. G.

    1979-01-01

    An extensive research and development activity to reduce the cost of manufacturing photovoltaic solar arrays by a factor of approximately one hundred is discussed. Proposed and actual manufacturing process descriptions were compared to manufacturing costs. An overview of this methodology is presented.

  13. Framework for Sustainability Performance Assessment for Manufacturing Processes- A Review

    NASA Astrophysics Data System (ADS)

    Singh, K.; Sultan, I.

    2017-07-01

    Manufacturing industries are facing tough competition due to increasing raw material cost and depleting natural resources. There is great pressure on the industry to produce environmental friendly products using environmental friendly processes. To address these issues modern manufacturing industries are focusing on sustainable manufacturing. To develop more sustainable societies, industries need to better understand how to respond to environmental, economic and social challenges. This paper proposed some framework and tools that accelerate the transition towards a sustainable system. The developed framework will be beneficial for sustainability assessment comparing different plans alongside material properties, ultimately helping the manufacturing industries to reduce the carbon emissions and material waste, besides improving energy efficiency. It is expected that this would be highly beneficial for determination of environmental impact of a process at early design stages. Therefore, it would greatly help the manufacturing industries for selection of process plan based on sustainable indices. Overall objective of this paper would have good impact on reducing air emissions and protecting environment. We expect this work to contribute to the development of a standard reference methodology to help further sustainability in the manufacturing sector.

  14. Silicon materials task of the low-cost solar array project. Phase 4: Effects of impurities and processing on silicon solar cells

    NASA Technical Reports Server (NTRS)

    Hopkins, R. H.; Hanes, M. H.; Davis, J. R.; Rohatgi, A.; Rai-Choudhury, P.; Mollenkopf, H. C.

    1981-01-01

    The effects of impurities, various thermochemical processes, and any impurity-process interactions upon the performance of terrestrial solar cells are defined. The results form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost benefit relationships for the use of less pure, less costly solar grade silicon.

  15. A spatially resolved retarding field energy analyzer design suitable for uniformity analysis across the surface of a semiconductor wafer

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Sharma, S., E-mail: shailesh.sharma6@mail.dcu.ie; National Centre for Plasma Science and Technology, Dublin City University, Glasnevin, Dublin 9; Gahan, D., E-mail: david.gahan@impedans.com

    2014-04-15

    A novel retarding field energy analyzer design capable of measuring the spatial uniformity of the ion energy and ion flux across the surface of a semiconductor wafer is presented. The design consists of 13 individual, compact-sized, analyzers, all of which are multiplexed and controlled by a single acquisition unit. The analyzers were tested to have less than 2% variability from unit to unit due to tight manufacturing tolerances. The main sensor assembly consists of a 300 mm disk to mimic a semiconductor wafer and the plasma sampling orifices of each sensor are flush with disk surface. This device is placedmore » directly on top of the rf biased electrode, at the wafer location, in an industrial capacitively coupled plasma reactor without the need for any modification to the electrode structure. The ion energy distribution, average ion energy, and average ion flux were measured at the 13 locations over the surface of the powered electrode to determine the degree of spatial nonuniformity. The ion energy and ion flux are shown to vary by approximately 20% and 5%, respectively, across the surface of the electrode for the range of conditions investigated in this study.« less

  16. Mask-to-wafer alignment system

    DOEpatents

    Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

    2003-11-04

    A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

  17. Wafer defect detection by a polarization-insensitive external differential interference contrast module.

    PubMed

    Nativ, Amit; Feldman, Haim; Shaked, Natan T

    2018-05-01

    We present a system that is based on a new external, polarization-insensitive differential interference contrast (DIC) module specifically adapted for detecting defects in semiconductor wafers. We obtained defect signal enhancement relative to the surrounding wafer pattern when compared with bright-field imaging. The new DIC module proposed is based on a shearing interferometer that connects externally at the output port of an optical microscope and enables imaging thin samples, such as wafer defects. This module does not require polarization optics (such as Wollaston or Nomarski prisms) and is insensitive to polarization, unlike traditional DIC techniques. In addition, it provides full control of the DIC shear and orientation, which allows obtaining a differential phase image directly on the camera (with no further digital processing) while enhancing defect detection capabilities, even if the size of the defect is smaller than the resolution limit. Our technique has the potential of future integration into semiconductor production lines.

  18. Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

    NASA Astrophysics Data System (ADS)

    Pohl, D.-L.; Hemperek, T.; Caicedo, I.; Gonella, L.; Hügging, F.; Janssen, J.; Krüger, H.; Macchiolo, A.; Owtscharenko, N.; Vigani, L.; Wermes, N.

    2017-06-01

    Pixel sensors using 8'' CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 × 1015 neq cm-2. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

  19. Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

    NASA Astrophysics Data System (ADS)

    Pa, Pai-Shan

    2010-01-01

    A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

  20. Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

    PubMed

    Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

    2014-06-01

    Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

  1. Methodology For Reduction Of Sampling On The Visual Inspection Of Developed And Etched Wafers

    NASA Astrophysics Data System (ADS)

    van de Ven, Jamie S.; Khorasani, Fred

    1989-07-01

    There is a lot of inspection in the manufacturing of semiconductor devices. Generally, the more important a manufacturing step, the higher is the level of inspection. In some cases 100% of the wafers are inspected after certain steps. Inspection is a non-value added and expensive activity. It requires an army of "inspectors," often times expensive equipment and becomes a "bottle neck" when the level of inspection is high. Although inspection helps identify quality problems, it hurts productivity. The new management, quality and productivity philosophies recommend against over inspection. [Point #3 in Dr. Deming's 14 Points for Management (1)] 100% inspection is quite unnecessary . Often the nature of a process allows us to reduce inspection drastically and still maintain a high level of confidence in quality. In section 2, we discuss such situations and show that some elementary probability theory allows us to determine sample sizes and measure the chances of catching a bad "lot" and accepting a good lot. In section 3, we provide an example and application of the theory, and make a few comments on money and time saved because of this work. Finally, in section 4, we draw some conclusions about the new quality and productivity philosophies and how applied statisticians and engineers should study every situation individually and avoid blindly using methods and tables given in books.

  2. Development of Probabilistic Structural Analysis Integrated with Manufacturing Processes

    NASA Technical Reports Server (NTRS)

    Pai, Shantaram S.; Nagpal, Vinod K.

    2007-01-01

    An effort has been initiated to integrate manufacturing process simulations with probabilistic structural analyses in order to capture the important impacts of manufacturing uncertainties on component stress levels and life. Two physics-based manufacturing process models (one for powdered metal forging and the other for annular deformation resistance welding) have been linked to the NESSUS structural analysis code. This paper describes the methodology developed to perform this integration including several examples. Although this effort is still underway, particularly for full integration of a probabilistic analysis, the progress to date has been encouraging and a software interface that implements the methodology has been developed. The purpose of this paper is to report this preliminary development.

  3. Engineering aspects of rate-related processes in food manufacturing.

    PubMed

    Adachi, Shuji

    2015-01-01

    Many rate-related phenomena occur in food manufacturing processes. This review addresses four of them, all of which are topics that the author has studied in order to design food manufacturing processes that are favorable from the standpoint of food engineering. They include chromatographic separation through continuous separation with a simulated moving adsorber, lipid oxidation kinetics in emulsions and microencapsulated systems, kinetic analysis and extraction in subcritical water, and water migration in pasta.

  4. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    NASA Astrophysics Data System (ADS)

    Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

    2017-06-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

  5. Automotive Manufacturing Processes. Volume V - Manufacturing Processes and Equipment for the Mass Production and Assembly of Motor Vehicles

    DOT National Transportation Integrated Search

    1981-02-01

    Extensive material substitution and resizing of the domestic automotive fleet, as well as the introduction of new technologies, will require major changes in the techniques and equipment used in the various manufacturing processes employed in the pro...

  6. Data quality and processing for decision making: divergence between corporate strategy and manufacturing processes

    NASA Astrophysics Data System (ADS)

    McNeil, Ronald D.; Miele, Renato; Shaul, Dennis

    2000-10-01

    Information technology is driving improvements in manufacturing systems. Results are higher productivity and quality. However, corporate strategy is driven by a number of factors and includes data and pressure from multiple stakeholders, which includes employees, managers, executives, stockholders, boards, suppliers and customers. It is also driven by information about competitors and emerging technology. Much information is based on processing of data and the resulting biases of the processors. Thus, stakeholders can base inputs on faulty perceptions, which are not reality based. Prior to processing, data used may be inaccurate. Sources of data and information may include demographic reports, statistical analyses, intelligence reports (e.g., marketing data), technology and primary data collection. The reliability and validity of data as well as the management of sources and information is critical element to strategy formulation. The paper explores data collection, processing and analyses from secondary and primary sources, information generation and report presentation for strategy formulation and contrast this with data and information utilized to drive internal process such as manufacturing. The hypothesis is that internal process, such as manufacturing, are subordinate to corporate strategies. The impact of possible divergence in quality of decisions at the corporate level on IT driven, quality-manufacturing processes based on measurable outcomes is significant. Recommendations for IT improvements at the corporate strategy level are given.

  7. Tracking the course of the manufacturing process in selective laser melting

    NASA Astrophysics Data System (ADS)

    Thombansen, U.; Gatej, A.; Pereira, M.

    2014-02-01

    An innovative optical train for a selective laser melting based manufacturing system (SLM) has been designed under the objective to track the course of the SLM process. In this, the thermal emission from the melt pool and the geometric properties of the interaction zone are addressed by applying a pyrometer and a camera system respectively. The optical system is designed such that all three radiations from processing laser, thermal emission and camera image are coupled coaxially and that they propagate on the same optical axis. As standard f-theta lenses for high power applications inevitably lead to aberrations and divergent optical axes for increasing deflection angles in combination with multiple wavelengths, a pre-focus system is used to implement a focusing unit which shapes the beam prior to passing the scanner. The sensor system records synchronously the current position of the laser beam, the current emission from the melt pool and an image of the interaction zone. Acquired data of the thermal emission is being visualized after processing which allows an instant evaluation of the course of the process at any position of each layer. As such, it provides a fully detailed history of the product This basic work realizes a first step towards self-optimization of the manufacturing process by providing information about quality relevant events during manufacture. The deviation from the planned course of the manufacturing process to the actual course of the manufacturing process can be used to adapt the manufacturing strategy from one layer to the next. In the current state, the system can be used to facilitate the setup of the manufacturing system as it allows identification of false machine settings without having to analyze the work piece.

  8. Using process monitor wafers to understand directed self-assembly defects

    NASA Astrophysics Data System (ADS)

    Cao, Yi; Her, YoungJun; Delgadillo, Paulina R.; Vandenbroeck, Nadia; Gronheid, Roel; Chan, Boon Teik; Hashimoto, Yukio; Romo, Ainhoa; Somervell, Mark; Nafus, Kathleen; Nealey, Paul F.

    2013-03-01

    As directed self-assembly (DSA) has gained momentum over the past few years, questions about its application to high volume manufacturing have arisen. One of the major concerns is about the fundamental limits of defectivity that can be attained with the technology. If DSA applications demonstrate defectivity that rivals of traditional lithographic technologies, the pathway to the cost benefits of the technology creates a very compelling case for its large scale implementation. To address this critical question, our team at IMEC has established a process monitor flow to track the defectivity behaviors of an exemplary chemo-epitaxy application for printing line/space patterns. Through establishing this baseline, we have been able to understand both traditional lithographic defect sources in new materials as well as new classes of assembly defects associated with DSA technology. Moreover, we have explored new materials and processing to lower the level of the defectivity baseline. The robustness of the material sets and process is investigated as well. In this paper, we will report the understandings learned from the IMEC DSA process monitor flow.

  9. Pattern centric design based sensitive patterns and process monitor in manufacturing

    NASA Astrophysics Data System (ADS)

    Hsiang, Chingyun; Cheng, Guojie; Wu, Kechih

    2017-03-01

    When design rule is mitigating to smaller dimension, process variation requirement is tighter than ever and challenges the limits of device yield. Masks, lithography, etching and other processes have to meet very tight specifications in order to keep defect and CD within the margins of the process window. Conventionally, Inspection and metrology equipments are utilized to monitor and control wafer quality in-line. In high throughput optical inspection, nuisance and review-classification become a tedious labor intensive job in manufacturing. Certain high-resolution SEM images are taken to validate defects after optical inspection. These high resolution SEM images catch not only optical inspection highlighted point, also its surrounding patterns. However, this pattern information is not well utilized in conventional quality control method. Using this complementary design based pattern monitor not only monitors and analyzes the variation of patterns sensitivity but also reduce nuisance and highlight defective patterns or killer defects. After grouping in either single or multiple layers, systematic defects can be identified quickly in this flow. In this paper, we applied design based pattern monitor in different layers to monitor process variation impacts on all kinds of patterns. First, the contour of high resolutions SEM image is extracted and aligned to design with offset adjustment and fine alignment [1]. Second, specified pattern rules can be applied on design clip area, the same size as SEM image, and form POI (pattern of interest) areas. Third, the discrepancy of contour and design measurement at different pattern types in measurement blocks. Fourth, defective patterns are reported by discrepancy detection criteria and pattern grouping [4]. Meanwhile, reported pattern defects are ranked by number and severity by discrepancy. In this step, process sensitive high repeatable systematic defects can be identified quickly Through this design based process pattern

  10. Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

    DOE PAGES

    Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; ...

    2015-10-15

    Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

  11. Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes

    Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

  12. A Digital Methodology for the Design Process of Aerospace Assemblies with Sustainable Composite Processes & Manufacture

    NASA Astrophysics Data System (ADS)

    McEwan, W.; Butterfield, J.

    2011-05-01

    The well established benefits of composite materials are driving a significant shift in design and manufacture strategies for original equipment manufacturers (OEMs). Thermoplastic composites have advantages over the traditional thermosetting materials with regards to sustainability and environmental impact, features which are becoming increasingly pertinent in the aerospace arena. However, when sustainability and environmental impact are considered as design drivers, integrated methods for part design and product development must be developed so that any benefits of sustainable composite material systems can be assessed during the design process. These methods must include mechanisms to account for process induced part variation and techniques related to re-forming, recycling and decommissioning, which are in their infancy. It is proposed in this paper that predictive techniques related to material specification, part processing and product cost of thermoplastic composite components, be integrated within a Through Life Management (TLM) product development methodology as part of a larger strategy of product system modeling to improve disciplinary concurrency, realistic part performance, and to place sustainability at the heart of the design process. This paper reports the enhancement of digital manufacturing tools as a means of drawing simulated part manufacturing scenarios, real time costing mechanisms, and broader lifecycle performance data capture into the design cycle. The work demonstrates predictive processes for sustainable composite product manufacture and how a Product-Process-Resource (PPR) structure can be customised and enhanced to include design intent driven by `Real' part geometry and consequent assembly. your paper.

  13. Manufacturing Process Applications Team (MATeam)

    NASA Technical Reports Server (NTRS)

    1978-01-01

    The activities of the Manufacturing Process Applications Team concerning the promotion of joint Industry/Federal Agency/NASA funded research and technology operating plan (RTOP) programs are reported. Direct transfers occurred in cutting tools, laser wire stripping, soldering, and portable X-ray unit technology. TROP program funding approval was obtained for the further development of the cutting tool Sialon and development of an automated nondestructive fracture toughness testing system.

  14. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

    PubMed

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-05-13

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

  15. Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

    NASA Astrophysics Data System (ADS)

    Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

    2004-08-01

    The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

  16. Manufacturing process of nanofluidics using afm probe

    NASA Astrophysics Data System (ADS)

    Karingula, Varun Kumar

    A new process for fabricating a nano fluidic device that can be used in medical application is developed and demonstrated. Nano channels are fabricated using a nano tip in indentation mode on AFM (Atomic Force Microscopy). The nano channels are integrated between the micro channels and act as a filter to separate biomolecules. Nano channels of 4 to7 m in length, 80nm in width, and at varying depths from 100nm to 850 nm allow the resulting device to separate selected groups of lysosomes and other viruses. Sharply developed vertical micro channels are produced from a deep reaction ion etching followed by deposition of different materials, such as gold and polymers, on the top surface, allowing the study of alternative ways of manufacturing a nanofluidic device. PDMS (Polydimethylsiloxane) bonding is performed to close the top surface of the device. An experimental setup is used to test and validate the device by pouring fluid through the channels. A detailed cost evaluation is conducted to compare the economical merits of the proposed process. It is shown that there is a 47:7% manufacturing time savings and a 60:6% manufacturing cost savings.

  17. Mining manufacturing data for discovery of high productivity process characteristics.

    PubMed

    Charaniya, Salim; Le, Huong; Rangwala, Huzefa; Mills, Keri; Johnson, Kevin; Karypis, George; Hu, Wei-Shou

    2010-06-01

    Modern manufacturing facilities for bioproducts are highly automated with advanced process monitoring and data archiving systems. The time dynamics of hundreds of process parameters and outcome variables over a large number of production runs are archived in the data warehouse. This vast amount of data is a vital resource to comprehend the complex characteristics of bioprocesses and enhance production robustness. Cell culture process data from 108 'trains' comprising production as well as inoculum bioreactors from Genentech's manufacturing facility were investigated. Each run constitutes over one-hundred on-line and off-line temporal parameters. A kernel-based approach combined with a maximum margin-based support vector regression algorithm was used to integrate all the process parameters and develop predictive models for a key cell culture performance parameter. The model was also used to identify and rank process parameters according to their relevance in predicting process outcome. Evaluation of cell culture stage-specific models indicates that production performance can be reliably predicted days prior to harvest. Strong associations between several temporal parameters at various manufacturing stages and final process outcome were uncovered. This model-based data mining represents an important step forward in establishing a process data-driven knowledge discovery in bioprocesses. Implementation of this methodology on the manufacturing floor can facilitate a real-time decision making process and thereby improve the robustness of large scale bioprocesses. 2010 Elsevier B.V. All rights reserved.

  18. Process science development at the Center for Optics Manufacturing

    NASA Astrophysics Data System (ADS)

    Pollicove, Harvey M.; Moore, Duncan T.; Golini, Donald

    1992-01-01

    The Center for Optics Manufacturing (COM) has organized a volunteer Process Science Committee that will cooperate in advancing the optical manufacturing sciences. The objective is to develop technical information and processes that improve manufacturing capability, especially in grinding and polishing technology. Chaired by Donald Golini of Litton Itek Optical Systems, the committee members are volunteers from several American Precision Optics Manufacturers Association (APOMA) companies and institutions. Many of the companies are also funding project elements. The committee will accelerate industry progress by integrating the research and development activities of cooperating APOMA companies and institutions involved in both COM and independent programs. In the short term, the effort concentrates on grinding and polishing process innovation. In later phases, the effort will aid in the design future generations of machines and processes. While the developments are directly adaptable to COM's OPTICAM program, the results will influence a wide range of innovation and application in all methods of optical fabrication. Several leaders in the field are participating in the research and development effort--Boston University, Eastman Kodak Company, Hughes Leitz Optical Technologies, Lawrence Livermore National Laboratory, Litton Itek Optical Systems, Melles Griot, Optical Components Inc., Precision Optical, Rank Pneumo, Schott Glass Technologies, Solution Technology, Texas Instruments, Tropel, and the universities of Arizona and Rochester. Other APOMA member companies will participate as resource needs grow. The collaboration is unique in the industry's history.

  19. Characterization of 193-nm resists for optical mask manufacturing

    NASA Astrophysics Data System (ADS)

    Fosshaug, Hans; Paulsson, Adisa; Berzinsh, Uldis; Magnusson, Helena

    2004-12-01

    The push for smaller linewidths and tighter critical dimension (CD) budgets forced manufacturers of optical pattern generators to move from traditional i-line to deep ultraviolet (DUV) resist processing. Entering the DUV area was not without pain. The process conditions, especially exposure times of a few hours, put very tough demands on the resist material itself. However, today 248nm laser writers are fully operating using a resist process that exhibits the requested resolution, CD uniformity and environmental stability. The continuous demands of CD performance made Micronic to investigate suitable resist candidate materials for the next generation optical writer using 193nm excimer laser exposure. This paper reports on resist benchmarking of one commercial as well as several newly developed resists. The resists were investigated using a wafer scanner. The data obtained illustrate the current performance of 193nm photoresists, and further demonstrate that despite good progress in resist formulation optimization, the status is still a bit from the required lithographic performance.

  20. Computational Process Modeling for Additive Manufacturing (OSU)

    NASA Technical Reports Server (NTRS)

    Bagg, Stacey; Zhang, Wei

    2015-01-01

    Powder-Bed Additive Manufacturing (AM) through Direct Metal Laser Sintering (DMLS) or Selective Laser Melting (SLM) is being used by NASA and the Aerospace industry to "print" parts that traditionally are very complex, high cost, or long schedule lead items. The process spreads a thin layer of metal powder over a build platform, then melts the powder in a series of welds in a desired shape. The next layer of powder is applied, and the process is repeated until layer-by-layer, a very complex part can be built. This reduces cost and schedule by eliminating very complex tooling and processes traditionally used in aerospace component manufacturing. To use the process to print end-use items, NASA seeks to understand SLM material well enough to develop a method of qualifying parts for space flight operation. Traditionally, a new material process takes many years and high investment to generate statistical databases and experiential knowledge, but computational modeling can truncate the schedule and cost -many experiments can be run quickly in a model, which would take years and a high material cost to run empirically. This project seeks to optimize material build parameters with reduced time and cost through modeling.

  1. Manufacture of Third-Generation Lentivirus for Preclinical Use, with Process Development Considerations for Translation to Good Manufacturing Practice.

    PubMed

    Gándara, Carolina; Affleck, Valerie; Stoll, Elizabeth Ann

    2018-02-01

    Lentiviral vectors are used in laboratories around the world for in vivo and ex vivo delivery of gene therapies, and increasingly clinical investigation as well as preclinical applications. The third-generation lentiviral vector system has many advantages, including high packaging capacity, stable gene expression in both dividing and post-mitotic cells, and low immunogenicity in the recipient organism. Yet, the manufacture of these vectors is challenging, especially at high titers required for direct use in vivo, and further challenges are presented by the process of translating preclinical gene therapies toward manufacture of products for clinical investigation. The goals of this paper are to report the protocol for manufacturing high-titer third-generation lentivirus for preclinical testing and to provide detailed information on considerations for translating preclinical viral vector manufacture toward scaled-up platforms and processes in order to make gene therapies under Good Manufacturing Practice that are suitable for clinical trials.

  2. Multi-functional micro electromechanical devices and method of bulk manufacturing same

    NASA Technical Reports Server (NTRS)

    Okojie, Robert S. (Inventor)

    2004-01-01

    A method of bulk manufacturing SiC sensors is disclosed and claimed. Materials other than SiC may be used as the substrate material. Sensors requiring that the SiC substrate be pierced are also disclosed and claimed. A process flow reversal is employed whereby the metallization is applied first before the recesses are etched into or through the wafer. Aluminum is deposited on the entire planar surface of the metallization. Photoresist is spun onto the substantially planar surface of the Aluminum which is subsequently masked (and developed and removed). Unwanted Aluminum is etched with aqueous TMAH and subsequently the metallization is dry etched. Photoresist is spun onto the still substantially planar surface of Aluminum and oxide and then masked (and developed and removed) leaving the unimidized photoresist behind. Next, ITO is applied over the still substantially planar surface of Aluminum, oxide and unimidized photoresist. Unimidized and exposed photoresist and ITO directly above it are removed with Acetone. Next, deep reactive ion etching attacks exposed oxide not protected by ITO. Finally, hot phosphoric acid removes the Al and ITO enabling wires to connect with the metallization. The back side of the SiC wafer may be also be etched.

  3. Study of process variables associated with manufacturing hermetically-sealed nickel-cadmium cells

    NASA Technical Reports Server (NTRS)

    Miller, L.

    1974-01-01

    A two year study of the major process variables associated with the manufacturing process for sealed, nickel-cadmium, areospace cells is summarized. Effort was directed toward identifying the major process variables associated with a manufacturing process, experimentally assessing each variable's effect, and imposing the necessary changes (optimization) and controls for the critical process variables to improve results and uniformity. A critical process variable associated with the sintered nickel plaque manufacturing process was identified as the manual forming operation. Critical process variables identified with the positive electrode impregnation/polarization process were impregnation solution temperature, free acid content, vacuum impregnation, and sintered plaque strength. Positive and negative electrodes were identified as a major source of carbonate contamination in sealed cells.

  4. Intelligent Processing Equipment Developments Within the Navy's Manufacturing Technology Centers of Excellence

    NASA Technical Reports Server (NTRS)

    Nanzetta, Philip

    1992-01-01

    The U.S. Navy has had an active Manufacturing Technology (MANTECH) Program aimed at developing advanced production processes and equipment since the late-1960's. During the past decade, however, the resources of the MANTECH program were concentrated in Centers of Excellence. Today, the Navy sponsors four manufacturing technology Centers of Excellence: the Automated Manufacturing Research Facility (AMRF); the Electronics Manufacturing Productivity Facility (EMPF); the National Center for Excellence in Metalworking Technology (NCEMT); and the Center of Excellence for Composites Manufacturing Technology (CECMT). This paper briefly describes each of the centers and summarizes typical Intelligent Equipment Processing (IEP) projects that were undertaken.

  5. A simulation study on garment manufacturing process

    NASA Astrophysics Data System (ADS)

    Liong, Choong-Yeun; Rahim, Nur Azreen Abdul

    2015-02-01

    Garment industry is an important industry and continues to evolve in order to meet the consumers' high demands. Therefore, elements of innovation and improvement are important. In this work, research studies were conducted at a local company in order to model the sewing process of clothes manufacturing by using simulation modeling. Clothes manufacturing at the company involves 14 main processes, which are connecting the pattern, center sewing and side neating, pockets sewing, backside-sewing, attaching the front and back, sleeves preparation, attaching the sleeves and over lock, collar preparation, collar sewing, bottomedge sewing, buttonholing sewing, removing excess thread, marking button, and button cross sewing. Those fourteen processes are operated by six tailors only. The last four sets of processes are done by a single tailor. Data collection was conducted by on site observation and the probability distribution of processing time for each of the processes is determined by using @Risk's Bestfit. Then a simulation model is developed using Arena Software based on the data collected. Animated simulation model is developed in order to facilitate understanding and verifying that the model represents the actual system. With such model, what if analysis and different scenarios of operations can be experimented with virtually. The animation and improvement models will be presented in further work.

  6. Development of a novel cold forging process to manufacture eccentric shafts

    NASA Astrophysics Data System (ADS)

    Pasler, Lukas; Liewald, Mathias

    2018-05-01

    Since the commercial usage of compact combustion engines, eccentric shafts have been used to transform translational into rotational motion. Over the years, several processes to manufacture these eccentric shafts or crankshafts have been developed. Especially for single-cylinder engines manufactured in small quantities, built crankshafts disclose advantages regarding tooling costs and performance. Those manufacturing processes do have one thing in common: They are all executed at elevated temperatures to enable the material to be formed to high forming degree. In this paper, a newly developed cold forging process is presented, which combines lateral extrusion and shifting for manufacturing a crank in one forming operation at room temperature. In comparison to the established upsetting and shifting methods to manufacture such components, the tool cavity or crank web thickness remains constant. Therefore, the developed new process presented in this paper consists of a combination of shifting and extrusion of the billet, which allows pushing material into the forming zone during shifting. In order to reduce the tensile stresses induced by the shifting process, compressive stresses are superimposed. It is expected that the process limits will be expanded regarding the horizontal displacement and form filling. In the following report, the simulation and design of the tooling concept are presented. Experiments were conducted and compared with corresponding simulation results afterwards.

  7. Process for manufacturing tantalum capacitors

    DOEpatents

    Lauf, Robert J.; Holcombe, Cressie E.; Dykes, Norman L.

    1993-01-01

    A process for manufacturing tantalum capacitors in which microwave energy is used to sinter a tantalum powder compact in order to achieve higher surface area and improved dielectric strength. The process comprises cold pressing tantalum powder with organic binders and lubricants to form a porous compact. After removal of the organics, the tantalum compact is heated to 1300.degree. to 2000.degree. C. by applying microwave radiation. Said compact is then anodized to form a dielectric oxide layer and infiltrated with a conductive material such as MnO.sub.2. Wire leads are then attached to form a capacitor to said capacitor is hermetically packaged to form the finished product.

  8. Process for manufacturing tantalum capacitors

    DOEpatents

    Lauf, R.J.; Holcombe, C.E.; Dykes, N.L.

    1993-02-02

    A process for manufacturing tantalum capacitors in which microwave energy is used to sinter a tantalum powder compact in order to achieve higher surface area and improved dielectric strength. The process comprises cold pressing tantalum powder with organic binders and lubricants to form a porous compact. After removal of the organics, the tantalum compact is heated to 1,300 to 2,000 C by applying microwave radiation. Said compact is then anodized to form a dielectric oxide layer and infiltrated with a conductive material such as MnO[sub 2]. Wire leads are then attached to form a capacitor to said capacitor is hermetically packaged to form the finished product.

  9. Uniform lateral etching of tungsten in deep trenches utilizing reaction-limited NF3 plasma process

    NASA Astrophysics Data System (ADS)

    Kofuji, Naoyuki; Mori, Masahito; Nishida, Toshiaki

    2017-06-01

    The reaction-limited etching of tungsten (W) with NF3 plasma was performed in an attempt to achieve the uniform lateral etching of W in a deep trench, a capability required by manufacturing processes for three-dimensional NAND flash memory. Reaction-limited etching was found to be possible at high pressures without ion irradiation. An almost constant etching rate that showed no dependence on NF3 pressure was obtained. The effect of varying the wafer temperature was also examined. A higher wafer temperature reduced the threshold pressure for reaction-limited etching and also increased the etching rate in the reaction-limited region. Therefore, the control of the wafer temperature is crucial to controlling the etching amount by this method. We found that the uniform lateral etching of W was possible even in a deep trench where the F radical concentration was low.

  10. A Wafer-Bonded, Floating Element Shear-Stress Sensor Using a Geometric Moire Optical Transduction Technique

    NASA Technical Reports Server (NTRS)

    Horowitz, Stephen; Chen, Tai-An; Chandrasekaran, Venkataraman; Tedjojuwono, Ken; Cattafesta, Louis; Nishida, Toshikazu; Sheplak, Mark

    2004-01-01

    This paper presents a geometric Moir optical-based floating-element shear stress sensor for wind tunnel turbulence measurements. The sensor was fabricated using an aligned wafer-bond/thin-back process producing optical gratings on the backside of a floating element and on the top surface of the support wafer. Measured results indicate a static sensitivity of 0.26 microns/Pa, a resonant frequency of 1.7 kHz, and a noise floor of 6.2 mPa/(square root)Hz.

  11. Intrinsic Gettering in Nitrogen-Doped and Hydrogen-Annealed Czochralski-Grown Silicon Wafers

    NASA Astrophysics Data System (ADS)

    Goto, Hiroyuki; Pan, Lian-Sheng; Tanaka, Masafumi; Kashima, Kazuhiko

    2001-06-01

    The properties of nitrogen-doped and hydrogen-annealed Czochralski-grown silicon (NHA-CZ-Si) wafers were investigated in this study. The quality of the subsurface was investigated by monitoring the generation lifetime of minority carriers, as measured by the capacitance-time measurements of a metal oxide silicon capacitor (MOS C-t). The intrinsic gettering (IG) ability was investigated by determining the nickel concentration on the surface and in the subsurface as measured by graphite furnace atomic absorption spectrometry (GFAAS) after the wafer was deliberately contaminated with nickel. From the results obtained, the generation lifetimes of these NHA-CZ-Si wafers were determined to be almost the same as, or a little longer than those of epitaxial wafers, and the IG ability was proportional to the total volume of oxygen precipitates [i.e., bulk micro defects (BMDs)], which was influenced by the oxygen and nitrogen concentrations in the wafers. Therefore, it is suggested that the subsurface of the NHA-CZ-Si wafers is of good quality and the IG capacity is controllable by the nitrogen and oxygen concentrations in the wafers.

  12. Bulk lifetime characterization of corona charged silicon wafers with high resistivity by means of microwave detected photoconductivity

    NASA Astrophysics Data System (ADS)

    Engst, C. R.; Rommel, M.; Bscheid, C.; Eisele, I.; Kutter, C.

    2017-12-01

    Minority carrier lifetime (lifetime) measurements are performed on corona-charged silicon wafers by means of Microwave Detected Photoconductivity (MDP). The corona charge is deposited on the front and back sides of oxidized wafers in order to adjust accumulation conditions. Once accumulation is established, interface recombination is suppressed and bulk lifetimes are obtained. Neither contacts nor non-CMOS compatible preparation techniques are required in order to achieve accumulation conditions, which makes the method ideally suited for inline characterization. The novel approach, termed ChargedMDP (CMDP), is used to investigate neutron transmutation doped (NTD) float zone silicon with resistivities ranging from 6.0 to 8.2 kΩ cm. The bulk properties of 150 mm NTD wafers are analyzed in detail by performing measurements of the carrier lifetime and the steady-state photoconductivity at various injection levels. The results are compared with MDP measurements of uncharged wafers as well as to the established charged microwave detected Photoconductance Decay (charge-PCD) method. Besides analyzing whole wafers, CMDP measurements are performed on oxide test-structures on a patterned wafer. Finally, the oxide properties are characterized by means of charge-PCD as well as capacitance-voltage measurements. With CMDP, average bulk lifetimes up to 33.1 ms are measured, whereby significant variations are observed among wafers, which are produced out of the same ingot but oxidized in different furnaces. The observed lifetime variations are assumed to be caused by contaminations, which are introduced during the oxidation process. The results obtained by CMDP were neither accessible by means of conventional MDP measurements of uncharged wafers nor with the established charge-PCD method.

  13. Analysis of the influence of manufacturing and alignment related errors on an optical tweezer system

    NASA Astrophysics Data System (ADS)

    Kampmann, R.; Sinzinger, S.

    2014-12-01

    In this work we present the design process as well as experimental results of an optical system for trapping particles in air. For positioning applications of micro-sized objects onto a glass wafer we developed a highly efficient optical tweezer. The focus of this paper is the iterative design process where we combine classical optics design software with a ray optics based force simulation tool. Thus we can find the best compromise which matches the optical systems restrictions with stable trapping conditions. Furthermore we analyze the influence of manufacturing related tolerances and errors in the alignment process of the optical elements on the optical forces. We present the design procedure for the necessary optical elements as well as experimental results for the aligned system.

  14. Through-wafer interrogation of microstructure motion for MEMS feedback control

    NASA Astrophysics Data System (ADS)

    Dawson, Jeremy M.; Chen, Jingdong; Brown, Kolin S.; Famouri, Parviz F.; Hornak, Lawrence A.

    1999-09-01

    Closed-loop MEMS control enables mechanical microsystems to adapt to the demands of the environment which they are actuating opening a new window of opportunity for future MEMS applications. Planar diffractive optical microsystems have the potential to enable the integrated optical interrogation of MEMS microstructure position fully decoupled from the means of mechanical actuation which is central to realization of feedback control. This paper presents the results of initial research evaluating through-wafer optical microsystems for MEMS integrated optical monitoring. Positional monitoring results obtained from a 1.3 micrometer wavelength through- wafer free-space optical probe of a lateral comb resonator fabricated using the Multi-User MEMS Process Service (MUMPS) are presented. Given the availability of positional information via probe signal feedback, a simulation of the application of nonlinear sliding control is presented illustrating position control of the lateral comb resonator structure.

  15. Manufacture of Third-Generation Lentivirus for Preclinical Use, with Process Development Considerations for Translation to Good Manufacturing Practice

    PubMed Central

    Gándara, Carolina; Affleck, Valerie; Stoll, Elizabeth Ann

    2018-01-01

    Lentiviral vectors are used in laboratories around the world for in vivo and ex vivo delivery of gene therapies, and increasingly clinical investigation as well as preclinical applications. The third-generation lentiviral vector system has many advantages, including high packaging capacity, stable gene expression in both dividing and post-mitotic cells, and low immunogenicity in the recipient organism. Yet, the manufacture of these vectors is challenging, especially at high titers required for direct use in vivo, and further challenges are presented by the process of translating preclinical gene therapies toward manufacture of products for clinical investigation. The goals of this paper are to report the protocol for manufacturing high-titer third-generation lentivirus for preclinical testing and to provide detailed information on considerations for translating preclinical viral vector manufacture toward scaled-up platforms and processes in order to make gene therapies under Good Manufacturing Practice that are suitable for clinical trials. PMID:29212357

  16. Wafer plane inspection for advanced reticle defects

    NASA Astrophysics Data System (ADS)

    Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

    2008-05-01

    Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

  17. A review of manufacturing metrology for improved reliability of silicon photovoltaic modules

    NASA Astrophysics Data System (ADS)

    Davis, Kristopher O.; Walters, Joseph; Schneller, Eric; Seigneur, Hubert; Brooker, R. Paul; Scardera, Giuseppe; Rodgers, Marianne P.; Mohajeri, Nahid; Shiradkar, Narendra; Dhere, Neelkanth G.; Wohlgemuth, John; Rudack, Andrew C.; Schoenfeld, Winston V.

    2014-10-01

    In this work, the use of manufacturing metrology across the supply chain to improve crystalline silicon (c-Si) photovoltaic (PV) module reliability and durability is addressed. Additionally, an overview and summary of a recent extensive literature survey of relevant measurement techniques aimed at reducing or eliminating the probability of field failures is presented. An assessment of potential gaps is also given, wherein the PV community could benefit from new research and demonstration efforts. This review is divided into three primary areas representing different parts of the c-Si PV supply chain: (1) feedstock production, crystallization and wafering; (2) cell manufacturing; and (3) module manufacturing.

  18. Silicon Valley's Processing Needs versus San Jose State University's Manufacturing Systems Processing Component: Implications for Industrial Technology

    ERIC Educational Resources Information Center

    Obi, Samuel C.

    2004-01-01

    Manufacturing professionals within universities tend to view manufacturing systems from a global perspective. This perspective tends to assume that manufacturing processes are employed equally in every manufacturing enterprise, irrespective of the geography and the needs of the people in those diverse regions. But in reality local and societal…

  19. Evaluation of anti-sticking layers performances for 200mm wafer scale Smart NILTM process through surface and defectivity characterizations

    NASA Astrophysics Data System (ADS)

    Delachat, F.; Phillipe, J.-C.; Larrey, V.; Fournel, F.; Bos, S.; Teyssèdre, H.; Chevalier, Xavier; Nicolet, Célia; Navarro, Christophe; Cayrefourcq, Ian

    2018-03-01

    In this work, an evaluation of various ASL processes for 200 mm wafer scale in the HERCULES® NIL equipment platform available at the CEA-Leti through the INSPIRE program is reported. The surface and adherence energies were correlated to the AFM and defectivity results in order to select the most promising ASL process for high resolution etch mask applications. The ASL performances of the selected process were evaluated by multiple working stamp fabrication using unpatterned and patterned masters though defectivity monitoring on optical based-inspection tools. Optical and SEM defect reviews were systematically performed. Multiple working stamps fabrication without degradation of the master defectivity was witnessed. This evaluation enabled to benchmark several ASL solutions based on the grafted technology develop by ARKEMA in order to reduce and optimize the soft stamp defectivity prior to its replication and therefore considerably reduce the final imprint defectivity for the Smart NIL process.

  20. The Imaging Properties of a Silicon Wafer X-Ray Telescope

    NASA Technical Reports Server (NTRS)

    Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

    1994-01-01

    Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

  1. Enhancing Manufacturing Process Education via Computer Simulation and Visualization

    ERIC Educational Resources Information Center

    Manohar, Priyadarshan A.; Acharya, Sushil; Wu, Peter

    2014-01-01

    Industrially significant metal manufacturing processes such as melting, casting, rolling, forging, machining, and forming are multi-stage, complex processes that are labor, time, and capital intensive. Academic research develops mathematical modeling of these processes that provide a theoretical framework for understanding the process variables…

  2. Feedstock powder processing research needs for additive manufacturing development

    DOE PAGES

    Anderson, Iver E.; White, Emma M. H.; Dehoff, Ryan

    2018-02-01

    Additive manufacturing (AM) promises to redesign traditional manufacturing by enabling the ultimate in agility for rapid component design changes in commercial products and for fabricating complex integrated parts. Here, by significantly increasing quality and yield of metallic alloy powders, the pace for design, development, and deployment of the most promising AM approaches can be greatly accelerated, resulting in rapid commercialization of these advanced manufacturing methods. By successful completion of a critical suite of processing research tasks that are intended to greatly enhance gas atomized powder quality and the precision and efficiency of powder production, researchers can help promote continued rapidmore » growth of AM. Finally, other powder-based or spray-based advanced manufacturing methods could also benefit from these research outcomes, promoting the next wave of sustainable manufacturing technologies for conventional and advanced materials.« less

  3. Feedstock powder processing research needs for additive manufacturing development

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Anderson, Iver E.; White, Emma M. H.; Dehoff, Ryan

    Additive manufacturing (AM) promises to redesign traditional manufacturing by enabling the ultimate in agility for rapid component design changes in commercial products and for fabricating complex integrated parts. Here, by significantly increasing quality and yield of metallic alloy powders, the pace for design, development, and deployment of the most promising AM approaches can be greatly accelerated, resulting in rapid commercialization of these advanced manufacturing methods. By successful completion of a critical suite of processing research tasks that are intended to greatly enhance gas atomized powder quality and the precision and efficiency of powder production, researchers can help promote continued rapidmore » growth of AM. Finally, other powder-based or spray-based advanced manufacturing methods could also benefit from these research outcomes, promoting the next wave of sustainable manufacturing technologies for conventional and advanced materials.« less

  4. Microstructure characterisation of Ti-6Al-4V from different additive manufacturing processes

    NASA Astrophysics Data System (ADS)

    Neikter, M.; Åkerfeldt, P.; Pederson, R.; Antti, M.-L.

    2017-10-01

    The focus of this work has been microstructure characterisation of Ti-6Al-4V manufactured by five different additive manufacturing (AM) processes. The microstructure features being characterised are the prior β size, grain boundary α and α lath thickness. It was found that material manufactured with powder bed fusion processes has smaller prior β grains than the material from directed energy deposition processes. The AM processes with fast cooling rate render in thinner α laths and also thinner, and in some cases discontinuous, grain boundary α. Furthermore, it has been observed that material manufactured with the directed energy deposition processes has parallel bands, except for one condition when the parameters were changed, while the powder bed fusion processes do not have any parallel bands.

  5. Discrete State Change Model of Manufacturing Quality to Aid Assembly Process Design

    NASA Astrophysics Data System (ADS)

    Koga, Tsuyoshi; Aoyama, Kazuhiro

    This paper proposes a representation model of the quality state change in an assembly process that can be used in a computer-aided process design system. In order to formalize the state change of the manufacturing quality in the assembly process, the functions, operations, and quality changes in the assembly process are represented as a network model that can simulate discrete events. This paper also develops a design method for the assembly process. The design method calculates the space of quality state change and outputs a better assembly process (better operations and better sequences) that can be used to obtain the intended quality state of the final product. A computational redesigning algorithm of the assembly process that considers the manufacturing quality is developed. The proposed method can be used to design an improved manufacturing process by simulating the quality state change. A prototype system for planning an assembly process is implemented and applied to the design of an auto-breaker assembly process. The result of the design example indicates that the proposed assembly process planning method outputs a better manufacturing scenario based on the simulation of the quality state change.

  6. Manufacturing processes for fabricating graphite/PMR 15 polyimide structural elements

    NASA Technical Reports Server (NTRS)

    Sheppard, C. H.; Hoggatt, J. T.; Symonds, W. A.

    1979-01-01

    Investigations were conducted to obtain commercially available graphite/PMR-15 polyimide prepreg, develop an autoclave manufacturing process, and demonstrate the process by manufacturing structural elements. Controls were established on polymer, prepreg, composite fabrication, and quality assurance, Successful material quality control and processes were demonstrated by fabricating major structural elements including flat laminates, hat sections, I beam sections, honeycomb sandwich structures, and molded graphite reinforced fittings. Successful fabrication of structural elements and simulated section of the space shuttle aft body flap shows that the graphite/PMR-15 polyimide system and the developed processes are ready for further evaluation in flight test hardware.

  7. Photolithography diagnostic expert systems: a systematic approach to problem solving in a wafer fabrication facility

    NASA Astrophysics Data System (ADS)

    Weatherwax Scott, Caroline; Tsareff, Christopher R.

    1990-06-01

    One of the main goals of process engineering in the semiconductor industry is to improve wafer fabrication productivity and throughput. Engineers must work continuously toward this goal in addition to performing sustaining and development tasks. To accomplish these objectives, managers must make efficient use of engineering resources. One of the tools being used to improve efficiency is the diagnostic expert system. Expert systems are knowledge based computer programs designed to lead the user through the analysis and solution of a problem. Several photolithography diagnostic expert systems have been implemented at the Hughes Technology Center to provide a systematic approach to process problem solving. This systematic approach was achieved by documenting cause and effect analyses for a wide variety of processing problems. This knowledge was organized in the form of IF-THEN rules, a common structure for knowledge representation in expert system technology. These rules form the knowledge base of the expert system which is stored in the computer. The systems also include the problem solving methodology used by the expert when addressing a problem in his area of expertise. Operators now use the expert systems to solve many process problems without engineering assistance. The systems also facilitate the collection of appropriate data to assist engineering in solving unanticipated problems. Currently, several expert systems have been implemented to cover all aspects of the photolithography process. The systems, which have been in use for over a year, include wafer surface preparation (HMDS), photoresist coat and softbake, align and expose on a wafer stepper, and develop inspection. These systems are part of a plan to implement an expert system diagnostic environment throughout the wafer fabrication facility. In this paper, the systems' construction is described, including knowledge acquisition, rule construction, knowledge refinement, testing, and evaluation. The roles

  8. Precision replenishable grinding tool and manufacturing process

    DOEpatents

    Makowiecki, D.M.; Kerns, J.A.; Blaedel, K.L.; Colella, N.J.; Davis, P.J.; Juntz, R.S.

    1998-06-09

    A reusable grinding tool consisting of a replaceable single layer of abrasive particles intimately bonded to a precisely configured tool substrate, and a process for manufacturing the grinding tool are disclosed. The tool substrate may be ceramic or metal and the abrasive particles are preferably diamond, but may be cubic boron nitride. The manufacturing process involves: coating a configured tool substrate with layers of metals, such as titanium, copper and titanium, by physical vapor deposition (PVD); applying the abrasive particles to the coated surface by a slurry technique; and brazing the abrasive particles to the tool substrate by alloying the metal layers. The precision control of the composition and thickness of the metal layers enables the bonding of a single layer or several layers of micron size abrasive particles to the tool surface. By the incorporation of an easily dissolved metal layer in the composition such allows the removal and replacement of the abrasive particles, thereby providing a process for replenishing a precisely machined grinding tool with fine abrasive particles, thus greatly reducing costs as compared to replacing expensive grinding tools. 11 figs.

  9. Precision replenishable grinding tool and manufacturing process

    DOEpatents

    Makowiecki, Daniel M.; Kerns, John A.; Blaedel, Kenneth L.; Colella, Nicholas J.; Davis, Pete J.; Juntz, Robert S.

    1998-01-01

    A reusable grinding tool consisting of a replaceable single layer of abrasive particles intimately bonded to a precisely configured tool substrate, and a process for manufacturing the grinding tool. The tool substrate may be ceramic or metal and the abrasive particles are preferably diamond, but may be cubic boron nitride. The manufacturing process involves: coating a configured tool substrate with layers of metals, such as titanium, copper and titanium, by physical vapor deposition (PVD); applying the abrasive particles to the coated surface by a slurry technique; and brazing the abrasive particles to the tool substrate by alloying the metal layers. The precision control of the composition and thickness of the metal layers enables the bonding of a single layer or several layers of micron size abrasive particles to the tool surface. By the incorporation of an easily dissolved metal layer in the composition such allows the removal and replacement of the abrasive particles, thereby providing a process for replenishing a precisely machined grinding tool with fine abrasive particles, thus greatly reducing costs as compared to replacing expensive grinding tools.

  10. Automotive Manufacturing Processes. Volume IV - Metal Stamping and Plastic Forming Processes

    DOT National Transportation Integrated Search

    1981-02-01

    Extensive material substitution and resizing of the domestic automotive fleet, as well as the introduction of new technologies, will require major changes in the techniques and equipment used in the various manufacturing processes employed in the pro...

  11. Biocompatibility of hydroxyapatite scaffolds processed by lithography-based additive manufacturing.

    PubMed

    Tesavibul, Passakorn; Chantaweroad, Surapol; Laohaprapanon, Apinya; Channasanon, Somruethai; Uppanan, Paweena; Tanodekaew, Siriporn; Chalermkarnnon, Prasert; Sitthiseripratip, Kriskrai

    2015-01-01

    The fabrication of hydroxyapatite scaffolds for bone tissue engineering applications by using lithography-based additive manufacturing techniques has been introduced due to the abilities to control porous structures with suitable resolutions. In this research, the use of hydroxyapatite cellular structures, which are processed by lithography-based additive manufacturing machine, as a bone tissue engineering scaffold was investigated. The utilization of digital light processing system for additive manufacturing machine in laboratory scale was performed in order to fabricate the hydroxyapatite scaffold, of which biocompatibilities were eventually evaluated by direct contact and cell-culturing tests. In addition, the density and compressive strength of the scaffolds were also characterized. The results show that the hydroxyapatite scaffold at 77% of porosity with 91% of theoretical density and 0.36 MPa of the compressive strength are able to be processed. In comparison with a conventionally sintered hydroxyapatite, the scaffold did not present any cytotoxic signs while the viability of cells at 95.1% was reported. After 14 days of cell-culturing tests, the scaffold was able to be attached by pre-osteoblasts (MC3T3-E1) leading to cell proliferation and differentiation. The hydroxyapatite scaffold for bone tissue engineering was able to be processed by the lithography-based additive manufacturing machine while the biocompatibilities were also confirmed.

  12. INTEGRATION OF COST MODELS AND PROCESS SIMULATION TOOLS FOR OPTIMUM COMPOSITE MANUFACTURING PROCESS

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Pack, Seongchan; Wilson, Daniel; Aitharaju, Venkat

    Manufacturing cost of resin transfer molded composite parts is significantly influenced by the cycle time, which is strongly related to the time for both filling and curing of the resin in the mold. The time for filling can be optimized by various injection strategies, and by suitably reducing the length of the resin flow distance during the injection. The curing time can be reduced by the usage of faster curing resins, but it requires a high pressure injection equipment, which is capital intensive. Predictive manufacturing simulation tools that are being developed recently for composite materials are able to provide variousmore » scenarios of processing conditions virtually well in advance of manufacturing the parts. In the present study, we integrate the cost models with process simulation tools to study the influence of various parameters such as injection strategies, injection pressure, compression control to minimize high pressure injection, resin curing rate, and demold time on the manufacturing cost as affected by the annual part volume. A representative automotive component was selected for the study and the results are presented in this paper« less

  13. The presence of Enterococcus, coliforms and E. coli in a commercial yeast manufacturing process.

    PubMed

    O'Brien, S S; Lindsay, D; von Holy, A

    2004-07-01

    This study evaluated a typical commercial yeast manufacturing process for bacterial contamination. Product line samples of a commercial yeast manufacturing process and the corresponding seed yeast manufacturing process were obtained upstream from the final compressed and dry yeast products. All samples were analysed before (non-PI) and after preliminary incubation (PI) at 37 degrees C for 24 h. The PI procedure was incorporated for amplification of bacterial counts below the lower detection limit. Enterococcus, coliform and Escherichia coli counts were quantified by standard pour-plate techniques using selective media. Presence at all stages and progressive increases in counts of Enterococcus, coliforms and E. coli during processing in the commercial manufacturing operation suggested that the primary source of contamination of both compressed and dry yeast with these bacteria was the seed yeast manufacturing process and that contamination was amplified throughout the commercial yeast manufacturing process. This was confirmed by surveys of the seed yeast manufacturing process which indicated that contamination of the seed yeast with Enterococcus, coliforms and E. coli occurred during scale up of seed yeast biomass destined as inoculum for the commercial fermentation.

  14. Performance improvements of binary diffractive structures via optimization of the photolithography and dry etch processes

    NASA Astrophysics Data System (ADS)

    Welch, Kevin; Leonard, Jerry; Jones, Richard D.

    2010-08-01

    Increasingly stringent requirements on the performance of diffractive optical elements (DOEs) used in wafer scanner illumination systems are driving continuous improvements in their associated manufacturing processes. Specifically, these processes are designed to improve the output pattern uniformity of off-axis illumination systems to minimize degradation in the ultimate imaging performance of a lithographic tool. In this paper, we discuss performance improvements in both photolithographic patterning and RIE etching of fused silica diffractive optical structures. In summary, optimized photolithographic processes were developed to increase critical dimension uniformity and featuresize linearity across the substrate. The photoresist film thickness was also optimized for integration with an improved etch process. This etch process was itself optimized for pattern transfer fidelity, sidewall profile (wall angle, trench bottom flatness), and across-wafer etch depth uniformity. Improvements observed with these processes on idealized test structures (for ease of analysis) led to their implementation in product flows, with comparable increases in performance and yield on customer designs.

  15. Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

    NASA Astrophysics Data System (ADS)

    Ostapenko, S.; Tarasov, I.

    2000-04-01

    A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

  16. Raman spectroscopy as a process analytical technology for pharmaceutical manufacturing and bioprocessing.

    PubMed

    Esmonde-White, Karen A; Cuellar, Maryann; Uerpmann, Carsten; Lenain, Bruno; Lewis, Ian R

    2017-01-01

    Adoption of Quality by Design (QbD) principles, regulatory support of QbD, process analytical technology (PAT), and continuous manufacturing are major factors effecting new approaches to pharmaceutical manufacturing and bioprocessing. In this review, we highlight new technology developments, data analysis models, and applications of Raman spectroscopy, which have expanded the scope of Raman spectroscopy as a process analytical technology. Emerging technologies such as transmission and enhanced reflection Raman, and new approaches to using available technologies, expand the scope of Raman spectroscopy in pharmaceutical manufacturing, and now Raman spectroscopy is successfully integrated into real-time release testing, continuous manufacturing, and statistical process control. Since the last major review of Raman as a pharmaceutical PAT in 2010, many new Raman applications in bioprocessing have emerged. Exciting reports of in situ Raman spectroscopy in bioprocesses complement a growing scientific field of biological and biomedical Raman spectroscopy. Raman spectroscopy has made a positive impact as a process analytical and control tool for pharmaceutical manufacturing and bioprocessing, with demonstrated scientific and financial benefits throughout a product's lifecycle.

  17. Beryllium Manufacturing Processes

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Goldberg, A

    2006-06-30

    This report is one of a number of reports that will be combined into a handbook on beryllium. Each report covers a specific topic. To-date, the following reports have been published: (1) Consolidation and Grades of Beryllium; (2) Mechanical Properties of Beryllium and the Factors Affecting these Properties; (3) Corrosion and Corrosion Protection of Beryllium; (4) Joining of Beryllium; (5) Atomic, Crystal, Elastic, Thermal, Nuclear, and other Properties of Beryllium; and (6) Beryllium Coating (Deposition) Processes and the Influence of Processing Parameters on Properties and Microstructure. The conventional method of using ingot-cast material is unsuitable for manufacturing a beryllium product.more » Beryllium is a highly reactive metal with a high melting point, making it susceptible to react with mold-wall materials forming beryllium compounds (BeO, etc.) that become entrapped in the solidified metal. In addition, the grain size is excessively large, being 50 to 100 {micro}m in diameter, while grain sizes of 15 {micro}m or less are required to meet acceptable strength and ductility requirements. Attempts at refining the as-cast-grain size have been unsuccessful. Because of the large grain size and limited slip systems, the casting will invariably crack during a hot-working step, which is an important step in the microstructural-refining process. The high reactivity of beryllium together with its high viscosity (even with substantial superheat) also makes it an unsuitable candidate for precision casting. In order to overcome these problems, alternative methods have been developed for the manufacturing of beryllium. The vast majority of these methods involve the use of beryllium powders. The powders are consolidated under pressure in vacuum at an elevated temperature to produce vacuum hot-pressed (VHP) blocks and vacuum hot-isostatic-pressed (HIP) forms and billets. The blocks (typically cylindrical), which are produced over a wide range of sizes (up to 183 cm dia

  18. The metallurgy and processing science of metal additive manufacturing

    DOE PAGES

    Sames, William J.; List, III, Frederick Alyious; Pannala, Sreekanth; ...

    2016-03-07

    Here, additive Manufacturing (AM), widely known as 3D printing, is a method of manufacturing that forms parts from powder, wire, or sheets in a process that proceeds layer-by-layer.Many techniques (using many different names) have been developed to accomplish this via melting or solid - state joining. In this review, these techniques for producing metal parts are explored, with a focus on the science of metal AM: processing defects, heat transfer, solidification, solid- state precipitation, mechanical properties, and post-processing metallurgy. The various metal AM techniques are compared, with analysis of the strengths and limitations of each. Few alloys have been developedmore » for commercial production, but recent development efforts are presented as a path for the ongoing development of new materials for AM processes.« less

  19. Manufacturing Squares: An Integrative Statistical Process Control Exercise

    ERIC Educational Resources Information Center

    Coy, Steven P.

    2016-01-01

    In the exercise, students in a junior-level operations management class are asked to manufacture a simple product. Given product specifications, they must design a production process, create roles and design jobs for each team member, and develop a statistical process control plan that efficiently and effectively controls quality during…

  20. Final Air Toxics Standards for Clay Ceramics Manufacturing, Glass Manufacturing, and Secondary Nonferrous Metals Processing Area Sources Fact Sheet

    EPA Pesticide Factsheets

    This page contains a December 2007 fact sheet with information regarding the National Emissions Standards for Hazardous Air Pollutants (NESHAP) for Clay Ceramics Manufacturing, Glass Manufacturing, and Secondary Nonferrous Metals Processing Area Sources

  1. Wafer chamber having a gas curtain for extreme-UV lithography

    DOEpatents

    Kanouff, Michael P.; Ray-Chaudhuri, Avijit K.

    2001-01-01

    An EUVL device includes a wafer chamber that is separated from the upstream optics by a barrier having an aperture that is permeable to the inert gas. Maintaining an inert gas curtain in the proximity of a wafer positioned in a chamber of an extreme ultraviolet lithography device can effectively prevent contaminants from reaching the optics in an extreme ultraviolet photolithography device even though solid window filters are not employed between the source of reflected radiation, e.g., the camera, and the wafer. The inert gas removes the contaminants by entrainment.

  2. Cancer mortality among US workers employed in semiconductor wafer fabrication.

    PubMed

    Boice, John D; Marano, Donald E; Munro, Heather M; Chadda, Bandana K; Signorello, Lisa B; Tarone, Robert E; Blot, William J; McLaughlin, Joseph K

    2010-11-01

    To evaluate potential cancer risks in the US semiconductor wafer fabrication industry. A cohort of 100,081 semiconductor workers employed between 1968 and 2002 was studied. Standardized mortality ratios and relative risks (RRs) were estimated. Standardized mortality ratios were similar and significantly low among fabrication and nonfabrication workers for all causes (0.54 and 0.54) and all cancers (0.74 and 0.72). Internal comparisons also showed similar overall cancer risks among fabrication workers (RR = 0.98), including process equipment operators and process equipment service technicians (OP/EST) employed in cleanrooms (RR = 0.97), compared with nonfabrication workers. Nonsignificantly elevated RRs were observed for a few cancer sites among OP/EST workers, but the numbers of deaths were small and there were no trends of increasing risk with duration of employment. Work in the US semiconductor industry, including semiconductor wafer fabrication in cleanrooms, was not associated with increased cancer mortality overall or mortality from any specific form of cancer. However, due to the young average age of this cohort and its associated relatively low numbers of deaths, regular mortality updates of this semiconductor worker cohort are warranted.

  3. Cold Spraying of Armstrong Process Titanium Powder for Additive Manufacturing

    NASA Astrophysics Data System (ADS)

    MacDonald, D.; Fernández, R.; Delloro, F.; Jodoin, B.

    2017-04-01

    Titanium parts are ideally suited for aerospace applications due to their unique combination of high specific strength and excellent corrosion resistance. However, titanium as bulk material is expensive and challenging/costly to machine. Production of complex titanium parts through additive manufacturing looks promising, but there are still many barriers to overcome before reaching mainstream commercialization. The cold gas dynamic spraying process offers the potential for additive manufacturing of large titanium parts due to its reduced reactive environment, its simplicity to operate, and the high deposition rates it offers. A few challenges are to be addressed before the additive manufacturing potential of titanium by cold gas dynamic spraying can be reached. In particular, it is known that titanium is easy to deposit by cold gas dynamic spraying, but the deposits produced are usually porous when nitrogen is used as the carrier gas. In this work, a method to manufacture low-porosity titanium components at high deposition efficiencies is revealed. The components are produced by combining low-pressure cold spray using nitrogen as the carrier gas with low-cost titanium powder produced using the Armstrong process. The microstructure and mechanical properties of additive manufactured titanium components are investigated.

  4. A DMAIC approach for process capability improvement an engine crankshaft manufacturing process

    NASA Astrophysics Data System (ADS)

    Sharma, G. V. S. S.; Rao, P. Srinivasa

    2014-05-01

    The define-measure-analyze-improve-control (DMAIC) approach is a five-strata approach, namely DMAIC. This approach is the scientific approach for reducing the deviations and improving the capability levels of the manufacturing processes. The present work elaborates on DMAIC approach applied in reducing the process variations of the stub-end-hole boring operation of the manufacture of crankshaft. This statistical process control study starts with selection of the critical-to-quality (CTQ) characteristic in the define stratum. The next stratum constitutes the collection of dimensional measurement data of the CTQ characteristic identified. This is followed by the analysis and improvement strata where the various quality control tools like Ishikawa diagram, physical mechanism analysis, failure modes effects analysis and analysis of variance are applied. Finally, the process monitoring charts are deployed at the workplace for regular monitoring and control of the concerned CTQ characteristic. By adopting DMAIC approach, standard deviation is reduced from 0.003 to 0.002. The process potential capability index ( C P) values improved from 1.29 to 2.02 and the process performance capability index ( C PK) values improved from 0.32 to 1.45, respectively.

  5. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In thismore » manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented« less

  6. Wafer-scale growth of highly textured piezoelectric thin films by pulsed laser deposition for micro-scale sensors and actuators

    NASA Astrophysics Data System (ADS)

    Nguyen, M. D.; Tiggelaar, R.; Aukes, T.; Rijnders, G.; Roelof, G.

    2017-11-01

    Piezoelectric lead-zirconate-titanate (PZT) thin films were deposited on 4-inch (111)Pt/Ti/SiO2/Si(001) wafers using large-area pulsed laser deposition (PLD). This study was focused on the homogeneity in film thickness, microstructure, ferroelectric and piezoelectric properties of PZT thin films. The results indicated that the highly textured (001)-oriented PZT thin films with wafer-scale thickness homogeneity (990 nm ± 0.8%) were obtained. The films were fabricated into piezoelectric cantilevers through a MEMS microfabrication process. The measured longitudinal piezoelectric coefficient (d 33f = 210 pm/V ± 1.6%) and piezoelectric transverse coefficient (e 31f = -18.8 C/m2 ± 2.8%) were high and homogeneity across wafers. The high piezoelectric properties on Si wafers will extend industrial application of PZT thin films and further development of piezoMEMS.

  7. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    PubMed Central

    Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

    2013-01-01

    Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

  8. Considerations in the sterile manufacture of polymeric microneedle arrays.

    PubMed

    McCrudden, Maelíosa T C; Alkilani, Ahlam Zaid; Courtenay, Aaron J; McCrudden, Cian M; McCloskey, Bronagh; Walker, Christine; Alshraiedeh, Nida; Lutton, Rebecca E M; Gilmore, Brendan F; Woolfson, A David; Donnelly, Ryan F

    2015-02-01

    We describe, for the first time, considerations in the sterile manufacture of polymeric microneedle arrays. Microneedles (MN) made from dissolving polymeric matrices and loaded with the model drugs ovalbumin (OVA) and ibuprofen sodium and hydrogel-forming MN composed of "super-swelling" polymers and their corresponding lyophilised wafer drug reservoirs loaded with OVA and ibuprofen sodium were prepared aseptically or sterilised using commonly employed sterilisation techniques. Moist and dry heat sterilisation, understandably, damaged all devices, leaving aseptic production and gamma sterilisation as the only viable options. No measureable bioburden was detected in any of the prepared devices, and endotoxin levels were always below the US Food & Drug Administration limits (20 endotoxin units/device). Hydrogel-forming MN were unaffected by gamma irradiation (25 kGy) in terms of their physical properties or capabilities in delivering OVA and ibuprofen sodium across excised neonatal porcine skin in vitro. However, OVA content in dissolving MN (down from approximately 101.1 % recovery to approximately 58.3 % recovery) and lyophilised wafer-type drug reservoirs (down from approximately 99.7 % recovery to approximately 60.1 % recovery) was significantly reduced by gamma irradiation, while the skin permeation profile of ibuprofen sodium from gamma-irradiated dissolving MN was markedly different from their non-irradiated counterparts. It is clear that MN poses a very low risk to human health when used appropriately, as evidenced here by low endotoxin levels and absence of microbial contamination. However, if guarantees of absolute sterility of MN products are ultimately required by regulatory authorities, it will be necessary to investigate the effect of lower gamma doses on dissolving MN loaded with active pharmaceutical ingredients and lyophilised wafers loaded with biomolecules in order to avoid the expense and inconvenience of aseptic processing.

  9. Manufacturing process and material selection in concurrent collaborative design of MEMS devices

    NASA Astrophysics Data System (ADS)

    Zha, Xuan F.; Du, H.

    2003-09-01

    In this paper we present knowledge of an intensive approach and system for selecting suitable manufacturing processes and materials for microelectromechanical systems (MEMS) devices in concurrent collaborative design environment. In the paper, fundamental issues on MEMS manufacturing process and material selection such as concurrent design framework, manufacturing process and material hierarchies, and selection strategy are first addressed. Then, a fuzzy decision support scheme for a multi-criteria decision-making problem is proposed for estimating, ranking and selecting possible manufacturing processes, materials and their combinations. A Web-based prototype advisory system for the MEMS manufacturing process and material selection, WebMEMS-MASS, is developed based on the client-knowledge server architecture and framework to help the designer find good processes and materials for MEMS devices. The system, as one of the important parts of an advanced simulation and modeling tool for MEMS design, is a concept level process and material selection tool, which can be used as a standalone application or a Java applet via the Web. The running sessions of the system are inter-linked with webpages of tutorials and reference pages to explain the facets, fabrication processes and material choices, and calculations and reasoning in selection are performed using process capability and material property data from a remote Web-based database and interactive knowledge base that can be maintained and updated via the Internet. The use of the developed system including operation scenario, use support, and integration with an MEMS collaborative design system is presented. Finally, an illustration example is provided.

  10. Manufacturing process modeling for composite materials and structures, Sandia blade reliability collaborative

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Guest, Daniel A.; Cairns, Douglas S.

    2014-02-01

    The increased use and interest in wind energy over the last few years has necessitated an increase in the manufacturing of wind turbine blades. This increase in manufacturing has in many ways out stepped the current understanding of not only the materials used but also the manufacturing methods used to construct composite laminates. The goal of this study is to develop a list of process parameters which influence the quality of composite laminates manufactured using vacuum assisted resin transfer molding and to evaluate how they influence laminate quality. Known to be primary factors for the manufacturing process are resin flowmore » rate and vacuum pressure. An incorrect balance of these parameters will often cause porosity or voids in laminates that ultimately degrade the strength of the composite. Fiber waviness has also been seen as a major contributor to failures in wind turbine blades and is often the effect of mishandling during the lay-up process. Based on laboratory tests conducted, a relationship between these parameters and laminate quality has been established which will be a valuable tool in developing best practices and standard procedures for the manufacture of wind turbine blade composites.« less

  11. Determination of the implantation dose in silicon wafers by X-ray fluorescence analysis

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Klockenkaemper, R.; Becker, M.; Bubert, H.

    1990-08-01

    The ion dose implanted in silicon wafers was determined by X-ray fluorescence analysis after the implantation process. As only near-surface layers below 1-{mu}m thickness were considered, the calibration could be carried out with external standards consisting of thin films of doped gelatine spread on pure wafers. Dose values for Cr and Co were determined between 4 {times} 10{sup 15} and 2 {times} 10{sup 17} atoms/cm{sup 2}, the detection limits being about 3 {times} 10{sup 14} atoms/cm{sup 2}. The results are precise and accurate apart from a residual scatter of less than 7%. This was confirmed by flame atomic absorption spectrometrymore » after volatilization of the silicon matrix as SiF{sub 4}. It was found that ion-current measurements carried out during the implantation process can have considerable systematic errors.« less

  12. Recent progress in 1.3- and 1.5-μm waveband wafer-fused VCSELs

    NASA Astrophysics Data System (ADS)

    Mereuta, A.; Caliman, A.; Sirbu, A.; Iakovlev, V.; Ellafi, D.; Rudra, A.; Wolf, P.; Bimberg, D.; Kapon, E.

    2016-11-01

    The progress of 1.3- and 1.5-μm waveband wafer-fused VCSELs is reported. The emission of single mode power of 6 - 8 mW at room temperature and up to 3 mW at 80°C were demonstrated. 10-Gb/s full wavelength-set VCSEL devices for CWDM systems with high yield and Telcordia-reliability were industrially manufactured. By increasing the compressive strain in the QWs and reducing the cavity photon life time the modulation bandwidth was increased to 11.5 GHz, and large-signal data transmission experiments show error-free operation and open eye diagrams from 25 to 35 Gb/s in both B2B and after 10-km, respectively.

  13. Cost-effective method of manufacturing a 3D MEMS optical switch

    NASA Astrophysics Data System (ADS)

    Carr, Emily; Zhang, Ping; Keebaugh, Doug; Chau, Kelvin

    2009-02-01

    growth of data and video transport networks. All-optical switching eliminates the need for optical-electrical conversion offering the ability to switch optical signals transparently: independent of data rates, formats and wavelength. It also provides network operators much needed automation capabilities to create, monitor and protect optical light paths. To further accelerate the market penetration, it is necessary to identify a path to reduce the manufacturing cost significantly as well as enhance the overall system performance, uniformity and reliability. Currently, most MEMS optical switches are assembled through die level flip-chip bonding with either epoxies or solder bumps. This is due to the alignment accuracy requirements of the switch assembly, defect matching of individual die, and cost of the individual components. In this paper, a wafer level assembly approach is reported based on silicon fusion bonding which aims to reduce the packaging time, defect count and cost through volume production. This approach is successfully demonstrated by the integration of two 6-inch wafers: a mirror array wafer and a "snap-guard" wafer, which provides a mechanical structure on top of the micromirror to prevent electrostatic snap-down. The direct silicon-to-silicon bond eliminates the CTEmismatch and stress issues caused by non-silicon bonding agents. Results from a completed integrated switch assembly will be presented, which demonstrates the reliability and uniformity of some key parameters of this MEMS optical switch.

  14. Materials, Processes, and Facile Manufacturing for Bioresorbable Electronics: A Review.

    PubMed

    Yu, Xiaowei; Shou, Wan; Mahajan, Bikram K; Huang, Xian; Pan, Heng

    2018-05-07

    Bioresorbable electronics refer to a new class of advanced electronics that can completely dissolve or disintegrate with environmentally and biologically benign byproducts in water and biofluids. They have provided a solution to the growing electronic waste problem with applications in temporary usage of electronics such as implantable devices and environmental sensors. Bioresorbable materials such as biodegradable polymers, dissolvable conductors, semiconductors, and dielectrics are extensively studied, enabling massive progress of bioresorbable electronic devices. Processing and patterning of these materials are predominantly relying on vacuum-based fabrication methods so far. However, for the purpose of commercialization, nonvacuum, low-cost, and facile manufacturing/printing approaches are the need of the hour. Bioresorbable electronic materials are generally more chemically reactive than conventional electronic materials, which require particular attention in developing the low-cost manufacturing processes in ambient environment. This review focuses on material reactivity, ink availability, printability, and process compatibility for facile manufacturing of bioresorbable electronics. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  15. Wafer-scale epitaxial graphene on SiC for sensing applications

    NASA Astrophysics Data System (ADS)

    Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

    2015-12-01

    The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

  16. W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

    NASA Technical Reports Server (NTRS)

    Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

    1997-01-01

    Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

  17. Metal Big Area Additive Manufacturing: Process Modeling and Validation

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Simunovic, Srdjan; Nycz, Andrzej; Noakes, Mark W

    Metal Big Area Additive Manufacturing (mBAAM) is a new additive manufacturing (AM) technology for printing large-scale 3D objects. mBAAM is based on the gas metal arc welding process and uses a continuous feed of welding wire to manufacture an object. An electric arc forms between the wire and the substrate, which melts the wire and deposits a bead of molten metal along the predetermined path. In general, the welding process parameters and local conditions determine the shape of the deposited bead. The sequence of the bead deposition and the corresponding thermal history of the manufactured object determine the long rangemore » effects, such as thermal-induced distortions and residual stresses. Therefore, the resulting performance or final properties of the manufactured object are dependent on its geometry and the deposition path, in addition to depending on the basic welding process parameters. Physical testing is critical for gaining the necessary knowledge for quality prints, but traversing the process parameter space in order to develop an optimized build strategy for each new design is impractical by pure experimental means. Computational modeling and optimization may accelerate development of a build process strategy and saves time and resources. Because computational modeling provides these opportunities, we have developed a physics-based Finite Element Method (FEM) simulation framework and numerical models to support the mBAAM process s development and design. In this paper, we performed a sequentially coupled heat transfer and stress analysis for predicting the final deformation of a small rectangular structure printed using the mild steel welding wire. Using the new simulation technologies, material was progressively added into the FEM simulation as the arc weld traversed the build path. In the sequentially coupled heat transfer and stress analysis, the heat transfer was performed to calculate the temperature evolution, which was used in a stress

  18. 24 CFR 3282.53 - Service of process on foreign manufacturers and importers.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ... 24 Housing and Urban Development 5 2010-04-01 2010-04-01 false Service of process on foreign manufacturers and importers. 3282.53 Section 3282.53 Housing and Urban Development Regulations Relating to... REGULATIONS Formal Procedures § 3282.53 Service of process on foreign manufacturers and importers. The...

  19. Systems-oriented survey of noncontact temperature measurement techniques for rapid thermal processing

    NASA Astrophysics Data System (ADS)

    Peyton, David; Kinoshita, Hiroyuki; Lo, G. Q.; Kwong, Dim-Lee

    1991-04-01

    Rapid Thermal Processing (RTP) is becoming a popular approach for future ULSI manufacturing due to its unique low thermal budget and process flexibility. Furthermore when RTP is combined with Chemical Vapor Deposition (CVD) the so-called RTP-CVD technology it can be used to deposit ultrathin films with extremely sharp interfaces and excellent material qualities. One major consequence of this type of processing however is the need for extremely tight control of wafer temperature both to obtain reproducible results for process control and to minimize slip and warpage arising from nonuniformities in temperature. Specifically temperature measurement systems suitable for RiP must have both high precision--within 1-2 degrees--and a short response time--to output an accurate reading on the order of milliseconds for closedloop control. Any such in-situ measurement technique must be non-contact since thermocouples cannot meet the response time requirements and have problems with conductive heat flow in the wafer. To date optical pyrometry has been the most widely used technique for RiP systems although a number of other techniques are being considered and researched. This article examines several such techniques from a systems perspective: optical pyrometry both conventional and a new approach using ellipsometric techniques for concurrent emissivity measurement Raman scattering infrared laser thermometry optical diffraction thermometry and photoacoustic thermometry. Each approach is evaluated in terms of its actual or estimated manufacturing cost remote sensing capability precision repeatability dependence on processing history range

  20. Particle monitoring and control in vacuum processing equipment

    NASA Astrophysics Data System (ADS)

    Borden, Peter G., Dr.; Gregg, John

    1989-10-01

    Particle contamination during vacuum processes has emerged as the largest single source of yield loss in VLSI manufacturing. While a number of tools have been available to help understand the sources and nature of this contamination, only recently has it been possible to monitor free particle levels within vacuum equipment in real-time. As a result, a better picture is available of how particle contamination can affect a variety of processes. This paper reviews some of the work that has been done to monitor particles in vacuum loadlocks and in processes such as etching, sputtering and ion implantation. The aim has been to make free particles in vacuum equipment a measurable process parameter. Achieving this allows particles to be controlled using statistical process control. It will be shown that free particle levels in load locks correlate to wafer surface counts, device yield and process conditions, but that these levels are considerable higher during production than when dummy wafers are run to qualify a system. It will also be shown how real-time free particle monitoring can be used to monitor and control cleaning cycles, how major episodic events can be detected, and how data can be gathered in a format suitable for statistical process control.

  1. Transfer of InP epilayers by wafer bonding

    NASA Astrophysics Data System (ADS)

    Hjort, Klas

    2004-08-01

    Wafer bonding increases the freedom of design in the integration of dissimilar materials. For example, it is interesting to combine III-V compounds that have direct band gap and high mobility with silicon (Si) that is extensively used in microelectronic applications. The interest to integrate III-V-based materials with Si arises primarily from two types of applications: smart pixels for optical intra- and inter-chip interconnects in the so-called optoelectronic integrated circuits, and optoelectronic devices using some material advantages of combining III-V with Si. Also, in the III-V industry larger substrates are crucial for higher efficiency in high-volume production, and especially so for monolithic microwave integrated circuits (MMIC). For indium phosphide (InP) the development of large-area substrates has not been able to keep up with market demands. One way to circumvent this problem is to use silicon substrates that are large-area, low-cost, and mechanically strong with high thermal conductivity. In addition, silicon is transparent at the emission wavelengths most often used in InP-based optoelectronics. Unfortunately, the large lattice-mismatch, 8.1%, between silicon and InP, has limited the success of heteroepitaxial growth. Hence, one alternative to be reviewed is InP-to-Si wafer bonding. When a direct semiconductor interface is not needed there are several other means of wafer bonding, e.g. adhesive, eutectic, and solid-state. These processes can be used for direct integration of small islets of epitaxially thin InP microelectronics onto other substrates, e.g. by transferring of InP-based epilayers to a Si-based microwave circuit by pick-and-place, BCB resist adhesive bonding and sacrificing of the InP substrate.

  2. Reliable four-point flexion test and model for die-to-wafer direct bonding

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Tabata, T., E-mail: toshiyuki.tabata@cea.fr; Sanchez, L.; Fournel, F.

    2015-07-07

    For many years, wafer-to-wafer (W2W) direct bonding has been very developed particularly in terms of bonding energy measurement and bonding mechanism comprehension. Nowadays, die-to-wafer (D2W) direct bonding has gained significant attention, for instance, in photonics and microelectro-mechanics, which supposes controlled and reliable fabrication processes. So, whatever the stuck materials may be, it is not obvious whether bonded D2W structures have the same bonding strength as bonded W2W ones, because of possible edge effects of dies. For that reason, it has been strongly required to develop a bonding energy measurement technique which is suitable for D2W structures. In this paper, bothmore » D2W- and W2W-type standard SiO{sub 2}-to-SiO{sub 2} direct bonding samples are fabricated from the same full-wafer bonding. Modifications of the four-point flexion test (4PT) technique and applications for measuring D2W direct bonding energies are reported. Thus, the comparison between the modified 4PT and the double-cantilever beam techniques is drawn, also considering possible impacts of the conditions of measures such as the water stress corrosion at the debonding interface and the friction error at the loading contact points. Finally, reliability of a modified technique and a new model established for measuring D2W direct bonding energies is demonstrated.« less

  3. Development of pulsed processes for the manufacture of solar cells

    NASA Technical Reports Server (NTRS)

    Minnucci, J. A.

    1979-01-01

    Low-energy ion implantation processes for the automated production of silicon solar cells were investigated. Phosphorus ions at an energy of 10 keV and dose of 2 x 10 to the 15th power/sq cm were implanted in silicon solar cells to produce junctions, while boron ions at 25 keV and 5 x 10 to the 15th power were implanted in the cells to produce effective back surface fields. An ion implantation facility with a beam current up to 4 mA and a production throughput of 300 wafers per hour was designed and installed. A design was prepared for a 100 mA, automated implanter with a production capacity of 100 MW sub e/sq cm per year. Two process sequences were developed which employ ion implantation and furnace or pulse annealing. A computer program was used to determine costs for junction formation by ion implantation and various furnace annealing cycles to demonstrate cost effectiveness of these methods.

  4. Process solutions for reducing PR residue over non-planar wafer

    NASA Astrophysics Data System (ADS)

    Lin, C. H.; Huang, C. H.; Yang, Elvis; Yang, T. H.; Chen, K. C.; Lu, Chih-Yuan

    2011-03-01

    SAS (Self-Aligned Source) process has been widely adopted on manufacturing NOR Flash devices. To form the SAS structure, the compromise between small space patterning and sufficiently removing photo resist residue in topographical substrate has been a critical challenge as the device scaling down. In this study, photo simulation, layout optimization, resist processing and tri-layer materials were evaluated to form defect-free and highly extendible SAS structure for NOR Flash devices. Photo simulation suggested more coherent light source allowed the incident light to reach the trench bottom that facilitates the removal of photo resist. Mask bias also benefited the process latitude extension for residue-free SAS printing. In the photo resist processing, both lowering the SB (Soft Bake) and raising PEB (Post-Exposure Bake) temperature of photo resist were helpful to broaden the process window but the final pattern profile was not good enough. Thermal flow for pos-exposure pattern shrinkage achieved small CD (Critical Dimension) patterning with residue-free, however the materials loading effect is another issue to be addressed at memory array boundary. Tri-layer scheme demonstrated good results in terms of free from residue, better substrate reflectivity control, enabling smaller space printing to loosen overlay specification and minimizing the poly gate clipping defect. It was finally proposed to combine with etch effort to from the SAS structure. Besides it is also promising to extend to even smaller technology nodes.

  5. Fit of single tooth zirconia copings: comparison between various manufacturing processes.

    PubMed

    Grenade, Charlotte; Mainjot, Amélie; Vanheusden, Alain

    2011-04-01

    Various CAD/CAM processes are commercially available to manufacture zirconia copings. Comparative data on their performance in terms of fit are needed. The purpose of this in vitro study was to compare the internal and marginal fit of single tooth zirconia copings manufactured with a CAD/CAM process (Procera; Nobel Biocare) and a mechanized manufacturing process (Ceramill; Amann Girrbach). Abutments (n=20) prepared in vivo for ceramic crowns served as a template for manufacturing both Procera and Ceramill zirconia copings. Copings were manufactured and cemented (Clearfil Esthetic Cement; Kuraray) on epoxy replicas of stone cast abutments. Specimens were sectioned. Nine measurements were performed for each coping. Over- and under-extended margins were evaluated. Comparisons between the 2 processes were performed with a generalized linear mixed model (α=.05). Internal gap values between Procera and Ceramill groups were not significantly different (P=.13). The mean marginal gap (SD) for Procera copings (51(50) μm) was significantly smaller than for Ceramill (81(66) μm) (P<.005). The percentages of over- and under-extended margins were 43% and 57% for Procera respectively, and 71% and 29% for Ceramill. Within the limitations of this in vitro study, the marginal fit of Procera copings was significantly better than that of Ceramill copings. Furthermore, Procera copings showed a smaller percentage of over-extended margins than did Ceramill copings. Copyright © 2011 The Editorial Council of the Journal of Prosthetic Dentistry. Published by Mosby, Inc. All rights reserved.

  6. New optoelectronic methodology for nondestructive evaluation of MEMS at the wafer level

    NASA Astrophysics Data System (ADS)

    Furlong, Cosme; Ferguson, Curtis F.; Melson, Michael J.

    2004-02-01

    One of the approaches to fabrication of MEMS involves surface micromachining to define dies on single crystal silicon wafers, dicing of the wafers to separate the dies, and electronic packaging of the individual dies. Dicing and packaging of MEMS accounts for a large fraction of the fabrication costs, therefore, nondestructive evaluation at the wafer level, before dicing, can have significant implications on improving production yield and costs. In this paper, advances in development of optoelectronic holography (OEH) techniques for nondestructive, noninvasive, full-field of view evaluation of MEMS at the wafer level are described. With OEH techniques, quantitative measurements of shape and deformation of MEMS, as related to their performance and integrity, are obtained with sub-micrometer spatial resolution and nanometer measuring accuracy. To inspect an entire wafer with OEH methodologies, measurements of overlapping regions of interest (ROI) on a wafer are recorded and adjacent ROIs are stitched together through efficient 3D correlation analysis algorithms. Capabilities of the OEH techniques are illustrated with representative applications, including determination of optimal inspection conditions to minimize inspection time while achieving sufficient levels of accuracy and resolution.

  7. Multi-wire slurry wafering demonstrations. [slicing silicon ingots for solar arrays

    NASA Technical Reports Server (NTRS)

    Chen, C. P.

    1978-01-01

    Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

  8. Switchable adhesion for wafer-handling based on dielectric elastomer stack transducers

    NASA Astrophysics Data System (ADS)

    Grotepaß, T.; Butz, J.; Förster-Zügel, F.; Schlaak, H. F.

    2016-04-01

    Vacuum grippers are often used for the handling of wafers and small devices. In order to evacuate the gripper, a gas flow is created that can harm the micro structures on the wafer. A promising alternative to vacuum grippers could be adhesive grippers with switchable adhesion. There have been some publications of gecko-inspired adhesive devices. Most of these former works consist of a structured surface which adheres to the object manipulated and an actuator for switching the adhesion. Until now different actuator principles have been investigated, like smart memory alloys and pneumatics. In this work for the first time dielectric elastomer stack transducers (DEST) are combined with a structured surface. DESTs are a promising new transducer technology with many applications in different industry sectors like medical devices, human-machine-interaction and soft robotics. Stacked dielectric elastomer transducers show thickness contraction originating from the electromechanical pressure of two compliant electrodes compressing an elastomeric dielectric when a voltage is applied. Since DESTs and the adhesive surfaces previously described are made of elastomers, it is self-evident to combine both systems in one device. The DESTs are fabricated by a spin coating process. If the flat surface of the spinning carrier is substituted for example by a perforated one, the structured elastomer surface and the DEST can be fabricated in one process. By electrical actuation the DEST contracts and laterally expands which causes the gecko-like cilia to adhere on the object to manipulate. This work describes the assembly and the experimental results of such a device using switchable adhesion. It is intended to be used for the handling of glass wafers.

  9. Capital intensity of photovoltaics manufacturing: Barrier to scale and opportunity for innovation

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Powell, Douglas M.; Fu, Ran; Horowitz, Kelsey

    In this study, using a bottom-up cost model, we assess the impact of initial factory capital expenditure (capex) on photovoltaic (PV) module minimum sustainable price (MSP) and industry-wide trends. We find capex to have two important impacts on PV manufacturing. First, capex strongly influences the per-unit MSP of a c-Si module: we calculate that the capex-related elements sum to 22% of MSP for an integrated wafer, cell, and module manufacturer. This fraction provides a significant opportunity to reduce MSP toward the U.S. DOE SunShot module price target through capex innovation.

  10. Capital intensity of photovoltaics manufacturing: Barrier to scale and opportunity for innovation

    DOE PAGES

    Powell, Douglas M.; Fu, Ran; Horowitz, Kelsey; ...

    2015-09-07

    In this study, using a bottom-up cost model, we assess the impact of initial factory capital expenditure (capex) on photovoltaic (PV) module minimum sustainable price (MSP) and industry-wide trends. We find capex to have two important impacts on PV manufacturing. First, capex strongly influences the per-unit MSP of a c-Si module: we calculate that the capex-related elements sum to 22% of MSP for an integrated wafer, cell, and module manufacturer. This fraction provides a significant opportunity to reduce MSP toward the U.S. DOE SunShot module price target through capex innovation.

  11. Materials processing in zero gravity. [space manufacturing

    NASA Technical Reports Server (NTRS)

    Wuenscher, H. F.

    1973-01-01

    Manufacturing processes which are expected to show drastic changes in a space environment due to the absence of earth gravity are classified according to (1) buoyancy and thermal convection sensitive processes and (2) processes where molecular forces like cohesion and adhesion remain as the relatively strongest and hence controlling factors. Some specific process demonstration experiments carried out during the Apollo 14 mission and in the Skylab program are described. These include chemical separation by electrophoresis, the M551 metals melting experiment, the M552 exothermic brazing experiment, the M553 sphere forming experiment, the M554 composite casting experiment, and the M555 gallium arsenide crystal growth experiment.

  12. Process development for green part printing using binder jetting additive manufacturing

    NASA Astrophysics Data System (ADS)

    Miyanaji, Hadi; Orth, Morgan; Akbar, Junaid Muhammad; Yang, Li

    2018-05-01

    Originally developed decades ago, the binder jetting additive manufacturing (BJ-AM) process possesses various advantages compared to other additive manufacturing (AM) technologies such as broad material compatibility and technological expandability. However, the adoption of BJ-AM has been limited by the lack of knowledge with the fundamental understanding of the process principles and characteristics, as well as the relatively few systematic design guideline that are available. In this work, the process design considerations for BJ-AM in green part fabrication were discussed in detail in order to provide a comprehensive perspective of the design for additive manufacturing for the process. Various process factors, including binder saturation, in-process drying, powder spreading, powder feedstock characteristics, binder characteristics and post-process curing, could significantly affect the printing quality of the green parts such as geometrical accuracy and part integrity. For powder feedstock with low flowability, even though process parameters could be optimized to partially offset the printing feasibility issue, the qualities of the green parts will be intrinsically limited due to the existence of large internal voids that are inaccessible to the binder. In addition, during the process development, the balanced combination between the saturation level and in-process drying is of critical importance in the quality control of the green parts.

  13. Thick resist for MEMS processing

    NASA Astrophysics Data System (ADS)

    Brown, Joe; Hamel, Clifford

    2001-11-01

    The need for technical innovation is always present in today's economy. Microfabrication methods have evolved in support of the demand for smaller and faster integrated circuits with price performance improvements always in the scope of the manufacturing design engineer. The dispersion of processing technology spans well beyond IC fabrication today with batch fabrication and wafer scale processing lending advantages to MEMES applications from biotechnology to consumer electronics from oil exploration to aerospace. Today the demand for innovative processing techniques that enable technology is apparent where only a few years ago appeared too costly or not reliable. In high volume applications where yield and cost improvements are measured in fractions of a percent it is imperative to have process technologies that produce consistent results. Only a few years ago thick resist coatings were limited to thickness less than 20 microns. Factors such as uniformity, edge bead and multiple coatings made high volume production impossible. New developments in photoresist formulation combined with advanced coating equipment techniques that closely controls process parameters have enable thick photoresist coatings of 70 microns with acceptable uniformity and edge bead in one pass. Packaging of microelectronic and micromechanical devices is often a significant cost factor and a reliability issue for high volume low cost production. Technologies such as flip- chip assembly provide a solution for cost and reliability improvements over wire bond techniques. The processing for such technology demands dimensional control and presents a significant cost savings if it were compatible with mainstream technologies. Thick photoresist layers, with good sidewall control would allow wafer-bumping technologies to penetrate the barriers to yield and production where costs for technology are the overriding issue. Single pass processing is paramount to the manufacturability of packaging

  14. Sulfur passivation techniques for III-V wafer bonding

    NASA Astrophysics Data System (ADS)

    Jackson, Michael James

    The use of direct wafer bonding in a multijunction III-V solar cell structure requires the formation of a low resistance bonded interface with minimal thermal treatment. A wafer bonded interface behaves as two independent surfaces in close proximity, hence a major source of resistance is Fermi level pinning common in III-V surfaces. This study demonstrates the use of sulfur passivation in III-V wafer bonding to reduce the energy barrier at the interface. Two different sulfur passivation processes are addressed. A dry sulfur passivation method that utilizes elemental sulfur vapor activated by ultraviolet light in vacuum is compared with aqueous sulfide and native oxide etch treatments. Through the addition of a sulfur desorption step in vacuum, the UV-S treatment achieves bondable surfaces free of particles contamination or surface roughening. X-ray photoelectron spectroscopy measurements of the sulfur treated GaAs surfaces find lower levels of oxide and the appearance of sulfide species. After 4 hrs of air exposure, the UV-S treated GaAs actually showed an increase in the amount of sulfide bonded to the semiconductor, resulting in less oxidation compared to the aqueous sulfide treatment. Large area bonding is achieved for sulfur treated GaAs / GaAs and InP / InP with bulk fracture strength achieved after annealing at 400 °C and 300 °C respectively, without large compressive forces. The electrical conductivity across a sulfur treated 400 °C bonded n-GaAs/n-GaAs interface significantly increased with a short anneal (1-2 minutes) at elevated temperatures (50--600 °C). Interfaces treated with the NH4OH oxide etch, on the other hand, exhibited only mild improvement in accordance with previously published studies in this area. TEM and STEM images revealed similar interfacial microstructure changes with annealing for both sulfur treated and NH4OH interfaces, whereby some areas have direct semiconductor-semiconductor contact without any interfacial layer. Fitting the

  15. Surface characteristics and damage distributions of diamond wire sawn wafers for silicon solar cells

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Sopori, Bhushan; Devayajanam, Srinivas; Basnyat, Prakash

    2016-01-01

    This paper describes surface characteristics, in terms of its morphology, roughness and near-surface damage of Si wafers cut by diamond wire sawing (DWS) of Si ingots under different cutting conditions. Diamond wire sawn Si wafers exhibit nearly-periodic surface features of different spatial wavelengths, which correspond to kinematics of various movements during wafering, such as ingot feed, wire reciprocation, and wire snap. The surface damage occurs in the form of frozen-in dislocations, phase changes, and microcracks. The in-depth damage was determined by conventional methods such as TEM, SEM and angle-polishing/defect-etching. However, because these methods only provide local information, we have alsomore » applied a new technique that determines average damage depth over a large area. This technique uses sequential measurement of the minority carrier lifetime after etching thin layers from the surfaces. The lateral spatial damage variations, which seem to be mainly related to wire reciprocation process, were observed by photoluminescence and minority carrier lifetime mapping. Our results show a strong correlation of damage depth on the diamond grit size and wire usage.« less

  16. Scaleable processes for the manufacture of therapeutic quantities of plasmid DNA.

    PubMed

    Shamlou, Parviz Ayazi

    2003-06-01

    The need for scaleable processes to manufacture therapeutic plasmid DNA (pDNA) is easy to overlook when attention is focused primarily on vector design and establishment of early clinical results. pDNA is a large molecule and has properties that are similar to those of the contaminating chromosomal DNA. These, combined with the low initial concentration of plasmids in the host cell, provide unique process challenges that require significant upfront design to establish robust manufacturing processes that can also comply with current Good Manufacturing Practice ('cGMP') and produce milligram-to-kilogram quantities of pDNA product. This review describes promising scaleable processes that are currently being assessed for production of therapeutic supercoiled pDNA. Fermentation strategies for improving supercoiled plasmid yield and reducing contaminant concentrations are reviewed, and downstream processes are assessed for their ability to efficiently remove cellular contaminants, separate the supercoiled form of the pDNA from its open circular and linear forms, and prepare the purified drug substance for formulation. Current strategies are presented for developing stable delivery systems, and approaches to quality assurance and quality control are discussed.

  17. Knowledge Assisted Integrated Design of a Component and Its Manufacturing Process

    NASA Astrophysics Data System (ADS)

    Gautham, B. P.; Kulkarni, Nagesh; Khan, Danish; Zagade, Pramod; Reddy, Sreedhar; Uppaluri, Rohith

    Integrated design of a product and its manufacturing processes would significantly reduce the total cost of the products as well as the cost of its development. However this would only be possible if we have a platform that allows us to link together simulations tools used for product design, performance evaluation and its manufacturing processes in a closed loop. In addition to that having a comprehensive knowledgebase that provides systematic knowledge guided assistance to product or process designers who may not possess in-depth design knowledge or in-depth knowledge of the simulation tools, would significantly speed up the end-to-end design process. In this paper, we propose a process and illustrate a case for achieving an integrated product and manufacturing process design assisted by knowledge support for the user to make decisions at various stages. We take transmission component design as an example. The example illustrates the design of a gear for its geometry, material selection and its manufacturing processes, particularly, carburizing-quenching and tempering, and feeding the material properties predicted during heat treatment into performance estimation in a closed loop. It also identifies and illustrates various decision stages in the integrated life cycle and discusses the use of knowledge engineering tools such as rule-based guidance, to assist the designer make informed decisions. Simulation tools developed on various commercial, open-source platforms as well as in-house tools along with knowledge engineering tools are linked to build a framework with appropriate navigation through user-friendly interfaces. This is illustrated through examples in this paper.

  18. Mobil Solar Energy Corporation thin EFG octagons. Final subcontract report, 1 April 1992--31 January 1994

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Kalejs, J.P.

    1994-06-01

    Mobil Solar Energy Corporation manufactures photovoltaic modules based on its unique Edge-defined Film-fed Growth (EFG) process for producing octagon-shaped hollow polycrystalline silicon tubes. The octagons are cut by lasers into 100 mm x 100 mm wafers which are suitable for solar cell processing. This process avoids slicing, grinding and polishing operations which are wasteful of material and are typical of most other wafer production methods. EFG wafers are fabricated into solar cells and modules using processes that have been specially developed to allow scaling up to high throughput rates. The goals of the Photovoltaic Manufacturing Technology Initiative (PVMaT) program atmore » Mobil Solar were to improve the EFG manufacturing line through technology advances that accelerate cost reduction in production and stimulate market growth for its product. The program was structured into three main tasks: to decrease silicon utilization by lowering wafer thickness from 400 to 200 {mu}m; to enhance laser cutting yields and throughput while improving the wafer strength; and to raise crystal growth productivity and yield. The technical problems faced and the advances made in the Mobil Solar PVMaT program are described. The author concludes with a presentation of the results of a detailed cost model for EFT module production. This model describes the accelerated reductions in manufacturing costs which are already in place and the future benefits anticipated to result from the technical achievements of the PVMaT program.« less

  19. Mobil Solar Energy Corporation thin EFG octagons

    NASA Astrophysics Data System (ADS)

    Kalejs, J. P.

    1994-06-01

    Mobil Solar Energy Corporation manufactures photovoltaic modules based on its unique Edge-defined Film-fed Growth (EFG) process for producing octagon-shaped hollow polycrystalline silicon tubes. The octagons are cut by lasers into 100 mm x 100 mm wafers which are suitable for solar cell processing. This process avoids slicing, grinding and polishing operations which are wasteful of material and are typical of most other wafer production methods. EFG wafers are fabricated into solar cells and modules using processes that have been specially developed to allow scaling up to high throughput rates. The goals of the Photovoltaic Manufacturing Technology Initiative (PVMaT) program at Mobil Solar were to improve the EFG manufacturing line through technology advances that accelerate cost reduction in production and stimulate market growth for its product. The program was structured into three main tasks: to decrease silicon utilization by lowering wafer thickness from 400 to 200 (mu)m; to enhance laser cutting yields and throughput while improving the wafer strength; and to raise crystal growth productivity and yield. The technical problems faced and the advances made in the Mobil Solar PVMaT program are described. The author concludes with a presentation of the results of a detailed cost model for EFT module production. This model describes the accelerated reductions in manufacturing costs which are already in place and the future benefits anticipated to result from the technical achievements of the PVMaT program.

  20. Towards a commercial process for the manufacture of genetically modified T cells for therapy

    PubMed Central

    Kaiser, A D; Assenmacher, M; Schröder, B; Meyer, M; Orentas, R; Bethke, U; Dropulic, B

    2015-01-01

    The recent successes of adoptive T-cell immunotherapy for the treatment of hematologic malignancies have highlighted the need for manufacturing processes that are robust and scalable for product commercialization. Here we review some of the more outstanding issues surrounding commercial scale manufacturing of personalized-adoptive T-cell medicinal products. These include closed system operations, improving process robustness and simplifying work flows, reducing labor intensity by implementing process automation, scalability and cost, as well as appropriate testing and tracking of products, all while maintaining strict adherence to Current Good Manufacturing Practices and regulatory guidelines. A decentralized manufacturing model is proposed, where in the future patients' cells could be processed at the point-of-care in the hospital. PMID:25613483

  1. Signal processing techniques for damage detection with piezoelectric wafer active sensors and embedded ultrasonic structural radar

    NASA Astrophysics Data System (ADS)

    Yu, Lingyu; Bao, Jingjing; Giurgiutiu, Victor

    2004-07-01

    Embedded ultrasonic structural radar (EUSR) algorithm is developed for using piezoelectric wafer active sensor (PWAS) array to detect defects within a large area of a thin-plate specimen. Signal processing techniques are used to extract the time of flight of the wave packages, and thereby to determine the location of the defects with the EUSR algorithm. In our research, the transient tone-burst wave propagation signals are generated and collected by the embedded PWAS. Then, with signal processing, the frequency contents of the signals and the time of flight of individual frequencies are determined. This paper starts with an introduction of embedded ultrasonic structural radar algorithm. Then we will describe the signal processing methods used to extract the time of flight of the wave packages. The signal processing methods being used include the wavelet denoising, the cross correlation, and Hilbert transform. Though hardware device can provide averaging function to eliminate the noise coming from the signal collection process, wavelet denoising is included to ensure better signal quality for the application in real severe environment. For better recognition of time of flight, cross correlation method is used. Hilbert transform is applied to the signals after cross correlation in order to extract the envelope of the signals. Signal processing and EUSR are both implemented by developing a graphical user-friendly interface program in LabView. We conclude with a description of our vision for applying EUSR signal analysis to structural health monitoring and embedded nondestructive evaluation. To this end, we envisage an automatic damage detection application utilizing embedded PWAS, EUSR, and advanced signal processing.

  2. Lamb wave propagation in monocrystalline silicon wafers.

    PubMed

    Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

  3. 2-dimensional ion velocity distributions measured by laser-induced fluorescence above a radio-frequency biased silicon wafer

    NASA Astrophysics Data System (ADS)

    Moore, Nathaniel B.; Gekelman, Walter; Pribyl, Patrick; Zhang, Yiting; Kushner, Mark J.

    2013-08-01

    The dynamics of ions traversing sheaths in low temperature plasmas are important to the formation of the ion energy distribution incident onto surfaces during microelectronics fabrication. Ion dynamics have been measured using laser-induced fluorescence (LIF) in the sheath above a 30 cm diameter, 2.2 MHz-biased silicon wafer in a commercial inductively coupled plasma processing reactor. The velocity distribution of argon ions was measured at thousands of positions above and radially along the surface of the wafer by utilizing a planar laser sheet from a pulsed, tunable dye laser. Velocities were measured both parallel and perpendicular to the wafer over an energy range of 0.4-600 eV. The resulting fluorescence was recorded using a fast CCD camera, which provided resolution of 0.4 mm in space and 30 ns in time. Data were taken at eight different phases during the 2.2 MHz cycle. The ion velocity distributions (IVDs) in the sheath were found to be spatially non-uniform near the edge of the wafer and phase-dependent as a function of height. Several cm above the wafer the IVD is Maxwellian and independent of phase. Experimental results were compared with simulations. The experimental time-averaged ion energy distribution function as a function of height compare favorably with results from the computer model.

  4. Small Scale Turbopump Manufacturing Technology and Material Processes

    NASA Technical Reports Server (NTRS)

    Alvarez, Erika; Morgan, Kristin; Wells, Doug; Zimmerman, Frank

    2011-01-01

    As part of an internal research and development project, NASA Marshall Space Flight Center (MSFC) has been developing a high specific impulse 9,000-lbf LOX/LH2 pump-fed engine testbed with the capability to throttle 10:1. A Fuel Turbopump (FTP) with the ability to operate across a speed range of 30,000-rpm to 100,000-rpm was developed and analyzed. This small size and flight-like Fuel Turbopump has completed the design and analysis phase and is currently in the manufacturing phase. This paper highlights the manufacturing and processes efforts to fabricate an approximately 20-lb turbopump with small flow passages, intricately bladed components and approximately 3-in diameter impellers. As a result of the small scale and tight tolerances of the hardware on this turbopump, several unique manufacturing and material challenges were encountered. Some of the technologies highlighted in this paper include the use of powder metallurgy technology to manufacture small impellers, electron beam welding of a turbine blisk shroud, and casting challenges. The use of risk reduction efforts such as non-destructive testing (NDT) and evaluation (NDE), fractography, material testing, and component spin testing are also discussed in this paper.

  5. Fabrication of SOI structures with buried cavities using Si wafer direct bonding and electrochemical etch-stop

    NASA Astrophysics Data System (ADS)

    Chung, Gwiy-Sang

    2003-10-01

    This paper describes the fabrication of SOI structures with buried cavities using SDB and electrochemical etch-stop. These methods are suitable for thick membrane fabrication with accurate thickness, uniformity, and flatness. After a feed-through hole for supplied voltage and buried cavities was formed on a handle Si wafer with p-type, the handle wafer was bonded to an active Si wafer consisting of a p-type substrate with an n-type epitaxial layer corresponding to membrane thickness. The bonded pair was then thinned until electrochemical etch-stop occurred at the pn junction during electrochemical etchback. By using the SDB SOI structure with buried cavities, active membranes, which have a free standing structure with a dimension of 900×900 μm2, were fabricated. It is confirmed that the fabrication process of the SDB SOI structure with buried cavities is a powerful and versatile technology for new MEMS applications.

  6. Manufacturability study of masks created by inverse lithography technology (ILT)

    NASA Astrophysics Data System (ADS)

    Martin, Patrick M.; Progler, C. J.; Xiao, G.; Gray, R.; Pang, L.; Liu, Y.

    2005-11-01

    As photolithography is pushed to fabricate deep-sub wavelength devices for 90nm, 65nm and smaller technology nodes using available exposure tools (i.e., 248nm, 193nm steppers), photomask capability is becoming extremely critical. For example, PSM masks require more complicated processing; aggressive OPC makes the writing time longer and sometimes unpredictable; and, high MEEF imposes much more stringent demands on mask quality. Therefore, in order for any new lithography technology to be adopted into production, mask manufacturability must be studied thoroughly and carefully. In this paper we will present the mask manufacturability study on mask patterns created using Inverse Lithography Technology (ILT). Unlike conventional OPC methodologies, ILT uses a unique outcome-based technology to mathematically determine the mask features that produce the desired on-wafer results. ILT solves the most critical litho challenges of the deep sub-wavelength era. Potential benefits include: higher yield; expanded litho process windows; superb pattern fidelity at 90, 65 & 45-nm nodes; and reduced time-to-silicon - all without changing the existing lithography infrastructure and design-to-silicon flow. In this study a number of cell structures were selected and used as test patterns. "Luminized patterns" were generated for binary mask and attenuated phase-shift mask. Both conventional OPC patterns and "luminized patterns" were put on a test reticle side by side, and they all have a number of variations in term of correction aggressivity level and mask complexity. Mask manufacturability, including data fracturing, writing time, mask inspection, and metrology were studied. The results demonstrate that, by optimizing the inspection recipe, masks created using ILT technology can be made and qualified using current processes with a reasonable turn-around time.

  7. Sensor-based monitoring and inspection of surface morphology in ultraprecision manufacturing processes

    NASA Astrophysics Data System (ADS)

    Rao, Prahalad Krishna

    measures (e.g., Fiedler number, Kirchoff index) extracted from these matrices are shown to be sensitive to evolving nano-surface morphology. For instance, we observed that prominent nanoscale morphological changes on CMP processed Cu wafers, although discernible visually, could not be tractably quantified using statistical metrology parameters, such as arithmetic average roughness (Sa), root mean square roughness (Sq), etc. In contrast, CMP induced nanoscale surface variations were captured on invoking graph theoretic topological invariants. Consequently, the graph theoretic approach can enable timely, non-contact, and in situ metrology of semiconductor wafers by obviating the need for reticent profile mapping techniques (e.g., AFM, SEM, etc.), and thereby prevent the propagation of yield losses over long production runs.

  8. Interferometric surface mapping with variable sensitivity.

    PubMed

    Jaerisch, W; Makosch, G

    1978-03-01

    In the photolithographic process, presently employed for the production of integrated circuits, sets of correlated masks are used for exposing the photoresist on silicon wafers. Various sets of masks which are printed in different printing tools must be aligned correctly with respect to the structures produced on the wafer in previous process steps. Even when perfect alignment is considered, displacements and distortions of the printed wafer patterns occur. They are caused by imperfections of the printing tools or/and wafer deformations resulting from high temperature processes. Since the electrical properties of the final integrated circuits and therefore the manufacturing yield depend to a great extent on the precision at which such patterns are superimposed, simple and fast overlay measurements and flatness measurements as well are very important in IC-manufacturing. A simple optical interference method for flatness measurements will be described which can be used under manufacturing conditions. This method permits testing of surface height variations by nearly grazing light incidence by absence of a physical reference plane. It can be applied to polished surfaces and rough surfaces as well.

  9. Interface and facet control during Czochralski growth of (111) InSb crystals for cost reduction and yield improvement of IR focal plane array substrates

    NASA Astrophysics Data System (ADS)

    Gray, Nathan W.; Perez-Rubio, Victor; Bolke, Joseph G.; Alexander, W. B.

    2014-10-01

    Focal plane arrays (FPAs) made on InSb wafers are the key cost-driving component in IR imaging systems. The electronic and crystallographic properties of the wafer directly determine the imaging device performance. The "facet effect" describes the non-uniform electronic properties of crystals resulting from anisotropic dopant segregation during bulk growth. When the segregation coefficient of dopant impurities changes notably across the melt/solid interface of a growing crystal the result is non-uniform electronic properties across wafers made from these crystals. The effect is more pronounced in InSb crystals grown on the (111) axis compared with other orientations and crystal systems. FPA devices made on these wafers suffer costly yield hits due to inconsistent device response and performance. Historically, InSb crystal growers have grown approximately 9-19 degree off-axis from the (111) to avoid the facet effect and produced wafers with improved uniformity of electronic properties. It has been shown by researchers in the 1960s that control of the facet effect can produce uniform small diameter crystals. In this paper, we share results employing a process that controls the facet effect when growing large diameter crystals from which 4, 5, and 6" wafers can be manufactured. The process change resulted in an increase in wafers yielded per crystal by several times, all with high crystal quality and uniform electronic properties. Since the crystals are grown on the (111) axis, manufacturing (111) oriented wafers is straightforward with standard semiconductor equipment and processes common to the high-volume silicon wafer industry. These benefits result in significant manufacturing cost savings and increased value to our customers.

  10. Increasing reticle inspection efficiency and reducing wafer print-checks using automated defect classification and simulation

    NASA Astrophysics Data System (ADS)

    Ryu, Sung Jae; Lim, Sung Taek; Vacca, Anthony; Fiekowsky, Peter; Fiekowsky, Dan

    2013-09-01

    IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically remain in the "requal" phase for extended, non-productive periods of time. The overall "requal" cycle time in which reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields. One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects. Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due to lithographic uncertainty presents significant cycle time loss and increased production costs. Fortunately, a software program has been developed which automates defect classification with simulated printability measurement greatly reducing requal cycle time and improving overall disposition accuracy. This product, called ADAS (Auto Defect Analysis System), has been tested in both engineering and high-volume production environments with very successful results. In this paper, data is presented supporting significant reduction for costly wafer print checks, improved inspection area productivity, and minimized risk of misclassified yield limiting defects.

  11. High-throughput automatic defect review for 300mm blank wafers with atomic force microscope

    NASA Astrophysics Data System (ADS)

    Zandiatashbar, Ardavan; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

    2015-03-01

    While feature size in lithography process continuously becomes smaller, defect sizes on blank wafers become more comparable to device sizes. Defects with nm-scale characteristic size could be misclassified by automated optical inspection (AOI) and require post-processing for proper classification. Atomic force microscope (AFM) is known to provide high lateral and the highest vertical resolution by mechanical probing among all techniques. However, its low throughput and tip life in addition to the laborious efforts for finding the defects have been the major limitations of this technique. In this paper we introduce automatic defect review (ADR) AFM as a post-inspection metrology tool for defect study and classification for 300 mm blank wafers and to overcome the limitations stated above. The ADR AFM provides high throughput, high resolution, and non-destructive means for obtaining 3D information for nm-scale defect review and classification.

  12. Effects of fluorine contamination on spin-on dielectric thickness in semiconductor manufacturing

    NASA Astrophysics Data System (ADS)

    Kim, Hyoung-ryeun; Hong, Soonsang; Kim, Samyoung; Oh, Changyeol; Hwang, Sung Min

    2018-03-01

    In the recent semiconductor industry, as the device shrinks, spin-on dielectric (SOD) has been adopted as a widely used material because of its excellent gap-fill, efficient throughput on mass production. SOD film must be uniformly thin, homogeneous and free of particle defects because it has been perfectly perserved after chemical-mechanical polishing (CMP) and etching process. Spin coating is one of the most common techniques for applying SOD thin films to substrates. In spin coating process, the film thickness and uniformity are strong function of the solution viscosity, the final spin speed and the surface properties. Especially, airborne molecular contaminants (AMCs), such as HF, HCl and NH3, are known to change to surface wetting characteristics. In this work, we study the SOD film thickness as a function of fluorine contamination on the wafer surface. To examine the effects of airborne molecular contamination, the wafers are directly exposed to HF fume followed by SOD coating. It appears that the film thickness decreases by higher contact angle on the wafer surface due to fluorine contamination. The thickness of the SOD film decreased with increasing fluorine contamination on the wafer surface. It means that the wafer surface with more hydrophobic property generates less hydrogen bonding with the functional group of Si-NH in polysilazane(PSZ)-SOD film. Therefore, the wetting properties of silicon wafer surfaces can be degraded by inorganic contamination in SOD coating process.

  13. Wellbore manufacturing processes for in situ heat treatment processes

    DOEpatents

    Davidson, Ian Alexander; Geddes, Cameron James; Rudolf, Randall Lynn; Selby, Bruce Allen; MacDonald, Duncan Charles

    2012-12-11

    A method includes making coiled tubing at a coiled tubing manufacturing unit coupled to a coiled tubing transportation system. One or more coiled tubing reels are transported from the coiled tubing manufacturing unit to one or more moveable well drilling systems using the coiled tubing transportation system. The coiled tubing transportation system runs from the tubing manufacturing unit to one or more movable well drilling systems, and then back to the coiled tubing manufacturing unit.

  14. Control of polysilicon on-film particulates with on-product measurements

    NASA Astrophysics Data System (ADS)

    Barker, Judith B.; Chain, Elizabeth E.; Plachecki, Vincent E.

    1997-08-01

    Historically, a number of in-line particle measurements have been performed on separate test wafers included with product wafers during polysilicon processes. By performing film thickness and particulate measurements directly on product wafers, instead, a number of benefits accrue: (1) reduced test wafer usage, (2) reduced test wafer storage requirements, (3) reduced need for equipment to reclaim test wafers, (4) reduced need for direct labor to reclaim test wafers, and (5) reduced engineering 'false alarms' due to incorrectly processed test wafers. Implementation of on-product measurements for the polysilicon diffusion process required a number of changes in both philosophy and methodology. We show the necessary steps to implementation of on-product particle measurements with concern for overall manufacturing efficiency and the need to maintain appropriate control. Particle results from the Tencor 7600 Surfscan are presented.

  15. 40 CFR 761.193 - Maintenance of monitoring records by persons who import, manufacture, process, distribute in...

    Code of Federal Regulations, 2013 CFR

    2013-07-01

    ... persons who import, manufacture, process, distribute in commerce, or use chemicals containing... records by persons who import, manufacture, process, distribute in commerce, or use chemicals containing inadvertently generated PCBs. (a) Persons who import, manufacture, process, distribute in commerce, or use...

  16. 40 CFR 761.193 - Maintenance of monitoring records by persons who import, manufacture, process, distribute in...

    Code of Federal Regulations, 2011 CFR

    2011-07-01

    ... persons who import, manufacture, process, distribute in commerce, or use chemicals containing... records by persons who import, manufacture, process, distribute in commerce, or use chemicals containing inadvertently generated PCBs. (a) Persons who import, manufacture, process, distribute in commerce, or use...

  17. 40 CFR 761.193 - Maintenance of monitoring records by persons who import, manufacture, process, distribute in...

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... persons who import, manufacture, process, distribute in commerce, or use chemicals containing... records by persons who import, manufacture, process, distribute in commerce, or use chemicals containing inadvertently generated PCBs. (a) Persons who import, manufacture, process, distribute in commerce, or use...

  18. 40 CFR 761.193 - Maintenance of monitoring records by persons who import, manufacture, process, distribute in...

    Code of Federal Regulations, 2014 CFR

    2014-07-01

    ... persons who import, manufacture, process, distribute in commerce, or use chemicals containing... records by persons who import, manufacture, process, distribute in commerce, or use chemicals containing inadvertently generated PCBs. (a) Persons who import, manufacture, process, distribute in commerce, or use...

  19. CMOS/SOS processing

    NASA Technical Reports Server (NTRS)

    Ramondetta, P.

    1980-01-01

    Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

  20. Defect recognition in CFRP components using various NDT methods within a smart manufacturing process

    NASA Astrophysics Data System (ADS)

    Schumacher, David; Meyendorf, Norbert; Hakim, Issa; Ewert, Uwe

    2018-04-01

    The manufacturing process of carbon fiber reinforced polymer (CFRP) components is gaining a more and more significant role when looking at the increasing amount of CFRPs used in industries today. The monitoring of the manufacturing process and hence the reliability of the manufactured products, is one of the major challenges we need to face in the near future. Common defects which arise during manufacturing process are e.g. porosity and voids which may lead to delaminations during operation and under load. To find irregularities and classify them as possible defects in an early stage of the manufacturing process is of high importance for the safety and reliability of the finished products, as well as of significant impact from an economical point of view. In this study we compare various NDT methods which were applied to similar CFRP laminate samples in order to detect and characterize regions of defective volume. Besides ultrasound, thermography and eddy current, different X-ray methods like radiography, laminography and computed tomography are used to investigate the samples. These methods are compared with the intention to evaluate their capability to reliably detect and characterize defective volume. Beyond the detection and evaluation of defects, we also investigate possibilities to combine various NDT methods within a smart manufacturing process in which the decision which method shall be applied is inherent within the process. Is it possible to design an in-line or at-line testing process which can recognize defects reliably and reduce testing time and costs? This study aims to show up opportunities of designing a smart NDT process synchronized to the production based on the concepts of smart production (Industry 4.0). A set of defective CFRP laminate samples and different NDT methods were used to demonstrate how effective defects are recognized and how communication between interconnected NDT sensors and the manufacturing process could be organized.

  1. Graphene photodetectors with a bandwidth  >76 GHz fabricated in a 6″ wafer process line

    NASA Astrophysics Data System (ADS)

    Schall, Daniel; Porschatis, Caroline; Otto, Martin; Neumaier, Daniel

    2017-03-01

    In recent years, the data traffic has grown exponentially and the forecasts indicate a huge market that could be addressed by communication infrastructure and service providers. However, the processing capacity, space, and energy consumption of the available technology is a serious bottleneck for the exploitation of these markets. Chip-integrated optical communication systems hold the promise of significantly improving these issues related to the current technology. At the moment, the answer to the question which material is best suited for ultrafast chip integrated communication systems is still open. In this manuscript we report on ultrafast graphene photodetectors with a bandwidth of more than 76 GHz well suitable for communication links faster than 100 GBit s-1 per channel. We extract an upper value of 7.2 ps for the timescale in which the bolometric photoresponse in graphene is generated. The photodetectors were fabricated on 6″ silicon-on-insulator wafers in a semiconductor pilot line, demonstrating the scalable fabrication of high-performance graphene based devices.

  2. Optimization of the Manufacturing Process of Conical Shell Structures Using Prepreg Laminatees

    NASA Astrophysics Data System (ADS)

    Khakimova, Regina; Zimmermann, Rolf; Burau, Florian; Siebert, Marc; Arbelo, Mariano; Castro, Saullo; Degenhardt, Richard

    2014-06-01

    The design and manufacture of an unstiffened composite conical structure which is a scaled-down version of the Ariane 5 Midlife Evolution Equipment Bay Structure is presented. For such benchmarking structures the fiber orientation error is critical and then the manufacturing process becomes a big challenge. The paper therefore is focused on the implementation of a tailoring study and on the manufacturing process. The conical structure will be tested to validate a new design approach.This study contributes to the European Union (EU) project DESICOS, whose aim is to develop less conservative design guidelines for imperfection sensitive thin-walled structures.

  3. Method for distributed agent-based non-expert simulation of manufacturing process behavior

    DOEpatents

    Ivezic, Nenad; Potok, Thomas E.

    2004-11-30

    A method for distributed agent based non-expert simulation of manufacturing process behavior on a single-processor computer comprises the steps of: object modeling a manufacturing technique having a plurality of processes; associating a distributed agent with each the process; and, programming each the agent to respond to discrete events corresponding to the manufacturing technique, wherein each discrete event triggers a programmed response. The method can further comprise the step of transmitting the discrete events to each agent in a message loop. In addition, the programming step comprises the step of conditioning each agent to respond to a discrete event selected from the group consisting of a clock tick message, a resources received message, and a request for output production message.

  4. Manufacturing process design for multi commodities in agriculture

    NASA Astrophysics Data System (ADS)

    Prasetyawan, Yudha; Santosa, Andrian Henry

    2017-06-01

    High-potential commodities within particular agricultural sectors should be accompanied by maximum benefit value that can be attained by both local farmers and business players. In several cases, the business players are small-medium enterprises (SMEs) which have limited resources to perform added value process of the local commodities into the potential products. The weaknesses of SMEs such as the manual production process with low productivity, limited capacity to maintain prices, and unattractive packaging due to conventional production. Agricultural commodity is commonly created into several products such as flour, chips, crackers, oil, juice, and other products. This research was initiated by collecting data by interview method particularly to obtain the perspectives of SMEs as the business players. Subsequently, the information was processed based on the Quality Function Deployment (QFD) to determine House of Quality from the first to fourth level. A proposed design as the result of QFD was produced and evaluated with Technology Assessment Model (TAM) and continued with a revised design. Finally, the revised design was analyzed with financial perspective to obtain the cost structure of investment, operational, maintenance, and workers. The machine that performs manufacturing process, as the result of revised design, was prototyped and tested to determined initial production process. The designed manufacturing process offers IDR 337,897, 651 of Net Present Value (NPV) in comparison with the existing process value of IDR 9,491,522 based on similar production input.

  5. Process and control systems for composites manufacturing

    NASA Technical Reports Server (NTRS)

    Tsiang, T. H.; Wanamaker, John L.

    1992-01-01

    A precise control of composite material processing would not only improve part quality, but it would also directly reduce the overall manufacturing cost. The development and incorporation of sensors will help to generate real-time information for material processing relationships and equipment characteristics. In the present work, the thermocouple, pressure transducer, and dielectrometer technologies were investigated. The monitoring sensors were integrated with the computerized control system in three non-autoclave fabrication techniques: hot-press, self contained tool (self heating and pressurizing), and pressure vessel). The sensors were implemented in the parts and tools.

  6. Manufacturing of tailored tubes with a process integrated heat treatment

    NASA Astrophysics Data System (ADS)

    Hordych, Illia; Boiarkin, Viacheslav; Rodman, Dmytro; Nürnberger, Florian

    2017-10-01

    The usage of work-pieces with tailored properties allows for reducing costs and materials. One example are tailored tubes that can be used as end parts e.g. in the automotive industry or in domestic applications as well as semi-finished products for subsequent controlled deformation processes. An innovative technology to manufacture tubes is roll forming with a subsequent inductive heating and adapted quenching to obtain tailored properties in the longitudinal direction. This processing offers a great potential for the production of tubes with a wide range of properties, although this novel approach still requires a suited process design. Based on experimental data, a process simulation is being developed. The simulation shall be suitable for a virtual design of the tubes and allows for gaining a deeper understanding of the required processing. The model proposed shall predict microstructural and mechanical tube properties by considering process parameters, different geometries, batch-related influences etc. A validation is carried out using experimental data of tubes manufactured from various steel grades.

  7. Development of Integrated Programs for Aerospace-vehicle Design (IPAD): Product manufacture interactions with the design process

    NASA Technical Reports Server (NTRS)

    Crowell, H. A.

    1979-01-01

    The product manufacturing interactions with the design process and the IPAD requirements to support the interactions are described. The data requirements supplied to manufacturing by design are identified and quantified. Trends in computer-aided manufacturing are discussed and the manufacturing process of the 1980's is anticipated.

  8. Electron beam additive manufacturing with wire - Analysis of the process

    NASA Astrophysics Data System (ADS)

    Weglowski, Marek St.; Błacha, Sylwester; Pilarczyk, Jan; Dutkiewicz, Jan; Rogal, Łukasz

    2018-05-01

    The electron beam additive manufacturing process with wire is a part of global trend to find fast and efficient methods for producing complex shapes elements from costly metal alloys such as stainless steels, nickel alloys, titanium alloys etc. whose production by other conventional technologies is unprofitable or technically impossible. Demand for additive manufacturing is linked to the development of new technologies in the automotive, aerospace and machinery industries. The aim of the presented work was to carried out research on electron beam additive manufacturing with a wire as a deposited (filler) material. The scope of the work was to investigate the influence of selected technological parameters such as: wire feed rate, beam current, travelling speed, acceleration voltage on stability of the deposition process and geometric dimensions of the padding welds. The research revealed that, at low beam currents, the deposition process is unstable. The padding weld reinforcement is non-uniform. Irregularity of the width, height and straightness of the padding welds can be observed. At too high acceleration voltage and beam current, burn-through of plate and excess penetration weld can be revealed. The achieved results and gained knowledge allowed to produce, based on EBAM with wire process, whole structure from stainless steel.

  9. Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

    NASA Astrophysics Data System (ADS)

    Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

    2016-04-01

    In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

  10. Readiness Assessment Towards Smart Manufacturing System for Tuna Processing Industry in Indonesia

    NASA Astrophysics Data System (ADS)

    Anggrahini, D.; Kurniati, N.; Karningsih, P. D.; Parenreng, S. M.; Syahroni, N.

    2018-04-01

    Marine product processing is one of the top priority clusters in the national development. Tuna, as a kind of deep ocean fishes, has the highest number of production that significantly increased throughout the years. Indonesia government encourages tuna processing industry, which are mostly dominated by small to medium enterprises, to grow continuously. Nowadays, manufacturers are facing substantial challenges in adopting modern system and technology that will lead a significant improvement through the internet of things (IoT). A smart factory transform integrated manufacturing process, in a high speed processing to respond customer needs. It has some positive impacts, such as increasing productivity, reducing set up time, shortening marketing and other support activities, hence the process is being more flexible and efficient. To implement smart manufacturing system, factories should know the readiness at any level of them, technology capability and strategy appropriateness. This exploratory study aims to identify the criterias, and develop an assessment tools to measure the level towards smart factory.

  11. Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

    NASA Astrophysics Data System (ADS)

    Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

    2018-03-01

    A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

  12. Full wafer size investigation of N+ and P+ co-implanted layers in 4H-SiC

    NASA Astrophysics Data System (ADS)

    Blanqué, S.; Lyonnet, J.; Pérez, R.; Terziyska, P.; Contreras, S.; Godignon, P.; Mestres, N.; Pascual, J.; Camassel, J.

    2005-03-01

    We report a full wafer size investigation of the homogeneity of electrical properties in the case of co-implanted nitrogen and phosphorus ions in 4H-SiC semi-insulating wafers. To match standard industrial requirements, implantation was done at room temperature. To achieve a detailed electrical knowledge, we worked on a 35 mm wafer on which 77 different reticules have been processed. Every reticule includes one Hall cross, one Van der Pauw test structure and different TLM patterns. Hall measurements have been made on all 77 different reticules, using an Accent HL5500 Hall System® from BioRad fitted with an home-made support to collect data from room temperature down to about 150 K. At room temperature, we find that the sheet carrier concentration is only 1/4 of the total implanted dose while the average mobility is 80.6 cm2/Vs. The standard deviation is, typically, 1.5 cm2/Vs.