X-ray topography as a process control tool in semiconductor and microcircuit manufacture

NASA Technical Reports Server (NTRS)

Parker, D. L.; Porter, W. A.

1977-01-01

A bent wafer camera, designed to identify crystal lattice defects in semiconductor materials, was investigated. The camera makes use of conventional X-ray topographs and an innovative slightly bent wafer which allows rays from the point source to strike all portions of the wafer simultaneously. In addition to being utilized in solving production process control problems, this camera design substantially reduces the cost per topograph.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2008-10-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-03-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Zaunbracher, K.

2011-07-01

Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finishedmore » cell performance.« less

Overview of several applications of chemical downstream etching (CDE) for IC manufacturing: advantages and drawbacks versus WET processes

NASA Astrophysics Data System (ADS)

de Buttet, Côme; Prevost, Emilie; Campo, Alain; Garnier, Philippe; Zoll, Stephane; Vallier, Laurent; Cunge, Gilles; Maury, Patrick; Massin, Thomas; Chhun, Sonarith

2017-03-01

Today the IC manufacturing faces lots of problematics linked to the continuous down scaling of printed structures. Some of those issues are related to wet processing, which are often used in the IC manufacturing flow for wafer cleaning, material etching and surface preparation. In the current work we summarize the limitations for the next nodes of wet processing such as metallic contaminations, wafer charging, corrosion and pattern collapse. As a replacement, we promoted the isotropic chemical dry etching (CDE) which is supposed to fix all the above drawbacks. Etching steps of SI3N4 layers were evaluated in order to prove the interest of such technique.

Wafer-shape metrics based foundry lithography

NASA Astrophysics Data System (ADS)

Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

2017-03-01

As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

NASA Astrophysics Data System (ADS)

Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

2018-03-01

The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Dorn, D.

2012-06-01

Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect bandmore » images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.« less

Silicon Chemical Vapor Deposition Process Using a Half-Inch Silicon Wafer for Minimal Manufacturing System

NASA Astrophysics Data System (ADS)

Li, Ning; Habuka, Hitoshi; Ikeda, Shin-ichi; Hara, Shiro

A chemical vapor deposition reactor for producing thin silicon films was designed and developed for achieving a new electronic device production system, the Minimal Manufacturing, using a half-inch wafer. This system requires a rapid process by a small footprint reactor. This was designed and verified by employing the technical issues, such as (i) vertical gas flow, (ii) thermal operation using a highly concentrated infrared flux, and (iii) reactor cleaning by chlorine trifluoride gas. The combination of (i) and (ii) could achieve a low heating power and a fast cooling designed by the heat balance of the small wafer placed at a position outside of the reflector. The cleaning process could be rapid by (iii). The heating step could be skipped because chlorine trifluoride gas was reactive at any temperature higher than room temperature.

Post exposure bake unit equipped with wafer-shape compensation technology

NASA Astrophysics Data System (ADS)

Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

2007-03-01

In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

Wafer hot spot identification through advanced photomask characterization techniques

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; McMurran, Jeff; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2016-10-01

As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that the classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced characterization methods in order to optimize the mask process to meet the wafer lithographer's needs. These advanced characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled wafer performance.

On-line photolithography modeling using spectrophotometry and Prolith/2

NASA Astrophysics Data System (ADS)

Engstrom, Herbert L.; Beacham, Jeanne E.

1994-05-01

Spectrophotometry has been applied to optimizing photolithography processes in semiconductor manufacturing. For many years thin film measurement systems have been used in manufacturing for controlling film deposition processes. The combination of film thickness mapping with photolithography modeling has expanded the applications of this technology. Experimental measurements of dose-to-clear, the minimum light exposure dose required to fully develop a photoresist, are described. It is shown how dose-to-clear and photoresist contrast may be determined rapidly and conveniently from measurements of a dose exposure matrix on a monitor wafer. Such experimental measurements may underestimate the dose-to- clear because of thickness variations of the photoresist and underlying layers on the product wafer. Online modeling of the photolithographic process together with film thickness maps of the entire wafer can overcome this problem. Such modeling also provides maps of dose-to- clear and resist linewidth that can be used to estimate and optimize yield.

40 CFR Table I-16 to Subpart I of... - Default Emission Destruction or Removal Efficiency (DRE) Factors for Electronics Manufacturing

Code of Federal Regulations, 2014 CFR

2014-07-01

... Manufacturing: Plasma Etch/Wafer Clean Process Type: CF4 75 CH3F 97 CHF3 97 CH2F2 97 C2F6 97 C3F8 97 C4F6 97 C4F8 97 C5F8 97 SF6 97 NF3 96 All other carbon-based plasma etch/wafer clean fluorinated GHG 60 Chamber...

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

PubMed

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

Wafer-level colinearity monitoring for TFH applications

NASA Astrophysics Data System (ADS)

Moore, Patrick; Newman, Gary; Abreau, Kelly J.

2000-06-01

Advances in thin film head (TFH) designs continue to outpace those in the IC industry. The transition to giant magneto resistive (GMR) designs is underway along with the push toward areal densities in the 20 Gbit/inch2 regime and beyond. This comes at a time when the popularity of the low-cost personal computer (PC) is extremely high, and PC prices are continuing to fall. Consequently, TFH manufacturers are forced to deal with pricing pressure in addition to technological demands. New methods of monitoring and improving yield are required along with advanced head designs. TFH manufacturing is a two-step process. The first is a wafer-level process consisting of manufacturing devices on substrates using processes similar to those in the IC industry. The second half is a slider-level process where wafers are diced into 'rowbars' containing many heads. Each rowbar is then lapped to obtain the desired performance from each head. Variation in the placement of specific layers of each device on the bar, known as a colinearity error, causes a change in device performance and directly impacts yield. The photolithography tool and process contribute to colinearity errors. These components include stepper lens distortion errors, stepper stage errors, reticle fabrication errors, and CD uniformity errors. Currently, colinearity is only very roughly estimated during wafer-level TFH production. An absolute metrology tool, such as a Nikon XY, could be used to quantify colinearity with improved accuracy, but this technique is impractical since TFH manufacturers typically do not have this type of equipment at the production site. More importantly, this measurement technique does not provide the rapid feedback needed in a high-volume production facility. Consequently, the wafer-fab must rely on resistivity-based measurements from slider-fab to quantify colinearity errors. The feedback of this data may require several weeks, making it useless as a process diagnostic. This study examines a method of quickly estimating colinearity at the wafer-level with a test reticle and metrology equipment routinely found in TFH facilities. Colinearity results are correlated to slider-fab measurements on production devices. Stepper contributions to colinearity are estimated, and compared across multiple steppers and stepper generations. Multiple techniques of integrating this diagnostic into production are investigated and discussed.

George E. Pake Prize: A Few Challenges in the Evolution of Semiconductor Device/Manufacturing Technology

NASA Astrophysics Data System (ADS)

Doering, Robert

In the early 1980s, the semiconductor industry faced the related challenges of ``scaling through the one-micron barrier'' and converting single-level-metal NMOS integrated circuits to multi-level-metal CMOS. Multiple advances in lithography technology and device materials/process integration led the way toward the deep-sub-micron transistors and interconnects that characterize today's electronic chips. In the 1990s, CMOS scaling advanced at an accelerated pace enabled by rapid advances in many aspects of optical lithography. However, the industry also needed to continue the progress in manufacturing on ever-larger silicon wafers to maintain economy-of-scale trends. Simultaneously, the increasing complexity and absolute-precision requirements of manufacturing compounded the necessity for new processes, tools, and control methodologies. This talk presents a personal perspective on some of the approaches that addressed the aforementioned challenges. In particular, early work on integrating silicides, lightly-doped-drain FETs, shallow recessed isolation, and double-level metal will be discussed. In addition, some pioneering efforts in deep-UV lithography and single-wafer processing will be covered. The latter will be mainly based on results from the MMST Program - a 100 M +, 5-year R&D effort, funded by DARPA, the U.S. Air Force, and Texas Instruments, that developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration of sub-3-day cycle time for manufacturing 350-nm CMOS integrated circuits in 1993. This was principally enabled by the development of: (1) 100% single-wafer processing, including rapid-thermal processing (RTP), and (2) computer-integrated-manufacturing (CIM), including real-time, in-situ process control.

Thin EFG octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-01-01

Mobil Solar Energy Corporation currently practices a unique crystal growth technology for producing crystalline silicon sheet, which is then cut with lasers into wafers. The wafers are processed into solar cells and incorporated into modules for photovoltaic applications. The silicon sheet is produced using a method known as Edge-defined Film-fed growth (EFG), in the form of hollow eight-sided polygons (octagons) with 10 cm faces. These are grown to lengths of 5 meters and thickness of 300 microns, with continuous melt replenishment, in compact furnaces designed to operate at a high sheet area production area of 135 sq cm/min. The present Photovoltaic Manufacturing Technology (PVMaT) three-year program seeks to advance the manufacturing line capabilities of the Mobil Solar crystal growth and cutting technologies. If successful, these advancements will provide significant reductions in already low silicon raw material usage, improve process productivity, laser cutting throughput and yield, and so lower both individual wafer cost and the cost of module production. This report summarizes the significant technical improvements in EFG technology achieved in Phase 1 of this program. Technical results are reported for each of the three main program areas: (1) thin octagon growth (crystal growth) -- to reduce the thickness of the octagon to an interim goal of 250 microns during Phase 1, with an ultimate goal of achieving 200 micron thicknesses; (2) laser cutting -- to improve the laser cutting process, so as to produce wafers with decreased laser cutting damage at increased wafer throughput rates; and (3) process control and product specification -- to implement advanced strategies in crystal growth process control and productivity designed to increase wafer yields.

Warpage Measurement of Thin Wafers by Reflectometry

NASA Astrophysics Data System (ADS)

Ng, Chi Seng; Asundi, Anand Krishna

To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

Reducing bottom anti-reflective coating (BARC) defects: optimizing and decoupling the filtration and dispense process

NASA Astrophysics Data System (ADS)

Brakensiek, Nickolas L.; Martin, Gary; Simmons, Sean; Batchelder, Traci

2006-03-01

Semiconductor device manufacturing is one of the cleanest manufacturing operations that can be found in the world today. It has to be that way; a particle on a wafer today can kill an entire device, which raises the costs, and therefore reduces the profits, of the manufacturing company in two ways: it must produce extra wafers to make up for the lost die, and it has less product to sell. In today's state-of-the-art fab, everything is filtered to the lowest pore size available. This practice is fairly easy for gases because a gas molecule is very small compared to the pore size of the filter. Filtering liquids, especially photochemicals such as photoresists and BARCs, can be much harder because the molecules that form the polymers used to manufacture the photochemicals are approaching the filter pore size. As a result, filters may plug up, filtration rates may drop, pressure drops across the filter may increase, or a filter may degrade. These conditions can then cause polymer shearing, microbubble formation, gel particle formation, and BARC chemical changes to occur before the BARC reaches the wafer. To investigate these possible interactions, an Entegris(R) IntelliGen(R) pump was installed on a TEL Mk8 TM track to see if the filtration process would have an effect on the BARC chemistry and coating defects. Various BARC chemicals such as DUV112 and DUV42P were pumped through various filter media having a variety of pore sizes at different filtration rates to investigate the interaction between the dispense process and the filtration process. The IntelliGen2 pump has the capability to filter the BARC independent of the dispense process. By using a designed experiment to look at various parameters such as dispense rate, filtration rate, and dispense volume, the effects of the complete pump system can be learned, and appropriate conditions can be applied to yield the cleanest BARC coating process. Results indicate that filtration rate and filter pore size play a dramatic role in the defect density on a coated wafer with the actual dispense properties such as dispense wafer speed and dispense time playing a lesser role.

1366 Project Silicon: Reclaiming US Silicon PV Leadership

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling ofmore » 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the crucial development step between the original research effort in Lexington and the GW factory scheduled to be online before the end of the decade. At the conclusion of the project, it is clear that the Direct Wafer™ technology will have a dramatic impact on the entire silicon photovoltaic supply chain by effectively doubling existing silicon capacity (by reducing silicon usage by 50%) and reducing supply chain capital costs by 35%. The technology, when fully-scaled in the US, will also lead to significant job growth, with the eventual creation of 1,000 jobs in Western New York.« less

A new approach to measure the temperature in rapid thermal processing

NASA Astrophysics Data System (ADS)

Yan, Jiang

This dissertation has presented the research work about a new method to measure the temperatures for the silicon wafer. The new technology is mainly for the rapid thermal processing (RTP) system. RTP is a promising technology in semiconductor manufacturing especially for the devices with minimum feature size less than 0.5 μm. The technique to measure the temperatures of the silicon wafer accurately is the key factor to apply the RTP technology to more critical processes in the manufacturing. Two methods which are mostly used nowadays, thermocouples and pyrometer, all have the limitation to be applied in the RTP. This is the motivation to study the new method using acoustic waves for the temperature measurement. The test system was designed and built up for the study of the acoustic method. The whole system mainly includes the transducer unit, circuit hardware, control software, the computer, and the chamber. The acoustic wave was generated by the PZT-5H transducer. The wave travels through the quartz rod into the silicon wafer. After traveling a certain distances in the wafer, the acoustic waves could be received by other transducers. By measuring the travel time and with the travel distance, the velocity of the acoustic wave traveling in the silicon wafer can be calculated. Because there is a relationship between the velocity and the temperature: the velocities of the acoustic waves traveling in the silicon wafer decrease as the temperatures of the wafer increase, the temperature of the wafer can be finally obtained. The thermocouples were used to check the measurement accuracy of the acoustic method. The temperature mapping across the 8″ silicon wafer was obtained with four transducer sensor unit. The temperatures of the wafer were measured using acoustic method at both static and dynamic status. The main purpose of the tests is to know the measurement accuracy for the new method. The goal of the research work regarding to the accuracy is <=+/-3°C. The measurement was also done under the different wafer conditions in order to clarify that the acoustic method is independent of the wafer conditions.

Thin EFG octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-06-01

This report describes the impact of the technical achievements made in the first 18 months of the three year PVMaT program at Mobil Solar on lowering the manufacturing costs of its photovoltaic polycrystalline silicon-based modules. Manufacturing cost decreases are being achieved through a reduction of silicon material utilization, increases in productivity and yield in crystal growth, and through improvements in the laser cutting process for EFG wafers. The yield, productivity, and throughput advances made possible by these technical achievements are shown to be able to enhance future market share growth for Mobil Solar products as a consequence of significant reductions in a number of direct manufacturing cost elements in EFG wafer and module production.

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fong, Theodore E.

2013-05-06

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

Thin edge-defined film-fed growth (EFG) octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1992-03-01

Mobil Solar Energy Corp. investigated manufacturing crystalline silicon wafers using the edge-defined film-fed growth (EFG) technique. This report identifies the following: (1) current capabilities for manufacturing 200-micron-thick crystalline silicon wafers (10 cm x 10 cm) produced by growing octagons using the EFG technique and laser cutting them into wafers; (2) potential manufacturing improvements from decreasing the thickness of the wafers, improving the quality of the laser cut edge, and increasing cutting speed, all of which lead to reduce manufacturing costs, improved performance, and increased production capacities; (3) problems that impede achieving these potentials; and (4) costs and other requirements involved in overcoming the problems.

Wafer-level manufacturing technology of glass microlenses

NASA Astrophysics Data System (ADS)

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Edge printability: techniques used to evaluate and improve extreme wafer edge printability

NASA Astrophysics Data System (ADS)

Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

2004-05-01

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

Planning for the semiconductor manufacturer of the future

NASA Technical Reports Server (NTRS)

Fargher, Hugh E.; Smith, Richard A.

1992-01-01

Texas Instruments (TI) is currently contracted by the Air Force Wright Laboratory and the Defense Advanced Research Projects Agency (DARPA) to develop the next generation flexible semiconductor wafer fabrication system called Microelectronics Manufacturing Science & Technology (MMST). Several revolutionary concepts are being pioneered on MMST, including the following: new single-wafer rapid thermal processes, in-situ sensors, cluster equipment, and advanced Computer Integrated Manufacturing (CIM) software. The objective of the project is to develop a manufacturing system capable of achieving an order of magnitude improvement in almost all aspects of wafer fabrication. TI was awarded the contract in Oct., 1988, and will complete development with a fabrication facility demonstration in April, 1993. An important part of MMST is development of the CIM environment responsible for coordinating all parts of the system. The CIM architecture being developed is based on a distributed object oriented framework made of several cooperating subsystems. The software subsystems include the following: process control for dynamic control of factory processes; modular processing system for controlling the processing equipment; generic equipment model which provides an interface between processing equipment and the rest of the factory; specification system which maintains factory documents and product specifications; simulator for modelling the factory for analysis purposes; scheduler for scheduling work on the factory floor; and the planner for planning and monitoring of orders within the factory. This paper first outlines the division of responsibility between the planner, scheduler, and simulator subsystems. It then describes the approach to incremental planning and the way in which uncertainty is modelled within the plan representation. Finally, current status and initial results are described.

Quantitative phase measurement for wafer-level optics

NASA Astrophysics Data System (ADS)

Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

2015-07-01

Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

Using the surface charge profiler for in-line monitoring of doping concentration in silicon epitaxial wafer manufacturing

NASA Astrophysics Data System (ADS)

Tower, Joshua P.; Kamieniecki, Emil; Nguyen, M. C.; Danel, Adrien

1999-08-01

The Surface Charge Profiler (SCP) has been introduced for monitoring and development of silicon epitaxial processes. The SCP measures the near-surface doping concentration and offers advantages that lead to yield enhancement in several ways. First, non-destructive measurement technology enables in-line process monitoring, eliminating the need to sacrifice production wafers for resistivity measurements. Additionally, the full-wafer mapping capability helps in development of improved epitaxial growth processes and early detection of reactor problems. As examples, we present the use of SCP to study the effects of susceptor degradation in barrel reactors and to study autodoping for development of improved dopant uniformity.

Disc resonator gyroscope fabrication process requiring no bonding alignment

NASA Technical Reports Server (NTRS)

Shcheglov, Kirill V. (Inventor)

2010-01-01

A method of fabricating a resonant vibratory sensor, such as a disc resonator gyro. A silicon baseplate wafer for a disc resonator gyro is provided with one or more locating marks. The disc resonator gyro is fabricated by bonding a blank resonator wafer, such as an SOI wafer, to the fabricated baseplate, and fabricating the resonator structure according to a pattern based at least in part upon the location of the at least one locating mark of the fabricated baseplate. MEMS-based processing is used for the fabrication processing. In some embodiments, the locating mark is visualized using optical and/or infrared viewing methods. A disc resonator gyroscope manufactured according to these methods is described.

Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

NASA Astrophysics Data System (ADS)

Turner, K. T.; Spearing, S. M.

2002-12-01

Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

A Lorentz force actuated magnetic field sensor with capacitive read-out

NASA Astrophysics Data System (ADS)

Stifter, M.; Steiner, H.; Kainz, A.; Keplinger, F.; Hortschitz, W.; Sauter, T.

2013-05-01

We present a novel design of a resonant magnetic field sensor with capacitive read-out permitting wafer level production. The device consists of a single-crystal silicon cantilever manufactured from the device layer of an SOI wafer. Cantilevers represent a very simple structure with respect to manufacturing and function. On the top of the structure, a gold lead carries AC currents that generate alternating Lorentz forces in an external magnetic field. The free end oscillation of the actuated cantilever depends on the eigenfrequencies of the structure. Particularly, the specific design of a U-shaped structure provides a larger force-to-stiffness-ratio than standard cantilevers. The electrodes for detecting cantilever deflections are separately fabricated on a Pyrex glass-wafer. They form the counterpart to the lead on the freely vibrating planar structure. Both wafers are mounted on top of each other. A custom SU-8 bonding process on wafer level creates a gap which defines the equilibrium distance between sensing electrodes and the vibrating structure. Additionally to the capacitive read-out, the cantilever oscillation was simultaneously measured with laser Doppler vibrometry through proper windows in the SOI handle wafer. Advantages and disadvantages of the asynchronous capacitive measurement configuration are discussed quantitatively and presented by a comprehensive experimental characterization of the device under test.

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

NASA Astrophysics Data System (ADS)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-07-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

NASA Astrophysics Data System (ADS)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-03-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

Propagation of resist heating mask error to wafer level

NASA Astrophysics Data System (ADS)

Babin, S. V.; Karklin, Linard

2006-10-01

As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the mask error budget - the resist heating CD error. In simulation of exposure using a stepper, variable MEEF was considered.

Development of a plan for automating integrated circuit processing

NASA Technical Reports Server (NTRS)

1971-01-01

The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

A novel patterning control strategy based on real-time fingerprint recognition and adaptive wafer level scanner optimization

NASA Astrophysics Data System (ADS)

Cekli, Hakki Ergun; Nije, Jelle; Ypma, Alexander; Bastani, Vahid; Sonntag, Dag; Niesing, Henk; Zhang, Linmiao; Ullah, Zakir; Subramony, Venky; Somasundaram, Ravin; Susanto, William; Matsunobu, Masazumi; Johnson, Jeff; Tabery, Cyrus; Lin, Chenxi; Zou, Yi

2018-03-01

In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a `fingerprint', on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching <3nm, requiring the allowable budget for process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel `computational process control strategy' which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each wafer and on every layer during the lithography steps. This metrology data will be used to obtain the process fingerprints. Also, the per exposure and per wafer correction potential of the scanners will be utilized for improved patterning control. Additionally, the fingerprint library will provide early detection of excursions for inline root cause analysis and process optimization guidance.

Accomplishments in Photovoltaic Manufacturing R&D | Photovoltaic Research |

Science.gov Websites

made that significantly reduced the cost of solar modules while increasing their reliability and -area efficiency. Manufacturing Processes Half the cost of producing a solar module is incurred in wafer project partners marked significant progress in module cost reduction. A few notable examples follow

Interferometric thickness calibration of 300 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Quandou; Griesmann, Ulf; Polvani, Robert

2005-12-01

The "Improved Infrared Interferometer" (IR 3) at the National Institute of Standards and Technology (NIST) is a phase-measuring interferometer, operating at a wavelength of 1550 nm, which is being developed for measuring the thickness and thickness variation of low-doped silicon wafers with diameters up to 300 mm. The purpose of the interferometer is to produce calibrated silicon wafers, with a certified measurement uncertainty, which can be used as reference wafers by wafer manufacturers and metrology tool manufacturers. We give an overview of the design of the interferometer and discuss its application to wafer thickness measurements. The conversion of optical thickness, as measured by the interferometer, to the wafer thickness requires knowledge of the refractive index of the material of the wafer. We describe a method for measuring the refractive index which is then used to establish absolute thickness and thickness variation maps for the wafer.

CD and defect improvement challenges for immersion processes

NASA Astrophysics Data System (ADS)

Ehara, Keisuke; Ema, Tatsuhiko; Yamasaki, Toshinari; Nakagawa, Seiji; Ishitani, Seiji; Morita, Akihiko; Kim, Jeonghun; Kanaoka, Masashi; Yasuda, Shuichi; Asai, Masaya

2009-03-01

The intention of this study is to develop an immersion lithography process using advanced track solutions to achieve world class critical dimension (CD) and defectivity performance in a state of the art manufacturing facility. This study looks at three important topics for immersion lithography: defectivity, CD control, and wafer backside contamination. The topic of defectivity is addressed through optimization of coat, develop, and rinse processes as well as implementation of soak steps and bevel cleaning as part of a comprehensive defect solution. Develop and rinse processing techniques are especially important in the effort to achieve a zero defect solution. Improved CD control is achieved using a biased hot plate (BHP) equipped with an electrostatic chuck. This electrostatic chuck BHP (eBHP) is not only able to operate at a very uniform temperature, but it also allows the user to bias the post exposure bake (PEB) temperature profile to compensate for systematic within-wafer (WiW) CD non-uniformities. Optimized CD results, pre and post etch, are presented for production wafers. Wafer backside particles can cause focus spots on an individual wafer or migrate to the exposure tool's wafer stage and cause problems for a multitude of wafers. A basic evaluation of the cleaning efficiency of a backside scrubber unit located on the track was performed as a precursor to a future study examining the impact of wafer backside condition on scanner focus errors as well as defectivity in an immersion scanner.

Analysis and evaluation in the production process and equipment area of the low-cost solar array project

NASA Technical Reports Server (NTRS)

Goldman, H.; Wolf, M.

1979-01-01

The energy consumed in manufacturing silicon solar cell modules was calculated for the current process, as well as for 1982 and 1986 projected processes. In addition, energy payback times for the above three sequences are shown. The module manufacturing energy was partitioned two ways. In one way, the silicon reduction, silicon purification, sheet formation, cell fabrication, and encapsulation energies were found. In addition, the facility, equipment, processing material and direct material lost-in-process energies were appropriated in junction formation processes and full module manufacturing sequences. A brief methodology accounting for the energy of silicon wafers lost-in-processing during cell manufacturing is described.

Model-based correction for local stress-induced overlay errors

NASA Astrophysics Data System (ADS)

Stobert, Ian; Krishnamurthy, Subramanian; Shi, Hongbo; Stiffler, Scott

2018-03-01

Manufacturing embedded DRAM deep trench capacitors can involve etching very deep holes into silicon wafers1. Due to various design constraints, these holes may not be uniformly distributed across the wafer surface. Some wafer processing steps for these trenches results in stress effects which can distort the silicon wafer in a manner that creates localized alignment issues between the trenches and the structures built above them on the wafer. In this paper, we describe a method to model these localized silicon distortions for complex layouts involving billions of deep trench structures. We describe wafer metrology techniques and data which have been used to verify the stress distortion model accuracy. We also provide a description of how this kind of model can be used to manipulate the polygons in the mask tape out flow to compensate for predicted localized misalignments between design shapes from a deep trench mask and subsequent masks.

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

NASA Astrophysics Data System (ADS)

Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

2013-03-01

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

Space station automation study: Automation requriements derived from space manufacturing concepts,volume 2

NASA Technical Reports Server (NTRS)

1984-01-01

Automation reuirements were developed for two manufacturing concepts: (1) Gallium Arsenide Electroepitaxial Crystal Production and Wafer Manufacturing Facility, and (2) Gallium Arsenide VLSI Microelectronics Chip Processing Facility. A functional overview of the ultimate design concept incoporating the two manufacturing facilities on the space station are provided. The concepts were selected to facilitate an in-depth analysis of manufacturing automation requirements in the form of process mechanization, teleoperation and robotics, sensors, and artificial intelligence. While the cost-effectiveness of these facilities was not analyzed, both appear entirely feasible for the year 2000 timeframe.

Free-world microelectronic manufacturing equipment

NASA Astrophysics Data System (ADS)

Kilby, J. S.; Arnold, W. H.; Booth, W. T.; Cunningham, J. A.; Hutcheson, J. D.; Owen, R. W.; Runyan, W. R.; McKenney, Barbara L.; McGrain, Moira; Taub, Renee G.

1988-12-01

Equipment is examined and evaluated for the manufacture of microelectronic integrated circuit devices and sources for that equipment within the Free World. Equipment suitable for the following are examined: single-crystal silicon slice manufacturing and processing; required lithographic processes; wafer processing; device packaging; and test of digital integrated circuits. Availability of the equipment is also discussed, now and in the near future. Very adequate equipment for most stages of the integrated circuit manufacturing process is available from several sources, in different countries, although the best and most widely used versions of most manufacturing equipment are made in the United States or Japan. There is also an active market in used equipment, suitable for manufacture of capable integrated circuits with performance somewhat short of the present state of the art.

A comparison of the mechanical and sensory properties of baked and extruded confectionery products

NASA Astrophysics Data System (ADS)

Butt, Saba; Charalambides, Maria; Mohammed, Idris K.; Powell, Hugh

2017-10-01

Traditional baking is the most common way of producing confectionery wafers, however over the past few decades, the extrusion process has become an increasingly important food manufacturing method and is commonly used in the manufacturing of breakfast cereals and filled snack products. This study aims to characterise products made via each of these manufacturing processes in order to understand the important parameters involved in the resulting texture of confectionery products such as wafers. Both of the named processes result in brittle, cellular foams comprising of cell walls and cell pores which may contain some of the confectionery filling. The mechanical response of the cell wall material and the geometry of the products influence the consumer perception and preference. X-Ray micro tomography (XRT) was used to generate geometry of the microstructure which was then fed to Finite Element (FE) for numerical analysis on both products. The FE models were used to determine properties such as solid modulus of the cell walls, Young's modulus of the entire foam and to investigate and compare the microstructural damage of baked wafers and extruded products. A sensory analysis study was performed on both products by a qualified sensory panel. The results of this study were then used to draw links between the mechanical behaviour and sensory perception of a consumer. The extruded product was found to be made up of a stiffer solid material and had a higher compressive modulus and fracture stress when compared to the baked wafer. The sensory panel observed textural differences between the baked and extruded products which were also found in the differences of the mechanical properties of the two products.

Manufacturability of the X Architecture at the 90-nm technology node

NASA Astrophysics Data System (ADS)

Smayling, Michael C.; Sarma, Robin C.; Nagata, Toshiyuki; Arora, Narain; Duane, Michael P.; Oemardani, Shiany; Shah, Santosh

2004-05-01

In this paper, we discuss the results from a test chip that demonstrate the manufacturability and integration-worthiness of the X Architecture at the 90-nm technology node. We discuss how a collaborative effort between the design and chip making communities used the current generation of mask, lithography, wafer processing, inspection and metrology equipment to create 45 degree wires in typical metal pitches for the upper layers on a 90-nm device in a production environment. Cadence Design Systems created the test structure design and chip validation tools for the project. Canon"s KrF ES3 and ArF AS2 scanners were used for the lithography. Applied Materials used its interconnect fabrication technologies to produce the multilayer copper, low-k interconnect on 300-mm wafers. The results were confirmed for critical dimension and defect levels using Applied Materials" wafer inspection and metrology systems.

A front-end wafer-level microsystem packaging technique with micro-cap array

NASA Astrophysics Data System (ADS)

Chiang, Yuh-Min

2002-09-01

The back-end packaging process is the remaining challenge for the micromachining industry to commercialize microsystem technology (MST) devices at low cost. This dissertation presents a novel wafer level protection technique as a final step of the front-end fabrication process for MSTs. It facilitates improved manufacturing throughput and automation in package assembly, wafer level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized micro-cap array, which consists of an assortment of small caps micro-molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments during packaging. The micro-cap array is first constructed by a micromachining process with micro-molding technique, then sealed to the device wafer at wafer level. Epoxy-based wafer-level micro cap array has been successfully fabricated and showed good compatibility with conventional back-end packaging processes. An adhesive transfer technique was demonstrated to seal the micro cap array with a MEMS device wafer. No damage or gross leak was observed while wafer dicing or later during a gross leak test. Applications of the micro cap array are demonstrated on MEMS, microactuators fabricated using CRONOS MUMPS process. Depending on the application needs, the micro-molded cap can be designed and modified to facilitate additional component functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. Successful fabrication of a micro cap array comprised with microlenses can provide active functions as well as passive protection. An optical tweezer array could be one possibility for applications of a micro cap with microlenses. The micro cap itself could serve as micro well for DNA or bacteria amplification as well.

Feed-forward alignment correction for advanced overlay process control using a standalone alignment station "Litho Booster"

NASA Astrophysics Data System (ADS)

Yahiro, Takehisa; Sawamura, Junpei; Dosho, Tomonori; Shiba, Yuji; Ando, Satoshi; Ishikawa, Jun; Morita, Masahiro; Shibazaki, Yuichi

2018-03-01

One of the main components of an On-Product Overlay (OPO) error budget is the process induced wafer error. This necessitates wafer-to-wafer correction in order to optimize overlay accuracy. This paper introduces the Litho Booster (LB), standalone alignment station as a solution to improving OPO. LB can execute high speed alignment measurements without throughput (THP) loss. LB can be installed in any lithography process control loop as a metrology tool, and is then able to provide feed-forward (FF) corrections to the scanners. In this paper, the detailed LB design is described and basic LB performance and OPO improvement is demonstrated. Litho Booster's extendibility and applicability as a solution for next generation manufacturing accuracy and productivity challenges are also outlined

Process tool monitoring and matching using interferometry technique

NASA Astrophysics Data System (ADS)

Anberg, Doug; Owen, David M.; Mileham, Jeffrey; Lee, Byoung-Ho; Bouche, Eric

2016-03-01

The semiconductor industry makes dramatic device technology changes over short time periods. As the semiconductor industry advances towards to the 10 nm device node, more precise management and control of processing tools has become a significant manufacturing challenge. Some processes require multiple tool sets and some tools have multiple chambers for mass production. Tool and chamber matching has become a critical consideration for meeting today's manufacturing requirements. Additionally, process tools and chamber conditions have to be monitored to ensure uniform process performance across the tool and chamber fleet. There are many parameters for managing and monitoring tools and chambers. Particle defect monitoring is a well-known and established example where defect inspection tools can directly detect particles on the wafer surface. However, leading edge processes are driving the need to also monitor invisible defects, i.e. stress, contamination, etc., because some device failures cannot be directly correlated with traditional visualized defect maps or other known sources. Some failure maps show the same signatures as stress or contamination maps, which implies correlation to device performance or yield. In this paper we present process tool monitoring and matching using an interferometry technique. There are many types of interferometry techniques used for various process monitoring applications. We use a Coherent Gradient Sensing (CGS) interferometer which is self-referencing and enables high throughput measurements. Using this technique, we can quickly measure the topography of an entire wafer surface and obtain stress and displacement data from the topography measurement. For improved tool and chamber matching and reduced device failure, wafer stress measurements can be implemented as a regular tool or chamber monitoring test for either unpatterned or patterned wafers as a good criteria for improved process stability.

WAMA: a method of optimizing reticle/die placement to increase litho cell productivity

NASA Astrophysics Data System (ADS)

Dor, Amos; Schwarz, Yoram

2005-05-01

This paper focuses on reticle/field placement methodology issues, the disadvantages of typical methods used in the industry, and the innovative way that the WAMA software solution achieves optimized placement. Typical wafer placement methodologies used in the semiconductor industry considers a very limited number of parameters, like placing the maximum amount of die on the wafer circle and manually modifying die placement to minimize edge yield degradation. This paper describes how WAMA software takes into account process characteristics, manufacturing constraints and business objectives to optimize placement for maximum stepper productivity and maximum good die (yield) on the wafer.

Lithographic chip identification: meeting the failure analysis challenge

NASA Astrophysics Data System (ADS)

Perkins, Lynn; Riddell, Kevin G.; Flack, Warren W.

1992-06-01

This paper describes a novel method using stepper photolithography to uniquely identify individual chips for permanent traceability. A commercially available 1X stepper is used to mark chips with an identifier or `serial number' which can be encoded with relevant information for the integrated circuit manufacturer. The permanent identification of individual chips can improve current methods of quality control, failure analysis, and inventory control. The need for this technology is escalating as manufacturers seek to provide six sigma quality control for their products and trace fabrication problems to their source. This need is especially acute for parts that fail after packaging and are returned to the manufacturer for analysis. Using this novel approach, failure analysis data can be tied back to a particular batch, wafer, or even a position within a wafer. Process control can be enhanced by identifying the root cause of chip failures. Chip identification also addresses manufacturers concerns with increasing incidences of chip theft. Since chips currently carry no identification other than the manufacturer's name and part number, recovery efforts are hampered by the inability to determine the sales history of a specific packaged chip. A definitive identifier or serial number for each chip would address this concern. The results of chip identification (patent pending) are easily viewed through a low power microscope. Batch number, wafer number, exposure step, and chip location within the exposure step can be recorded, as can dates and other items of interest. An explanation of the chip identification procedure and processing requirements are described. Experimental testing and results are presented, and potential applications are discussed.

ROI on yield data analysis systems through a business process management strategy

NASA Astrophysics Data System (ADS)

Rehani, Manu; Strader, Nathan; Hanson, Jeff

2005-05-01

The overriding motivation for yield engineering is profitability. This is achieved through application of yield management. The first application is to continually reduce waste in the form of yield loss. New products, new technologies and the dynamic state of the process and equipment keep introducing new ways to cause yield loss. In response, the yield management efforts have to continually come up with new solutions to minimize it. The second application of yield engineering is to aid in accurate product pricing. This is achieved through predicting future results of the yield engineering effort. The more accurate the yield prediction, the more accurate the wafer start volume, the more accurate the wafer pricing. Another aspect of yield prediction pertains to gauging the impact of a yield problem and predicting how long that will last. The ability to predict such impacts again feeds into wafer start calculations and wafer pricing. The question then is that if the stakes on yield management are so high why is it that most yield management efforts are run like science and engineering projects and less like manufacturing? In the eighties manufacturing put the theory of constraints1 into practice and put a premium on stability and predictability in manufacturing activities, why can't the same be done for yield management activities? This line of introspection led us to define and implement a business process to manage the yield engineering activities. We analyzed the best known methods (BKM) and deployed a workflow tool to make them the standard operating procedure (SOP) for yield managment. We present a case study in deploying a Business Process Management solution for Semiconductor Yield Engineering in a high-mix ASIC environment. We will present a description of the situation prior to deployment, a window into the development process and a valuation of the benefits.

Lasers in energy device manufacturing

NASA Astrophysics Data System (ADS)

Ostendorf, A.; Schoonderbeek, A.

2008-02-01

Global warming is a current topic all over the world. CO II emissions must be lowered to stop the already started climate change. Developing regenerative energy sources, like photovoltaics and fuel cells contributes to the solution of this problem. Innovative technologies and strategies need to be competitive with conventional energy sources. During the last years, the photovoltaic solar cell industry has experienced enormous growth. However, for solar cells to be competitive on the longer term, both an increase in efficiency as well as reduction in costs is necessary. An effective method to reduce costs of silicon solar cells is reducing the wafer thickness, because silicon makes up a large part of production costs. Consequently, contact free laser processing has a large advantage, because of the decrease in waste materials due to broken wafers as caused by other manufacturing processes. Additionally, many novel high efficiency solar cell concepts are only economically feasible with laser technology, e.g. for scribing silicon thin-film solar cells. This paper describes laser hole drilling, structuring and texturing of silicon wafer based solar cells and describes thin film solar cell scribing. Furthermore, different types of lasers are discussed with respect to processing quality and time.

Development of parametric material, energy, and emission inventories for wafer fabrication in the semiconductor industry.

PubMed

Murphy, Cynthia F; Kenig, George A; Allen, David T; Laurent, Jean-Philippe; Dyer, David E

2003-12-01

Currently available data suggest that most of the energy and material consumption related to the production of an integrated circuit is due to the wafer fabrication process. The complexity of wafer manufacturing, requiring hundreds of steps that vary from product to product and from facility to facility and which change every few years, has discouraged the development of material, energy, and emission inventory modules for the purpose of insertion into life cycle assessments. To address this difficulty, a flexible, process-based system for estimating material requirements, energy requirements, and emissions in wafer fabrication has been developed. The method accounts for mass and energy use atthe unit operation level. Parametric unit operation modules have been developed that can be used to predict changes in inventory as the result of changes in product design, equipment selection, or process flow. A case study of the application of the modules is given for energy consumption, but a similar methodology can be used for materials, individually or aggregated.

Setting new standards in MEMS

NASA Astrophysics Data System (ADS)

Rimskog, Magnus; O'Loughlin, Brian J.

2007-02-01

Silex Microsystems handles a wide range of customized MEMS components. This speech will be describing Silex's MEMS foundry work model for providing customized solutions based on MEMS in a cost effective and well controlled manner. Factors for success are the capabilities to reformulate a customer product concept to manufacturing processes in the wafer fab, using standard process modules and production equipment. A well-controlled system increases the likelihood of a first batch success and enables fast ramp-up into volume production. The following success factors can be listed: strong enduring relationships with the customers; highly qualified well-experienced specialists working close with the customer; process solutions and building blocks ready to use out of a library; addressing manufacturing issues in the early design phase; in-house know how to meet demands for volume manufacturing; access to a wafer fab with high capacity, good organization, high availability of equipment, and short lead times; process development done in the manufacturing environment using production equipment for easy ramp-up to volume production. The article covers a method of working to address these factors: to have a long and enduring relationships with customers utilizing MEMS expertise and working close with customers, to translate their product ideas to MEMS components; to have stable process solutions for features such as Low ohmic vias, Spiked electrodes, Cantilevers, Silicon optical mirrors, Micro needles, etc, which can be used and modified for the customer needs; to use a structured development and design methodology in order to handle hundreds of process modules, and setting up standard run sheets. It is also very important to do real time process development in the manufacturing line. It minimizes the lead-time for the ramp-up of production; to have access to a state of the art Wafer Fab which is well organized, controlled and flexible, with high capacity and short lead-time for prototypes. It is crucial to have intimate control of processes, equipment, organization, production flow control and WIP. This has been addressed by using a fully computerized control and reporting system.

Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2006-03-01

Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

Throughput increase by adjustment of the BARC drying time with coat track process

NASA Astrophysics Data System (ADS)

Brakensiek, Nickolas L.; Long, Ryan

2005-05-01

Throughput of a coater module within the coater track is related to the solvent evaporation rate from the material that is being coated. Evaporation rate is controlled by the spin dynamics of the wafer and airflow dynamics over the wafer. Balancing these effects is the key to achieving very uniform coatings across a flat unpatterned wafer. As today"s coat tracks are being pushed to higher throughputs to match the scanner, the coat module throughput must be increased as well. For chemical manufacturers the evaporation rate of the material depends on the solvent used. One measure of relative evaporation rates is to compare flash points of a solvent. The lower the flash point, the quicker the solvent will evaporate. It is possible to formulate products with these volatile solvents although at a price. Shipping and manufacturing a more flammable product increase chances of fire, thereby increasing insurance premiums. Also, the end user of these chemicals will have to take extra precautions in the fab and in storage of these more flammable chemicals. An alternative coat process is possible which would allow higher throughput in a distinct coat module without sacrificing safety. A tradeoff is required for this process, that being a more complicated coat process and a higher viscosity chemical. The coat process uses the fact that evaporation rate depends on the spin dynamics of the wafer by utilizing a series of spin speeds that first would set the thickness of the material followed by a high spin speed to remove the residual solvent. This new process can yield a throughput of over 150 wafers per hour (wph) given two coat modules. The thickness uniformity of less than 2 nm (3 sigma) is still excellent, while drying times are shorter than 10 seconds to achieve the 150 wph throughput targets.

Emission factors of air toxics from semiconductor manufacturing in Korea.

PubMed

Eom, Yun-Sung; Hong, Ji-Hyung; Lee, Suk-Jo; Lee, Eun-Jung; Cha, Jun-Seok; Lee, Dae-Gyun; Bang, Sun-Ae

2006-11-01

The development of local, accurate emission factors is very important for the estimation of reliable national emissions and air quality management. For that, this study is performed for pollutants released to the atmosphere with source-specific emission tests from the semiconductor manufacturing industry. The semiconductor manufacturing industry is one of the major sources of air toxics or hazardous air pollutants (HAPs); thus, understanding the emission characteristics of the emission source is a very important factor in the development of a control strategy. However, in Korea, there is a general lack of information available on air emissions from the semiconductor industry. The major emission sources of air toxics examined from the semiconductor manufacturing industry were wet chemical stations, coating applications, gaseous operations, photolithography, and miscellaneous devices in the wafer fabrication and semiconductor packaging processes. In this study, analyses of emission characteristics, and the estimations of emission data and factors for air toxics, such as acids, bases, heavy metals, and volatile organic compounds from the semiconductor manufacturing process have been performed. The concentration of hydrogen chloride from the packaging process was the highest among all of the processes. In addition, the emission factor of total volatile organic compounds (TVOCs) for the packaging process was higher than that of the wafer fabrication process. Emission factors estimated in this study were compared with those of Taiwan for evaluation, and they were found to be of similar level in the case of TVOCs and fluorine compounds.

Applications of colored petri net and genetic algorithms to cluster tool scheduling

NASA Astrophysics Data System (ADS)

Liu, Tung-Kuan; Kuo, Chih-Jen; Hsiao, Yung-Chin; Tsai, Jinn-Tsong; Chou, Jyh-Horng

2005-12-01

In this paper, we propose a method, which uses Coloured Petri Net (CPN) and genetic algorithm (GA) to obtain an optimal deadlock-free schedule and to solve re-entrant problem for the flexible process of the cluster tool. The process of the cluster tool for producing a wafer usually can be classified into three types: 1) sequential process, 2) parallel process, and 3) sequential parallel process. But these processes are not economical enough to produce a variety of wafers in small volume. Therefore, this paper will propose the flexible process where the operations of fabricating wafers are randomly arranged to achieve the best utilization of the cluster tool. However, the flexible process may have deadlock and re-entrant problems which can be detected by CPN. On the other hand, GAs have been applied to find the optimal schedule for many types of manufacturing processes. Therefore, we successfully integrate CPN and GAs to obtain an optimal schedule with the deadlock and re-entrant problems for the flexible process of the cluster tool.

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

NASA Astrophysics Data System (ADS)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

Implementation of activity-based costing (ABC) to drive cost reduction efforts in a semiconductor manufacturing operation

NASA Astrophysics Data System (ADS)

Naguib, Hussein; Bol, Igor I.; Lora, J.; Chowdhry, R.

1994-09-01

This paper presents a case study on the implementation of ABC to calculate the cost per wafer and to drive cost reduction efforts for a new IC product line. The cost reduction activities were conducted through the efforts of 11 cross-functional teams which included members of the finance, purchasing, technology development, process engineering, equipment engineering, production control, and facility groups. The activities of these cross functional teams were coordinated by a cost council. It will be shown that these activities have resulted in a 57% reduction in the wafer manufacturing cost of the new product line. Factors contributed to successful implementation of an ABC management system are discussed.

First 65nm tape-out using inverse lithography technology (ILT)

NASA Astrophysics Data System (ADS)

Hung, Chi-Yuan; Zhang, Bin; Tang, Deming; Guo, Eric; Pang, Linyong; Liu, Yong; Moore, Andrew; Wang, Kechang

2005-11-01

This paper presents SMIC's first 65nm tape out results, in particularly, using ILT. ILT mathematically determines the mask features that produce the desired on-wafer results with best wafer pattern fidelity, largest process window or both. SMIC applied it to its first 65nm tape-out to study ILT performance and benefits for deep sub-wavelength lithography. SMIC selected 3 SRAM designs as the first test case, because SRAM bit-cells contain features which are challenging lithographically. Mask patterns generated from both conventional OPC and ILT were placed on the mask side-by-side. Mask manufacturability (including fracturing, writing time, inspection, and metrology) and wafer print performance of ILT were studied. The results demonstrated that ILT achieved better CD accuracy, produced substantially larger process window than conventional OPC, and met SMIC's 65nm process window requirements.

Context-based virtual metrology

NASA Astrophysics Data System (ADS)

Ebersbach, Peter; Urbanowicz, Adam M.; Likhachev, Dmitriy; Hartig, Carsten; Shifrin, Michael

2018-03-01

Hybrid and data feed forward methodologies are well established for advanced optical process control solutions in highvolume semiconductor manufacturing. Appropriate information from previous measurements, transferred into advanced optical model(s) at following step(s), provides enhanced accuracy and exactness of the measured topographic (thicknesses, critical dimensions, etc.) and material parameters. In some cases, hybrid or feed-forward data are missed or invalid for dies or for a whole wafer. We focus on approaches of virtual metrology to re-create hybrid or feed-forward data inputs in high-volume manufacturing. We discuss missing data inputs reconstruction which is based on various interpolation and extrapolation schemes and uses information about wafer's process history. Moreover, we demonstrate data reconstruction approach based on machine learning techniques utilizing optical model and measured spectra. And finally, we investigate metrics that allow one to assess error margin of virtual data input.

Overlay improvements using a real time machine learning algorithm

NASA Astrophysics Data System (ADS)

Schmitt-Weaver, Emil; Kubis, Michael; Henke, Wolfgang; Slotboom, Daan; Hoogenboom, Tom; Mulkens, Jan; Coogans, Martyn; ten Berge, Peter; Verkleij, Dick; van de Mast, Frank

2014-04-01

While semiconductor manufacturing is moving towards the 14nm node using immersion lithography, the overlay requirements are tightened to below 5nm. Next to improvements in the immersion scanner platform, enhancements in the overlay optimization and process control are needed to enable these low overlay numbers. Whereas conventional overlay control methods address wafer and lot variation autonomously with wafer pre exposure alignment metrology and post exposure overlay metrology, we see a need to reduce these variations by correlating more of the TWINSCAN system's sensor data directly to the post exposure YieldStar metrology in time. In this paper we will present the results of a study on applying a real time control algorithm based on machine learning technology. Machine learning methods use context and TWINSCAN system sensor data paired with post exposure YieldStar metrology to recognize generic behavior and train the control system to anticipate on this generic behavior. Specific for this study, the data concerns immersion scanner context, sensor data and on-wafer measured overlay data. By making the link between the scanner data and the wafer data we are able to establish a real time relationship. The result is an inline controller that accounts for small changes in scanner hardware performance in time while picking up subtle lot to lot and wafer to wafer deviations introduced by wafer processing.

Automatic vision-based grain optimization and analysis of multi-crystalline solar wafers using hierarchical region growing

NASA Astrophysics Data System (ADS)

Fan, Shu-Kai S.; Tsai, Du-Ming; Chuang, Wei-Che

2017-04-01

Solar power has become an attractive alternative source of energy. The multi-crystalline solar cell has been widely accepted in the market because it has a relatively low manufacturing cost. Multi-crystalline solar wafers with larger grain sizes and fewer grain boundaries are higher quality and convert energy more efficiently than mono-crystalline solar cells. In this article, a new image processing method is proposed for assessing the wafer quality. An adaptive segmentation algorithm based on region growing is developed to separate the closed regions of individual grains. Using the proposed method, the shape and size of each grain in the wafer image can be precisely evaluated. Two measures of average grain size are taken from the literature and modified to estimate the average grain size. The resulting average grain size estimate dictates the quality of the crystalline solar wafers and can be considered a viable quantitative indicator of conversion efficiency.

Computational metrology: enabling full-lot high-density fingerprint information without adding wafer metrology budget, and driving improved monitoring and process control

NASA Astrophysics Data System (ADS)

Kim, Hyun-Sok; Hyun, Min-Sung; Ju, Jae-Wuk; Kim, Young-Sik; Lambregts, Cees; van Rhee, Peter; Kim, Johan; McNamara, Elliott; Tel, Wim; Böcker, Paul; Oh, Nang-Lyeom; Lee, Jun-Hyung

2018-03-01

Computational metrology has been proposed as the way forward to resolve the need for increased metrology density, resulting from extending correction capabilities, without adding actual metrology budget. By exploiting TWINSCAN based metrology information, dense overlay fingerprints for every wafer can be computed. This extended metrology dataset enables new use cases, such as monitoring and control based on fingerprints for every wafer of the lot. This paper gives a detailed description, discusses the accuracy of the fingerprints computed, and will show results obtained in a DRAM HVM manufacturing environment. Also an outlook for improvements and extensions will be shared.

MOCVD process technology for affordable, high-yield, high-performance MESFET structures. Phase 3: MIMIC

NASA Astrophysics Data System (ADS)

1993-01-01

Under the MIMIC Program, Spire has pursued improvements in the manufacturing of low cost, high quality gallium arsenide MOCVD wafers for advanced MIMIC FET applications. As a demonstration of such improvements, Spire was tasked to supply MOCVD wafers for comparison to MBE wafers in the fabrication of millimeter and microwave integrated circuits. In this, the final technical report for Spire's two-year MIMIC contract, we report the results of our work. The main objectives of Spire's MIMIC Phase 3 Program, as outlined in the Statement of Work, were as follows: Optimize the MOCVD growth conditions for the best possible electrical and morphological gallium arsenide. Optimization should include substrate and source qualification as well as determination of the optimum reactor growth conditions; Perform all work on 75 millimeter diameter wafers, using a reactor capable of at least three wafers per run; and Evaluate epitaxial layers using electrical, optical, and morphological tests to obtain thickness, carrier concentration, and mobility data across wafers.

Research and Development Advances Impacting Diminishing Manufacturing Sources and Material Shortages Management

DTIC Science & Technology

2016-06-01

commercially available in 2 to 3 years. The fabs that fabricate today’s ICs service high-volume customers. Manufacturing the small volumes needed by DOD...is simply not cost effective and is disruptive to the process flow. There are smaller specialty fabs that focus on smaller orders and process smaller...process wafers with leading-edge technology, these fabs would have to invest in the same tools as the high-volume fabs —a prohibitive expense. Multi

Manufacturing of High-Efficiency Bi-Facial Tandem Concentrator Solar Cells: February 20, 2009--August 20, 2010

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojtczuk , S.

2011-06-01

Spire Semiconductor made concentrator photovoltaic (CPV) cells using a new bi-facial growth process and met both main program goals: a) 42.5% efficiency 500X (AM1.5D, 25C, 100mW/cm2); and b) Ready to supply at least 3MW/year of such cells at end of program. We explored a unique simple fabrication process to make a N/P 3-junction InGaP/GaAs/InGaAs tandem cells . First, the InGaAs bottom cell is grown on the back of a GaAs wafer. The wafers are then loaded into a cassette, spin-rinsed to remove particles, dipped in dilute NH4OH and spin-dried. The wafers are then removed from the cassette loaded the reactormore » for GaAs middle and InGaP top cell growth on the opposite wafer face (bi-facial growth). By making the epitaxial growth process a bit more complex, we are able to avoid more complex processing (such as large area wafer bonding or epitaxial liftoff) used in the inverted metamorphic (IMM) approach to make similar tandem stacks. We believe the yield is improved compared to an IMM process. After bi-facial epigrowth, standard III-V cell steps (back metal, photolithography for front grid, cap etch, AR coat, dice) are used in the remainder of the process.« less

Accelerating yield ramp through design and manufacturing collaboration

NASA Astrophysics Data System (ADS)

Sarma, Robin C.; Dai, Huixiong; Smayling, Michael C.; Duane, Michael P.

2004-12-01

Ramping an integrated circuit from first silicon bring-up to production yield levels is a challenge for all semiconductor products on the path to profitable market entry. Two approaches to accelerating yield ramp are presented. The first is the use of laser mask writers for fast throughput, high yield, and cost effective pattern transfer. The second is the use of electrical test to find a defect and identify the physical region to probe in failure analysis that is most likely to uncover the root cause. This provides feedback to the design team on modifications to make to the design to avoid the yield issue in a future tape-out revision. Additionally, the process parameter responsible for the root cause of the defect is forward annotated through the design, mask and wafer coordinate systems so it can be monitored in-line on subsequent lots of the manufacturing run. This results in an improved recipe for the manufacturing equipment to potentially prevent the recurrence of the defect and raise yield levels on the following material. The test diagnostics approach is enabled by the seamless traceability of a feature across the design, photomask and wafer, made possible by a common data model for design, mask pattern generation and wafer fabrication.

Precision of a CAD/CAM-engineered surgical template based on a facebow for orthognathic surgery: an experiment with a rapid prototyping maxillary model.

PubMed

Lee, Jae-Won; Lim, Se-Ho; Kim, Moon-Key; Kang, Sang-Hoon

2015-12-01

We examined the precision of a computer-aided design/computer-aided manufacturing-engineered, manufactured, facebow-based surgical guide template (facebow wafer) by comparing it with a bite splint-type orthognathic computer-aided design/computer-aided manufacturing-engineered surgical guide template (bite wafer). We used 24 rapid prototyping (RP) models of the craniofacial skeleton with maxillary deformities. Twelve RP models each were used for the facebow wafer group and the bite wafer group (experimental group). Experimental maxillary orthognathic surgery was performed on the RP models of both groups. Errors were evaluated through comparisons with surgical simulations. We measured the minimum distances from 3 planes of reference to determine the vertical, lateral, and anteroposterior errors at specific measurement points. The measured errors were compared between experimental groups using a t test. There were significant intergroup differences in the lateral error when we compared the absolute values of the 3-D linear distance, as well as vertical, lateral, and anteroposterior errors between experimental groups. The bite wafer method exhibited little lateral error overall and little error in the anterior tooth region. The facebow wafer method exhibited very little vertical error in the posterior molar region. The clinical precision of the facebow wafer method did not significantly exceed that of the bite wafer method. Copyright © 2015 Elsevier Inc. All rights reserved.

Laser wafering for silicon solar.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurfacemore » damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.« less

Solar cell circuit and method for manufacturing solar cells

NASA Technical Reports Server (NTRS)

Mardesich, Nick (Inventor)

2010-01-01

The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

Effects of fluorine contamination on spin-on dielectric thickness in semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Kim, Hyoung-ryeun; Hong, Soonsang; Kim, Samyoung; Oh, Changyeol; Hwang, Sung Min

2018-03-01

In the recent semiconductor industry, as the device shrinks, spin-on dielectric (SOD) has been adopted as a widely used material because of its excellent gap-fill, efficient throughput on mass production. SOD film must be uniformly thin, homogeneous and free of particle defects because it has been perfectly perserved after chemical-mechanical polishing (CMP) and etching process. Spin coating is one of the most common techniques for applying SOD thin films to substrates. In spin coating process, the film thickness and uniformity are strong function of the solution viscosity, the final spin speed and the surface properties. Especially, airborne molecular contaminants (AMCs), such as HF, HCl and NH3, are known to change to surface wetting characteristics. In this work, we study the SOD film thickness as a function of fluorine contamination on the wafer surface. To examine the effects of airborne molecular contamination, the wafers are directly exposed to HF fume followed by SOD coating. It appears that the film thickness decreases by higher contact angle on the wafer surface due to fluorine contamination. The thickness of the SOD film decreased with increasing fluorine contamination on the wafer surface. It means that the wafer surface with more hydrophobic property generates less hydrogen bonding with the functional group of Si-NH in polysilazane(PSZ)-SOD film. Therefore, the wetting properties of silicon wafer surfaces can be degraded by inorganic contamination in SOD coating process.

Evaluation of the Technical Feasibility and Effective Cost of Various Wafer Thicknesses for the Manufacture of Solar Cells

NASA Technical Reports Server (NTRS)

1979-01-01

Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.

Evaluation of the technical feasibility and effective cost of various wafer thicknesses for the manufacture of solar cells

NASA Technical Reports Server (NTRS)

1978-01-01

Three wafering demonstration runs were completed on the Yasunaga wire saw. Wafer thickness/taper uniformity is excellent. Many small problems were encountered with Yasunaga accessories, slowing the effort. A wafer characterization cycle was defined and will be initiated during the next period.

Development of Pulsed Processes for the Manufacture of Solar Cells

NASA Technical Reports Server (NTRS)

1979-01-01

The development status of the process based upon ion implantation for the introduction of junctions and back surface fields is described. A process sequence is presented employing ion implantation and pulse processing. Efforts to improve throughout and descrease process element costs for furnace annealing are described. Design studies for a modular 3,000 wafer per hour pulse processor are discussed.

Extending i-line capabilities through variance characterization and tool enhancement

NASA Astrophysics Data System (ADS)

Miller, Dan; Salinas, Adrian; Peterson, Joel; Vickers, David; Williams, Dan

2006-03-01

Continuous economic pressures have moved a large percent of integrated device manufacturing (IDM) operations either overseas or to foundry operations over the last 10 years. These pressures have left the IDM fabs in the U.S. with required COO improvements in order to maintain operations domestically. While the assets of many of these factories are at a very favorable point in the depreciation life cycle, the equipment and processes are constrained to the quality of the equipment in its original state and the degradation over its installed life. With the objective to enhance output and improve process performance, this factory and their primary lithography process tool supplier have been able to extend the usable life of the existing process tools, increase the output of the tool base, and improve the distribution of the CDs on the product produced. Texas Instruments Incorporated lead an investigation with the POLARIS ® Systems & Services business of FSI International to determine the sources of variance in the i-line processing of a wide array of IC device types. Data from the sources of variance were investigated such as PEB temp, PEB delay time, develop recipe, develop time, and develop programming. While PEB processes are a primary driver of acid catalyzed resists, the develop mode is shown in this work to have an overwhelming impact on the wafer to wafer and across wafer CD performance of these i-line processes. These changes have been able to improve the wafer to wafer CD distribution by more than 80 %, and the within wafer CD distribution by more than 50 % while enabling a greater than 50 % increase in lithography cluster throughput. The paper will discuss the contribution from each of the sources of variance and their importance in overall system performance.

Fabrication of spherical microlens array by combining lapping on silicon wafer and rapid surface molding

NASA Astrophysics Data System (ADS)

Liu, Xiaohua; Zhou, Tianfeng; Zhang, Lin; Zhou, Wenchen; Yu, Jianfeng; Lee, L. James; Yi, Allen Y.

2018-07-01

Silicon is a promising mold material for compression molding because of its properties of hardness and abrasion resistance. Silicon wafers with carbide-bonded graphene coating and micro-patterns were evaluated as molds for the fabrication of microlens arrays. This study presents an efficient but flexible manufacturing method for microlens arrays that combines a lapping method and a rapid molding procedure. Unlike conventional processes for microstructures on silicon wafers, such as diamond machining and photolithography, this research demonstrates a unique approach by employing precision steel balls and diamond slurries to create microlenses with accurate geometry. The feasibility of this method was demonstrated by the fabrication of several microlens arrays with different aperture sizes and pitches on silicon molds. The geometrical accuracy and surface roughness of the microlens arrays were measured using an optical profiler. The measurement results indicated good agreement with the optical profile of the design. The silicon molds were then used to copy the microstructures onto polymer substrates. The uniformity and quality of the samples molded through rapid surface molding were also assessed and statistically quantified. To further evaluate the optical functionality of the molded microlens arrays, the focal lengths of the microlens arrays were measured using a simple optical setup. The measurements showed that the microlens arrays molded in this research were compatible with conventional manufacturing methods. This research demonstrated an alternative low-cost and efficient method for microstructure fabrication on silicon wafers, together with the follow-up optical molding processes.

The establishment of a production-ready manufacturing process utilizing thin silicon substrates for solar cells

NASA Technical Reports Server (NTRS)

Pryor, R. A.

1980-01-01

Three inch diameter Czochralski silicon substrates sliced directly to 5 mil, 8 mil, and 27 mil thicknesses with wire saw techniques were procured. Processing sequences incorporating either diffusion or ion implantation technologies were employed to produce n+p or n+pp+ solar cell structures. These cells were evaluated for performance, ease of fabrication, and cost effectiveness. It was determined that the use of 7 mil or even 4 mil wafers would provide near term cost reductions for solar cell manufacturers.

Evaluation of four inch diameter VGF-Ge substrates used for manufacturing multi-junction solar cell

NASA Astrophysics Data System (ADS)

Kewei, Cao; Tong, Liu; Jingming, Liu; Hui, Xie; Dongyan, Tao; Youwen, Zhao; Zhiyuan, Dong; Feng, Hui

2016-06-01

Low dislocation density Ge wafers grown by a vertical gradient freeze (VGF) method used for the fabrication of multi-junction photovoltaic cells (MJC) have been studied by a whole wafer scale measurement of the lattice parameter, X-ray rocking curves, etch pit density (EPD), impurities concentration, minority carrier lifetime and residual stress. Impurity content in the VGF-Ge wafers, including that of B, is quite low although B2O3 encapsulation is used in the growth process. An obvious difference exists across the whole wafer regarding the distribution of etch pit density, lattice parameter, full width at half maximum (FWHM) of the X-ray rocking curve and residual stress measured by Raman spectra. These are in contrast to a reference Ge substrate wafer grown by the Cz method. The influence of the VGF-Ge substrate on the performance of the MJC is analyzed and evaluated by a comparison of the statistical results of cell parameters. Project supported by the National Natural Science Foundation of China (No. 61474104).

Efficient 'Optical Furnace': A Cheaper Way to Make Solar Cells is Reaching the Marketplace

DOE Office of Scientific and Technical Information (OSTI.GOV)

von Kuegelgen, T.

In Bhushan Sopori's laboratory, you'll find a series of optical furnaces he has developed for fabricating solar cells. When not in use, they sit there discreetly among the lab equipment. But when a solar silicon wafer is placed inside one for processing, Sopori walks over to a computer and types in a temperature profile. Almost immediately this fires up the furnace, which glows inside and selectively heats up the silicon wafer to 800 degrees centigrade by the intense light it produces. Sopori, a principal engineer at the National Renewable Energy Laboratory, has been researching and developing optical furnace technology formore » around 20 years. He says it's a challenging technology to develop because there are many issues to consider when you process a solar cell, especially in optics. Despite the challenges, Sopori and his research team have advanced the technology to the point where it will benefit all solar cell manufacturers. They are now developing a commercial version of the furnace in partnership with a manufacturer. 'This advanced optical furnace is highly energy efficient, and it can be used to manufacture any type of solar cell,' he says. Each type of solar cell or manufacturing process typically requires a different furnace configuration and temperature profile. With NREL's new optical furnace system, a solar cell manufacturer can ask the computer for any temperature profile needed for processing a solar cell, and the same type of furnace is suitable for several solar cell fabrication process steps. 'In the future, solar cell manufacturers will only need this one optical furnace because it can be used for any process, including diffusion, metallization and oxidation,' Sopori says. 'This helps reduce manufacturing costs.' One startup company, Applied Optical Systems, has recognized the furnace's potential for manufacturing thin-film silicon cells. 'We'd like to develop thin-film silicon cells with higher efficiencies, up to 15 to 18 percent, and we believe this furnace will enable us to do so,' says A. Rangappan, founder and CEO of Applied Optical Systems. Rangappan also says it will take only a few minutes for the optical furnace to process a thin-film solar cell, which reduces manufacturing costs. Overall, he estimates the company's solar cell will cost around 80 cents per watt. For manufacturing these thin-film silicon cells, Applied Optical Systems and NREL have developed a partnership through a cooperative research and development agreement (CRADA) to construct an optical furnace system prototype. DOE is providing $500,000 from its Technology Commercialization Development Fund to help offset the prototype's development costs because of the technology's significant market potential. The program has provided the NREL technology transfer office with a total of $4 million to expand such collaborative efforts between NREL researchers and companies. Applied Optical will construct a small version of the optical furnace based on the prototype design in NREL's process development and integration laboratory through a separate CRADA. This small furnace will only develop one solar cell wafer at a time. Then, the company will construct a large, commercial-scale optical furnace at its own facilities, which will turn out around 1,000 solar cell wafers per hour. 'We hope to start using the optical furnace for manufacturing within four to five years,' Rangappan says. Meanwhile, another partnership using the optical furnace has evolved between NREL and SiXtron Advanced Materials, another startup. Together they'll use the optical furnace to optimize the metallization process for novel antireflective solar cell coatings. The process is not only expected to yield higher efficiencies for silicon-based solar cells, but also lowers processing costs and eliminates safety concerns for manufacturers. Most solar cell manufacturers currently use a plasma-enhanced chemical vapor deposition (PECVD) system with compressed and extremely pyrophoric silane gas (SiH4) for applying passivation antireflective coatings (ARC). If silane is exposed to air, the SiH4 will explode - a serious safety issue for high-volume manufacturers. SiXtron's process uses a solid, silicon-based polymer that's converted into noncompressed, nonexplosive gas, which then flows to a standard PECVD system. 'The solid source is so safe to handle that it can be shipped by FedEx,' says Zbigniew Barwicz, president and CEO of SiXtron. Barwicz says manufacturers can use the same PECVD processing equipment for the SiXtron process that they already use for SiH4, a plug-and-play solution. For this novel passivation ARC process, NREL is helping to optimize the metallization parameters. NREL has developed a new technology called optical processing. One of the applications of this process is fire-through contact formation of silicon solar cells.« less

Uniform lateral etching of tungsten in deep trenches utilizing reaction-limited NF3 plasma process

NASA Astrophysics Data System (ADS)

Kofuji, Naoyuki; Mori, Masahito; Nishida, Toshiaki

2017-06-01

The reaction-limited etching of tungsten (W) with NF3 plasma was performed in an attempt to achieve the uniform lateral etching of W in a deep trench, a capability required by manufacturing processes for three-dimensional NAND flash memory. Reaction-limited etching was found to be possible at high pressures without ion irradiation. An almost constant etching rate that showed no dependence on NF3 pressure was obtained. The effect of varying the wafer temperature was also examined. A higher wafer temperature reduced the threshold pressure for reaction-limited etching and also increased the etching rate in the reaction-limited region. Therefore, the control of the wafer temperature is crucial to controlling the etching amount by this method. We found that the uniform lateral etching of W was possible even in a deep trench where the F radical concentration was low.

Overlay Tolerances For VLSI Using Wafer Steppers

NASA Astrophysics Data System (ADS)

Levinson, Harry J.; Rice, Rory

1988-01-01

In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his merchandise appear as attractive as possible, the lithographer is frequently placed in the position of having to explain subtle issues in order to justify his decisions. It is the purpose of this paper to provide that explanation.

Fabless company mask technology approach: fabless but not fab-careless

NASA Astrophysics Data System (ADS)

Hisamura, Toshiyuki; Wu, Xin

2009-10-01

There are two different foundry-fabless working models in the aspect of mask. Some foundries have in-house mask facility while others contract with merchant mask vendors. Significant progress has been made in both kinds of situations. Xilinx as one of the pioneers of fabless semiconductor companies has been continually working very closely with both merchant mask vendors and mask facilities of foundries in past many years, contributed well in both technology development and benefited from corporations. Our involvement in manufacturing is driven by the following three elements: The first element is to understand the new fabrication and mask technologies and then find a suitable design / layout style to better utilize these new technologies and avoid potential risks. Because Xilinx has always been involved in early stage of advanced technology nodes, this early understanding and adoption is especially important. The second element is time to market. Reduction in mask and wafer manufacturing cycle-time can ensure faster time to market. The third element is quality. Commitment to quality is our highest priority for our customers. We have enough visibility on any manufacturing issues affecting the device functionality. Good correlation has consistently been observed between FPGA speed uniformity and the poly mask Critical Dimension (CD) uniformity performance. To achieve FPGA speed uniformity requirement, the manufacturing process as well as the mask and wafer CD uniformity has to be monitored. Xilinx works closely with the wafer foundries and mask suppliers to improve productivity and the yield from initial development stage of mask making operations. As an example, defect density reduction is one of the biggest challenges for mask supplier in development stage to meet the yield target satisfying the mask cost and mask turn-around-time (TAT) requirement. Historically, masks were considered to be defect free but at these advanced process nodes, that assumption no longer holds true. There is a need to be flexible enough on unrepairable defect at early stage but also a need for efficient risk management system on mask defect waivers. Mask defects are often waived in low design criticality area in favor of scrapping the mask and delaying the mask and wafer schedule. Xilinx's involvement in mask manufacturing has contributed significantly to our success in past many nodes and will continue.

Reducing the Cost of Solar Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scanlon, B.

2012-04-01

Solar-powered electricity prices could soon approach those of power from coal or natural gas thanks to collaborative research with solar startup Ampulse Corporation at the National Renewable Energy Laboratory. Silicon wafers account for almost half the cost of today's solar photovoltaic panels, so reducing or eliminating wafer costs is essential to bringing prices down. Current crystalline silicon technology converts energy in a highly efficient manner; however, that technology is manufactured with processes that could stand some improvement. The industry needs a method that is less complex, creates less waste and uses less energy. First, half the refined silicon is lostmore » as dust in the wafer-sawing process, driving module costs higher. Wafers are sawn off of large cylindrical ingots, or boules, of silicon. A typical 2-meter boule loses as many as 6,000 potential wafers during sawing. Second, the wafers produced are much thicker than necessary. To efficiently convert sunlight into electricity, the wafers need be only one-tenth the typical thickness. NREL, the Oak Ridge National Laboratory and Ampulse have partnered on an approach to eliminate this waste and dramatically lower the cost of the finished solar panels. By using a chemical vapor deposition process to grow the silicon on inexpensive foil, Ampulse is able to make the solar cells just thick enough to convert most of the solar energy into electricity. No more sawdust - and no more wasting refined silicon materials. NREL developed the technology to grow high-quality silicon and ORNL developed the metal foil that has the correct crystal structure to support that growth. Ampulse is installing a pilot manufacturing line in NREL's Process Development Integration Laboratory, where solar companies can work closely with lab scientists on integrated equipment to answer pressing questions related to their technology development, as well as rapidly overcoming R and D challenges and risk. NREL's program is focused on transformative innovation in the domestic PV industry. With knowledge and expertise acquired from the PDIL pilot production line tools, Ampulse plans to design a full-scale production line to accommodate long rolls of metal foil. The Ampulse process 'goes straight from pure silicon-containing gas to high-quality crystal silicon film,' said Brent Nelson, the operational manager for the Process Development Integration Laboratory. 'The advantage is you can make the wafer just as thin as you need it - 10 microns or less.' Most of today's solar cells are made out of wafer crystalline silicon, though thin-film cells made of more exotic elements such as copper, indium, gallium, arsenic, cadmium, tellurium and others are making a strong push into the market. The advantage of silicon is its abundance, because it is derived from sand. Silicon's disadvantage is that purifying it into wafers suitable for solar cells can be expensive and energy intensive. Manufacturers add carbon and heat to sand to produce metallurgical-grade silicon, which is useful in other industries, but not yet suitable for making solar cells. So this metallurgical-grade silicon is then converted to pure trichlorosilane (SiCl3) or silane (SiH4) gas. Typically, the purified gas is then converted to create a silicon feedstock at 1,000 degrees Celsius. This feedstock is melted at 1,414 C and recrystallized into crystal ingots that are finally sawed into wafers. The Ampulse method differs in that it eliminates the last two steps in the traditional process and works directly with the silane gas growing only the needed silicon right onto a foil substrate. A team of NREL scientists had developed a way to use a process called hot-wire chemical vapor deposition to thicken silicon wafers with near perfect crystal structure. Using a hot tungsten filament much like the one found in an incandescent light bulb, the silane gas molecules are broken apart and deposited onto the wafer using the chemical vapor deposition technique at about 700 C - a much lower temperature than needed to make the wafer. The hot filament decomposes the gas, allowing silicon layers to deposit directly onto the substrate. Armed with this new technique, Branz and Teplin searched for ways to grow the silicon on cheaper materials and still use it for solar cells. They found the ideal synergy when visiting venture capitalists from Battelle Ventures asked them whether they could do anything useful with a breakthrough from Oak Ridge's superconducting wire development group. The new development, called the rolling assisted biaxially textured substrate (RABiTS), was just the opportunity the two scientists had been seeking. If metal foil is to work as a substrate, it must be able to act as a seed crystal so the silicon can grow on it with the correct structure. The RABiTS process forms crystals in the foil that are correctly oriented to receive the silicon atoms and lock them into just the right positions.« less

Wafer level reliability testing: An idea whose time has come

NASA Technical Reports Server (NTRS)

Trapp, O. D.

1987-01-01

Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

A repeatable and scalable fabrication method for sharp, hollow silicon microneedles

NASA Astrophysics Data System (ADS)

Kim, H.; Theogarajan, L. S.; Pennathur, S.

2018-03-01

Scalability and manufacturability are impeding the mass commercialization of microneedles in the medical field. Specifically, microneedle geometries need to be sharp, beveled, and completely controllable, difficult to achieve with microelectromechanical fabrication techniques. In this work, we performed a parametric study using silicon etch chemistries to optimize the fabrication of scalable and manufacturable beveled silicon hollow microneedles. We theoretically verified our parametric results with diffusion reaction equations and created a design guideline for a various set of miconeedles (80-160 µm needle base width, 100-1000 µm pitch, 40-50 µm inner bore diameter, and 150-350 µm height) to show the repeatability, scalability, and manufacturability of our process. As a result, hollow silicon microneedles with any dimensions can be fabricated with less than 2% non-uniformity across a wafer and 5% deviation between different processes. The key to achieving such high uniformity and consistency is a non-agitated HF-HNO3 bath, silicon nitride masks, and surrounding silicon filler materials with well-defined dimensions. Our proposed method is non-labor intensive, well defined by theory, and straightforward for wafer scale mass production, opening doors to a plethora of potential medical and biosensing applications.

Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

NASA Astrophysics Data System (ADS)

Kubis, Michael; Wise, Rich; Reijnen, Liesbeth; Viatkina, Katja; Jaenen, Patrick; Luca, Melisa; Mernier, Guillaume; Chahine, Charlotte; Hellin, David; Kam, Benjamin; Sobieski, Daniel; Vertommen, Johan; Mulkens, Jan; Dusa, Mircea; Dixit, Girish; Shamma, Nader; Leray, Philippe

2016-03-01

With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

Six Sigma-based approach to optimise the diffusion process of crystalline silicon solar cell manufacturing

NASA Astrophysics Data System (ADS)

Prasad, A. Guru; Saravanan, S.; Gijo, E. V.; Dasari, Sreenivasa Murty; Tatachar, Raghu; Suratkar, Prakash

2016-02-01

Silicon-based photovoltaics (PV) plays the dominant role in the history of PV due to the continuous process and technology improvement in silicon solar cells and its manufacturing flow. In general, silicon solar cell process uses either p-type- or n-type-doped silicon as the starting material. Currently, most of the PV industries use p-type, boron-doped silicon wafer as the starting material. In this work too, the boron-doped wafers were considered as the starting material to create pn junction and phosphorus was used as n-type doping material. Industries use either phosphorous oxy chloride (POCl3) or ortho phosphoric acid (H3PO4) as the precursor for doping phosphorous. While the industries use POCl3 as the precursor, the throughput is lesser than that of the industries' use of H3PO4 due to the manufacturing limitations of the POCl3-based equipments. Hence, in order to achieve the operational excellence in POCl3-based equipments, business strategies such as the Six Sigma methodology have to be adapted. This paper describes the application of Six Sigma Define-Measure-Analyze-Improve-Control methodology for throughput improvement of the phosphorus doping process. The optimised recipe has been implemented in the production and it is running successfully. As a result of this project, an effective gain of 0.9 MW was reported per annum.

Silicon materials task of the low-cost solar array project. Phase 4: Effects of impurities and processing on silicon solar cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Hanes, M. H.; Davis, J. R.; Rohatgi, A.; Rai-Choudhury, P.; Mollenkopf, H. C.

1981-01-01

The effects of impurities, various thermochemical processes, and any impurity-process interactions upon the performance of terrestrial solar cells are defined. The results form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost benefit relationships for the use of less pure, less costly solar grade silicon.

Automated defect spatial signature analysis for semiconductor manufacturing process

DOEpatents

Tobin, Jr., Kenneth W.; Gleason, Shaun S.; Karnowski, Thomas P.; Sari-Sarraf, Hamed

1999-01-01

An apparatus and method for performing automated defect spatial signature alysis on a data set representing defect coordinates and wafer processing information includes categorizing data from the data set into a plurality of high level categories, classifying the categorized data contained in each high level category into user-labeled signature events, and correlating the categorized, classified signature events to a present or incipient anomalous process condition.

Using an extractive Fourier transform infrared spectrometer for improving cleanroom air quality in a semiconductor manufacturing plant.

PubMed

Li, Shou-Nan; Chang, Chin-Ta; Shih, Hui-Ya; Tang, Andy; Li, Alen; Chen, Yin-Yung

2003-01-01

A mobile extractive Fourier transform infrared (FTIR) spectrometer was successfully used to locate, identify, and quantify the "odor" sources inside the cleanroom of a semiconductor manufacturing plant. It was found that ozone (O(3)) gas with a peak concentration of 120 ppm was unexpectedly releasing from a headspace of a drain for transporting used ozonized water and that silicon tetrafluoride (SiF(4)) with a peak concentration of 3 ppm was off-gassed from silicon wafers after dry-etching processing. When the sources of the odors was pinpointed by the FTIR, engineering control measures were applied. For O(3) control, a water-sealed pipeline was added to prevent the O(3) gas (emitting from the ozonized water) from entering the mixing unit. A ventilation system also was applied to the mixing unit in case of O(3) release. For SiF(4) mitigation, before the wafer-out chamber was opened, N(2) gas with a flow rate of 150 L/min was used for 100 sec to purge the wafer-out chamber, and a vacuum system was simultaneously activated to pump away the purging N(2). The effectiveness of the control measures was assured by using the FTIR. In addition, the FTIR was used to monitor the potential hazardous gas emissions during preventative maintenance of the semiconductor manufacturing equipment.

Solid state laser applications in photovoltaics manufacturing

NASA Astrophysics Data System (ADS)

Dunsky, Corey; Colville, Finlay

2008-02-01

Photovoltaic energy conversion devices are on a rapidly accelerating growth path driven by increasing government and societal pressure to use renewable energy as part of an overall strategy to address global warming attributed to greenhouse gas emissions. Initially supported in several countries by generous tax subsidies, solar cell manufacturers are relentlessly pushing the performance/cost ratio of these devices in a quest to reach true cost parity with grid electricity. Clearly this eventual goal will result in further acceleration in the overall market growth. Silicon wafer based solar cells are currently the mainstay of solar end-user installations with a cost up to three times grid electricity. But next-generation technology in the form of thin-film devices promises streamlined, high-volume manufacturing and greatly reduced silicon consumption, resulting in dramatically lower per unit fabrication costs. Notwithstanding the modest conversion efficiency of thin-film devices compared to wafered silicon products (around 6-10% versus 15-20%), this cost reduction is driving existing and start-up solar manufacturers to switch to thin-film production. A key aspect of these devices is patterning large panels to create a monolithic array of series-interconnected cells to form a low current, high voltage module. This patterning is accomplished in three critical scribing processes called P1, P2, and P3. Lasers are the technology of choice for these processes, delivering the desired combination of high throughput and narrow, clean scribes. This paper examines these processes and discusses the optimization of industrial lasers to meet their specific needs.

Advanced overlay: sampling and modeling for optimized run-to-run control

NASA Astrophysics Data System (ADS)

Subramany, Lokesh; Chung, WoongJae; Samudrala, Pavan; Gao, Haiyong; Aung, Nyan; Gomez, Juan Manuel; Gutjahr, Karsten; Park, DongSuk; Snow, Patrick; Garcia-Medina, Miguel; Yap, Lipkong; Demirer, Onur Nihat; Pierson, Bill; Robinson, John C.

2016-03-01

In recent years overlay (OVL) control schemes have become more complicated in order to meet the ever shrinking margins of advanced technology nodes. As a result, this brings up new challenges to be addressed for effective run-to- run OVL control. This work addresses two of these challenges by new advanced analysis techniques: (1) sampling optimization for run-to-run control and (2) bias-variance tradeoff in modeling. The first challenge in a high order OVL control strategy is to optimize the number of measurements and the locations on the wafer, so that the "sample plan" of measurements provides high quality information about the OVL signature on the wafer with acceptable metrology throughput. We solve this tradeoff between accuracy and throughput by using a smart sampling scheme which utilizes various design-based and data-based metrics to increase model accuracy and reduce model uncertainty while avoiding wafer to wafer and within wafer measurement noise caused by metrology, scanner or process. This sort of sampling scheme, combined with an advanced field by field extrapolated modeling algorithm helps to maximize model stability and minimize on product overlay (OPO). Second, the use of higher order overlay models means more degrees of freedom, which enables increased capability to correct for complicated overlay signatures, but also increases sensitivity to process or metrology induced noise. This is also known as the bias-variance trade-off. A high order model that minimizes the bias between the modeled and raw overlay signature on a single wafer will also have a higher variation from wafer to wafer or lot to lot, that is unless an advanced modeling approach is used. In this paper, we characterize the bias-variance trade off to find the optimal scheme. The sampling and modeling solutions proposed in this study are validated by advanced process control (APC) simulations to estimate run-to-run performance, lot-to-lot and wafer-to- wafer model term monitoring to estimate stability and ultimately high volume manufacturing tests to monitor OPO by densely measured OVL data.

Clean solutions to the incoming wafer quality impact on lithography process yield limits in a dynamic copper/low-k research and development environment

NASA Astrophysics Data System (ADS)

Lysaght, Patrick S.; Ybarra, Israel; Sax, Harry; Gupta, Gaurav; West, Michael; Doros, Theodore G.; Beach, James V.; Mello, Jim

2000-06-01

The continued growth of the semiconductor manufacturing industry has been due, in large part, to improved lithographic resolution and overlay across increasingly larger chip areas. Optical lithography continues to be the mainstream technology for the industry with extensions of optical lithography being employed to support 180 nm product and process development. While the industry momentum is behind optical extensions to 130 nm, the key challenge will be maintaining an adequate and affordable process latitude (depth of focus/exposure window) necessary for 10% post-etch critical dimension (CD) control. If the full potential of optical lithography is to be exploited, the current lithographic systems can not be compromised by incoming wafer quality. Impurity specifications of novel Low-k dielectric materials, plating solutions, chemical-mechanical planarization (CMP) slurries, and chemical vapor deposition (CVD) precursors are not well understood and more stringent control measures will be required to meet defect density targets as identified in the National Technology Roadmap for Semiconductors (NTRS). This paper identifies several specific poor quality wafer issues that have been effectively addressed as a result of the introduction of a set of flexible and reliable wafer back surface clean processes developed on the SEZ Spin-Processor 203 configured for processing of 200 mm diameter wafers. Patterned wafers have been back surface etched by means of a novel spin process contamination elimination (SpCE) technique with the wafer suspended by a dynamic nitrogen (N2) flow, device side down, via the Bernoulli effect. Figure 1 illustrates the wafer-chuck orientation within the process chamber during back side etch processing. This paper addresses a number of direct and immediate benefits to the MicraScan IIITM deep-ultraviolet (DUV) step-and-scan system at SEMATECH. These enhancements have resulted from the resolution of three significant problems: (1) back surface particle/residual contamination, (2) wafer flatness, and (3) control of contaminant materials such as copper (Cu). Data associated with the SpCE process, optimized for flatness improvement, particle removal, and Cu contamination control is presented in this paper, as it relates to excessive consumption of the usable depth of focus (UDOF) and comprehensive yield enhancement in photolithography. Additionally, data illustrating a highly effective means of eliminating copper from the wafer backside, bevel/edge, and frontside edge exclusion zone (0.5 mm - 3 mm), is presented. The data, obtained within the framework of standard and experimental copper/low-k device production at SEMATECH, quantifies the benefits of implementing the SEZ SpCE clean operation. Furthermore, this data confirms the feasibility of utilizing existing (non-copper) process equipment in conjunction with the development of copper applications by verifying the reliability and cost effectiveness of SpCE functionality.

Integrated manufacturing approach to attain benchmark team performance

NASA Astrophysics Data System (ADS)

Chen, Shau-Ron; Nguyen, Andrew; Naguib, Hussein

1994-09-01

A Self-Directed Work Team (SDWT) was developed to transfer a polyimide process module from the research laboratory to our wafer fab facility for applications in IC specialty devices. The SDWT implemented processes and tools based on the integration of five manufacturing strategies for continuous improvement. These were: Leadership Through Quality (LTQ), Total Productive Maintenance (TMP), Cycle Time Management (CTM), Activity-Based Costing (ABC), and Total Employee Involvement (TEI). Utilizing these management techniques simultaneously, the team achieved six sigma control of all critical parameters, increased Overall Equipment Effectiveness (OEE) from 20% to 90%, reduced cycle time by 95%, cut polyimide manufacturing cost by 70%, and improved its overall team member skill level by 33%.

Wave-front propagation of rinsing flows on rotating semiconductor wafers

NASA Astrophysics Data System (ADS)

Frostad, John M.; Ylitalo, Andy; Walls, Daniel J.; Mui, David S. L.; Fuller, Gerald G.

2016-11-01

The semiconductor manufacturing industry is migrating to a cleaning technology that involves dispersing cleaning solutions onto a rotating wafer, similar to spin-coating. Advantages include a more continuous overall fabrication process, lower particle level, no cross contamination from the back side of a wafer, and less usage of harsh chemicals for a lower environmental impact. Rapid rotation of the wafer during rinsing can be more effective, but centrifugal forces can pull spiral-like ribbons of liquid radially outward from the advancing wave-front where particles can build up, causing higher instances of device failure at these locations. A better understanding of the rinsing flow is essential for reducing yield losses while taking advantage of the benefits of rotation. In the present work, high-speed video and image processing are used to study the dynamics of the advancing wave-front from an impinging jet on a rotating substrate. The flow-rate and rotation-speed are varied for substrates coated with a thin layer of a second liquid that has a different surface tension than the jet liquid. The difference in surface tension of the two fluids gives rise to Marangoni stresses at the interface that have a significant impact on the rinsing process, despite the extremely short time-scales involved.

Advanced manufacturing rules check (MRC) for fully automated assessment of complex reticle designs

NASA Astrophysics Data System (ADS)

Gladhill, R.; Aguilar, D.; Buck, P. D.; Dawkins, D.; Nolke, S.; Riddick, J.; Straub, J. A.

2005-11-01

Advanced electronic design automation (EDA) tools, with their simulation, modeling, design rule checking, and optical proximity correction capabilities, have facilitated the improvement of first pass wafer yields. While the data produced by these tools may have been processed for optimal wafer manufacturing, it is possible for the same data to be far from ideal for photomask manufacturing, particularly at lithography and inspection stages, resulting in production delays and increased costs. The same EDA tools used to produce the data can be used to detect potential problems for photomask manufacturing in the data. A production implementation of automated photomask manufacturing rule checking (MRC) is presented and discussed for various photomask lithography and inspection lines. This paper will focus on identifying data which may cause production delays at the mask inspection stage. It will be shown how photomask MRC can be used to discover data related problems prior to inspection, separating jobs which are likely to have problems at inspection from those which are not. Photomask MRC can also be used to identify geometries requiring adjustment of inspection parameters for optimal inspection, and to assist with any special handling or change of routing requirements. With this foreknowledge, steps can be taken to avoid production delays that increase manufacturing costs. Finally, the data flow implemented for MRC can be used as a platform for other photomask data preparation tasks.

Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

NASA Astrophysics Data System (ADS)

Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

2016-02-01

In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

Sensor-based atomic layer deposition for rapid process learning and enhanced manufacturability

NASA Astrophysics Data System (ADS)

Lei, Wei

In the search for sensor based atomic layer deposition (ALD) process to accelerate process learning and enhance manufacturability, we have explored new reactor designs and applied in-situ process sensing to W and HfO 2 ALD processes. A novel wafer scale ALD reactor, which features fast gas switching, good process sensing compatibility and significant similarity to the real manufacturing environment, is constructed. The reactor has a unique movable reactor cap design that allows two possible operation modes: (1) steady-state flow with alternating gas species; or (2) fill-and-pump-out cycling of each gas, accelerating the pump-out by lifting the cap to employ the large chamber volume as ballast. Downstream quadrupole mass spectrometry (QMS) sampling is applied for in-situ process sensing of tungsten ALD process. The QMS reveals essential surface reaction dynamics through real-time signals associated with byproduct generation as well as precursor introduction and depletion for each ALD half cycle, which are then used for process learning and optimization. More subtle interactions such as imperfect surface saturation and reactant dose interaction are also directly observed by QMS, indicating that ALD process is more complicated than the suggested layer-by-layer growth. By integrating in real-time the byproduct QMS signals over each exposure and plotting it against process cycle number, the deposition kinetics on the wafer is directly measured. For continuous ALD runs, the total integrated byproduct QMS signal in each ALD run is also linear to ALD film thickness, and therefore can be used for ALD film thickness metrology. The in-situ process sensing is also applied to HfO2 ALD process that is carried out in a furnace type ALD reactor. Precursor dose end-point control is applied to precisely control the precursor dose in each half cycle. Multiple process sensors, including quartz crystal microbalance (QCM) and QMS are used to provide real time process information. The sensing results confirm the proposed surface reaction path and once again reveal the complexity of ALD processes. The impact of this work includes: (1) It explores new ALD reactor designs which enable the implementation of in-situ process sensors for rapid process learning and enhanced manufacturability; (2) It demonstrates in the first time that in-situ QMS can reveal detailed process dynamics and film growth kinetics in wafer-scale ALD process, and thus can be used for ALD film thickness metrology. (3) Based on results from two different processes carried out in two different reactors, it is clear that ALD is a more complicated process than normally believed or advertised, but real-time observation of the operational chemistries in ALD by in-situ sensors provides critical insight to the process and the basis for more effective process control for ALD applications.

Laser pattern generator challenges in airborne molecular contamination protection

NASA Astrophysics Data System (ADS)

Ekberg, Mats; Skotte, Per-Uno; Utterback, Tomas; Paul, Swaraj; Kishkovich, Oleg P.; Hudzik, James S.

2003-08-01

The introduction of photomask laser pattern generators presents new challenges to system designers and manufacturers. One of the laser pattern generator's environmental operating challenges is Airborne Molecular Contamination (AMC), which affects both chemically amplified resists (CAResist) and laser optics. Similar challenges in CAResist protection have already been addressed in semiconductor wafer lithography with reasonable solutions and experience gained by all those involved. However, photomask and photomask equipment manufacturers have not previously had a comparable experience, and some photomask AMC issues differ from those seen in semiconductor wafer lithography. Culminating years of AMC experience, the authors discuss specific requirements of Photomask AMC. Air sampling and material of construction analysis were performed to understand these particular AMC challenges and used to develop an appropriate filtration specification for different classes of contaminates. The authors portray the importance of cooperation between tool designers and AMC experts early in the design stage to assure goal attainment to maximize both process stability and machine productivity in advanced mask making. In conclusion, the authors provide valuable recommendations to both laser tool users and other equipment manufacturers.

Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

NASA Technical Reports Server (NTRS)

Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

2013-01-01

A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

Mask manufacturing of advanced technology designs using multi-beam lithography (Part 1)

NASA Astrophysics Data System (ADS)

Green, Michael; Ham, Young; Dillon, Brian; Kasprowicz, Bryan; Hur, Ik Boum; Park, Joong Hee; Choi, Yohan; McMurran, Jeff; Kamberian, Henry; Chalom, Daniel; Klikovits, Jan; Jurkovic, Michal; Hudek, Peter

2016-10-01

As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask manufacturers. Techniques including advanced Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the new challenges are continued shrinking Sub-Resolution Assist Features (SRAFs), curvilinear SRAFs, and other complex mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible solutions to these coming challenges. In this paper, we study one such process, characterizing mask manufacturing capability of 10nm and below structures with particular focus on minimum resolution and pattern fidelity.

Mask manufacturing of advanced technology designs using multi-beam lithography (part 2)

NASA Astrophysics Data System (ADS)

Green, Michael; Ham, Young; Dillon, Brian; Kasprowicz, Bryan; Hur, Ik Boum; Park, Joong Hee; Choi, Yohan; McMurran, Jeff; Kamberian, Henry; Chalom, Daniel; Klikovits, Jan; Jurkovic, Michal; Hudek, Peter

2016-09-01

As optical lithography is extended into 10nm and below nodes, advanced designs are becoming a key challenge for mask manufacturers. Techniques including advanced optical proximity correction (OPC) and Inverse Lithography Technology (ILT) result in structures that pose a range of issues across the mask manufacturing process. Among the new challenges are continued shrinking sub-resolution assist features (SRAFs), curvilinear SRAFs, and other complex mask geometries that are counter-intuitive relative to the desired wafer pattern. Considerable capability improvements over current mask making methods are necessary to meet the new requirements particularly regarding minimum feature resolution and pattern fidelity. Advanced processes using the IMS Multi-beam Mask Writer (MBMW) are feasible solutions to these coming challenges. In this paper, Part 2 of our study, we further characterize an MBMW process for 10nm and below logic node mask manufacturing including advanced pattern analysis and write time demonstration.

Low cost back contact heterojunction solar cells on thin c-Si wafers. integrating laser and thin film processing for improved manufacturability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hegedus, Steven S.

2015-09-08

An interdigitated back contact (IBC) Si wafer solar cell with deposited a-Si heterojunction (HJ) emitter and contacts is considered the ultimate single junction Si solar cell design. This was confirmed in 2014 by both Panasonic and Sharp Solar producing IBC-HJ cells breaking the previous record Si solar cell efficiency of 25%. But manufacturability at low cost is a concern for the complex IBC-HJ device structure. In this research program, our goals were to addressed the broad industry need for a high-efficiency c-Si cell that overcomes the dominant module cost barriers by 1) developing thin Si wafers synthesized by innovative, kerflessmore » techniques; 2) integrating laser-based processing into most aspects of solar cell fabrication, ensuring high speed and low thermal budgets ; 3) developing an all back contact cell structure compatible with thin wafers using a simplified, low-temperature fabrication process; and 4) designing the contact patterning to enable simplified module assembly. There were a number of significant achievements from this 3 year program. Regarding the front surface, we developed and applied new method to characterize critical interface recombination parameters including interface defect density Dit and hole and electron capture cross-section for use as input for 2D simulation of the IBC cell to guide design and loss analysis. We optimized the antireflection and passivation properties of the front surface texture and a-Si/a-SiN/a-SiC stack depositions to obtain a very low (< 6 mA/cm2) front surface optical losses (reflection and absorption) while maintaining excellent surface passivation (SRV<5 cm/s). We worked with kerfless wafer manufacturers to apply defect-engineering techniques to improve bulk minority-carrier lifetime of thin kerfless wafers by both reducing initial impurities during growth and developing post-growth gettering techniques. This led insights about the kinetics of nickel, chromium, and dislocations in PV-grade silicon and to achieving millisecond lifetimes in kerfless silicon materials. Laser fired contacts to n-Si were developed for the first time using a Al/Sb/Ti metal stack giving contact resistances < 5 mOhm-cm2 when fired through several different dielectric layers. A new 2 step laser+chemical etch isolation technique was developed using a sacrificial top coating which avoids laser damage to Si passivation. Regarding the heterojunction emitter, analysis of front FHJ (1D) and IBC (2D) cells with range of p-layer conditions found that a 2-stage high/low doped p-layer was optimum: the low doped region has lower defects giving higher Voc and the high doped region gave a better contact to the metal. A significant effort was spent studying the patterning process and its contribution to degradation of passivation and reproducibility. Several promising new cleaning, contact and deposition patterning and processing approaches were implemented leading to fabrication of several runs with cells having 19-20% efficiency which were stable over several months. This program resulted in the training and support of 12 graduate students, publication of 21 journal papers and 14 conference papers.« less

In-situ sensing using mass spectrometry and its use for run-to-run control on a W-CVD cluster tool

NASA Astrophysics Data System (ADS)

Gougousi, T.; Sreenivasan, R.; Xu, Y.; Henn-Lecordier, L.; Rubloff, G. W.; Kidder, , J. N.; Zafiriou, E.

2001-01-01

A 300 amu closed-ion-source RGA (Leybold-Inficon Transpector 2) sampling gases directly from the reactor of an ULVAC ERA-1000 cluster tool has been used for real time process monitoring of a W CVD process. The process involves H2 reduction of WF6 at a total pressure of 67 Pa (0.5 torr) to produce W films on Si wafers heated at temperatures around 350 °C. The normalized RGA signals for the H2 reagent depletion and the HF product generation were correlated with the W film weight as measured post-process with an electronic microbalance for the establishment of thin-film weight (thickness) metrology. The metrology uncertainty (about 7% for the HF product) was limited primarily by the very low conversion efficiency of the W CVD process (around 2-3%). The HF metrology was then used to drive a robust run-to-run control algorithm, with the deposition time selected as the manipulated (or controlled) variable. For that purpose, during a 10 wafer run, a systematic process drift was introduced as a -5 °C processing temperature change for each successive wafer, in an otherwise unchanged process recipe. Without adjustment of the deposition time the W film weight (thickness) would have declined by about 50% by the 10th wafer. With the aid of the process control algorithm, an adjusted deposition time was computed so as to maintain constant HF sensing signal, resulting in weight (thickness) control comparable to the accuracy of the thickness metrology. These results suggest that in-situ chemical sensing, and particularly mass spectrometry, provide the basis for wafer state metrology as needed to achieve run-to-run control. Furthermore, since the control accuracy was consistent with the metrology accuracy, we anticipate significant improvements for processes as used in manufacturing, where conversion rates are much higher (40-50%) and corresponding signals for metrology will be much larger.

CZT sensors for Computed Tomography: from crystal growth to image quality

NASA Astrophysics Data System (ADS)

Iniewski, K.

2016-12-01

Recent advances in Traveling Heater Method (THM) growth and device fabrication that require additional processing steps have enabled to dramatically improve hole transport properties and reduce polarization effects in Cadmium Zinc Telluride (CZT) material. As a result high flux operation of CZT sensors at rates in excess of 200 Mcps/mm2 is now possible and has enabled multiple medical imaging companies to start building prototype Computed Tomography (CT) scanners. CZT sensors are also finding new commercial applications in non-destructive testing (NDT) and baggage scanning. In order to prepare for high volume commercial production we are moving from individual tile processing to whole wafer processing using silicon methodologies, such as waxless processing, cassette based/touchless wafer handling. We have been developing parametric level screening at the wafer stage to ensure high wafer quality before detector fabrication in order to maximize production yields. These process improvements enable us, and other CZT manufacturers who pursue similar developments, to provide high volume production for photon counting applications in an economically feasible manner. CZT sensors are capable of delivering both high count rates and high-resolution spectroscopic performance, although it is challenging to achieve both of these attributes simultaneously. The paper discusses material challenges, detector design trade-offs and ASIC architectures required to build cost-effective CZT based detection systems. Photon counting ASICs are essential part of the integrated module platforms as charge-sensitive electronics needs to deal with charge-sharing and pile-up effects.

Advances in photonic MOEMS-MEMS device thinning and polishing

NASA Astrophysics Data System (ADS)

McAneny, James J.; Kennedy, Mark; McGroggan, Tom

2010-02-01

As devices continue to increase in density and complexity, ever more stringent specifications are placed on the wafer scale equipment manufacturers to produce higher quality and higher output. This results in greater investment and more resource being diverted into producing tools and processes which can meet the latest demanding criteria. Substrate materials employed in the fabrication process range from Silicon through InP and include GaAs, InSb and other optical networking or waveguide materials. With this diversity of substrate materials presented, controlling the geometries and surfaces grows progressively more challenging. This article highlights the key parameters which require close monitoring and control in order to produce highly precise wafers as part of the fabrication process. Several as cut and commercially available standard polished wafer materials were used in empirical trials to test tooling options in generating high levels of geometric control over the dimensions while producing high quality surface finishes. Specific attention was given to the measurement and control of: flatness; parallelism/TTV; surface roughness and final target thickness as common specifications required by the industry. By combining the process variables of: plate speed, download pressure, slurry flow rate and concentration, pad type and wafer travel path across the polish pad, the effect of altering these variables was recorded and analysed to realize the optimum process conditions for the materials under test. The results being then used to design improved methods and tooling for the thinning and polishing of photonic materials applied to MOEMS-MEMS device fabrication.

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

NASA Technical Reports Server (NTRS)

Buehler, Martin G.

1988-01-01

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

NASA Astrophysics Data System (ADS)

Syed, Ahmed Rashid

Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by employing broadband quartz rod-transducer assembles). Experimental results, as predicted by prior rigorous simulations, prove that the temperature measurement accuracy obtained through several dynamic runs using the above specified approach, is better than +/-2°C. Furthermore, these results are highly repeatable and independent of wafer treatment conditions, thereby extolling the versatility and immunity of the new method from environmental conditions.

Wafering economies for industrialization from a wafer manufacturer's viewpoint

NASA Technical Reports Server (NTRS)

Rosenfield, T. P.; Fuerst, F. P.

1982-01-01

The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

Finding the right way: DFM versus area efficiency for 65 nm gate layer lithography

NASA Astrophysics Data System (ADS)

Sarma, Chandra S.; Scheer, Steven; Herold, Klaus; Fonseca, Carlos; Thomas, Alan; Schroeder, Uwe P.

2006-03-01

DFM (Design for Manufacturing) has become a buzzword for lithography since the 90nm node. Implementing DFM intelligently can boost yield rates and reliability in semiconductor manufacturing significantly. However, any restriction on the design space will always result in an area loss, thus diminishing the effective shrink factor for a given technology. For a lithographer, the key task is to develop a manufacturable process, while not sacrificing too much area. We have developed a high performing lithography process for attenuated gate level lithography that is based on aggressive illumination and a newly optimized SRAF placement schemes. In this paper we present our methodology and results for this optimization, using an anchored simulation model. The wafer results largely confirm the predictions of the simulations. The use of aggressive SRAF (Sub Resolution Assist Features) strategy leads to reduction of forbidden pitch regions without any SRAF printing. The data show that our OPC is capable of correcting the PC tip to tip distance without bridging between the tips in dense SRAM cells. SRAF strategy for various 2D cases has also been verified on wafer. We have shown that aggressive illumination schemes yielding a high performing lithography process can be employed without sacrificing area. By carefully choosing processing conditions, we were able develop a process that has very little restrictions for design. In our approach, the remaining issues can be addressed by DFM, partly in data prep procedures, which are largely area neutral and transparent to the designers. Hence, we have shown successfully, that DFM and effective technology shrinks are not mutually exclusive.

Novel wafer stepper with violet LED light source

NASA Astrophysics Data System (ADS)

Ting, Yung-Chiang; Shy, Shyi-Long

2014-03-01

Novel wafer stepper by using contact or proximity printing will be developed, using violet LED light source to replace Hg Arc. lamp or laser. Mirror, filter and condenser lens for Hg Arc. Lamp or laser and reduction lens for projection printing can be discarded. Reliability and manufacturing cost of wafer stepper can be improved. Exposure result by using IP3600 resist and wafer stepper with violet LED light source (wave-length 360nm to 410 nm) will be obtained. This novel wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist with sub-micron to 100 micron thickness.

Performance improvements of binary diffractive structures via optimization of the photolithography and dry etch processes

NASA Astrophysics Data System (ADS)

Welch, Kevin; Leonard, Jerry; Jones, Richard D.

2010-08-01

Increasingly stringent requirements on the performance of diffractive optical elements (DOEs) used in wafer scanner illumination systems are driving continuous improvements in their associated manufacturing processes. Specifically, these processes are designed to improve the output pattern uniformity of off-axis illumination systems to minimize degradation in the ultimate imaging performance of a lithographic tool. In this paper, we discuss performance improvements in both photolithographic patterning and RIE etching of fused silica diffractive optical structures. In summary, optimized photolithographic processes were developed to increase critical dimension uniformity and featuresize linearity across the substrate. The photoresist film thickness was also optimized for integration with an improved etch process. This etch process was itself optimized for pattern transfer fidelity, sidewall profile (wall angle, trench bottom flatness), and across-wafer etch depth uniformity. Improvements observed with these processes on idealized test structures (for ease of analysis) led to their implementation in product flows, with comparable increases in performance and yield on customer designs.

Particle detection for patterned wafers of 100nm design rule by evanescent light illumination: analysis of evanescent light scattering using Finite-Difference Time-Domain (FDTD) method

NASA Astrophysics Data System (ADS)

Yoshioka, Toshie; Miyoshi, Takashi; Takaya, Yasuhiro

2005-12-01

To realize high productivity and reliability of the semiconductor, patterned wafers inspection technology to maintain high yield becomes essential in modern semiconductor manufacturing processes. As circuit feature is scaled below 100nm, the conventional imaging and light scattering methods are impossible to apply to the patterned wafers inspection technique, because of diffraction limit and lower S/N ratio. So, we propose a new particle detection method using annular evanescent light illumination. In this method, a converging annular light used as a light source is incident on a micro-hemispherical lens. When the converging angle is larger than critical angle, annular evanescent light is generated under the bottom surface of the hemispherical lens. Evanescent light is localized near by the bottom surface and decays exponentially away from the bottom surface. So, the evanescent light selectively illuminates the particles on the patterned wafer surface, because it can't illuminate the patterned wafer surface. The proposed method evaluates particles on a patterned wafer surface by detecting scattered evanescent light distribution from particles. To analyze the fundamental characteristics of the proposed method, the computer simulation was performed using FDTD method. The simulation results show that the proposed method is effective for detecting 100nm size particle on patterned wafer of 100nm lines and spaces, particularly under the condition that the evanescent light illumination with p-polarization and parallel incident to the line orientation. Finally, the experiment results suggest that 220nm size particle on patterned wafer of about 200nm lines and spaces can be detected.

In-cell overlay metrology by using optical metrology tool

NASA Astrophysics Data System (ADS)

Lee, Honggoo; Han, Sangjun; Hong, Minhyung; Kim, Seungyoung; Lee, Jieun; Lee, DongYoung; Oh, Eungryong; Choi, Ahlin; Park, Hyowon; Liang, Waley; Choi, DongSub; Kim, Nakyoon; Lee, Jeongpyo; Pandev, Stilian; Jeon, Sanghuck; Robinson, John C.

2018-03-01

Overlay is one of the most critical process control steps of semiconductor manufacturing technology. A typical advanced scheme includes an overlay feedback loop based on after litho optical imaging overlay metrology on scribeline targets. The after litho control loop typically involves high frequency sampling: every lot or nearly every lot. An after etch overlay metrology step is often included, at a lower sampling frequency, in order to characterize and compensate for bias. The after etch metrology step often involves CD-SEM metrology, in this case in-cell and ondevice. This work explores an alternative approach using spectroscopic ellipsometry (SE) metrology and a machine learning analysis technique. Advanced 1x nm DRAM wafers were prepared, including both nominal (POR) wafers with mean overlay offsets, as well as DOE wafers with intentional across wafer overlay modulation. After litho metrology was measured using optical imaging metrology, as well as after etch metrology using both SE and CD-SEM for comparison. We investigate 2 types of machine learning techniques with SE data: model-less and model-based, showing excellent performance for after etch in-cell on-device overlay metrology.

The opportunity and challenge of spin coat based nanoimprint lithography

NASA Astrophysics Data System (ADS)

Jung, Wooyung; Cho, Jungbin; Choi, Eunhyuk; Lim, Yonghyun; Bok, Cheolkyu; Tsuji, Masatoshi; Kobayashi, Kei; Kono, Takuya; Nakasugi, Tetsuro

2017-03-01

Since multi patterning with spacer was introduced in NAND flash memory1, multi patterning with spacer has been a promising solution to overcome the resolution limit. However, the increase in process cost of multi patterning with spacer must be a serious burden to device manufacturers as half pitch of patterns gets smaller.2, 3 Even though Nano Imprint Lithography (NIL) has been considered as one of strong candidates to avoid cost issue of multi patterning with spacer, there are still negative viewpoints; template damage induced from particles between template and wafer, overlay degradation induced from shear force between template and wafer, and throughput loss induced from dispensing and spreading resist droplet. Jet and Flash Imprint Lithography (J-FIL4, 5, 6) has contributed to throughput improvement, but still has these above problems. J-FIL consists of 5 steps; dispense of resist droplets on wafer, imprinting template on wafer, filling the gap between template and wafer with resist, UV curing, and separation of template from wafer. If dispensing resist droplets by inkjet is replaced with coating resist at spin coater, additional progress in NIL can be achieved. Template damage from particle can be suppressed by thick resist which is spin-coated at spin coater and covers most of particles on wafer, shear force between template and wafer can be minimized with thick resist, and finally additional throughput enhancement can be achieved by skipping dispense of resist droplets on wafer. On the other hand, spin-coat-based NIL has side effect such as pattern collapse which comes from high separation energy of resist. It is expected that pattern collapse can be improved by the development of resist with low separation energy.

High-density plasma deposition manufacturing productivity improvement

NASA Astrophysics Data System (ADS)

Olmer, Leonard J.; Hudson, Chris P.

1999-09-01

High Density Plasma (HDP) deposition provides a means to deposit high quality dielectrics meeting submicron gap fill requirements. But, compared to traditional PECVD processing, HDP is relatively expensive due to the higher capital cost of the equipment. In order to keep processing costs low, it became necessary to maximize the wafer throughput of HDP processing without degrading the film properties. The approach taken was to optimize the post deposition microwave in-situ clean efficiency. A regression model, based on actual data, indicated that number of wafers processed before a chamber clean was the dominant factor. Furthermore, a design change in the ceramic hardware, surrounding the electrostatic chuck, provided thermal isolation resulting in an enhanced clean rate of the chamber process kit. An infra-red detector located in the chamber exhaust line provided a means to endpoint the clean and in-film particle data confirmed the infra-red results. The combination of increased chamber clean frequency, optimized clean time and improved process.

Big data driven cycle time parallel prediction for production planning in wafer manufacturing

NASA Astrophysics Data System (ADS)

Wang, Junliang; Yang, Jungang; Zhang, Jie; Wang, Xiaoxi; Zhang, Wenjun Chris

2018-07-01

Cycle time forecasting (CTF) is one of the most crucial issues for production planning to keep high delivery reliability in semiconductor wafer fabrication systems (SWFS). This paper proposes a novel data-intensive cycle time (CT) prediction system with parallel computing to rapidly forecast the CT of wafer lots with large datasets. First, a density peak based radial basis function network (DP-RBFN) is designed to forecast the CT with the diverse and agglomerative CT data. Second, the network learning method based on a clustering technique is proposed to determine the density peak. Third, a parallel computing approach for network training is proposed in order to speed up the training process with large scaled CT data. Finally, an experiment with respect to SWFS is presented, which demonstrates that the proposed CTF system can not only speed up the training process of the model but also outperform the radial basis function network, the back-propagation-network and multivariate regression methodology based CTF methods in terms of the mean absolute deviation and standard deviation.

Relation between film character and wafer alignment: critical alignment issues on HV device for VLSI manufacturing

NASA Astrophysics Data System (ADS)

Lo, Yi-Chuan; Lee, Chih-Hsiung; Lin, Hsun-Peng; Peng, Chiou-Shian

1998-06-01

Several continuous splits for wafer alignment target topography conditions to improve epitaxy film alignment were applied. The alignment evaluation among former layer pad oxide thickness (250 angstrom - 500 angstrom), drive oxide thickness (6000 angstrom - 10000 angstrom), nitride film thickness (600 angstrom - 1500 angstrom), initial oxide etch (fully wet etch, fully dry etch and dry plus wet etch) will be split to this experiment. Also various epitaxy deposition recipe such as: epitaxy source (SiHCl2 or SiCHCl3) and growth rate (1.3 micrometer/min approximately 2.0 micrometer/min) will be used to optimize the process window for alignment issue. All the reflectance signal and cross section photography of alignment target during NIKON stepper alignment process will be examined. Experimental results show epitaxy recipe plays an important role to wafer alignment. Low growth rate with good performance conformity epitaxy lead to alignment target avoid washout, pattern shift and distortion. All the results (signal monitor and film character) combined with NIKON's stepper standard laser scanning alignment system will be discussed in this paper.

Hybrid overlay metrology for high order correction by using CDSEM

NASA Astrophysics Data System (ADS)

Leray, Philippe; Halder, Sandip; Lorusso, Gian; Baudemprez, Bart; Inoue, Osamu; Okagawa, Yutaka

2016-03-01

Overlay control has become one of the most critical issues for semiconductor manufacturing. Advanced lithographic scanners use high-order corrections or correction per exposure to reduce the residual overlay. It is not enough in traditional feedback of overlay measurement by using ADI wafer because overlay error depends on other process (etching process and film stress, etc.). It needs high accuracy overlay measurement by using AEI wafer. WIS (Wafer Induced Shift) is the main issue for optical overlay, IBO (Image Based Overlay) and DBO (Diffraction Based Overlay). We design dedicated SEM overlay targets for dual damascene process of N10 by i-ArF multi-patterning. The pattern is same as device-pattern locally. Optical overlay tools select segmented pattern to reduce the WIS. However segmentation has limit, especially the via-pattern, for keeping the sensitivity and accuracy. We evaluate difference between the viapattern and relaxed pitch gratings which are similar to optical overlay target at AEI. CDSEM can estimate asymmetry property of target from image of pattern edge. CDSEM can estimate asymmetry property of target from image of pattern edge. We will compare full map of SEM overlay to full map of optical overlay for high order correction ( correctables and residual fingerprints).

Development of lightweight THUNDER with fiber composite layers

NASA Astrophysics Data System (ADS)

Yoon, Kwang J.; Shin, Sukjoon; Kim, Jusik; Park, Hoon C.; Kwak, Moon K.

2000-06-01

This paper is concerned with design, manufacturing and performance test of lightweight THUNDER using a top fiber composite layer with near-zero CTE, a PZT ceramic wafer and a bottom glass/epoxy layer with high CTE. The main point of this design is to replace the heavy metal layers of THUNDER by the lightweight fiber reinforced plastic layers without losing capabilities to generate high force and displacement. It is possible to save weight up to about 30 percent if we replace the metallic backing materials by the light fiber composite layer. We can also have design flexibility by selecting the fiber direction and the size of prepreg layers. In addition to the lightweight advantage and design flexibility, the proposed device can be manufactured without adhesive layers when we use epoxy resin prepreg system. Glass/epoxy prepregs, a ceramic wafer with electrode surfaces, and a graphite/epoxy prepreg were simply stacked and cured at an elevated temperature by following autoclave bagging process. It was found that the manufactured composite laminate device had a sufficient curvature after detaching form a flat mold. From experimental actuation tests, it was observed that the developed actuator could generate larger actuation displacement than THUNDER.

High-Volume Production of Lightweight Multijunction Solar Cells

NASA Technical Reports Server (NTRS)

Youtsey, Christopher

2015-01-01

MicroLink Devices, Inc., has transitioned its 6-inch epitaxial lift-off (ELO) solar cell fabrication process into a manufacturing platform capable of sustaining large-volume production. This Phase II project improves the ELO process by reducing cycle time and increasing the yield of large-area devices. In addition, all critical device fabrication processes have transitioned to 6-inch production tool sets designed for volume production. An emphasis on automated cassette-to-cassette and batch processes minimizes operator dependence and cell performance variability. MicroLink Devices established a pilot production line capable of at least 1,500 6-inch wafers per month at greater than 80 percent yield. The company also increased the yield and manufacturability of the 6-inch reclaim process, which is crucial to reducing the cost of the cells.

Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

NASA Astrophysics Data System (ADS)

Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

2012-11-01

Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

76 FR 6786 - Notice of a Regional Project Waiver of Section 1605 (Buy American) of the American Recovery and...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-02-08

... manufactured wafer swing check valves. The wafer swing check valves will be used for the filter feed pumps as... check valves will prevent backflow into the filter feed pumps at the Glen Water Reclamation Facility in...

The uses of Man-Made diamond in wafering applications

NASA Technical Reports Server (NTRS)

Fallon, D. B.

1982-01-01

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Consideration of correlativity between litho and etching shape

NASA Astrophysics Data System (ADS)

Matsuoka, Ryoichi; Mito, Hiroaki; Shinoda, Shinichi; Toyoda, Yasutaka

2012-03-01

We developed an effective method for evaluating the correlation of shape of Litho and Etching pattern. The purpose of this method, makes the relations of the shape after that is the etching pattern an index in wafer same as a pattern shape on wafer made by a lithography process. Therefore, this method measures the characteristic of the shape of the wafer pattern by the lithography process and can predict the hotspot pattern shape by the etching process. The method adopts a metrology management system based on DBM (Design Based Metrology). This is the high accurate contouring created by an edge detection algorithm used wafer CD-SEM. Currently, as semiconductor manufacture moves towards even smaller feature size, this necessitates more aggressive optical proximity correction (OPC) to drive the super-resolution technology (RET). In other words, there is a trade-off between highly precise RET and lithography management, and this has a big impact on the semiconductor market that centers on the semiconductor business. 2-dimensional shape of wafer quantification is important as optimal solution over these problems. Although 1-dimensional shape measurement has been performed by the conventional technique, 2-dimensional shape management is needed in the mass production line under the influence of RET. We developed the technique of analyzing distribution of shape edge performance as the shape management technique. In this study, we conducted experiments for correlation method of the pattern (Measurement Based Contouring) as two-dimensional litho and etch evaluation technique. That is, observation of the identical position of a litho and etch was considered. It is possible to analyze variability of the edge of the same position with high precision.

Virtual overlay metrology for fault detection supported with integrated metrology and machine learning

NASA Astrophysics Data System (ADS)

Lee, Hong-Goo; Schmitt-Weaver, Emil; Kim, Min-Suk; Han, Sang-Jun; Kim, Myoung-Soo; Kwon, Won-Taik; Park, Sung-Ki; Ryan, Kevin; Theeuwes, Thomas; Sun, Kyu-Tae; Lim, Young-Wan; Slotboom, Daan; Kubis, Michael; Staecker, Jens

2015-03-01

While semiconductor manufacturing moves toward the 7nm node for logic and 15nm node for memory, an increased emphasis has been placed on reducing the influence known contributors have toward the on product overlay budget. With a machine learning technique known as function approximation, we use a neural network to gain insight to how known contributors, such as those collected with scanner metrology, influence the on product overlay budget. The result is a sufficiently trained function that can approximate overlay for all wafers exposed with the lithography system. As a real world application, inline metrology can be used to measure overlay for a few wafers while using the trained function to approximate overlay vector maps for the entire lot of wafers. With the approximated overlay vector maps for all wafers coming off the track, a process engineer can redirect wafers or lots with overlay signatures outside the standard population to offline metrology for excursion validation. With this added flexibility, engineers will be given more opportunities to catch wafers that need to be reworked, resulting in improved yield. The quality of the derived corrections from measured overlay metrology feedback can be improved using the approximated overlay to trigger, which wafers should or shouldn't be, measured inline. As a development or integration engineer the approximated overlay can be used to gain insight into lots and wafers used for design of experiments (DOE) troubleshooting. In this paper we will present the results of a case study that follows the machine learning function approximation approach to data analysis, with production overlay measured on an inline metrology system at SK hynix.

Wafer plane inspection with soft resist thresholding

NASA Astrophysics Data System (ADS)

Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

2008-10-01

Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just finishing beta testing with a customer developing advanced node designs.

Extension of optical lithography by mask-litho integration with computational lithography

NASA Astrophysics Data System (ADS)

Takigawa, T.; Gronlund, K.; Wiley, J.

2010-05-01

Wafer lithography process windows can be enlarged by using source mask co-optimization (SMO). Recently, SMO including freeform wafer scanner illumination sources has been developed. Freeform sources are generated by a programmable illumination system using a micro-mirror array or by custom Diffractive Optical Elements (DOE). The combination of freeform sources and complex masks generated by SMO show increased wafer lithography process window and reduced MEEF. Full-chip mask optimization using source optimized by SMO can generate complex masks with small variable feature size sub-resolution assist features (SRAF). These complex masks create challenges for accurate mask pattern writing and low false-defect inspection. The accuracy of the small variable-sized mask SRAF patterns is degraded by short range mask process proximity effects. To address the accuracy needed for these complex masks, we developed a highly accurate mask process correction (MPC) capability. It is also difficult to achieve low false-defect inspections of complex masks with conventional mask defect inspection systems. A printability check system, Mask Lithography Manufacturability Check (M-LMC), is developed and integrated with 199-nm high NA inspection system, NPI. M-LMC successfully identifies printable defects from all of the masses of raw defect images collected during the inspection of a complex mask. Long range mask CD uniformity errors are compensated by scanner dose control. A mask CD uniformity error map obtained by mask metrology system is used as input data to the scanner. Using this method, wafer CD uniformity is improved. As reviewed above, mask-litho integration technology with computational lithography is becoming increasingly important.

Graphene growth on Ge(100)/Si(100) substrates by CVD method.

PubMed

Pasternak, Iwona; Wesolowski, Marek; Jozwik, Iwona; Lukosius, Mindaugas; Lupina, Grzegorz; Dabrowski, Pawel; Baranowski, Jacek M; Strupinski, Wlodek

2016-02-22

The successful integration of graphene into microelectronic devices is strongly dependent on the availability of direct deposition processes, which can provide uniform, large area and high quality graphene on nonmetallic substrates. As of today the dominant technology is based on Si and obtaining graphene with Si is treated as the most advantageous solution. However, the formation of carbide during the growth process makes manufacturing graphene on Si wafers extremely challenging. To overcome these difficulties and reach the set goals, we proposed growth of high quality graphene layers by the CVD method on Ge(100)/Si(100) wafers. In addition, a stochastic model was applied in order to describe the graphene growth process on the Ge(100)/Si(100) substrate and to determine the direction of further processes. As a result, high quality graphene was grown, which was proved by Raman spectroscopy results, showing uniform monolayer films with FWHM of the 2D band of 32 cm(-1).

Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response

PubMed Central

Brito, Nuno; Ferreira, Carlos; Alves, Filipe; Cabral, Jorge; Gaspar, João; Monteiro, João; Rocha, Luís

2016-01-01

The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr), quality factor (Q), and pull-in voltage (Vpi) within 1.5 s with repeatability better than 5 ppt (parts per thousand). A full-wafer with 420 devices under test (DUTs) has been evaluated detecting the faulty devices and providing important design specification feedback to the designers. PMID:27657087

Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response.

PubMed

Brito, Nuno; Ferreira, Carlos; Alves, Filipe; Cabral, Jorge; Gaspar, João; Monteiro, João; Rocha, Luís

2016-09-21

The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr), quality factor (Q), and pull-in voltage (Vpi) within 1.5 s with repeatability better than 5 ppt (parts per thousand). A full-wafer with 420 devices under test (DUTs) has been evaluated detecting the faulty devices and providing important design specification feedback to the designers.

Systems-oriented survey of noncontact temperature measurement techniques for rapid thermal processing

NASA Astrophysics Data System (ADS)

Peyton, David; Kinoshita, Hiroyuki; Lo, G. Q.; Kwong, Dim-Lee

1991-04-01

Rapid Thermal Processing (RTP) is becoming a popular approach for future ULSI manufacturing due to its unique low thermal budget and process flexibility. Furthermore when RTP is combined with Chemical Vapor Deposition (CVD) the so-called RTP-CVD technology it can be used to deposit ultrathin films with extremely sharp interfaces and excellent material qualities. One major consequence of this type of processing however is the need for extremely tight control of wafer temperature both to obtain reproducible results for process control and to minimize slip and warpage arising from nonuniformities in temperature. Specifically temperature measurement systems suitable for RiP must have both high precision--within 1-2 degrees--and a short response time--to output an accurate reading on the order of milliseconds for closedloop control. Any such in-situ measurement technique must be non-contact since thermocouples cannot meet the response time requirements and have problems with conductive heat flow in the wafer. To date optical pyrometry has been the most widely used technique for RiP systems although a number of other techniques are being considered and researched. This article examines several such techniques from a systems perspective: optical pyrometry both conventional and a new approach using ellipsometric techniques for concurrent emissivity measurement Raman scattering infrared laser thermometry optical diffraction thermometry and photoacoustic thermometry. Each approach is evaluated in terms of its actual or estimated manufacturing cost remote sensing capability precision repeatability dependence on processing history range

Enabling inspection solutions for future mask technologies through the development of massively parallel E-Beam inspection

NASA Astrophysics Data System (ADS)

Malloy, Matt; Thiel, Brad; Bunday, Benjamin D.; Wurm, Stefan; Jindal, Vibhu; Mukhtar, Maseeh; Quoi, Kathy; Kemen, Thomas; Zeidler, Dirk; Eberle, Anna Lena; Garbowski, Tomasz; Dellemann, Gregor; Peters, Jan Hendrik

2015-09-01

The new device architectures and materials being introduced for sub-10nm manufacturing, combined with the complexity of multiple patterning and the need for improved hotspot detection strategies, have pushed current wafer inspection technologies to their limits. In parallel, gaps in mask inspection capability are growing as new generations of mask technologies are developed to support these sub-10nm wafer manufacturing requirements. In particular, the challenges associated with nanoimprint and extreme ultraviolet (EUV) mask inspection require new strategies that enable fast inspection at high sensitivity. The tradeoffs between sensitivity and throughput for optical and e-beam inspection are well understood. Optical inspection offers the highest throughput and is the current workhorse of the industry for both wafer and mask inspection. E-beam inspection offers the highest sensitivity but has historically lacked the throughput required for widespread adoption in the manufacturing environment. It is unlikely that continued incremental improvements to either technology will meet tomorrow's requirements, and therefore a new inspection technology approach is required; one that combines the high-throughput performance of optical with the high-sensitivity capabilities of e-beam inspection. To support the industry in meeting these challenges SUNY Poly SEMATECH has evaluated disruptive technologies that can meet the requirements for high volume manufacturing (HVM), for both the wafer fab [1] and the mask shop. Highspeed massively parallel e-beam defect inspection has been identified as the leading candidate for addressing the key gaps limiting today's patterned defect inspection techniques. As of late 2014 SUNY Poly SEMATECH completed a review, system analysis, and proof of concept evaluation of multiple e-beam technologies for defect inspection. A champion approach has been identified based on a multibeam technology from Carl Zeiss. This paper includes a discussion on the need for high-speed e-beam inspection and then provides initial imaging results from EUV masks and wafers from 61 and 91 beam demonstration systems. Progress towards high resolution and consistent intentional defect arrays (IDA) is also shown.

Radiation-tolerant imaging device

DOEpatents

Colella, N.J.; Kimbrough, J.R.

1996-11-19

A barrier at a uniform depth for an entire wafer is used to produce imaging devices less susceptible to noise pulses produced by the passage of ionizing radiation. The barrier prevents charge created in the bulk silicon of a CCD detector or a semiconductor logic or memory device from entering the collection volume of each pixel in the imaging device. The charge barrier is a physical barrier, a potential barrier, or a combination of both. The physical barrier is formed by an SiO{sub 2} insulator. The potential barrier is formed by increasing the concentration of majority carriers (holes) to combine with the electron`s generated by the ionizing radiation. A manufacturer of CCD imaging devices can produce radiation-tolerant devices by merely changing the wafer type fed into his process stream from a standard wafer to one possessing a barrier beneath its surface, thus introducing a very small added cost to his production cost. An effective barrier type is an SiO{sub 2} layer. 7 figs.

Curved channel MCP improvement program

NASA Technical Reports Server (NTRS)

Laprade, Bruce N.; Corbett, Michael B.

1987-01-01

Blowholes and blemishes were determined to start at two stages of manufacturing. Sperical blowholes resulted from trapped gas between the high melting temperature bond glass and the MCP wafer. During thermal processing, the trapped gas expanded and displaced the softened channel glass to form a spherical inclusion. This defect was eliminated by grinding the prefritted bond wafer and channel plate wafer to a flatness which ensured intimate contact prior to fusion. Elliptical blowholes or blemishes were introduced during the fiber draw stage. Contaminants trapped between the core bar and clad tubing volatized providing large quantities of expanding gas. These pockets of gas became elongated to an ellipsoidal shape during fiber draw. Special cleanliness procedures were developed for the grinding, polishing, and acid etching of core bars. Improvements in channel curvature fabrication were implemented. The design of the shearing fixture was evaluated. A new design was developed which eliminated an off-axis moment. The shearing furnace design was evaluated. Steady state thermal conditions instead of thermal transient conditions were determined to reduce curvature nonuniformity.

Radiation-tolerant imaging device

DOEpatents

Colella, Nicholas J.; Kimbrough, Joseph R.

1996-01-01

A barrier at a uniform depth for an entire wafer is used to produce imaging devices less susceptible to noise pulses produced by the passage of ionizing radiation. The barrier prevents charge created in the bulk silicon of a CCD detector or a semiconductor logic or memory device from entering the collection volume of each pixel in the imaging device. The charge barrier is a physical barrier, a potential barrier, or a combination of both. The physical barrier is formed by an SiO.sub.2 insulator. The potential barrier is formed by increasing the concentration of majority carriers (holes) to combine with the electron's generated by the ionizing radiation. A manufacturer of CCD imaging devices can produce radiation-tolerant devices by merely changing the wafer type fed into his process stream from a standard wafer to one possessing a barrier beneath its surface, thus introducing a very small added cost to his production cost. An effective barrier type is an SiO.sub.2 layer.

40 CFR Table I-12 to Subpart I of... - Default Emission Factors (1-Uij) for Gas Utilization Rates (Uij) and By-Product Formation Rates...

Code of Federal Regulations, 2014 CFR

2014-07-01

... Use With the Stack Test Method (300 mm and 450 mm Wafers) I Table I-12 to Subpart I of Part 98... (Bijk) for Semiconductor Manufacturing for Use With the Stack Test Method (300 mm and 450 mm Wafers...

40 CFR Table I-11 to Subpart I of... - Default Emission Factors (1-Uij) for Gas Utilization Rates (Uij) and By-Product Formation Rates...

Code of Federal Regulations, 2014 CFR

2014-07-01

... Use With the Stack Test Method (150 mm and 200 mm Wafers) I Table I-11 to Subpart I of Part 98... (Bijk) for Semiconductor Manufacturing for Use With the Stack Test Method (150 mm and 200 mm Wafers...

Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

NASA Astrophysics Data System (ADS)

Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

2018-04-01

Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

A novel approach: high resolution inspection with wafer plane defect detection

NASA Astrophysics Data System (ADS)

Hess, Carl; Wihl, Mark; Shi, Rui-fang; Xiong, Yalin; Pang, Song

2008-05-01

High Resolution reticle inspection is well-established as a proven, effective, and efficient means of detecting yield-limiting mask defects as well as defects which are not immediately yield-limiting yet can enable manufacturing process improvements. Historically, RAPID products have enabled detection of both classes of these defects. The newly-developed Wafer Plane Inspection (WPI) detector technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. Wafer Plane Inspection accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. This has the effect of reducing sensitivity to non-printing defects while enabling higher sensitivity focused in high MEEF areas where small reticle defects still yield significant printing defects on wafers. WPI is a new inspection mode that has been developed by KLA-Tencor and is currently under test with multiple customers. It employs the same transmitted and reflected-light high-resolution images as the industry-standard high-resolution inspections, but with much more sophisticated processing involved. A rigorous mask pattern recovery algorithm is used to convert the transmitted and reflected light images into a modeled representation of the reticle. Lithographic modeling of the scanner is then used to generate an aerial image of the mask. This is followed by resist modeling to determine the exposure of the photoresist. The defect detectors are then applied on this photoresist plane so that only printing defects are detected. Note that no hardware modifications to the inspection system are required to enable this detector. The same tool will be able to perform both our standard High Resolution inspections and the Wafer Plane Inspection detector. This approach has several important features. The ability to ignore non-printing defects and to apply additional effective sensitivity in high MEEF areas enables advanced node development. In addition, the modeling allows the inclusion of important polarization effects that occur in the resist for high NA operation. This allows for the results to better match wafer print results compared to alternate approaches. Finally, the simulation easily allows for the application of arbitrary illumination profiles. With this approach, users of WPI can make use of unique or custom scanner illumination profiles. This allows the more precise modeling of profiles without inspection system hardware modification or loss of company intellectual property. This paper examines WPI in Die:Die mode. Future work includes a review of Die:Database WPI capability.

Analysis of the influence of manufacturing and alignment related errors on an optical tweezer system

NASA Astrophysics Data System (ADS)

Kampmann, R.; Sinzinger, S.

2014-12-01

In this work we present the design process as well as experimental results of an optical system for trapping particles in air. For positioning applications of micro-sized objects onto a glass wafer we developed a highly efficient optical tweezer. The focus of this paper is the iterative design process where we combine classical optics design software with a ray optics based force simulation tool. Thus we can find the best compromise which matches the optical systems restrictions with stable trapping conditions. Furthermore we analyze the influence of manufacturing related tolerances and errors in the alignment process of the optical elements on the optical forces. We present the design procedure for the necessary optical elements as well as experimental results for the aligned system.

Low-temperature magnetotransport in Si/SiGe heterostructures on 300 mm Si wafers

NASA Astrophysics Data System (ADS)

Scappucci, Giordano; Yeoh, L.; Sabbagh, D.; Sammak, A.; Boter, J.; Droulers, G.; Kalhor, N.; Brousse, D.; Veldhorst, M.; Vandersypen, L. M. K.; Thomas, N.; Roberts, J.; Pillarisetty, R.; Amin, P.; George, H. C.; Singh, K. J.; Clarke, J. S.

Undoped Si/SiGe heterostructures are a promising material stack for the development of spin qubits in silicon. To deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. Electron mobility and valley splitting are two key electrical metrics of substrate quality relevant for qubits. Here we present low-temperature magnetotransport measurements of strained Si quantum wells with mobilities in excess of 100000 cm2/Vs fabricated on 300 mm wafers within the framework of advanced semiconductor manufacturing. These results are benchmarked against the results obtained in Si quantum wells deposited on 100 mm Si wafers in an academic research environment. To ensure rapid progress in quantum wells quality we have implemented fast feedback loops from materials growth, to heterostructure FET fabrication, and low temperature characterisation. On this topic we will present recent progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

Scanning electron microscope automatic defect classification of process induced defects

NASA Astrophysics Data System (ADS)

Wolfe, Scott; McGarvey, Steve

2017-03-01

With the integration of high speed Scanning Electron Microscope (SEM) based Automated Defect Redetection (ADR) in both high volume semiconductor manufacturing and Research and Development (R and D), the need for reliable SEM Automated Defect Classification (ADC) has grown tremendously in the past few years. In many high volume manufacturing facilities and R and D operations, defect inspection is performed on EBeam (EB), Bright Field (BF) or Dark Field (DF) defect inspection equipment. A comma separated value (CSV) file is created by both the patterned and non-patterned defect inspection tools. The defect inspection result file contains a list of the inspection anomalies detected during the inspection tools' examination of each structure, or the examination of an entire wafers surface for non-patterned applications. This file is imported into the Defect Review Scanning Electron Microscope (DRSEM). Following the defect inspection result file import, the DRSEM automatically moves the wafer to each defect coordinate and performs ADR. During ADR the DRSEM operates in a reference mode, capturing a SEM image at the exact position of the anomalies coordinates and capturing a SEM image of a reference location in the center of the wafer. A Defect reference image is created based on the Reference image minus the Defect image. The exact coordinates of the defect is calculated based on the calculated defect position and the anomalies stage coordinate calculated when the high magnification SEM defect image is captured. The captured SEM image is processed through either DRSEM ADC binning, exporting to a Yield Analysis System (YAS), or a combination of both. Process Engineers, Yield Analysis Engineers or Failure Analysis Engineers will manually review the captured images to insure that either the YAS defect binning is accurately classifying the defects or that the DRSEM defect binning is accurately classifying the defects. This paper is an exploration of the feasibility of the utilization of a Hitachi RS4000 Defect Review SEM to perform Automatic Defect Classification with the objective of the total automated classification accuracy being greater than human based defect classification binning when the defects do not require multiple process step knowledge for accurate classification. The implementation of DRSEM ADC has the potential to improve the response time between defect detection and defect classification. Faster defect classification will allow for rapid response to yield anomalies that will ultimately reduce the wafer and/or the die yield.

Application of overlay modeling and control with Zernike polynomials in an HVM environment

NASA Astrophysics Data System (ADS)

Ju, JaeWuk; Kim, MinGyu; Lee, JuHan; Nabeth, Jeremy; Jeon, Sanghuck; Heo, Hoyoung; Robinson, John C.; Pierson, Bill

2016-03-01

Shrinking technology nodes and smaller process margins require improved photolithography overlay control. Generally, overlay measurement results are modeled with Cartesian polynomial functions for both intra-field and inter-field models and the model coefficients are sent to an advanced process control (APC) system operating in an XY Cartesian basis. Dampened overlay corrections, typically via exponentially or linearly weighted moving average in time, are then retrieved from the APC system to apply on the scanner in XY Cartesian form for subsequent lot exposure. The goal of the above method is to process lots with corrections that target the least possible overlay misregistration in steady state as well as in change point situations. In this study, we model overlay errors on product using Zernike polynomials with same fitting capability as the process of reference (POR) to represent the wafer-level terms, and use the standard Cartesian polynomials to represent the field-level terms. APC calculations for wafer-level correction are performed in Zernike basis while field-level calculations use standard XY Cartesian basis. Finally, weighted wafer-level correction terms are converted to XY Cartesian space in order to be applied on the scanner, along with field-level corrections, for future wafer exposures. Since Zernike polynomials have the property of being orthogonal in the unit disk we are able to reduce the amount of collinearity between terms and improve overlay stability. Our real time Zernike modeling and feedback evaluation was performed on a 20-lot dataset in a high volume manufacturing (HVM) environment. The measured on-product results were compared to POR and showed a 7% reduction in overlay variation including a 22% terms variation. This led to an on-product raw overlay Mean + 3Sigma X&Y improvement of 5% and resulted in 0.1% yield improvement.

The iMoD display: considerations and challenges in fabricating MOEMS on large area glass substrates

NASA Astrophysics Data System (ADS)

Chui, Clarence; Floyd, Philip D.; Heald, David; Arbuckle, Brian; Lewis, Alan; Kothari, Manish; Cummings, Bill; Palmateer, Lauren; Bos, Jan; Chang, Daniel; Chiang, Jedi; Wang, Li-Ming; Pao, Edmon; Su, Fritz; Huang, Vincent; Lin, Wen-Jian; Tang, Wen-Chung; Yeh, Jia-Jiun; Chan, Chen-Chun; Shu, Fang-Ann; Ju, Yuh-Diing

2007-01-01

QUALCOMM has developed and transferred to manufacturing iMoD displays, a MEMS-based reflective display technology. The iMoD array architecture allows for development at wafer scale, yet easily scales up to enable fabrication on flat-panel display (FPD) lines. In this paper, we will describe the device operation, process flow and fabrication, technology transfer issues, and display performance.

Advanced Technology for Pyrotechnic Mixtures and Munitions

DTIC Science & Technology

1977-07-01

or at ambient I ,/ BLENDING AND CASTING CURING REMOVING MOLD WAFER MANUFACTURING ? / I / SI ,/ iAUTOMATIC LOADING Figure 1. Plastic Bonded Starter Mix...material (fines) is recycled through the compacting rollers. asshwn The Chilsonator used at EA consisted only of the compaction rollers and the controls ...standardized process controls . Oversize material is pulverized and combined with the undersize material for s" ,regranulation in another batch. 2 ,Both the

Glass ceramic ZERODUR enabling nanometer precision

NASA Astrophysics Data System (ADS)

Jedamzik, Ralf; Kunisch, Clemens; Nieder, Johannes; Westerhoff, Thomas

2014-03-01

The IC Lithography roadmap foresees manufacturing of devices with critical dimension of < 20 nm. Overlay specification of single digit nanometer asking for nanometer positioning accuracy requiring sub nanometer position measurement accuracy. The glass ceramic ZERODUR® is a well-established material in critical components of microlithography wafer stepper and offered with an extremely low coefficient of thermal expansion (CTE), the tightest tolerance available on market. SCHOTT is continuously improving manufacturing processes and it's method to measure and characterize the CTE behavior of ZERODUR® to full fill the ever tighter CTE specification for wafer stepper components. In this paper we present the ZERODUR® Lithography Roadmap on the CTE metrology and tolerance. Additionally, simulation calculations based on a physical model are presented predicting the long term CTE behavior of ZERODUR® components to optimize dimensional stability of precision positioning devices. CTE data of several low thermal expansion materials are compared regarding their temperature dependence between - 50°C and + 100°C. ZERODUR® TAILORED 22°C is full filling the tight CTE tolerance of +/- 10 ppb / K within the broadest temperature interval compared to all other materials of this investigation. The data presented in this paper explicitly demonstrates the capability of ZERODUR® to enable the nanometer precision required for future generation of lithography equipment and processes.

Visualization and minimization of clustering of micro-pillars and walls due to liquid film evaporation

NASA Astrophysics Data System (ADS)

Kim, Tae-Hong; Kim, Jungchul; Kim, Ho-Young

2013-11-01

The spin drying, in which a rinsing liquid deposited on a wafer is rapidly dried by wafer spinning, is an essential step in the semiconductor manufacturing process. While the liquid evaporates, its meniscus straddles neighboring submicron-size patterns such as pillars and walls. Then the capillary effects that pull the patterns together may lead to direct contact of the patterns, which is often referred to as pattern leaning. This poses a problem becoming more and more serious as the pattern size shrinks and the aspect ratio of the patterns increases. While the clustering behavior of high-aspect-ratio micro- and nanopillars was investigated before, a technical strategy to prevent such clustering has been pursed in industrial practices without being supported by the recently established theory of elastocapillarity. Here we visualize the clustering behavior of polymer micropatterns with the evaporation of liquid film while varying the sizes and temperature of the micropatterns. We find a critical role of substrate temperature in preventing the leaning of the patterns via changing the evaporation rate and behavior of the liquid film. Also, we construct a regime map that guides us to find a process condition to avoid pattern leaning in semiconductor manufacturing. This work was supported by the National Research Foundation of Korea (grant no. 2012-008023).

Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

DOEpatents

Lin, YuPo J [Naperville, IL; Henry, Michael P [Batavia, IL; Snyder, Seth W [Lincolnwood, IL

2011-07-12

An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

Wafer-scale fabrication of polymer-based microdevices via injection molding and photolithographic micropatterning protocols.

PubMed

Lee, Dae-Sik; Yang, Haesik; Chung, Kwang-Hyo; Pyo, Hyeon-Bong

2005-08-15

Because of their broad applications in biomedical analysis, integrated, polymer-based microdevices incorporating micropatterned metallic and insulating layers are significant in contemporary research. In this study, micropatterns for temperature sensing and microelectrode sets for electroanalysis have been implemented on an injection-molded thin polymer membrane by employing conventional semiconductor processing techniques (i.e., standard photolithographic methods). Cyclic olefin copolymer (COC) is chosen as the polymer substrate because of its high chemical and thermal stability. A COC 5-in. wafer (1-mm thickness) is manufactured using an injection molding method, in which polymer membranes (approximately 130 microm thick and 3 mm x 6 mm in area) are implemented simultaneously in order to reduce local thermal mass around micropatterned heaters and temperature sensors. The highly polished surface (approximately 4 nm within 40 microm x 40 microm area) of the fabricated COC wafer as well as its good resistance to typical process chemicals makes it possible to use the standard photolithographic and etching protocols on the COC wafer. Gold micropatterns with a minimum 5-microm line width are fabricated for making microheaters, temperature sensors, and microelectrodes. An insulating layer of aluminum oxide (Al2O3) is prepared at a COC-endurable low temperature (approximately 120 degrees C) by using atomic layer deposition and micropatterning for the electrode contacts. The fabricated microdevice for heating and temperature sensing shows improved performance of thermal isolation, and microelectrodes display good electrochemical performances for electrochemical sensors. Thus, this novel 5-in. wafer-level microfabrication method is a simple and cost-effective protocol to prepare polymer substrate and demonstrates good potential for application to highly integrated and miniaturized biomedical devices.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Technical Reports Server (NTRS)

Sewell, James S.; Bozada, Christopher A.

1994-01-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Astrophysics Data System (ADS)

Sewell, James S.; Bozada, Christopher A.

1994-02-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Kill ratio calculation for in-line yield prediction

NASA Astrophysics Data System (ADS)

Lorenzo, Alfonso; Oter, David; Cruceta, Sergio; Valtuena, Juan F.; Gonzalez, Gerardo; Mata, Carlos

1999-04-01

The search for better yields in IC manufacturing calls for a smarter use of the vast amount of data that can be generated by a world class production line.In this scenario, in-line inspection processes produce thousands of wafer maps, number of defects, defect type and pictures every day. A step forward is to correlate these with the other big data- generator area: test. In this paper, we present how these data can be put together and correlated to obtain a very useful yield predicting tool. This correlation will first allow us to calculate the kill ratio, i.e. the probability for a defect of a certain size in a certain layer to kill the die. Then we will use that number to estimate the cosmetic yield that a wafer will have.

A Novel High-Efficiency Rear-Contact Solar Cell with Bifacial Sensitivity

NASA Astrophysics Data System (ADS)

Hezel, R.

At present, wafer-based silicon solar cells have a share of more than 90% of the photovoltaic market. Despite rapid growth in the manufacturing volume, accompanied by a significant drop in the module selling price, the high costs currently associated with photovoltaic power generation are one of the most important obstacles to widespread global use of solar electricity. Up to a certain level, a higher production volume is a key driver in cost reduction. However, apart from a drastic reduction of the silicon wafer thickness in conjunction with improved light-trapping schemes, innovative processing sequences combining very high solar cell efficiencies with simple and cost-effective fabrication techniques are needed to become competitive with conventional energy sources and thus to move solar energy from niche to mainstream.

Effect of wafer geometry on lithography chucking processes

NASA Astrophysics Data System (ADS)

Turner, Kevin T.; Sinha, Jaydeep K.

2015-03-01

Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

Particle monitoring and control in vacuum processing equipment

NASA Astrophysics Data System (ADS)

Borden, Peter G., Dr.; Gregg, John

1989-10-01

Particle contamination during vacuum processes has emerged as the largest single source of yield loss in VLSI manufacturing. While a number of tools have been available to help understand the sources and nature of this contamination, only recently has it been possible to monitor free particle levels within vacuum equipment in real-time. As a result, a better picture is available of how particle contamination can affect a variety of processes. This paper reviews some of the work that has been done to monitor particles in vacuum loadlocks and in processes such as etching, sputtering and ion implantation. The aim has been to make free particles in vacuum equipment a measurable process parameter. Achieving this allows particles to be controlled using statistical process control. It will be shown that free particle levels in load locks correlate to wafer surface counts, device yield and process conditions, but that these levels are considerable higher during production than when dummy wafers are run to qualify a system. It will also be shown how real-time free particle monitoring can be used to monitor and control cleaning cycles, how major episodic events can be detected, and how data can be gathered in a format suitable for statistical process control.

Prospects of III-nitride optoelectronics grown on Si.

PubMed

Zhu, D; Wallis, D J; Humphreys, C J

2013-10-01

The use of III-nitride-based light-emitting diodes (LEDs) is now widespread in applications such as indicator lamps, display panels, backlighting for liquid-crystal display TVs and computer screens, traffic lights, etc. To meet the huge market demand and lower the manufacturing cost, the LED industry is moving fast from 2 inch to 4 inch and recently to 6 inch wafer sizes. Although Al2O3 (sapphire) and SiC remain the dominant substrate materials for the epitaxy of nitride LEDs, the use of large Si substrates attracts great interest because Si wafers are readily available in large diameters at low cost. In addition, such wafers are compatible with existing processing lines for 6 inch and larger wafers commonly used in the electronics industry. During the last decade, much exciting progress has been achieved in improving the performance of GaN-on-Si devices. In this contribution, the status and prospects of III-nitride optoelectronics grown on Si substrates are reviewed. The issues involved in the growth of GaN-based LED structures on Si and possible solutions are outlined, together with a brief introduction to some novel in situ and ex situ monitoring/characterization tools, which are especially useful for the growth of GaN-on-Si structures.

Off-target model based OPC

NASA Astrophysics Data System (ADS)

Lu, Mark; Liang, Curtis; King, Dion; Melvin, Lawrence S., III

2005-11-01

Model-based Optical Proximity correction has become an indispensable tool for achieving wafer pattern to design fidelity at current manufacturing process nodes. Most model-based OPC is performed considering the nominal process condition, with limited consideration of through process manufacturing robustness. This study examines the use of off-target process models - models that represent non-nominal process states such as would occur with a dose or focus variation - to understands and manipulate the final pattern correction to a more process robust configuration. The study will first examine and validate the process of generating an off-target model, then examine the quality of the off-target model. Once the off-target model is proven, it will be used to demonstrate methods of generating process robust corrections. The concepts are demonstrated using a 0.13 μm logic gate process. Preliminary indications show success in both off-target model production and process robust corrections. With these off-target models as tools, mask production cycle times can be reduced.

Mechanical impedance measurements for improved cost-effective process monitoring

NASA Astrophysics Data System (ADS)

Clopet, Caroline R.; Pullen, Deborah A.; Badcock, Rodney A.; Ralph, Brian; Fernando, Gerard F.; Mahon, Steve W.

1999-06-01

The aerospace industry has seen a considerably growth in composite usage over the past ten years, especially with the development of cost effective manufacturing techniques such as Resin Transfer Molding and Resin Infusion under Flexible Tooling. The relatively high cost of raw material and conservative processing schedules has limited their growth further in non-aerospace technologies. In-situ process monitoring has been explored for some time as a means to improving the cost efficiency of manufacturing with dielectric spectroscopy and optical fiber sensors being the two primary techniques developed to date. A new emerging technique is discussed here making use of piezoelectric wafers with the ability to sense not only aspects of resin flow but also to detect the change in properties of the resin as it cures. Experimental investigations to date have shown a correlation between mechanical impedance measurements and the mechanical properties of cured epoxy systems with potential for full process monitoring.

Improvements in Cz silicon PV module manufacturing

NASA Astrophysics Data System (ADS)

King, Richard R.; Mitchell, Kim W.; Jester, Theresa L.

1997-02-01

Work focused on reducing the cost per watt of Cz Si photovoltaic modules under Phase I of Siemens Solar Industries' DOE/NREL PVMaT 4A subcontract is described. Module cost components are analyzed and solutions to high-cost items are discussed in terms of specific module designs. The approaches of using larger cells and modules to reduce per-part processing cost, and of minimizing yield loss are particularly leveraging. Yield components for various parts of the fabrication process and various types of defects are shown, and measurements of the force required to break wafers throughout the cell fabrication sequence are given. The most significant type of yield loss is mechanical breakage. The implementation of statistical process control on key manufacturing processes at Siemens Solar Industries is described. Module configurations prototyped during Phase I of this project and scheduled to begin production in Phase II have a projected cost per watt reduction of 19%.

VLED for Si wafer-level packaging

NASA Astrophysics Data System (ADS)

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

NASA Astrophysics Data System (ADS)

Green, Martin A.

2014-03-01

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Empirical OPC rule inference for rapid RET application

NASA Astrophysics Data System (ADS)

Kulkarni, Anand P.

2006-10-01

A given technological node (45 nm, 65 nm) can be expected to process thousands of individual designs. Iterative methods applied at the node consume valuable days in determining proper placement of OPC features, and manufacturing and testing mask correspondence to wafer patterns in a trial-and-error fashion for each design. Repeating this fabrication process for each individual design is a time-consuming and expensive process. We present a novel technique which sidesteps the requirement to iterate through the model-based OPC analysis and pattern verification cycle on subsequent designs at the same node. Our approach relies on the inference of rules from a correct pattern at the wafer surface it relates to the OPC and pre-OPC pattern layout files. We begin with an offline phase where we obtain a "gold standard" design file that has been fab-tested at the node with a prepared, post-OPC layout file that corresponds to the intended on-wafer pattern. We then run an offline analysis to infer rules to be used in this method. During the analysis, our method implicitly identifies contextual OPC strategies for optimal placement of RET features on any design at that node. Using these strategies, we can apply OPC to subsequent designs at the same node with accuracy comparable to the original design file but significantly smaller expected runtimes. The technique promises to offer a rapid and accurate complement to existing RET application strategies.

Filters for Submillimeter Electromagnetic Waves

NASA Technical Reports Server (NTRS)

Berdahl, C. M.

1986-01-01

New manufacturing process produces filters strong, yet have small, precise dimensions and smooth surface finish essential for dichroic filtering at submillimeter wavelengths. Many filters, each one essentially wafer containing fine metal grid made at same time. Stacked square wires plated, fused, and etched to form arrays of holes. Grid of nickel and tin held in brass ring. Wall thickness, thickness of filter (hole depth) and lateral hole dimensions all depend upon operating frequency and filter characteristics.

Plasma etched surface scanning inspection recipe creation based on bidirectional reflectance distribution function and polystyrene latex spheres

NASA Astrophysics Data System (ADS)

Saldana, Tiffany; McGarvey, Steve; Ayres, Steve

2014-04-01

The continual increasing demands upon Plasma Etching systems to self-clean and continue Plasma Etching with minimal downtime allows for the examination of SiCN, SiO2 and SiN defectivity based upon Surface Scanning Inspection Systems (SSIS) wafer scan results. Historically all Surface Scanning Inspection System wafer scanning recipes have been based upon Polystyrene Spheres wafer deposition for each film stack and the subsequent creation of light scattering sizing response curves. This paper explores the feasibility of the elimination of Polystyrene Latex Sphere (PSL) and/or process particle deposition on both filmed and bare Silicon wafers prior to Surface Scanning Inspection System recipe creation. The study will explore the theoretical maximal Surface Scanning Inspection System sensitivity based on PSL recipe creation in conjunction with the maximal sensitivity derived from Bidirectional Reflectance Distribution Function (BRDF) maximal sensitivity modeling recipe creation. The surface roughness (Root Mean Square) of plasma etched wafers varies dependent upon the process film stack. Decrease of the root mean square value of the wafer sample surface equates to higher surface scanning inspection system sensitivity. Maximal sensitivity SSIS scan results from bare and filmed wafers inspected with recipes created based upon Polystyrene/Particle Deposition and recipes created based upon BRDF modeling will be overlaid against each other to determine maximal sensitivity and capture rate for each type of recipe that was created with differing recipe creation modes. A statistically valid sample of defects from each Surface Scanning Inspection system recipe creation mode and each bare wafer/filmed substrate will be reviewed post SSIS System processing on a Defect Review Scanning Electron Microscope (DRSEM). Native defects, Polystyrene Latex Spheres will be collected from each statistically valid defect bin category/size. The data collected from the DRSEM will be utilized to determine the maximum sensitivity capture rate for each recipe creation mode. Emphasis will be placed upon the sizing accuracy of PSL versus BRDF modeling results based upon automated DRSEM defect sizing. An examination the scattering response for both Mie and Rayleigh will be explored in relationship to the reported sizing variance of the SSIS to make a determination of the absolute sizing accuracy of the recipes there were generated based upon BRDF modeling. This paper explores both the commercial and technical considerations of the elimination of PSL deposition as a precursor to SSIS recipe creation. Successful integration of BRDF modeling into the technical aspect of SSIS recipe creation process has the potential to dramatically reduce the recipe creation timeline and vetting period. Integration of BRDF modeling has the potential to greatly reduce the overhead operation costs for High Volume Manufacturing sites by eliminating the associated costs of third party PSL deposition.

Studying post-etching silicon crystal defects on 300mm wafer by automatic defect review AFM

NASA Astrophysics Data System (ADS)

Zandiatashbar, Ardavan; Taylor, Patrick A.; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

2016-03-01

Single crystal silicon wafers are the fundamental elements of semiconductor manufacturing industry. The wafers produced by Czochralski (CZ) process are very high quality single crystalline materials with known defects that are formed during the crystal growth or modified by further processing. While defects can be unfavorable for yield for some manufactured electrical devices, a group of defects like oxide precipitates can have both positive and negative impacts on the final device. The spatial distribution of these defects may be found by scattering techniques. However, due to limitations of scattering (i.e. light wavelength), many crystal defects are either poorly classified or not detected. Therefore a high throughput and accurate characterization of their shape and dimension is essential for reviewing the defects and proper classification. While scanning electron microscopy (SEM) can provide high resolution twodimensional images, atomic force microscopy (AFM) is essential for obtaining three-dimensional information of the defects of interest (DOI) as it is known to provide the highest vertical resolution among all techniques [1]. However AFM's low throughput, limited tip life, and laborious efforts for locating the DOI have been the limitations of this technique for defect review for 300 mm wafers. To address these limitations of AFM, automatic defect review AFM has been introduced recently [2], and is utilized in this work for studying DOI on 300 mm silicon wafer. In this work, we carefully etched a 300 mm silicon wafer with a gaseous acid in a reducing atmosphere at a temperature and for a sufficient duration to decorate and grow the crystal defects to a size capable of being detected as light scattering defects [3]. The etched defects form a shallow structure and their distribution and relative size are inspected by laser light scattering (LLS). However, several groups of defects couldn't be properly sized by the LLS due to the very shallow depth and low light scattering. Likewise, SEM cannot be used effectively for post-inspection defect review and classification of these very shallow types of defects. To verify and obtain accurate shape and three-dimensional information of those defects, automatic defect review AFM (ADR AFM) is utilized for accurate locating and imaging of DOI. In ADR AFM, non-contact mode imaging is used for non-destructive characterization and preserving tip sharpness for data repeatability and reproducibility. Locating DOI and imaging are performed automatically with a throughput of many defects per hour. Topography images of DOI has been collected and compared with SEM images. The ADR AFM has been shown as a non-destructive metrology tool for defect review and obtaining three-dimensional topography information.

The CD control improvement by using CDSEM 2D measurement of complex OPC patterns

NASA Astrophysics Data System (ADS)

Chou, William; Cheng, Jeffrey; Lee, Adder; Cheng, James; Tzeng, Alex C.; Lu, Colbert; Yang, Ray; Lee, Hong Jen; Bandoh, Hideaki; Santo, Izumi; Zhang, Hao; Chen, Chien Kang

2016-10-01

As the process node becomes more advanced, the accuracy and precision in OPC pattern CD are required in mask manufacturing. CD SEM is an essential tool to confirm the mask quality such as CD control, CD uniformity and CD mean to target (MTT). Unfortunately, in some cases of arbitrary enclosed patterns or aggressive OPC patterns, for instance, line with tiny jogs and curvilinear SRAF, CD variation depending on region of interest (ROI) is a very serious problem in mask CD control, even it decreases the wafer yield. For overcoming this situation, the 2-dimensional (2D) method by Holon is adopted. In this paper, we summarize the comparisons of error budget between conventional (1D) and 2D data using CD SEM and the CD performance between mask and wafer by complex OPC patterns including ILT features.

Beads-Milling of Waste Si Sawdust into High-Performance Nanoflakes for Lithium-Ion Batteries

NASA Astrophysics Data System (ADS)

Kasukabe, Takatoshi; Nishihara, Hirotomo; Kimura, Katsuya; Matsumoto, Taketoshi; Kobayashi, Hikaru; Okai, Makoto; Kyotani, Takashi

2017-02-01

Nowadays, ca. 176,640 tons/year of silicon (Si) (>4N) is manufactured for Si wafers used for semiconductor industry. The production of the highly pure Si wafers inevitably includes very high-temperature steps at 1400-2000 °C, which is energy-consuming and environmentally unfriendly. Inefficiently, ca. 45-55% of such costly Si is lost simply as sawdust in the cutting process. In this work, we develop a cost-effective way to recycle Si sawdust as a high-performance anode material for lithium-ion batteries. By a beads-milling process, nanoflakes with extremely small thickness (15-17 nm) and large diameter (0.2-1 μm) are obtained. The nanoflake framework is transformed into a high-performance porous structure, named wrinkled structure, through a self-organization induced by lithiation/delithiation cycling. Under capacity restriction up to 1200 mAh g-1, the best sample can retain the constant capacity over 800 cycles with a reasonably high coulombic efficiency (98-99.8%).

Structured wafer for device processing

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-05-20

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Structured wafer for device processing

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-11-25

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Multivariable control of a rapid thermal processor using ultrasonic sensors

NASA Astrophysics Data System (ADS)

Dankoski, Paul C. P.

The semiconductor manufacturing industry faces the need for tighter control of thermal budget and process variations as circuit feature sizes decrease. Strategies to meet this need include supervisory control, run-to-run control, and real-time feedback control. Typically, the level of control chosen depends upon the actuation and sensing available. Rapid Thermal Processing (RTP) is one step of the manufacturing cycle requiring precise temperature control and hence real-time feedback control. At the outset of this research, the primary ingredient lacking from in-situ RTP temperature control was a suitable sensor. This research looks at an alternative to the traditional approach of pyrometry, which is limited by the unknown and possibly time-varying wafer emissivity. The technique is based upon the temperature dependence of the propagation time of an acoustic wave in the wafer. The aim of this thesis is to evaluate the ultrasonic sensors as a potentially viable sensor for control in RTP. To do this, an experimental implementation was developed at the Center for Integrated Systems. Because of the difficulty in applying a known temperature standard in an RTP environment, calibration to absolute temperature is nontrivial. Given reference propagation delays, multivariable model-based feedback control is applied to the system. The modelling and implementation details are described. The control techniques have been applied to a number of research processes including rapid thermal annealing and rapid thermal crystallization of thin silicon films on quartz/glass substrates.

Stability and imaging of the ASML EUV alpha demo tool

NASA Astrophysics Data System (ADS)

Hermans, Jan V.; Baudemprez, Bart; Lorusso, Gian; Hendrickx, Eric; van Dijk, Andre; Jonckheere, Rik; Goethals, Anne-Marie

2009-03-01

Extreme Ultra-Violet (EUV) lithography is the leading candidate for semiconductor manufacturing of the 22nm technology node and beyond, due to the very short wavelength of 13.5nm. However, reducing the wavelength adds complexity to the lithographic process. The impact of the EUV specific conditions on lithographic performance needs to be understood, before bringing EUV lithography into pre-production. To provide early learning on EUV, an EUV fullfield scanner, the Alpha Demo Tool (ADT) from ASML was installed at IMEC, using a Numerical Aperture (NA) of 0.25. In this paper we report on different aspects of the ADT: the imaging and overlay performance and both short and long-term stability. For 40nm dense Lines-Spaces (LS), the ADT shows an across field overlapping process window of 270nm Depth Of Focus (DOF) at 10% Exposure Latitude (EL) and a wafer CD Uniformity (CDU) of 3nm 3σ, without any corrections for process or reticle. The wafer CDU is correlated to different factors that are known to influence the CD fingerprint from traditional lithography: slit intensity uniformity, focus plane deviation and reticle CD error. Taking these contributions into account, the CD through slit fingerprint for 40nm LS is simulated with excellent agreement to experimental data. The ADT shows good CD stability over 9 months of operation, both intrafield and across wafer. The projection optics reflectivity has not degraded over 9 months. Measured overlay performance with respect to a dry tool shows |Mean|+3σ below 20nm with more correction potential by applying field-by-field corrections (|Mean|+3σ <=10nm). For 22nm SRAM application, both contact hole and metal layer were printed in EUV with 10% CD and 15nm overlay control. Below 40nm, the ADT shows good wafer CDU for 30nm dense and isolated lines (on the same wafer) and 38nm dense Contact Holes (CH). First 28nm dense line CDU data are achieved. The results indicate that the ADT can be used effectively for EUV process development before installation of the pre-production tool, the ASML NXE Gen. 1 at IMEC.

Multi-functional micro electromechanical devices and method of bulk manufacturing same

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2004-01-01

A method of bulk manufacturing SiC sensors is disclosed and claimed. Materials other than SiC may be used as the substrate material. Sensors requiring that the SiC substrate be pierced are also disclosed and claimed. A process flow reversal is employed whereby the metallization is applied first before the recesses are etched into or through the wafer. Aluminum is deposited on the entire planar surface of the metallization. Photoresist is spun onto the substantially planar surface of the Aluminum which is subsequently masked (and developed and removed). Unwanted Aluminum is etched with aqueous TMAH and subsequently the metallization is dry etched. Photoresist is spun onto the still substantially planar surface of Aluminum and oxide and then masked (and developed and removed) leaving the unimidized photoresist behind. Next, ITO is applied over the still substantially planar surface of Aluminum, oxide and unimidized photoresist. Unimidized and exposed photoresist and ITO directly above it are removed with Acetone. Next, deep reactive ion etching attacks exposed oxide not protected by ITO. Finally, hot phosphoric acid removes the Al and ITO enabling wires to connect with the metallization. The back side of the SiC wafer may be also be etched.

Development of high-efficiency solar cells on thin silicon through design optimization and defect passivation

NASA Astrophysics Data System (ADS)

Sheoran, Manav

The focus of this research is to investigate the potential of lower quality cast multicrystalline Si (mc-Si) as well as thin single and mc-Si cells. The overall goal of this research is to improve fundamental understanding of the hydrogen passivation of defects in low-cost Si and the fabrication of high-efficiency solar cells on thin crystalline silicon through low-cost technology development. This is addressed by a combination of five research tasks. The key results of these tasks are summarized below. A novel method was developed to determine the concentration and flux of H diffusing into the Si. The understanding of defect passivation acquired in task 1 was used to fabricate high-efficiency solar cells on cast mc-Si wafers. An optimized co-firing process was developed, which resulted in ˜17% efficient 4 cm2 screen-printed solar cells with single-layer AR coating, and no surface texturing or selective emitter. The HEM mc-Si wafer gave an average efficiency of 16.5%, with a maximum of 16.9%. The identical process applied to the un-textured Float zone (FZ) wafers gave an efficiency of 17.2%. These cells were fabricated using the same simple, manufacturable process involving POCl3 diffusion for a 45 O/sq emitter, PECVD SiNx:H deposition for single-layer antireflection coating and rapid co-firing of a Ag grid, an Al back contact, and Al-BSF formation in a belt furnace. A high-efficiency of 17.1% was achieved on high sheet-resistance HEM mc-Si with good quality contacts. The effects of changing several device parameters on the efficiency of the solar cells was modeled with PC1D and guidelines were established to improve the efficiency from ˜17% to over 20% cells on low lifetime (100 mus), thin (140 mum) silicon wafers. The understanding of enhanced defect hydrogenation and the optimized fabrication sequence was applied to fabricate high-efficiency solar cells on top, middle, and bottom regions of several mc-Si ingots. Screen-printed solar cells were fabricated on different regions of four boron doped ingots and one gallium doped ingot. High post-diffusion and post-hydrogenation lifetime values were obtained, which resulted in high-screen printed cell efficiencies of . 15.9% for wafers from all the regions and ingots, except for the bottom region of the lower-resistivity boron-doped ingot and the gallium-doped ingot. Using a lower-resistivity boron-doped mc-Si ingot did not improve the efficiency. Solar cells fabricated on the first two ingots grown by a novel process, which produced single-crystal Si wafers by HEM casting method, achieved efficiencies of 16% and 17.2% on planar and textured surfaces, respectively. Lifetime in the middle region of both the ingots exceeded 100 mus after cell processing; however top and bottom regions had lower lifetimes due to the impurities that could not be gettered or passivated. Due to the single-crystal nature of the mono-cast ingots, the wafers were textured easily, which decreased the front surface reflectance from 11.8 to 5.3% and resulted in an enhanced Jsc by ˜3mA/cm2. Large area (100 cm2) solar cells fabricated from the middle regions of this novel mono-cast material achieved an efficiency of 16.5%. The mono-cast grown by the HEM process is still under optimization, however, these results show that the material has a great potential for achieving high-efficiencies at a lower cost. Since the cost of Si material alone is ˜50% in a PV module, attempts were made to fabricate thin Si cells with full area Al-BSF and to identify the key factors responsible for efficiency loss in thin cells with conventional Al-BSF. It was found that the high BSRV (300-400 cm/s) and low back surface reflectance (BSR) (63-70%) associated with the full area Al-BSF were the major reasons for the reduced performance of thin cells. Model calculations showed that a BSRV of . 100 cm/s and BSR of ≤ 95% can virtually eliminate the efficiency gap between 300 mum and 115 mum thick cells for these ≥ 200 mus bulk lifetime wafers. Manufacturing cost modeling showed that reducing the mc-Si wafer thickness from 300 mum to 115-150 mum reduces the module manufacturing cost in spite of ˜1% lower cell efficiency. Full area Al-BSF cells suffered efficiency loss upon thinning due to a relatively higher BSRV and poor BSR of Al-BSF. Therefore, in attempts were made to fabricate, characterize and model, a device structure with local back-surface field. Thin solar cells, without any bowing, were fabricated using the dielectric passivated structure and screen-printed contacts. (Abstract shortened by UMI.)

150-nm generation lithography equipment

NASA Astrophysics Data System (ADS)

Deguchi, Nobuyoshi; Uzawa, Shigeyuki

1999-07-01

Lithography by step-and-scan exposure is expected to be the mainstream for semiconductor manufacturing below 180 nm resolution patterns. We have developed a scanner for 150 nm features on either 200 mm or 300 mm wafers. For this system, the synchronous stage system has been redesigned which makes it possible to improve imaging performance and overlay accuracy. A new 300 mm wafer stage enhances productivity while weighting almost the same as the stage for 200 mm wafers. The mainbody mechanical frame incorporates reactive force receiver system to counter the inertial energy and vibrational issues associated with high speed wafer and reticle stage scanning. This report outlines the total system design, new technologies and performance data of the Cannon FPA-5000ES2 step-and-scan exposure tool developed for the 150 nm generation lithography.

Advanced plasma etch technologies for nanopatterning

NASA Astrophysics Data System (ADS)

Wise, Rich

2013-10-01

Advances in patterning techniques have enabled the extension of immersion lithography from 65/45 nm through 14/10 nm device technologies. A key to this increase in patterning capability has been innovation in the subsequent dry plasma etch processing steps. Multiple exposure techniques, such as litho-etch-litho-etch, sidewall image transfer, line/cut mask, and self-aligned structures, have been implemented to solution required device scaling. Advances in dry plasma etch process control across wafer uniformity and etch selectivity to both masking materials have enabled adoption of vertical devices and thin film scaling for increased device performance at a given pitch. Plasma etch processes, such as trilayer etches, aggressive critical dimension shrink techniques, and the extension of resist trim processes, have increased the attainable device dimensions at a given imaging capability. Precise control of the plasma etch parameters affecting across-design variation, defectivity, profile stability within wafer, within lot, and across tools has been successfully implemented to provide manufacturable patterning technology solutions. IBM has addressed these patterning challenges through an integrated total patterning solutions team to provide seamless and synergistic patterning processes to device and integration internal customers. We will discuss these challenges and the innovative plasma etch solutions pioneered by IBM and our alliance partners.

Advanced plasma etch technologies for nanopatterning

NASA Astrophysics Data System (ADS)

Wise, Rich

2012-03-01

Advances in patterning techniques have enabled the extension of immersion lithography from 65/45nm through 14/10nm device technologies. A key to this increase in patterning capability has been innovation in the subsequent dry plasma etch processing steps. Multiple exposure techniques such as litho-etch-litho-etch, sidewall image transfer, line/cut mask and self-aligned structures have been implemented to solution required device scaling. Advances in dry plasma etch process control, across wafer uniformity and etch selectivity to both masking materials and have enabled adoption of vertical devices and thin film scaling for increased device performance at a given pitch. Plasma etch processes such as trilayer etches, aggressive CD shrink techniques, and the extension of resist trim processes have increased the attainable device dimensions at a given imaging capability. Precise control of the plasma etch parameters affecting across design variation, defectivity, profile stability within wafer, within lot, and across tools have been successfully implemented to provide manufacturable patterning technology solutions. IBM has addressed these patterning challenges through an integrated Total Patterning Solutions team to provide seamless and synergistic patterning processes to device and integration internal customers. This paper will discuss these challenges and the innovative plasma etch solutions pioneered by IBM and our alliance partners.

Overcoming low-alignment signal contrast induced alignment failure by alignment signal enhancement

NASA Astrophysics Data System (ADS)

Lee, Byeong Soo; Kim, Young Ha; Hwang, Hyunwoo; Lee, Jeongjin; Kong, Jeong Heung; Kang, Young Seog; Paarhuis, Bart; Kok, Haico; de Graaf, Roelof; Weichselbaum, Stefan; Droste, Richard; Mason, Christopher; Aarts, Igor; de Boeij, Wim P.

2016-03-01

Overlay is one of the key factors which enables optical lithography extension to 1X node DRAM manufacturing. It is natural that accurate wafer alignment is a prerequisite for good device overlay. However, alignment failures or misalignments are commonly observed in a fab. There are many factors which could induce alignment problems. Low alignment signal contrast is one of the main issues. Alignment signal contrast can be degraded by opaque stack materials or by alignment mark degradation due to processes like CMP. This issue can be compounded by mark sub-segmentation from design rules in combination with double or quadruple spacer process. Alignment signal contrast can be improved by applying new material or process optimization, which sometimes lead to the addition of another process-step with higher costs. If we can amplify the signal components containing the position information and reduce other unwanted signal and background contributions then we can improve alignment performance without process change. In this paper we use ASML's new alignment sensor (as was introduced and released on the NXT:1980Di) and sample wafers with special stacks which can induce poor alignment signal to demonstrate alignment and overlay improvement.

Cost of ownership for inspection equipment

NASA Astrophysics Data System (ADS)

Dance, Daren L.; Bryson, Phil

1993-08-01

Cost of Ownership (CoO) models are increasingly a part of the semiconductor equipment evaluation and selection process. These models enable semiconductor manufacturers and equipment suppliers to quantify a system in terms of dollars per wafer. Because of the complex nature of the semiconductor manufacturing process, there are several key attributes that must be considered in order to accurately reflect the true 'cost of ownership'. While most CoO work to date has been applied to production equipment, the need to understand cost of ownership for inspection and metrology equipment presents unique challenges. Critical parameters such as detection sensitivity as a function of size and type of defect are not included in current CoO models yet are, without question, major factors in the technical evaluation process and life-cycle cost. This paper illustrates the relationship between these parameters, as components of the alpha and beta risk, and cost of ownership.

Alternative method for steam generation for thermal oxidation of silicon

NASA Astrophysics Data System (ADS)

Spiegelman, Jeffrey J.

2010-02-01

Thermal oxidation of silicon is an important process step in MEMS device fabrication. Thicker oxide layers are often used as structural components and can take days or weeks to grow, causing high gas costs, maintenance issues, and a process bottleneck. Pyrolytic steam, which is generated from hydrogen and oxygen combustion, was the default process, but has serious drawbacks: cost, safety, particles, permitting, reduced growth rate, rapid hydrogen consumption, component breakdown and limited steam flow rates. Results from data collected over a 24 month period by a MEMS manufacturer supports replacement of pyrolytic torches with RASIRC Steamer technology to reduce process cycle time and enable expansion previously limited by local hydrogen permitting. Data was gathered to determine whether Steamers can meet or exceed pyrolytic torch performance. The RASIRC Steamer uses de-ionized water as its steam source, eliminating dependence on hydrogen and oxygen. A non-porous hydrophilic membrane selectively allows water vapor to pass. All other molecules are greatly restricted, so contaminants in water such as dissolved gases, ions, total organic compounds (TOC), particles, and metals can be removed in the steam phase. The MEMS manufacturer improved growth rate by 7% over the growth range from 1μm to 3.5μm. Over a four month period, wafer uniformity, refractive index, wafer stress, and etch rate were tracked with no significant difference found. The elimination of hydrogen generated a four-month return on investment (ROI). Mean time between failure (MTBF) was increased from 3 weeks to 32 weeks based on three Steamers operating over eight months.

Evolution of gettering technologies for vacuum tubes to getters for MEMS

NASA Astrophysics Data System (ADS)

Amiotti, M.

2008-05-01

Getter materials are technically proven and industrially accepted practical ways to maintain vacuum inside hermetically sealed tubes or devices to assure high reliability and long lifetime of the operating devices. The most industrially proven vacuum tube is the cathode rays tubes (CRTs), where large surfaces are available for the deposition of an evaporated barium film by a radio frequency inductive heating of a stainless steel container filled with a BaAl4 powder mixed to Ni powder. The evolution of the CRTs manufacturing technologies required also new types of barium getters able to withstand some thermal process in air without any deterioration of the evaporation characteristics. In other vacuum tubes such as traveling waves tubes, the space available for the evaporation of a barium film and the sorption capacity required to assure the vacuum for the lifetime of the devices did not allow the use of the barium film, prompting the development of sintered non evaporable getter pills that can be activated during the manufacturing process or by flowing current through an embedded resistance. The same sintered non evaporable getter pills could find usage also in evacuated parts to thermally isolate the infrared sensors for different final applications. In high energy physics particle accelerators, the getter technology moved from localized vacuum getter pumps or getter strips to a getter coating over the surface of vacuum chambers in order to guarantee a more uniform pumping speed. With the advent of solid state electronics, new challenges faced the getter technology to assure long life to vacuum or inert gas filled hermetical packages containing microelectronic devices, especially in the telecommunication and military applications. A well known problem of GaAs devices with Pd or Pt metalization is the H2 poisoning of the metal gate: to prevent this degradation a two layer getter film has been develop to absorb a large quantity of H2 per unit of getter surface. The development of Micro Electro Mechanical Systems (MEMS) with moving parts in a vacuum environment required the development of a new generation of getter film, few microns thick, that can be selectively patterned onto a silicon or glass wafer (usually 4'' or 8''). This wafer with patterned getter film can be used directly as the cap wafer of a wafer to wafer bonded MEMS structure, assuring long life and reliability to the moving MEMS structure especially in automotive applications where thermal cycles are required for qualification.

Multiproject wafers: not just for million-dollar mask sets

NASA Astrophysics Data System (ADS)

Morse, Richard D.

2003-06-01

With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task dictates careful consideration of the alternative methods.

Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

PubMed

Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

2012-03-01

Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

Silicon crystals: Process for manufacturing wafer-like silicon crystals with a columnar structure

NASA Technical Reports Server (NTRS)

Authier, B.

1978-01-01

Wafer-like crystals suitable for making solar cells are formed by pouring molten Si containing suitable dopants into a mold of the desired shape and allowing it to solidify in a temperature gradient, whereby the large surface of the melt in contact with the mold is kept at less than 200 D and the free surface is kept at a temperature of 200-1000 D higher, but below the melting point of Si. The mold can also be made in the form of a slit, whereby the 2 sides of the mold are kept at different temperatures. A mold was milled in the surface of a cylindrical graphite block 200 mm in diameter. The granite block was induction heated and the bottom of the mold was cooled by means of a water-cooled Cu plate, so that the surface of the mold in contact with one of the largest surfaces of the melt was held at approximately 800 D. The free surface of the melt was subjected to thermal radiation from a graphite plate located 2 mm from the surface and heated to 1500 D. The Si crystal formed after slow cooling to room temperature had a columnar structure and was cut with a diamond saw into wafers approximately 500 mm thick. Solar cells prepared from these wafers had efficiencies of 10 to 11%.

Reduction of wafer-edge overlay errors using advanced correction models, optimized for minimal metrology requirements

NASA Astrophysics Data System (ADS)

Kim, Min-Suk; Won, Hwa-Yeon; Jeong, Jong-Mun; Böcker, Paul; Vergaij-Huizer, Lydia; Kupers, Michiel; Jovanović, Milenko; Sochal, Inez; Ryan, Kevin; Sun, Kyu-Tae; Lim, Young-Wan; Byun, Jin-Moo; Kim, Gwang-Gon; Suh, Jung-Joon

2016-03-01

In order to optimize yield in DRAM semiconductor manufacturing for 2x nodes and beyond, the (processing induced) overlay fingerprint towards the edge of the wafer needs to be reduced. Traditionally, this is achieved by acquiring denser overlay metrology at the edge of the wafer, to feed field-by-field corrections. Although field-by-field corrections can be effective in reducing localized overlay errors, the requirement for dense metrology to determine the corrections can become a limiting factor due to a significant increase of metrology time and cost. In this study, a more cost-effective solution has been found in extending the regular correction model with an edge-specific component. This new overlay correction model can be driven by an optimized, sparser sampling especially at the wafer edge area, and also allows for a reduction of noise propagation. Lithography correction potential has been maximized, with significantly less metrology needs. Evaluations have been performed, demonstrating the benefit of edge models in terms of on-product overlay performance, as well as cell based overlay performance based on metrology-to-cell matching improvements. Performance can be increased compared to POR modeling and sampling, which can contribute to (overlay based) yield improvement. Based on advanced modeling including edge components, metrology requirements have been optimized, enabling integrated metrology which drives down overall metrology fab footprint and lithography cycle time.

Within-wafer CD variation induced by wafer shape

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

2016-03-01

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer PEB temperature non-uniformity attributed to wafer warpage is uncorrectable, and the photo-resist profile variation is believed to affect across-wafer etch bias uniformity to some degree.

Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

NASA Astrophysics Data System (ADS)

Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

2001-11-01

The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

CDU improvement technology of etching pattern using photo lithography

NASA Astrophysics Data System (ADS)

Tadokoro, Masahide; Shinozuka, Shinichi; Jyousaka, Megumi; Ogata, Kunie; Morimoto, Tamotsu; Konishi, Yoshitaka

2008-03-01

Semiconductor manufacturing technology has shifted towards finer design rules, and demands for critical dimension uniformity (CDU) of resist patterns have become greater than ever. One of the methods for improving Resist Pattern CDU is to control post-exposure bake (PEB) temperature. When ArF resist is used, there is a certain relationship between critical dimension (CD) and PEB temperature. By utilizing this relationship, Resist Pattern CDU can be improved through control of within-wafer temperature distribution in the PEB process. Resist Pattern CDU improvement contributes to Etching Pattern CDU improvement to a certain degree. To further improve Etching Pattern CDU, etcher-specific CD variation needs to be controlled. In this evaluation, 1. We verified whether etcher-specific CD variation can be controlled and consequently Etching Pattern CDU can be further improved by controlling resist patterns through PEB control. 2. Verifying whether Etching Pattern CDU improvement through has any effect on the reduction in wiring resistance variation. The evaluation procedure is as follows.1. Wafers with base film of Doped Poly-Si (D-Poly) were prepared. 2. Resist patterns were created on them. 3. To determine etcher-specific characteristics, the first etching was performed, and after cleaning off the resist and BARC, CD of etched D-Poly was measured. 4. Using the obtained within-wafer CD distribution of the etching patterns, within-wafer temperature distribution in the PEB process was modified. 5. Resist patterns were created again, followed by the second etching and cleaning, which was followed by CD measurement. We used Optical CD Measurement (OCD) for measurement of resist patterns and etching patterns as OCD is minimally affected by Line Edge Roughness (LER). As a result, 1. We confirmed the effect of Resist Pattern CD control through PEB control on the reduction in etcher-specific CD variation and the improvement in Etching Pattern CDU. 2. The improvement in Etching Pattern CDU has an effect on the reduction in wiring resistance variation. The method for Etching Pattern CDU improvement through PEB control reduces within-wafer variation of MOS transistor's gate length. Therefore, with this method, we can expect to observe uniform within-wafer MOS transistor characteristics.

Development of microchannel plate x-ray optics

NASA Technical Reports Server (NTRS)

Kaaret, Philip; Chen, Andrew

1994-01-01

The goal of this research program was to develop a novel technique for focusing x-rays based on the optical system of a lobster's eye. A lobster eye employs many closely packed reflecting surfaces arranged within a spherical or cylindrical shell. These optics have two unique properties: they have unlimited fields of view and can be manufactured via replication of identical structures. Because the angular resolution is given by the ratio of the size of the individual optical elements to the focal length, optical elements with sizes on the order of one hundred microns are required to achieve good angular resolution with a compact telescope. We employed anisotropic etching of single crystal silicon wafers for the fabrication of micron-scale optical elements. This technique, commonly referred to as silicon micromachining, is based on silicon fabrication techniques developed by the microelectronics industry. An anisotropic etchant is a chemical which etches certain silicon crystal planes much more rapidly than others. Using wafers in which the slowly etched crystal planes are aligned perpendicularly to the wafer surface, it is possible to etch a pattern completely through a wafer with very little distortion. Our optics consist of rectangular pores etched completely through group of zone axes (110) oriented silicon wafers. The larger surfaces of the pores (the mirror elements) were aligned with the group of zone axes (111) planes of the crystal perpendicular to the wafer surface. We have succeeded in producing silicon lenses with a geometry suitable for 1-d focusing x-ray optics. These lenses have an aspect ratio (40:1) suitable for x-ray reflection and have very good optical surface alignment. We have developed a number of process refinements which improved the quality of the lens geometry and the repeatability of the etch process. A significant progress was made in obtaining good optical surface quality. The RMS roughness was decreased from 110 A for our initial lenses to 30 A in the final lenses. A further factor of three improvement in surface quality is required for the production of efficient x-ray optics. In addition to the silicon fabrication, an x-ray beam line was constructed at Columbia for testing the optics.

High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Antoniadis, H.

Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink highmore » efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.« less

DISC - APOLLO 11

NASA Image and Video Library

1969-07-14

S69-39148 (July 1969) --- Close-up view of the one and one-half inch silicon disk which will be left on the moon by the Apollo 11 astronauts. The disk bears messages of goodwill from heads of state of many nations. The process used to make this wafer is the same as that used to manufacture integrated circuits for electronic equipment. It involves making tiny photographic images and depositing metal on the images. The Kennedy half-dollar illustrates the relative size of the memorial disk.

Silicon materials task of the low-cost solar array project. Phase 4: Effects of impurities and processing on silicon solar cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Hanes, M. H.; Davis, J. R.; Rohatgi, A.; Raichoudhury, P.; Mollenkopf, H. C.

1981-01-01

The results of the study form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost-benefit relationships for the use of less pure, less costly solar grade silicon. Cr is highly mobile in silicon even at temperatures as low as 600 C. Contrasting with earlier data for Mo, Ti, and V, Cr concentrations vary from place to place in polycrystalline silicon wafers and the electrically-active Cr concentration in the polysilicon is more than an order of magnitude smaller than would be projected from single crystal impurity data. We hypothesize that Cr diffuses during ingot cooldown after growth, preferentially segregates to grain and becomes electrically deactivated. Accelerated aging data from Ni-contaminated silicon imply that no significant impurity-induced cell performance reduction should be expected over a twenty year device lifetime.

Identification of a new source of reticle contamination

NASA Astrophysics Data System (ADS)

Grenon, Brian J.; Brinkley, David

2016-10-01

Since the introduction of 248 and 193 nm lithography sub-pellicle contamination has been a significant problem and a major contributor to reticle costs and semiconductor yield losses. The most common contaminant identified has been ammonium sulfate commonly called haze, however there have been many other contaminants identified and grouped in the category as haze. In attempts to mitigate the cause of this problem various processes and manufacturing protocols have been put in place to either prevent the problem or identify the source of the problem before there is a negative impact in the wafer fab. In spite of efforts to manage the effects of sub-pellicle contamination in the wafer fab, the problem continues to exist. Over the years we have identified many of the compounds and their sources that exist on the sub-pellicle surface, however one has been elusive. This paper will provide both the identification of this compound and its source.

Process Development for Automated Solar Cell and Module Production. Task 4: Automated Array Assembly

NASA Technical Reports Server (NTRS)

1979-01-01

A baseline sequence for the manufacture of solar cell modules was specified. Starting with silicon wafers, the process goes through damage etching, texture etching, junction formation, plasma edge etch, aluminum back surface field formation, and screen printed metallization to produce finished solar cells. The cells were then series connected on a ribbon and bonded into a finished glass tedlar module. A number of steps required additional developmental effort to verify technical and economic feasibility. These steps include texture etching, plasma edge etch, aluminum back surface field formation, array layup and interconnect, and module edge sealing and framing.

Advances in dual-tone development for pitch frequency doubling

NASA Astrophysics Data System (ADS)

Fonseca, Carlos; Somervell, Mark; Scheer, Steven; Kuwahara, Yuhei; Nafus, Kathleen; Gronheid, Roel; Tarutani, Shinji; Enomoto, Yuuichiro

2010-04-01

Dual-tone development (DTD) has been previously proposed as a potential cost-effective double patterning technique1. DTD was reported as early as in the late 1990's2. The basic principle of dual-tone imaging involves processing exposed resist latent images in both positive tone (aqueous base) and negative tone (organic solvent) developers. Conceptually, DTD has attractive cost benefits since it enables pitch doubling without the need for multiple etch steps of patterned resist layers. While the concept for DTD technique is simple to understand, there are many challenges that must be overcome and understood in order to make it a manufacturing solution. Previous work by the authors demonstrated feasibility of DTD imaging for 50nm half-pitch features at 0.80NA (k1 = 0.21) and discussed challenges lying ahead for printing sub-40nm half-pitch features with DTD. While previous experimental results suggested that clever processing on the wafer track can be used to enable DTD beyond 50nm halfpitch, it also suggest that identifying suitable resist materials or chemistries is essential for achieving successful imaging results with novel resist processing methods on the wafer track. In this work, we present recent advances in the search for resist materials that work in conjunction with novel resist processing methods on the wafer track to enable DTD. Recent experimental results with new resist chemistries, specifically designed for DTD, are presented in this work. We also present simulation studies that help and support identifying resist properties that could enable DTD imaging, which ultimately lead to producing viable DTD resist materials.

National Manufacturing Strategy: Is a National Manufacturing Strategy Essential to National Security?

DTIC Science & Technology

2011-05-01

cycle found nearly a quarter of all homeowners owning more than their home was worth. 11 Both Paul Volcker and Warren Buffet arrived at similar...November 15, 2010; Warren Buffet , Testimony, Financial Crisis Inquiry Commission, June 2, 2010; “Subprime Mortgage Crisis,” http://en.wikipedia.org...overseas manufacturing. Case Study: Semiconductor Wafer Industry. The history of the semiconductor industry is an instructive account . It begins with

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horowitz, Kelsey A; Bench Reese, Samantha R; Remo, Timothy W

This brochure, published as an annual research highlight of the Clean Energy Manufacturing Analysis Center (CEMAC), summarizes CEMAC analysis of silicon carbide (SiC) power electronics for variable frequency motor drives. The key finding presented is that variations in manufacturing expertise, yields, and access to existing facilities impact regional costs and manufacturing location decisions for SiC ingots, wafers, chips, and power modules more than do core country-specific factors such as labor and electricity costs.

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

2018-04-01

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

Wafer screening device and methods for wafer screening

DOEpatents

Sopori, Bhushan; Rupnowski, Przemyslaw

2014-07-15

Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

Thinning of PLZT ceramic wafers for sensor integration

NASA Astrophysics Data System (ADS)

Jin, Na; Liu, Weiguo

2010-08-01

Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

Cost-effective method of manufacturing a 3D MEMS optical switch

NASA Astrophysics Data System (ADS)

Carr, Emily; Zhang, Ping; Keebaugh, Doug; Chau, Kelvin

2009-02-01

growth of data and video transport networks. All-optical switching eliminates the need for optical-electrical conversion offering the ability to switch optical signals transparently: independent of data rates, formats and wavelength. It also provides network operators much needed automation capabilities to create, monitor and protect optical light paths. To further accelerate the market penetration, it is necessary to identify a path to reduce the manufacturing cost significantly as well as enhance the overall system performance, uniformity and reliability. Currently, most MEMS optical switches are assembled through die level flip-chip bonding with either epoxies or solder bumps. This is due to the alignment accuracy requirements of the switch assembly, defect matching of individual die, and cost of the individual components. In this paper, a wafer level assembly approach is reported based on silicon fusion bonding which aims to reduce the packaging time, defect count and cost through volume production. This approach is successfully demonstrated by the integration of two 6-inch wafers: a mirror array wafer and a "snap-guard" wafer, which provides a mechanical structure on top of the micromirror to prevent electrostatic snap-down. The direct silicon-to-silicon bond eliminates the CTEmismatch and stress issues caused by non-silicon bonding agents. Results from a completed integrated switch assembly will be presented, which demonstrates the reliability and uniformity of some key parameters of this MEMS optical switch.

Design and manufacture of a lightweight piezo-composite curved actuator

NASA Astrophysics Data System (ADS)

Yoon, K. Joon; Shin, Seokjun; Park, Hoon C.; Goo, Nam Seo

2002-02-01

In this paper we are concerned with the design, manufacture and performance test of a lightweight piezo-composite curved actuator (called LIPCA) using a top carbon fiber composite layer with near-zero coefficient of thermal expansion (CTE), a middle PZT ceramic wafer, and a bottom glass/epoxy layer with a high CTE. The main point of the design for LIPCA is to replace the heavy metal layers of THUNDERTM by lightweight fiber reinforced plastic layers without losing the capabilities for generating high force and large displacement. It is possible to save up to about 40% of the weight if we replace the metallic backing material by the light fiber composite layer. We can also have design flexibility by selecting the fiber direction and the size of prepreg layers. In addition to the lightweight advantage and design flexibility, the proposed device can be manufactured without adhesive layers when we use an epoxy resin prepreg system. Glass/epoxy prepregs, a ceramic wafer with electrode surfaces, and a carbon prepreg were simply stacked and cured at an elevated temperature (177 °C) after following an autoclave bagging process. We found that the manufactured composite laminate device had a sufficient curvature after being detached from a flat mould. An analysis method using the classical lamination theory is presented to predict the curvature of LIPCA after curing at an elevated temperature. The predicted curvatures are in quite good agreement with the experimental values. In order to investigate the merits of LIPCA, performance tests of both LIPCA and THUNDERTM have been conducted under the same boundary conditions. From the experimental actuation tests, it was observed that the developed actuator could generate larger actuation displacement than THUNDERTM.

Automatic cassette to cassette radiant impulse processor

NASA Astrophysics Data System (ADS)

Sheets, Ronald E.

1985-01-01

Single wafer rapid annealing using high temperature isothermal processing has become increasingly popular in recent years. In addition to annealing, this process is also being investigated for suicide formation, passivation, glass reflow and alloying. Regardless of the application, there is a strong necessity to automate in order to maintain process control, repeatability, cleanliness and throughput. These requirements have been carefully addressed during the design and development of the Model 180 Radiant Impulse Processor which is a totally automatic cassette to cassette wafer processing system. Process control and repeatability are maintained by a closed loop optical pyrometer system which maintains the wafer at the programmed temperature-time conditions. Programmed recipes containing up to 10 steps may be easily entered on the computer keyboard or loaded in from a recipe library stored on a standard 5 {1}/{4″} floppy disk. Cold wall heating chamber construction, controlled environment (N 2, A, forming gas) and quartz wafer carriers prevent contamination of the wafer during high temperature processing. Throughputs of 150-240 wafers per hour are achieved by quickly heating the wafer to temperature (450-1400°C) in 3-6 s with a high intensity, uniform (± 1%) radiant flux of 100 {W}/{cm 2}, parallel wafer handling system and a wafer cool down stage.

Thick resist for MEMS processing

NASA Astrophysics Data System (ADS)

Brown, Joe; Hamel, Clifford

2001-11-01

The need for technical innovation is always present in today's economy. Microfabrication methods have evolved in support of the demand for smaller and faster integrated circuits with price performance improvements always in the scope of the manufacturing design engineer. The dispersion of processing technology spans well beyond IC fabrication today with batch fabrication and wafer scale processing lending advantages to MEMES applications from biotechnology to consumer electronics from oil exploration to aerospace. Today the demand for innovative processing techniques that enable technology is apparent where only a few years ago appeared too costly or not reliable. In high volume applications where yield and cost improvements are measured in fractions of a percent it is imperative to have process technologies that produce consistent results. Only a few years ago thick resist coatings were limited to thickness less than 20 microns. Factors such as uniformity, edge bead and multiple coatings made high volume production impossible. New developments in photoresist formulation combined with advanced coating equipment techniques that closely controls process parameters have enable thick photoresist coatings of 70 microns with acceptable uniformity and edge bead in one pass. Packaging of microelectronic and micromechanical devices is often a significant cost factor and a reliability issue for high volume low cost production. Technologies such as flip- chip assembly provide a solution for cost and reliability improvements over wire bond techniques. The processing for such technology demands dimensional control and presents a significant cost savings if it were compatible with mainstream technologies. Thick photoresist layers, with good sidewall control would allow wafer-bumping technologies to penetrate the barriers to yield and production where costs for technology are the overriding issue. Single pass processing is paramount to the manufacturability of packaging technology. Uniformity and edge bead control defined the success of process implementation. Today advanced packaging solutions are created with thick photoresist coatings. The techniques and results will be presented.

Considerations in the sterile manufacture of polymeric microneedle arrays.

PubMed

McCrudden, Maelíosa T C; Alkilani, Ahlam Zaid; Courtenay, Aaron J; McCrudden, Cian M; McCloskey, Bronagh; Walker, Christine; Alshraiedeh, Nida; Lutton, Rebecca E M; Gilmore, Brendan F; Woolfson, A David; Donnelly, Ryan F

2015-02-01

We describe, for the first time, considerations in the sterile manufacture of polymeric microneedle arrays. Microneedles (MN) made from dissolving polymeric matrices and loaded with the model drugs ovalbumin (OVA) and ibuprofen sodium and hydrogel-forming MN composed of "super-swelling" polymers and their corresponding lyophilised wafer drug reservoirs loaded with OVA and ibuprofen sodium were prepared aseptically or sterilised using commonly employed sterilisation techniques. Moist and dry heat sterilisation, understandably, damaged all devices, leaving aseptic production and gamma sterilisation as the only viable options. No measureable bioburden was detected in any of the prepared devices, and endotoxin levels were always below the US Food & Drug Administration limits (20 endotoxin units/device). Hydrogel-forming MN were unaffected by gamma irradiation (25 kGy) in terms of their physical properties or capabilities in delivering OVA and ibuprofen sodium across excised neonatal porcine skin in vitro. However, OVA content in dissolving MN (down from approximately 101.1 % recovery to approximately 58.3 % recovery) and lyophilised wafer-type drug reservoirs (down from approximately 99.7 % recovery to approximately 60.1 % recovery) was significantly reduced by gamma irradiation, while the skin permeation profile of ibuprofen sodium from gamma-irradiated dissolving MN was markedly different from their non-irradiated counterparts. It is clear that MN poses a very low risk to human health when used appropriately, as evidenced here by low endotoxin levels and absence of microbial contamination. However, if guarantees of absolute sterility of MN products are ultimately required by regulatory authorities, it will be necessary to investigate the effect of lower gamma doses on dissolving MN loaded with active pharmaceutical ingredients and lyophilised wafers loaded with biomolecules in order to avoid the expense and inconvenience of aseptic processing.

Beads-Milling of Waste Si Sawdust into High-Performance Nanoflakes for Lithium-Ion Batteries

PubMed Central

Kasukabe, Takatoshi; Nishihara, Hirotomo; Kimura, Katsuya; Matsumoto, Taketoshi; Kobayashi, Hikaru; Okai, Makoto; Kyotani, Takashi

2017-01-01

Nowadays, ca. 176,640 tons/year of silicon (Si) (>4N) is manufactured for Si wafers used for semiconductor industry. The production of the highly pure Si wafers inevitably includes very high-temperature steps at 1400–2000 °C, which is energy-consuming and environmentally unfriendly. Inefficiently, ca. 45–55% of such costly Si is lost simply as sawdust in the cutting process. In this work, we develop a cost-effective way to recycle Si sawdust as a high-performance anode material for lithium-ion batteries. By a beads-milling process, nanoflakes with extremely small thickness (15–17 nm) and large diameter (0.2–1 μm) are obtained. The nanoflake framework is transformed into a high-performance porous structure, named wrinkled structure, through a self-organization induced by lithiation/delithiation cycling. Under capacity restriction up to 1200 mAh g−1, the best sample can retain the constant capacity over 800 cycles with a reasonably high coulombic efficiency (98–99.8%). PMID:28218271

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Support apparatus for semiconductor wafer processing

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

2003-06-10

A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

A model-based approach for the scattering-bar printing avoidance

NASA Astrophysics Data System (ADS)

Du, Yaojun; Li, Liang; Zhang, Jingjing; Shao, Feng; Zuniga, Christian; Deng, Yunfei

2018-03-01

As the technology node for the semiconductor manufacturing approaches advanced nodes, the scattering-bars (SBs) are more crucial than ever to ensure a good on-wafer printability of the line space pattern and hole pattern. The main pattern with small pitches requires a very narrow PV (process variation) band. A delicate SB addition scheme is thus needed to maintain a sufficient PW (process window) for the semi-iso- and iso-patterns. In general, the wider, longer, and closer to main feature SBs will be more effective in enhancing the printability; on the other hand, they are also more likely to be printed on the wafer; resulting in undesired defects transferable to subsequent processes. In this work, we have developed a model based approach for the scattering-bar printing avoidance (SPA). A specially designed optical model was tuned based on a broad range of test patterns which contain a variation of CDs and SB placements showing printing and non-printing scattering bars. A printing threshold is then obtained to check the extra-printings of SBs. The accuracy of this threshold is verified by pre-designed test patterns. The printing threshold associated with our novel SPA model allows us to set up a proper SB rule.

MEMS/MOEMS foundry services at INO

NASA Astrophysics Data System (ADS)

García-Blanco, Sonia; Ilias, Samir; Williamson, Fraser; Généreux, Francis; Le Noc, Loïc; Poirier, Michel; Proulx, Christian; Tremblay, Bruno; Provençal, Francis; Desroches, Yan; Caron, Jean-Sol; Larouche, Carl; Beaupré, Patrick; Fortin, Benoit; Topart, Patrice; Picard, Francis; Alain, Christine; Pope, Timothy; Jerominek, Hubert

2010-06-01

In the MEMS manufacturing world, the "fabless" model is getting increasing importance in recent years as a way for MEMS manufactures and startups to minimize equipment costs and initial capital investment. In order for this model to be successful, the fabless company needs to work closely with a MEMS foundry service provider. Due to the lack of standardization in MEMS processes, as opposed to CMOS microfabrication, the experience in MEMS development processes and the flexibility of the MEMS foundry are of vital importance. A multidisciplinary team together with a complete microfabrication toolset allows INO to offer unique MEMS foundry services to fabless companies looking for low to mid-volume production. Companies that benefit from their own microfabrication facilities can also be interested in INO's assistance in conducting their research and development work during periods where production runs keep their whole staff busy. Services include design, prototyping, fabrication, packaging, and testing of various MEMS and MOEMS devices on wafers fully compatible with CMOS integration. Wafer diameters ranging typically from 1 inch to 6 inches can be accepted while 8-inch wafers can be processed in some instances. Standard microfabrication techniques such as metal, dielectric, and semiconductor film deposition and etching as well as photolithographic pattern transfer are available. A stepper permits reduction of the critical dimension to around 0.4 μm. Metals deposited by vacuum deposition methods include Au, Ag, Al, Al alloys, Ti, Cr, Cu, Mo, MoCr, Ni, Pt, and V with thickness varying from 5 nm to 2 μm. Electroplating of several materials including Ni, Au and In is also available. In addition, INO has developed and built a gold black deposition facility to answer customer's needs for broadband microbolometric detectors. The gold black deposited presents specular reflectance of less than 10% in the wavelength range from 0.2 μm to 100 μm with thickness ranging from 20 to 35 μm and a density of 0.3% the bulk density of gold. Two Balzers thin-film deposition instruments (BAP-800 and BAK-760) permit INO to offer optical thin film manufacturing. Recent work in this field includes the design and development of a custom filter for the James Webb Space Telescope (JWST) as collaboration with the Canadian company ComDEV. An overview of the different microfabrication foundry services offered by INO will be presented together with the most recent achievements in the field of MEMS/MOEMS.

Presidential Green Chemistry Challenge: 2002 Small Business Award

EPA Pesticide Factsheets

Presidential Green Chemistry Challenge 2002 award winner, SC Fluids, with Los Alamos National Laboratory, developed supercritical CO2 resist remover technology to clean residues from semiconductor wafers during manufacture.

Resolving critical dimension drift over time in plasma etching through virtual metrology based wafer-to-wafer control

NASA Astrophysics Data System (ADS)

Lee, Ho Ki; Baek, Kye Hyun; Shin, Kyoungsub

2017-06-01

As semiconductor devices are scaled down to sub-20 nm, process window of plasma etching gets extremely small so that process drift or shift becomes more significant. This study addresses one of typical process drift issues caused by consumable parts erosion over time and provides feasible solution by using virtual metrology (VM) based wafer-to-wafer control. Since erosion of a shower head has center-to-edge area dependency, critical dimensions (CDs) at the wafer center and edge area get reversed over time. That CD trend is successfully estimated on a wafer-to-wafer basis by a partial least square (PLS) model which combines variables from optical emission spectroscopy (OES), VI-probe and equipment state gauges. R 2 of the PLS model reaches 0.89 and its prediction performance is confirmed in a mass production line. As a result, the model can be exploited as a VM for wafer-to-wafer control. With the VM, advanced process control (APC) strategy is implemented to solve the CD drift. Three σ of CD across wafer is improved from the range (1.3-2.9 nm) to the range (0.79-1.7 nm). Hopefully, results introduced in this paper will contribute to accelerating implementation of VM based APC strategy in semiconductor industry.

Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

NASA Astrophysics Data System (ADS)

Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

2018-03-01

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up to 7KW. The wafer surface is coated with Yttrium oxide film which allows Silicon Etch chemistry. At Fab-8, we carried investigations in 14 nm FEOL critical etch process which has direct impact on yield, using SensorArray EtchTemp-SE wafer, we measured ESC temperature profile across multiple chambers, for both plasma on and plasma off, promising results achieved on chamber temperature signature identification, guideline for chamber to chamber matching improvement. Correlation between wafer mean temperature and determining criticality-process parameters of recess depth and CD is observed. Furthermore, detail zonal temperature/profile correlation is investigated to identify individual correlation in each chuck zone, and provided unique process knobs corresponding to each chunk. Meanwhile, passive ESC Chuck DOE was done to modulate wafer temperature at different zones, and Sensor Array wafer measurements verified temperature responding well with the ESC set point. Correlation R2 = 0.9979 for outer ring and R2 = 0.9981 for Mid Outer ring is observed, as shown in . Experiments planning to modulate edge zone ESC temperature to tune profile within-wafer uniformity and prove gain in edge yield enhancement and to improve edge yield is underway.

Characterization of 193-nm resists for optical mask manufacturing

NASA Astrophysics Data System (ADS)

Fosshaug, Hans; Paulsson, Adisa; Berzinsh, Uldis; Magnusson, Helena

2004-12-01

The push for smaller linewidths and tighter critical dimension (CD) budgets forced manufacturers of optical pattern generators to move from traditional i-line to deep ultraviolet (DUV) resist processing. Entering the DUV area was not without pain. The process conditions, especially exposure times of a few hours, put very tough demands on the resist material itself. However, today 248nm laser writers are fully operating using a resist process that exhibits the requested resolution, CD uniformity and environmental stability. The continuous demands of CD performance made Micronic to investigate suitable resist candidate materials for the next generation optical writer using 193nm excimer laser exposure. This paper reports on resist benchmarking of one commercial as well as several newly developed resists. The resists were investigated using a wafer scanner. The data obtained illustrate the current performance of 193nm photoresists, and further demonstrate that despite good progress in resist formulation optimization, the status is still a bit from the required lithographic performance.

Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

NASA Astrophysics Data System (ADS)

Miki, N.; Spearing, S. M.

2003-11-01

Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

NASA Astrophysics Data System (ADS)

Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

2015-07-01

Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

Wafer hot spot identification through advanced photomask characterization techniques: part 2

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; Cho, Young; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2017-03-01

Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.

Study of correlation between overlay and displacement measured by Coherent Gradient Sensing (CGS) interferometry

NASA Astrophysics Data System (ADS)

Mileham, Jeffrey; Tanaka, Yasushi; Anberg, Doug; Owen, David M.; Lee, Byoung-Ho; Bouche, Eric

2016-03-01

Within the semiconductor lithographic process, alignment control is one of the most critical considerations. In order to realize high device performance, semiconductor technology is approaching the 10 nm design rule, which requires progressively smaller overlay budgets. Simultaneously, structures are expanding in the 3rd dimension, thereby increasing the potential for inter-layer distortion. For these reasons, device patterning is becoming increasingly difficult as the portion of the overlay budget attributed to process-induced variation increases. After lithography, overlay gives valuable feedback to the lithography tool; however overlay measurements typically have limited density, especially at the wafer edge, due to throughput considerations. Moreover, since overlay is measured after lithography, it can only react to, but not predict the process-induced overlay. This study is a joint investigation in a high-volume manufacturing environment of the portion of overlay associated with displacement induced by a single process across many chambers. Displacement measurements are measured by Coherent Gradient Sensing (CGS) interferometry, which generates high-density displacement maps (>3 million points on a 300 mm wafer) such that the stresses induced die-by-die and process-by-process can be tracked in detail. The results indicate the relationship between displacement and overlay shows the ability to forecast overlay values before the lithographic process. Details of the correlation including overlay/displacement range, and lot-to-lot displacement variability are considered.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hegedus, Steven S.

An interdigitated back contact (IBC) Si wafer solar cell with deposited a-Si heterojunction (HJ) emitter and contacts is considered the ultimate single junction Si solar cell design. This was confirmed in 2014 by both Panasonic and Sharp Solar producing IBC-HJ cells breaking the previous record Si solar cell efficiency of 25%. But manufacturability at low cost is a concern for the complex IBC-HJ device structure. In this research program, our goals were to addressed the broad industry need for a high-efficiency c-Si cell that overcomes the dominant module cost barriers by 1) developing thin Si wafers synthesized by innovative, kerflessmore » techniques; 2) integrating laser-based processing into most aspects of solar cell fabrication, ensuring high speed and low thermal budgets ; 3) developing an all back contact cell structure compatible with thin wafers using a simplified, low-temperature fabrication process; and 4) designing the contact patterning to enable simplified module assembly. There were a number of significant achievements from this 3 year program. Regarding the front surface, we developed and applied new method to characterize critical interface recombination parameters including interface defect density Dit and hole and electron capture cross-section for use as input for 2D simulation of the IBC cell to guide design and loss analysis. We optimized the antireflection and passivation properties of the front surface texture and a-Si/a-SiN/a-SiC stack depositions to obtain a very low (< 6 mA/cm2) front surface optical losses (reflection and absorption) while maintaining excellent surface passivation (SRV<5 cm/s). We worked with kerfless wafer manufacturers to apply defect-engineering techniques to improve bulk minority-carrier lifetime of thin kerfless wafers by both reducing initial impurities during growth and developing post-growth gettering techniques. This led insights about the kinetics of nickel, chromium, and dislocations in PV-grade silicon and to achieving millisecond lifetimes in kerfless silicon materials. Laser fired contacts to n-Si were developed for the first time using a Al/Sb/Ti metal stack giving contact resistances < 5 mOhm-cm2 when fired through several different dielectric layers. A new 2 step laser+chemical etch isolation technique was developed using a sacrificial top coating which avoids laser damage to Si passivation. Regarding the heterojunction emitter, analysis of front FHJ (1D) and IBC (2D) cells with range of p-layer conditions found that a 2-stage high/low doped p-layer was optimum: the low doped region has lower defects giving higher Voc and the high doped region gave a better contact to the metal. A significant effort was spent studying the patterning process and its contribution to degradation of passivation and reproducibility. Several promising new cleaning, contact and deposition patterning and processing approaches were implemented leading to fabrication of several runs with cells having 19-20% efficiency which were stable over several months. This program resulted in the training and support of 12 graduate students, publication of 21 journal papers and 14 conference papers.« less

Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

PubMed

Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

2015-11-01

Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. Copyright © 2015 Elsevier B.V. All rights reserved.

Controlling high-throughput manufacturing at the nano-scale

NASA Astrophysics Data System (ADS)

Cooper, Khershed P.

2013-09-01

Interest in nano-scale manufacturing research and development is growing. The reason is to accelerate the translation of discoveries and inventions of nanoscience and nanotechnology into products that would benefit industry, economy and society. Ongoing research in nanomanufacturing is focused primarily on developing novel nanofabrication techniques for a variety of applications—materials, energy, electronics, photonics, biomedical, etc. Our goal is to foster the development of high-throughput methods of fabricating nano-enabled products. Large-area parallel processing and highspeed continuous processing are high-throughput means for mass production. An example of large-area processing is step-and-repeat nanoimprinting, by which nanostructures are reproduced again and again over a large area, such as a 12 in wafer. Roll-to-roll processing is an example of continuous processing, by which it is possible to print and imprint multi-level nanostructures and nanodevices on a moving flexible substrate. The big pay-off is high-volume production and low unit cost. However, the anticipated cost benefits can only be realized if the increased production rate is accompanied by high yields of high quality products. To ensure product quality, we need to design and construct manufacturing systems such that the processes can be closely monitored and controlled. One approach is to bring cyber-physical systems (CPS) concepts to nanomanufacturing. CPS involves the control of a physical system such as manufacturing through modeling, computation, communication and control. Such a closely coupled system will involve in-situ metrology and closed-loop control of the physical processes guided by physics-based models and driven by appropriate instrumentation, sensing and actuation. This paper will discuss these ideas in the context of controlling high-throughput manufacturing at the nano-scale.

High-efficiency screen-printed belt co-fired solar cells on cast multicrystalline silicon

NASA Astrophysics Data System (ADS)

Upadhyaya, Ajay; Sheoran, Manav; Rohatgi, Ajeet

2005-01-01

High-efficiency 4cm2 untextured screen-printed solar cells were achieved on cast multicrystalline silicon. These cells were fabricated using a simple manufacturable process involving POCl3 diffusion for emitter, PECVD SiNx:H deposition for a single-layer antireflection coating and rapid co-firing of Ag grid, Al backcontact, and Al-BSF in a belt furnace. An optimized process sequence contributed to effective impurity gettering and defect passivation, resulting in high average bulk lifetimes in the range of 100-250 μs after the cell processing. The contact firing contributed to good ohmic contacts with low series resistance of <1Ωcm2, low backsurface recombination velocity of <500cm/s, and high fill factors of ˜0.78. These parameters resulted in 16.9% and 16.8% efficient untextured screen-printed cells with a single layer AR coating on heat exchanger method (HEM) and Baysix mc-Si. The identical process applied to the untextured float zone wafers gave an efficiency of 17.2%. The same optimized co-firing cycle, when applied to HEM mc-Si wafers with starting lifetimes varying over a wide range of 4-70 μs, resulted in cell efficiencies in the range of 16.5%-17%.

Irradiation resistance of intravolume shading elements embedded in photomasks used for CD uniformity control by local intra-field transmission attenuation

NASA Astrophysics Data System (ADS)

Zait, Eitan; Ben-Zvi, Guy; Dmitriev, Vladimir; Oshemkov, Sergey; Pforr, Rainer; Hennig, Mario

2006-05-01

Intra-field CD variation is, besides OPC errors, a main contributor to the total CD variation budget in IC manufacturing. It is caused mainly by mask CD errors. In advanced memory device manufacturing the minimum features are close to the resolution limit resulting in large mask error enhancement factors hence large intra-field CD variations. Consequently tight CD Control (CDC) of the mask features is required, which results in increasing significantly the cost of mask and hence the litho process costs. Alternatively there is a search for such techniques (1) which will allow improving the intrafield CD control for a given moderate mask and scanner imaging performance. Currently a new technique (2) has been proposed which is based on correcting the printed CD by applying shading elements generated in the substrate bulk of the mask by ultrashort pulsed laser exposure. The blank transmittance across a feature is controlled by changing the density of light scattering pixels. The technique has been demonstrated to be very successful in correcting intra-field CD variations caused by the mask and the projection system (2). A key application criterion of this technique in device manufacturing is the stability of the absorbing pixels against DUV light irradiation being applied during mask projection in scanners. This paper describes the procedures and results of such an investigation. To do it with acceptable effort a special experimental setup has been chosen allowing an evaluation within reasonable time. A 193nm excimer laser with pulse duration of 25 ns has been used for blank irradiation. Accumulated dose equivalent to 100,000 300 mm wafer exposures has been applied to Half Tone PSM mask areas with and without CDC shadowing elements. This allows the discrimination of effects appearing in treated and untreated glass regions. Several intensities have been investigated to define an acceptable threshold intensity to avoid glass compaction or generation of color centers in the glass. The impact of the irradiation on the mask transmittance of both areas has been studied by measurements of the printed CD on wafer using a wafer scanner before and after DUV irradiation.

Airborne chemical contamination of a chemically amplified resist

NASA Astrophysics Data System (ADS)

MacDonald, Scott A.; Clecak, Nicholas J.; Wendt, H. R.; Willson, C. Grant; Snyder, Clinton D.; Knors, C. J.; Deyoe, N. B.; Maltabes, John G.; Morrow, James R.; McGuire, Anne E.; Holmes, Steven J.

1991-06-01

We have found that the performance of the t-BOC/onium salt resist system is severely degraded by vapor from organic bases. This effect is very pronounced and can be observed when the coated wafers stand for 15 minutes in air containing as little as 15 parts per billion (ppb) of an organic base. The observed effect, caused by this chemical contamination, depends on the tone of the resist system. For negative tone systems the UV exposure dose, required to obtain the correct linewidth, increases. While for the positive tone system, one observes the generation of a skin at the resist-air interface. Both effects are caused by the photogenerated acid being neutralized by the airborne organic base. There are a wide variety of commonly used materials which can liberate trace amounts of volatile amines and degrade resist performance. For example, fresh paint on a laboratory wall can exhibit this detrimental effect. These effects can be minimized by storing and processing the resist coated wafers in air that has passed through a specially designed, high efficiency carbon filter. The implementation of localized air filtration, to bathe the resist in chemically pure air, enabled this resist system to operate in a manufacturing environment at a rate of 100 wafers/hour.

Machine learning for fab automated diagnostics

NASA Astrophysics Data System (ADS)

Giollo, Manuel; Lam, Auguste; Gkorou, Dimitra; Liu, Xing Lan; van Haren, Richard

2017-06-01

Process optimization depends largely on field engineer's knowledge and expertise. However, this practice turns out to be less sustainable due to the fab complexity which is continuously increasing in order to support the extreme miniaturization of Integrated Circuits. On the one hand, process optimization and root cause analysis of tools is necessary for a smooth fab operation. On the other hand, the growth in number of wafer processing steps is adding a considerable new source of noise which may have a significant impact at the nanometer scale. This paper explores the ability of historical process data and Machine Learning to support field engineers in production analysis and monitoring. We implement an automated workflow in order to analyze a large volume of information, and build a predictive model of overlay variation. The proposed workflow addresses significant problems that are typical in fab production, like missing measurements, small number of samples, confounding effects due to heterogeneity of data, and subpopulation effects. We evaluate the proposed workflow on a real usecase and we show that it is able to predict overlay excursions observed in Integrated Circuits manufacturing. The chosen design focuses on linear and interpretable models of the wafer history, which highlight the process steps that are causing defective products. This is a fundamental feature for diagnostics, as it supports process engineers in the continuous improvement of the production line.

Single Crystal DMs for Space-Based Observatories

NASA Astrophysics Data System (ADS)

Bierden, Paul

We propose to demonstrate the feasibility of a new manufacturing process for large aperture, high-actuator count microelectromechanical deformable mirrors (MEMS-DMs). These DMs are designed to fill a critical technology gap in NASA s plan for high- contrast space-based exoplanet observatories. We will manufacture a prototype DM with a continuous mirror facesheet, having an active aperture of 50mm diameter, supported by 2040 electrostatic actuators (50 across the diameter of the active aperture), spaced at a pitch of 1mm. The DM will be manufactured using silicon microfabrication tools. The strategic motivation for the proposed project is to advance MEMS DMs as an enabling technology in NASA s rapidly emerging program for extrasolar planet exploration. That goal is supported by an Astro2010 white paper on Technologies for Direct Optical Imaging of Exoplanets, which concluded that DMs are a critical component for all proposed internal coronagraph instrument concepts. That white paper pointed to great strides made by DM developers in the past decade, and acknowledged the components made by Boston Micromachines Corporation to be the most notable MEMS-based technology option. The principal manufacturing innovation in this project will be assembly of the DM through fusion bonding of three separate single crystal silicon wafers comprising the device s substrate, actuator array, and facesheet. The most significant challenge of this project will be to develop processes that allow reliable fusion bonds between multiple compliant silicon layers while yielding an optically flat surface and a robust electromechanical system. The compliance of the DM, which is required for its electromechanical function, will make it challenging to achieve the intimate, planar contact that is generally needed for success in fusion bonding. The manufacturing approach will use photolithography and reactive ion etching to pattern structural layers. Three wafer-scale devices will be patterned and etched independently: one for the substrate and fixed electrode layer, one for the actuator layer, and one for the mirror layer. Subsequently, each of these wafers will be bonded through a thermal fusion process to the others. In an innovative new processing technique, we will employ sacrificial oxide pillars to add temporary support to the otherwise compliant device structures. These pillars will be dissolved after assembly. The result will be a stress-free, single crystal silicon device with broadly expanded design space for geometric parameters such as actuator pitch, mirror diameter, array size, and actuator gap. Consequently, this approach will allow us to make devices with characteristics that are needed for some important NASA applications in space-based coronography, especially where larger array sizes, greater actuator pitch, and better optical surface quality are needed. The significance of this work is that it will provide a technology platform that meets or exceeds the superb optical performance that has been demonstrated in conventional pizezoelectrically actuated DMs, while retaining the advantages in cost, repeatability, and thermal insensitivity that have been demonstrated in the newer generation of MEMS electrostatically actuated DMs. The shift to bonded single-crystal structures will eliminate the single biggest drawback in previously reported NASA-fielded MEMS DM technology: device susceptibility to stress-induced scalloping and print through artifacts resulting from polycrystalline thin film surface micromachining. With single crystal structures bonded at atomic scales, uncorrected surface topography can be controlled to subnanometer levels, enabling the advancement of NASA s next-generation space-based coronagraphs.

Mechanical Strength and Broadband Transparency Improvement of Glass Wafers via Surface Nanostructures.

PubMed

Kumar, Amarendra; Kashyap, Kunal; Hou, Max T; Yeh, J Andrew

2016-06-17

In this study, we mechanically strengthened a borosilicate glass wafer by doubling its bending strength and simultaneously enhancing its transparency using surface nanostructures for different applications including sensors, displays and panels. A fabrication method that combines dry and wet etching is used for surface nanostructure fabrication. Specifically, we improved the bending strength of plain borosilicate glass by 96% using these surface nanostructures on both sides. Besides bending strength improvement, a limited optical transmittance enhancement of 3% was also observed in the visible light wavelength region (400-800 nm). Both strength and transparency were improved by using surface nanostructures of 500 nm depth on both sides of the borosilicate glass without affecting its bulk properties or the glass manufacturing process. Moreover, we observed comparatively smaller fragments during the breaking of the nanostructured glass, which is indicative of strengthening. The range for the nanostructure depth is defined for different applications with which improvements of the strength and transparency of borosilicate glass substrate are obtained.

Method for forming silicon on a glass substrate

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics.

Method for forming silicon on a glass substrate

DOEpatents

McCarthy, A.M.

1995-03-07

A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics. 15 figs.

Mechanical Strength and Broadband Transparency Improvement of Glass Wafers via Surface Nanostructures

PubMed Central

Kumar, Amarendra; Kashyap, Kunal; Hou, Max T.; Yeh, J. Andrew

2016-01-01

In this study, we mechanically strengthened a borosilicate glass wafer by doubling its bending strength and simultaneously enhancing its transparency using surface nanostructures for different applications including sensors, displays and panels. A fabrication method that combines dry and wet etching is used for surface nanostructure fabrication. Specifically, we improved the bending strength of plain borosilicate glass by 96% using these surface nanostructures on both sides. Besides bending strength improvement, a limited optical transmittance enhancement of 3% was also observed in the visible light wavelength region (400–800 nm). Both strength and transparency were improved by using surface nanostructures of 500 nm depth on both sides of the borosilicate glass without affecting its bulk properties or the glass manufacturing process. Moreover, we observed comparatively smaller fragments during the breaking of the nanostructured glass, which is indicative of strengthening. The range for the nanostructure depth is defined for different applications with which improvements of the strength and transparency of borosilicate glass substrate are obtained. PMID:27322276

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

Method for wafer edge profile extraction using optical images obtained in edge defect inspection process

NASA Astrophysics Data System (ADS)

Okamoto, Hiroaki; Sakaguchi, Naoshi; Hayano, Fuminori

2010-03-01

It is becoming increasingly important to monitor wafer edge profiles in the immersion lithography era. A Nikon edge defect inspection tool acquires the circumferential optical images of the wafer edge during its inspection process. Nikon's unique illumination system and optics make it possible to then convert the brightness data of the captured images to quantifiable edge profile information. During this process the wafer's outer shape is also calculated. Test results show that even newly shipped bare wafers may not have a constant shape over 360 degree. In some cases repeated deformations with 90 degree pitch are observed.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Mass production of silicon pore optics for ATHENA

NASA Astrophysics Data System (ADS)

Wille, Eric; Bavdaz, Marcos; Collon, Maximilien

2016-07-01

Silicon Pore Optics (SPO) provide high angular resolution with low effective area density as required for the Advanced Telescope for High Energy Astrophysics (Athena). The x-ray telescope consists of several hundreds of SPO mirror modules. During the development of the process steps of the SPO technology, specific requirements of a future mass production have been considered right from the beginning. The manufacturing methods heavily utilise off-the-shelf equipment from the semiconductor industry, robotic automation and parallel processing. This allows to upscale the present production flow in a cost effective way, to produce hundreds of mirror modules per year. Considering manufacturing predictions based on the current technology status, we present an analysis of the time and resources required for the Athena flight programme. This includes the full production process starting with Si wafers up to the integration of the mirror modules. We present the times required for the individual process steps and identify the equipment required to produce two mirror modules per day. A preliminary timeline for building and commissioning the required infrastructure, and for flight model production of about 1000 mirror modules, is presented.

Reticle haze: an industrial approach

NASA Astrophysics Data System (ADS)

Gough, Stuart; Gérard, Xavier; Bichebois, Pascal; Roche, Agnès; Sundermann, Frank; Guyader, Véronique; Bièron, Yann; Galvier, Jean; Nicoleau, Serge

2007-02-01

Crystal growth on advanced reticles is currently a world wide industrial problem in high end semiconductor production environment, crystals are mainly found on reticles that use high energy photons at 193nm wavelength. The most common crystals to be found on masks are ammonium sulphate, a combination of sulphate, from maskshop residues after clean, pellicle materials and storage conditions and amines from clean room, tool and storage environments. High energy photons act as a catalyst to form crystals on both the pattern side as well as the backglass surface. After a number of exposures crystals can grow in size and eventually become printable. In order to detect HAZE before critical dimensions have been reached suitable detection methods need to be implemented to ensure image integrity. These detection methods are different and complementary depending on the surface to be inspected. Once crystals have started growing, the only method to regain mask quality is to clean the mask at the manufacturers site. This brings with it several undesirable situations, not only is the mask unavailable for production but the cleaning of a mask leads to a potential risk of damaging the mask especially for sub resolution patterns such as scatter bars and phase and transmission changes for eaPSM (Embedded Attenuated Phase Shift Mask) masks. This paper will discuss the initial haze issues seen in a 300mm wafer fab and actions put in place to address the problem. An explanation of results gained from haze reduction actions implemented in a wafer fab will be given. Haze seen by reticle inspection and surface analysis tools can be characterised by typical contamination patterns. These signatures appear after a certain number of wafers exposed depending on several reticle variables such as transmission, Binary, eaPSM, Pellicle. Details will be given of how reticles are managed to ensure minimum impact to a production environment with an appropriate reticle control plan. AMC (Airborne Molecular Contamination) in wafer fab and equipment environment is a key factor for crystal growth. The type of filtration installed to reduce AMC and method of atmospheric monitoring for critical areas will be explained. Choice of reticle storage conditions and materials used for transport during the life of the reticle will be included. Improvements in maskshop cleaning processes, reticle materials and environmental control have lead to extended mask lifetime in the wafer fab of more than 20 times. The fundamental differences and relative monitoring will be described and gain from implemented actions will be presented Once crystals have started growing, the only method to regain mask quality is to clean the mask at the manufacturers site. This brings with it several undesirable situations, not only is the mask unavailable for production but the cleaning of a mask leads to a potential risk of damaging the mask especially for sub resolution patterns such as scatter bars and phase and transmission changes for eaPSM (Embedded Attenuated Phase Shift Mask) masks. This paper will discuss the initial haze issues seen in a 300mm wafer fab and actions put in place to address the problem. An explanation of results gained from haze reduction actions implemented in a wafer fab will be given. Haze seen by reticle inspection and surface analysis tools can be characterised by typical contamination patterns. These signatures appear after a certain number of wafers exposed depending on several reticle variables such as transmission, Binary, eaPSM, Pellicle. Details will be given of how reticles are managed to ensure minimum impact to a production environment with an appropriate reticle control plan. AMC (Airborne Molecular Contamination) in wafer fab and equipment environment is a key factor for crystal growth. The type of filtration installed to reduce AMC and method of atmospheric monitoring for critical areas will be explained. Choice of reticle storage conditions and materials used for transport during the life of the reticle will be included. Improvements in maskshop cleaning processes, reticle materials and environmental control have lead to extended mask lifetime in the wafer fab of more than 20 times. The fundamental differences and relative monitoring will be described and gain from implemented actions will be presented

Methodology For Reduction Of Sampling On The Visual Inspection Of Developed And Etched Wafers

NASA Astrophysics Data System (ADS)

van de Ven, Jamie S.; Khorasani, Fred

1989-07-01

There is a lot of inspection in the manufacturing of semiconductor devices. Generally, the more important a manufacturing step, the higher is the level of inspection. In some cases 100% of the wafers are inspected after certain steps. Inspection is a non-value added and expensive activity. It requires an army of "inspectors," often times expensive equipment and becomes a "bottle neck" when the level of inspection is high. Although inspection helps identify quality problems, it hurts productivity. The new management, quality and productivity philosophies recommend against over inspection. [Point #3 in Dr. Deming's 14 Points for Management (1)] 100% inspection is quite unnecessary . Often the nature of a process allows us to reduce inspection drastically and still maintain a high level of confidence in quality. In section 2, we discuss such situations and show that some elementary probability theory allows us to determine sample sizes and measure the chances of catching a bad "lot" and accepting a good lot. In section 3, we provide an example and application of the theory, and make a few comments on money and time saved because of this work. Finally, in section 4, we draw some conclusions about the new quality and productivity philosophies and how applied statisticians and engineers should study every situation individually and avoid blindly using methods and tables given in books.

Low-to-high refractive index contrast transition (RICT) device for low loss polymer-based optical coupling

NASA Astrophysics Data System (ADS)

Calabretta, N.; Cooman, I. A.; Stabile, R.

2018-04-01

We propose for the first time a coupling device concept for passive low-loss optical coupling, which is compatible with the ‘generic’ indium phosphide (InP) multi-project-wafer manufacturing. A low-to-high vertical refractive index contrast transition InP waveguide is designed and tapered down to adiabatically couple light into a top polymer waveguide. The on-chip embedded polymer waveguide is engineered at the chip facets for offering refractive-index and spot-size-matching to silica fiber-arrays. Numerical analysis shows that coupling losses lower than 1.5 dB can be achieved for a TE-polarized light between the InP waveguide and the on-chip embedded polymer waveguide at 1550 nm wavelength. The performance is mainly limited by the difficulty to control single-mode operation. However, coupling losses lower than 1.9 dB can be achieved for a bandwidth as large as 200 nm. Moreover, the foreseen fabrication process steps are indicated, which are compatible with the ‘generic’ InP multi-project-wafer manufacturing. A fabrication error tolerance study is performed, indicating that fabrication errors occur only in 0.25 dB worst case excess losses, as long as high precision lithography is used. The obtained results are promising and may open the route to large port counts and cheap packaging of InP-based photonic integrated chips.

Model-Based Infrared Metrology for Advanced Technology Nodes and 300 mm Wafer Processing

NASA Astrophysics Data System (ADS)

Rosenthal, Peter A.; Duran, Carlos; Tower, Josh; Mazurenko, Alex; Mantz, Ulrich; Weidner, Peter; Kasic, Alexander

2005-09-01

The use of infrared spectroscopy for production semiconductor process monitoring has evolved recently from primarily unpatterned, i.e. blanket test wafer measurements in a limited historical application space of blanket epitaxial, BPSG, and FSG layers to new applications involving patterned product wafer measurements, and new measurement capabilities. Over the last several years, the semiconductor industry has adopted a new set of materials associated with copper/low-k interconnects, and new structures incorporating exotic materials including silicon germanium, SOI substrates and high aspect ratio trenches. The new device architectures and more chemically sophisticated materials have raised new process control and metrology challenges that are not addressed by current measurement technology. To address the challenges we have developed a new infrared metrology tool designed for emerging semiconductor production processes, in a package compatible with modern production and R&D environments. The tool incorporates recent advances in reflectance instrumentation including highly accurate signal processing, optimized reflectometry optics, and model-based calibration and analysis algorithms. To meet the production requirements of the modern automated fab, the measurement hardware has been integrated with a fully automated 300 mm platform incorporating front opening unified pod (FOUP) interfaces, automated pattern recognition and high throughput ultra clean robotics. The tool employs a suite of automated dispersion-model analysis algorithms capable of extracting a variety of layer properties from measured spectra. The new tool provides excellent measurement precision, tool matching, and a platform for deploying many new production and development applications. In this paper we will explore the use of model based infrared analysis as a tool for characterizing novel bottle capacitor structures employed in high density dynamic random access memory (DRAM) chips. We will explore the capability of the tool for characterizing multiple geometric parameters associated with the manufacturing process that are important to the yield and performance of advanced bottle DRAM devices.

Printed polymer photonic devices for optical interconnect systems

NASA Astrophysics Data System (ADS)

Subbaraman, Harish; Pan, Zeyu; Zhang, Cheng; Li, Qiaochu; Guo, L. J.; Chen, Ray T.

2016-03-01

Polymer photonic device fabrication usually relies on the utilization of clean-room processes, including photolithography, e-beam lithography, reactive ion etching (RIE) and lift-off methods etc, which are expensive and are limited to areas as large as a wafer. Utilizing a novel and a scalable printing process involving ink-jet printing and imprinting, we have fabricated polymer based photonic interconnect components, such as electro-optic polymer based modulators and ring resonator switches, and thermo-optic polymer switch based delay networks and demonstrated their operation. Specifically, a modulator operating at 15MHz and a 2-bit delay network providing up to 35.4ps are presented. In this paper, we also discuss the manufacturing challenges that need to be overcome in order to make roll-to-roll manufacturing practically viable. We discuss a few manufacturing challenges, such as inspection and quality control, registration, and web control, that need to be overcome in order to realize true implementation of roll-to-roll manufacturing of flexible polymer photonic systems. We have overcome these challenges, and currently utilizing our inhouse developed hardware and software tools, <10μm alignment accuracy at a 5m/min is demonstrated. Such a scalable roll-to-roll manufacturing scheme will enable the development of unique optoelectronic devices which can be used in a myriad of different applications, including communication, sensing, medicine, security, imaging, energy, lighting etc.

New getter configuration at wafer level for assuring long term stability of MEMs

NASA Astrophysics Data System (ADS)

Moraja, Marco; Amiotti, Marco; Kullberg, Richard C.

2003-01-01

The evolution from ceramic packages to wafer to wafer hermetic sealing poses tremendous technical challenges to integrate a proper getter inside the MEMs to assure a long term stability and reliability of the devices. The state of the art solution to integrate a getter inside the MEMs of the last generation consists in patterning the getter material with a specific geometry onto the Si cap wafer. The practical implementation of this solution consists in a 4" or 6" Si wafers with grooves or particular incisures, where the getter material is placed in form of a thick film. The typical thickness of these thick films is in the range of few microns, depending on the gas load to be handled during the lifetime of the device. The structure of the thick getter film is highly porous in order to improve sorption performances, but at the same time there are no loose particles thanks to a proprietary manufacturing method. The getter thick film is composed of a Zr special alloy with a proper composition to optimize the sorption performances. The getter thick film can be placed selectively into grooves without affecting the lateral regions, surrounding the grooves where the hermetic sealing is performed.

Cameras for semiconductor process control

NASA Technical Reports Server (NTRS)

Porter, W. A.; Parker, D. L.

1977-01-01

The application of X-ray topography to semiconductor process control is described, considering the novel features of the high speed camera and the difficulties associated with this technique. The most significant results on the effects of material defects on device performance are presented, including results obtained using wafers processed entirely within this institute. Defects were identified using the X-ray camera and correlations made with probe data. Also included are temperature dependent effects of material defects. Recent applications and improvements of X-ray topographs of silicon-on-sapphire and gallium arsenide are presented with a description of a real time TV system prototype and of the most recent vacuum chuck design. Discussion is included of our promotion of the use of the camera by various semiconductor manufacturers.

Dissolution of Oxygen Precipitate Nuclei in n-Type CZ-Si Wafers to Improve Their Material Quality: Experimental Results

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, Bhushan; Basnyat, Prakash; Devayajanam, Srinivas

2017-01-01

We present experimental results which show that oxygen-related precipitate nuclei (OPN) present in p-doped, n-type, Czochralski wafers can be dissolved using a flash-annealing process, yielding very high quality wafers for high-efficiency solar cells. Flash annealing consists of heating a wafer in an optical furnace to temperature between 1150 and 1250 degrees C for a short time. This process produces a large increase in the minority carrier lifetime (MCLT) and homogenizes each wafer. We have tested wafers from different axial locations of two ingots. All wafers reach nearly the same high value of MCLT. The OPN dissolution is confirmed by oxygenmore » analysis using Fourier transform infrared spectra and injection-level dependence of MCLT.« less

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2010 CFR

2010-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer... where wastewater undergoes treatment (such as pH adjustment) before discharge, and are not used to...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2011 CFR

2011-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer... where wastewater undergoes treatment (such as pH adjustment) before discharge, and are not used to...

Faster diffraction-based overlay measurements with smaller targets using 3D gratings

NASA Astrophysics Data System (ADS)

Li, Jie; Kritsun, Oleg; Liu, Yongdong; Dasari, Prasad; Volkman, Catherine; Hu, Jiangtao

2012-03-01

Diffraction-based overlay (DBO) technologies have been developed to address the overlay metrology challenges for 22nm technology node and beyond. Most DBO technologies require specially designed targets that consist of multiple measurement pads, which consume too much space and increase measurement time. The traditional empirical approach (eDBO) using normal incidence spectroscopic reflectometry (NISR) relies on linear response of the reflectance with respect to overlay displacement within a small range. It offers convenience of quick recipe setup since there is no need to establish a model. However it requires three or four pads per direction (x or y) which adds burden to throughput and target size. Recent advances in modeling capability and computation power enabled mDBO, which allows overlay measurement with reduced number of pads, thus reducing measurement time and DBO target space. In this paper we evaluate the performance of single pad mDBO measurements using two 3D targets that have different grating shapes: squares in boxes and L-shapes in boxes. Good overlay sensitivities are observed for both targets. The correlation to programmed shifts and image-based overlay (IBO) is excellent. Despite the difference in shapes, the mDBO results are comparable for square and L-shape targets. The impact of process variations on overlay measurements is studied using a focus and exposure matrix (FEM) wafer. Although the FEM wafer has larger process variations, the correlation of mDBO results with IBO measurements is as good as the normal process wafer. We demonstrate the feasibility of single pad DBO measurements with faster throughput and smaller target size, which is particularly important in high volume manufacturing environment.

Focus control enhancement and on-product focus response analysis methodology

NASA Astrophysics Data System (ADS)

Kim, Young Ki; Chen, Yen-Jen; Hao, Xueli; Samudrala, Pavan; Gomez, Juan-Manuel; Mahoney, Mark O.; Kamalizadeh, Ferhad; Hanson, Justin K.; Lee, Shawn; Tian, Ye

2016-03-01

With decreasing CDOF (Critical Depth Of Focus) for 20/14nm technology and beyond, focus errors are becoming increasingly critical for on-product performance. Current on product focus control techniques in high volume manufacturing are limited; It is difficult to define measurable focus error and optimize focus response on product with existing methods due to lack of credible focus measurement methodologies. Next to developments in imaging and focus control capability of scanners and general tool stability maintenance, on-product focus control improvements are also required to meet on-product imaging specifications. In this paper, we discuss focus monitoring, wafer (edge) fingerprint correction and on-product focus budget analysis through diffraction based focus (DBF) measurement methodology. Several examples will be presented showing better focus response and control on product wafers. Also, a method will be discussed for a focus interlock automation system on product for a high volume manufacturing (HVM) environment.

An overview of crystalline silicon solar cell technology: Past, present, and future

NASA Astrophysics Data System (ADS)

Sopian, K.; Cheow, S. L.; Zaidi, S. H.

2017-09-01

Crystalline silicon (c-Si) solar cell, ever since its inception, has been identified as the only economically and environmentally sustainable renewable resource to replace fossil fuels. Performance c-Si based photovoltaic (PV) technology has been equal to the task. Its price has been reduced by a factor of 250 over last twenty years (from ˜ 76 USD to ˜ 0.3 USD); its market growth is expected to reach 100 GWP by 2020. Unfortunately, it is still 3-4 times higher than carbon-based fuels. With the matured PV manufacturing technology as it exists today, continuing price reduction poses stiff challenges. Alternate manufacturing approaches in combination with thin wafers, low (< 10 x) optical enhancement with Fresnel lenses, band-gap engineering for enhanced optical absorption, and newer, advanced solar cell configurations including partially transparent bifacial and back contact solar cells will be required. This paper will present a detailed, cost-based analysis of advanced solar cell manufacturing technologies aimed at higher (˜ 22 %) efficiency with existing equipment and processes.

Boron diffusion in silicon devices

DOEpatents

Rohatgi, Ajeet; Kim, Dong Seop; Nakayashiki, Kenta; Rounsaville, Brian

2010-09-07

Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat ramp-up associated with a first heating cycle that results in a release of an amount of boron for diffusion into the wafer.

Wafer-Level Vacuum Packaging of Smart Sensors.

PubMed

Hilton, Allan; Temple, Dorota S

2016-10-31

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

Wafer-level vacuum/hermetic packaging technologies for MEMS

NASA Astrophysics Data System (ADS)

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

Wafer-Level Vacuum Packaging of Smart Sensors

PubMed Central

Hilton, Allan; Temple, Dorota S.

2016-01-01

The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology. PMID:27809249

Robust wafer identification recognition based on asterisk-shape filter and high-low score comparison method.

PubMed

Hsu, Wei-Chih; Yu, Tsan-Ying; Chen, Kuan-Liang

2009-12-10

Wafer identifications (wafer ID) can be used to identify wafers from each other so that wafer processing can be traced easily. Wafer ID recognition is one of the problems of optical character recognition. The process to recognize wafer IDs is similar to that used in recognizing car license-plate characters. However, due to some unique characteristics, such as the irregular space between two characters and the unsuccessive strokes of wafer ID, it will not get a good result to recognize wafer ID by directly utilizing the approaches used in car license-plate character recognition. Wafer ID scratches are engraved by a laser scribe almost along the following four fixed directions: horizontal, vertical, plus 45 degrees , and minus 45 degrees orientations. The closer to the center line of a wafer ID scratch, the higher the gray level will be. These and other characteristics increase the difficulty to recognize the wafer ID. In this paper a wafer ID recognition scheme based on an asterisk-shape filter and a high-low score comparison method is proposed to cope with the serious influence of uneven luminance and make recognition more efficiently. Our proposed approach consists of some processing stages. Especially in the final recognition stage, a template-matching method combined with stroke analysis is used as a recognizing scheme. This is because wafer IDs are composed of Semiconductor Equipment and Materials International (SEMI) standard Arabic numbers and English alphabets, and thus the template ID images are easy to obtain. Furthermore, compared with the approach that requires prior training, such as a support vector machine, which often needs a large amount of training image samples, no prior training is required for our approach. The testing results show that our proposed scheme can efficiently and correctly segment out and recognize the wafer ID with high performance.

Controllable laser thermal cleavage of sapphire wafers

NASA Astrophysics Data System (ADS)

Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

2018-03-01

Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

Design, fabrication and skin-electrode contact analysis of polymer microneedle-based ECG electrodes

NASA Astrophysics Data System (ADS)

O'Mahony, Conor; Grygoryev, Konstantin; Ciarlone, Antonio; Giannoni, Giuseppe; Kenthao, Anan; Galvin, Paul

2016-08-01

Microneedle-based ‘dry’ electrodes have immense potential for use in diagnostic procedures such as electrocardiography (ECG) analysis, as they eliminate several of the drawbacks associated with the conventional ‘wet’ electrodes currently used for physiological signal recording. To be commercially successful in such a competitive market, it is essential that dry electrodes are manufacturable in high volumes and at low cost. In addition, the topographical nature of these emerging devices means that electrode performance is likely to be highly dependent on the quality of the skin-electrode contact. This paper presents a low-cost, wafer-level micromoulding technology for the fabrication of polymeric ECG electrodes that use microneedle structures to make a direct electrical contact to the body. The double-sided moulding process can be used to eliminate post-process via creation and wafer dicing steps. In addition, measurement techniques have been developed to characterize the skin-electrode contact force. We perform the first analysis of signal-to-noise ratio dependency on contact force, and show that although microneedle-based electrodes can outperform conventional gel electrodes, the quality of ECG recordings is significantly dependent on temporal and mechanical aspects of the skin-electrode interface.

Strategy For Yield Control And Enhancement In VLSI Wafer Manufacturing

NASA Astrophysics Data System (ADS)

Neilson, B.; Rickey, D.; Bane, R. P.

1988-01-01

In most fully utilized integrated circuit (IC) production facilities, profit is very closely linked with yield. In even the most controlled manufacturing environments, defects due to foreign material are a still major contributor to yield loss. Ideally, an IC manufacturer will have ample engineering resources to address any problem that arises. In the real world, staffing limitations require that some tasks must be left undone and potential benefits left unrealized. Therefore, it is important to prioritize problems in a manner that will give the maximum benefit to the manufacturer. When offered a smorgasbord of problems to solve, most people (engineers included) will start with what is most interesting or the most comfortable to work on. By providing a system that accurately predicts the impact of a wide variety of defect types, a rational method of prioritizing engineering effort can be made. To that effect, a program was developed to determine and rank the major yield detractors in a mixed analog/digital FET manufacturing line. The two classical methods of determining yield detractors are chip failure analysis and defect monitoring on drop in test die. Both of these methods have short comings: 1) Chip failure analysis is painstaking and very time consuming. As a result, the sample size is very small. 2) Drop in test die are usually designed for device parametric analysis rather than defect analysis. To provide enough wafer real estate to do meaningful defect analysis would render the wafer worthless for production. To avoid these problems, a defect monitor was designed that provided enough area to detect defects at the same rate or better than the NMOS product die whose yield was to be optimized. The defect monitor was comprehensive and electrically testable using such equipment as the Prometrix LM25 and other digital testers. This enabled the quick accumulation of data which could be handled statistically and mapped individually. By scaling the defect densities found on the monitors to the known sensitivities of the product wafer, the defect types were ranked by defect limiting yield. (Limiting yield is the resultant product yield if there were no other failure mechanisms other than the type being considered.) These results were then compared to the product failure analysis results to verify that the monitor was finding the same types of defects in the same proportion which were troubling our product. Finally, the major defect types were isolated and reduced using the short loop capability of the monitor.

Technological innovations for a sustainable business model in the semiconductor industry

NASA Astrophysics Data System (ADS)

Levinson, Harry J.

2014-09-01

Increasing costs of wafer processing, particularly for lithographic processes, have made it increasingly difficult to achieve simultaneous reductions in cost-per-function and area per device. Multiple patterning techniques have made possible the fabrication of circuit layouts below the resolution limit of single optical exposures but have led to significant increases in the costs of patterning. Innovative techniques, such as self-aligned double patterning (SADP) have enabled good device performance when using less expensive patterning equipment. Other innovations have directly reduced the cost of manufacturing. A number of technical challenges must be overcome to enable a return to single-exposure patterning using short wavelength optical techniques, such as EUV patterning.

A review of nanoimprint lithography for high-volume semiconductor device manufacturing

NASA Astrophysics Data System (ADS)

Resnick, Douglas J.; Choi, Jin

2017-06-01

Imprint lithography has been shown to be a promising technique for the replication of nanoscale features. Jet and flash imprint lithography (J-FIL) [jet and flash imprint lithography and J-FIL are trademarks of Molecular Imprints, Inc.] involves the field-by-field deposition and exposure of a low-viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid, which then quickly flows into the relief patterns in the mask by capillary action. After this filling step, the resist is cross-linked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Included on the list are overlay, throughput, and defectivity. The most demanding devices now require an overlay of better than 4 nm, 3σ. Throughput for an imprint tool is generally targeted at 80 wafers/h. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. The purpose of this paper is to report the status of throughput and defectivity work and to describe the progress made in addressing overlay for advanced devices. To address high-order corrections, a high-order distortion correction (HODC) system is introduced. The combination of applying magnification actuation to the mask and temperature correction to the wafer is described in detail. Examples are presented for the correction of K7, K11, and K17 distortions as well as distortions on actual device wafers.

The development of 8 inch roll-to-plate nanoimprint lithography (8-R2P-NIL) system

NASA Astrophysics Data System (ADS)

Lee, Lai Seng; Mohamed, Khairudin; Ooi, Su Guan

2017-07-01

Growth in semiconductor and integrated circuit industry was observed in the past decennium of years for industrial technology which followed Moore's law. The line width of nanostructure to be exposed was influenced by the essential technology of photolithography. Thus, it is crucial to have a low cost and high throughput manufacturing process for nanostructures. Nanoimprint Lithography technique invented by Stephen Y. Chou was considered as major nanolithography process to be used in future integrated circuit and integrated optics. The drawbacks of high imprint pressure, high imprint temperature, air bubbles formation, resist sticking to mold and low throughput of thermal nanoimprint lithography on silicon wafer have yet to be solved. Thus, the objectives of this work is to develop a high throughput, low imprint force, room temperature UV assisted 8 inch roll to plate nanoimprint lithography system capable of imprinting nanostructures on 200 mm silicon wafer using roller imprint with flexible mold. A piece of resist spin coated silicon wafer was placed onto vacuum chuck drives forward by a stepper motor. A quartz roller wrapped with a piece of transparent flexible mold was used as imprint roller. The imprinted nanostructures were cured by 10 W, 365 nm UV LED which situated inside the quartz roller. Heat generated by UV LED was dissipated by micro heat pipe. The flexible mold detaches from imprinted nanostructures in a 'line peeling' pattern and imprint pressure was measured by ultra-thin force sensors. This system has imprinting speed capability ranging from 0.19 mm/s to 5.65 mm/s, equivalent to imprinting capability of 3 to 20 pieces of 8 inch wafers per hour. Speed synchronization between imprint roller and vacuum chuck was achieved by controlling pulse rate supplied to stepper motor which drive the vacuum chuck. The speed different ranging from 2 nm/s to 98 nm/s is achievable. Vacuum chuck height was controlled by stepper motor with displacement of 5 nm/step.

SEM based overlay measurement between resist and buried patterns

NASA Astrophysics Data System (ADS)

Inoue, Osamu; Okagawa, Yutaka; Hasumi, Kazuhisa; Shao, Chuanyu; Leray, Philippe; Lorusso, Gian; Baudemprez, Bart

2016-03-01

With the continuous shrink in pattern size and increased density, overlay control has become one of the most critical issues in semiconductor manufacturing. Recently, SEM based overlay of AEI (After Etch Inspection) wafer has been used for reference and optimization of optical overlay (both Image Based Overlay (IBO) and Diffraction Based Overlay (DBO)). Overlay measurement at AEI stage contributes monitor and forecast the yield after formation by etch and calibrate optical measurement tools. however those overlay value seems difficult directly for feedback to a scanner. Therefore, there is a clear need to have SEM based overlay measurements of ADI (After Develop Inspection) wafers in order to serve as reference for optical overlay and make necessary corrections before wafers go to etch. Furthermore, to make the corrections as accurate as possible, actual device like feature dimensions need to be measured post ADI. This device size measurement is very unique feature of CDSEM , which can be measured with smaller area. This is currently possible only with the CD-SEM. This device size measurement is very unique feature of CD-SEM , which can be measured with smaller area. In this study, we assess SEM based overlay measurement of ADI and AEI wafer by using a sample from an N10 process flow. First, we demonstrate SEM based overlay performance at AEI by using dual damascene process for Via 0 (V0) and metal 1 (M1) layer. We also discuss the overlay measurements between litho-etch-litho stages of a triple patterned M1 layer and double pattern V0. Second, to illustrate the complexities in image acquisition and measurement we will measure overlay between M1B resist and buried M1A-Hard mask trench. Finally, we will show how high accelerating voltage can detect buried pattern information by BSE (Back Scattering Electron). In this paper we discuss the merits of this method versus standard optical metrology based corrections.

Method and apparatus for thermal processing of semiconductor substrates

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Mattson, Brad S.; Savas, Stephen E.

2002-01-01

An improved apparatus and method for thermal processing of semiconductor wafers. The apparatus and method provide the temperature stability and uniformity of a conventional batch furnace as well as the processing speed and reduced time-at-temperature of a lamp-heated rapid thermal processor (RTP). Individual wafers are rapidly inserted into and withdrawn from a furnace cavity held at a nearly constant and isothermal temperature. The speeds of insertion and withdrawal are sufficiently large to limit thermal stresses and thereby reduce or prevent plastic deformation of the wafer as it enters and leaves the furnace. By processing the semiconductor wafer in a substantially isothermal cavity, the wafer temperature and spatial uniformity of the wafer temperature can be ensured by measuring and controlling only temperatures of the cavity walls. Further, peak power requirements are very small compared to lamp-heated RTPs because the cavity temperature is not cycled and the thermal mass of the cavity is relatively large. Increased speeds of insertion and/or removal may also be used with non-isothermal furnaces.

Method and apparatus for thermal processing of semiconductor substrates

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Mattson, Brad S.; Savas, Stephen E.

2000-01-01

An improved apparatus and method for thermal processing of semiconductor wafers. The apparatus and method provide the temperature stability and uniformity of a conventional batch furnace as well as the processing speed and reduced time-at-temperature of a lamp-heated rapid thermal processor (RTP). Individual wafers are rapidly inserted into and withdrawn from a furnace cavity held at a nearly constant and isothermal temperature. The speeds of insertion and withdrawal are sufficiently large to limit thermal stresses and thereby reduce or prevent plastic deformation of the wafer as it enters and leaves the furnace. By processing the semiconductor wafer in a substantially isothermal cavity, the wafer temperature and spatial uniformity of the wafer temperature can be ensured by measuring and controlling only temperatures of the cavity walls. Further, peak power requirements are very small compared to lamp-heated RTPs because the cavity temperature is not cycled and the thermal mass of the cavity is relatively large. Increased speeds of insertion and/or removal may also be used with non-isothermal furnaces.

Microeconomics of yield learning and process control in semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Monahan, Kevin M.

2003-06-01

Simple microeconomic models that directly link yield learning to profitability in semiconductor manufacturing have been rare or non-existent. In this work, we review such a model and provide links to inspection capability and cost. Using a small number of input parameters, we explain current yield management practices in 200mm factories. The model is then used to extrapolate requirements for 300mm factories, including the impact of technology transitions to 130nm design rules and below. We show that the dramatic increase in value per wafer at the 300mm transition becomes a driver for increasing metrology and inspection capability and sampling. These analyses correlate well wtih actual factory data and often identify millions of dollars in potential cost savings. We demonstrate this using the example of grating-based overlay metrology for the 65nm node.

Silicon pore optics for future x-ray telescopes

NASA Astrophysics Data System (ADS)

Wille, Eric; Bavdaz, Marcos; Wallace, Kotska; Shortt, Brian; Collon, Maximilien; Ackermann, Marcelo; Günther, Ramses; Olde Riekerink, Mark; Koelewijn, Arenda; Haneveld, Jeroen; van Baren, Coen; Erhard, Markus; Kampf, Dirk; Christensen, Finn; Krumrey, Michael; Freyberg, Michael; Burwitz, Vadim

2017-11-01

Lightweight X-ray Wolter optics with a high angular resolution will enable the next generation of X-ray telescopes in space. The candidate mission ATHENA (Advanced Telescope for High Energy Astrophysics) required a mirror assembly of 1 m2 effective area (at 1 keV) and an angular resolution of 10 arcsec or better. These specifications can only be achieved with a novel technology like Silicon Pore Optics, which is being developed by ESA together with a consortium of European industry. Silicon Pore Optics are made of commercial Si wafers using process technology adapted from the semiconductor industry. We present the recent upgrades made to the manufacturing processes and equipment, ranging from the manufacture of single mirror plates towards complete focusing mirror modules mounted in flight configuration, and results from first vibration tests. The performance of the mirror modules is tested at X-ray facilities that were recently extended to measure optics at a focal distance up to 20 m.

Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

NASA Astrophysics Data System (ADS)

Consiglio, Steven P.

To continue the rapid progress of the semiconductor industry as described by Moore's Law, the feasibility of new material systems for front end of the line (FEOL) process technologies needs to be investigated, since the currently employed polysilicon/SiO2-based transistor system is reaching its fundamental scaling limits. Revolutionary breakthroughs in complementary-metal-oxide-semiconductor (CMOS) technology were recently announced by Intel Corporation and International Business Machines Corporation (IBM), with both organizations revealing significant progress in the implementation of hafnium-based high-k dielectrics along with metal gates. This announcement was heralded by Gordon Moore as "...the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s." Accordingly, the study described herein focuses on the growth of Hf-based dielectrics and Hf-based metal gates using chemical vapor-based deposition methods, specifically metallorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). A family of Hf source complexes that has received much attention recently due to their desirable properties for implementation in wafer scale manufacturing is the Hf dialkylamide precursors. These precursors are room temperature liquids and possess sufficient volatility and desirable decomposition characteristics for both MOCVD and ALD processing. Another benefit of using these sources is the existence of chemically compatible Si dialkylamide sources as co-precursors for use in Hf silicate growth. The first part of this study investigates properties of MOCVD-deposited HfO2 and HfSixOy using dimethylamido Hf and Si precursor sources using a customized MOCVD reactor. The second part of this study involves a study of wet and dry surface pre-treatments for ALD growth of HfO2 using tetrakis(ethylmethylamido)hafnium in a wafer scale manufacturing environment. The third part of this study is an investigation of the properties of conductive HfN grown via plasma-assisted atomic layer deposition (PA-ALD) using tetrakis(ethylmethylamido)hafnium on a modified commercially available wafer processing tool. Key properties of these materials for use as gate stack replacement materials are addressed and future directions for further characterization and novel material investigations are proposed.

PULSION® HP: Tunable, High Productivity Plasma Doping

NASA Astrophysics Data System (ADS)

Felch, S. B.; Torregrosa, F.; Etienne, H.; Spiegel, Y.; Roux, L.; Turnbaugh, D.

2011-01-01

Plasma doping has been explored for many implant applications for over two decades and is now being used in semiconductor manufacturing for two applications: DRAM polysilicon counter-doping and contact doping. The PULSION HP is a new plasma doping tool developed by Ion Beam Services for high-volume production that enables customer control of the dominant mechanism—deposition, implant, or etch. The key features of this tool are a proprietary, remote RF plasma source that enables a high density plasma with low chamber pressure, resulting in a wide process space, and special chamber and wafer electrode designs that optimize doping uniformity.

Surface Wave Metrology for Copper/Low-k Interconnects

NASA Astrophysics Data System (ADS)

Gostein, M.; Maznev, A. A.; Mazurenko, A.; Tower, J.

2005-09-01

We review recent advances in the application of laser-induced surface acoustic wave metrology to issues in copper/low-k interconnect development and manufacturing. We illustrate how the metrology technique can be used to measure copper thickness uniformity on a range of features from solid pads to arrays of lines, focusing on specific processing issues in copper electrochemical deposition (ECD) and chemical-mechanical polishing (CMP). In addition, we review recent developments in surface wave metrology for the characterization of low-k dielectric elastic modulus, including the ability to measure within-wafer uniformity of elastic modulus and to characterize porous, anisotropic films.

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

NASA Astrophysics Data System (ADS)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

The impact of 14nm photomask variability and uncertainty on computational lithography solutions

NASA Astrophysics Data System (ADS)

Sturtevant, John; Tejnil, Edita; Buck, Peter D.; Schulze, Steffen; Kalk, Franklin; Nakagawa, Kent; Ning, Guoxiang; Ackmann, Paul; Gans, Fritz; Buergel, Christian

2013-09-01

Computational lithography solutions rely upon accurate process models to faithfully represent the imaging system output for a defined set of process and design inputs. These models rely upon the accurate representation of multiple parameters associated with the scanner and the photomask. Many input variables for simulation are based upon designed or recipe-requested values or independent measurements. It is known, however, that certain measurement methodologies, while precise, can have significant inaccuracies. Additionally, there are known errors associated with the representation of certain system parameters. With shrinking total CD control budgets, appropriate accounting for all sources of error becomes more important, and the cumulative consequence of input errors to the computational lithography model can become significant. In this work, we examine via simulation, the impact of errors in the representation of photomask properties including CD bias, corner rounding, refractive index, thickness, and sidewall angle. The factors that are most critical to be accurately represented in the model are cataloged. CD bias values are based on state of the art mask manufacturing data and other variables changes are speculated, highlighting the need for improved metrology and communication between mask and OPC model experts. The simulations are done by ignoring the wafer photoresist model, and show the sensitivity of predictions to various model inputs associated with the mask. It is shown that the wafer simulations are very dependent upon the 1D/2D representation of the mask and for 3D, that the mask sidewall angle is a very sensitive factor influencing simulated wafer CD results.

Advanced process control and novel test methods for PVD silicon and elastomeric silicone coatings utilized on ion implant disks, heatsinks and selected platens

DOE Office of Scientific and Technical Information (OSTI.GOV)

Springer, J.; Allen, B.; Wriggins, W.

Coatings play multiple key roles in the proper functioning of mature and current ion implanters. Batch and serial implanters require strategic control of elemental and particulate contamination which often includes scrutiny of the silicon surface coatings encountering direct beam contact. Elastomeric Silicone Coatings must accommodate wafer loading and unloading as well as direct backside contact during implant plus must maintain rigid elemental and particulate specifications. The semiconductor industry has had a significant and continuous effort to obtain ultra-pure silicon coatings with sustained process performance and long life. Low particles and reduced elemental levels for silicon coatings are a major requirementmore » for process engineers, OEM manufacturers, and second source suppliers. Relevant data will be presented. Some emphasis and detail will be placed on the structure and characteristics of a relatively new PVD Silicon Coating process that is very dense and homogeneous. Wear rate under typical ion beam test conditions will be discussed. The PVD Silicon Coating that will be presented here is used on disk shields, wafer handling fingers/fences, exclusion zones of heat sinks, beam dumps and other beamline components. Older, legacy implanters can now provide extended process capability using this new generation PVD silicon - even on implanter systems that were shipped long before the advent of silicon coating for contamination control. Low particles and reduced elemental levels are critical performance criteria for the silicone elastomers used on disk heatsinks and serial implanter platens. Novel evaluation techniques and custom engineered tools are used to investigate the surface interaction characteristics of multiple Elastomeric Silicone Coatings currently in use by the industry - specifically, friction and perpendicular stiction. These parameters are presented as methods to investigate the critical wafer load and unload function. Unique tools and test methods have been developed that deliver accurate and repeatable data, which will be described.« less

Advanced process control and novel test methods for PVD silicon and elastomeric silicone coatings utilized on ion implant disks, heatsinks and selected platens

NASA Astrophysics Data System (ADS)

Springer, J.; Allen, B.; Wriggins, W.; Kuzbyt, R.; Sinclair, R.

2012-11-01

Coatings play multiple key roles in the proper functioning of mature and current ion implanters. Batch and serial implanters require strategic control of elemental and particulate contamination which often includes scrutiny of the silicon surface coatings encountering direct beam contact. Elastomeric Silicone Coatings must accommodate wafer loading and unloading as well as direct backside contact during implant plus must maintain rigid elemental and particulate specifications. The semiconductor industry has had a significant and continuous effort to obtain ultra-pure silicon coatings with sustained process performance and long life. Low particles and reduced elemental levels for silicon coatings are a major requirement for process engineers, OEM manufacturers, and second source suppliers. Relevant data will be presented. Some emphasis and detail will be placed on the structure and characteristics of a relatively new PVD Silicon Coating process that is very dense and homogeneous. Wear rate under typical ion beam test conditions will be discussed. The PVD Silicon Coating that will be presented here is used on disk shields, wafer handling fingers/fences, exclusion zones of heat sinks, beam dumps and other beamline components. Older, legacy implanters can now provide extended process capability using this new generation PVD silicon - even on implanter systems that were shipped long before the advent of silicon coating for contamination control. Low particles and reduced elemental levels are critical performance criteria for the silicone elastomers used on disk heatsinks and serial implanter platens. Novel evaluation techniques and custom engineered tools are used to investigate the surface interaction characteristics of multiple Elastomeric Silicone Coatings currently in use by the industry - specifically, friction and perpendicular stiction. These parameters are presented as methods to investigate the critical wafer load and unload function. Unique tools and test methods have been developed that deliver accurate and repeatable data, which will be described.

SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

NASA Astrophysics Data System (ADS)

Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

2016-10-01

Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and yield. Soft stamps, usually based on silicone rubber, behave fundamentally different compared to rigid stamps on the macro-, micro- and nanometer level. The main limitation of traditional silicones is that they are too soft to support sub-micron features against surface tension based stamp deformation and collapse [4] and handling a soft stamp to achieve accurate feature placement on wafer scales to allow overlay alignment with sub-100nm overlay accuracy.

Characterization of sub-0.18-μm critical dimension pattern collapse for yield improvement

NASA Astrophysics Data System (ADS)

Zhong, Tom X.; Gurer, Emir; Lee, Ed C.; Bai, Hong; Gendron, Bill; Krishna, Murthy S.; Reynolds, Reese M.

1999-09-01

In this study, we demonstrate that surface-resist interface interactions are becoming more crucial in DUV lithography as we enter deep into the sub-wavelength era of smaller critical dimension (CD) size and high aspect ratio. This interaction reveals itself as an adhesion reduction of the resist film due to the smaller contact area between the feature and the substrate. Considerable yield improvements in a manufacturing environment can be realized if pattern collapsing of smaller features is prevented by means of proper priming. In addition, next generation photoresist processing equipments must be able to deliver excellent on-wafer results with minimum chemical consumption as environmental health and safety (EHS) requirements are better appreciated in the marketplace. HMDS is not only highly toxic but it is also a prime threat to CD control of most deep ultra violet (DUV) photoresists used for sub-0.18 micrometer design rules. The by-product NH3 created during priming process with HMDS can neutralize the photo-acid created during the exposure step. There are many technical opportunities in this usually neglected priming process step. In this study, we characterized sub-0.18 micrometer isolated line pattern collapse for UV5 resist on bare Si wafers by using a scanning electron microscope (SEM). The smallest line width printability on wafers primed with different contact angles was analyzed by using both top down and cross section SEM images. Our results show that there is a strong effect of substrate surface and film interface interaction on device yields. More specifically, there is a strong correlation between pattern integrity of features down to 115 nm and vapor prime process conditions. In general, wafers with higher contact angle can support smaller line widths. These results suggest that higher contact angle than the current specification will be required for sub-0.1 micrometer design rule for improved yield. An alternative material to HMDS will probably be needed due to more stringent future requirements and weak bonding characteristics of HMDS. Based on the result of this study, we propose an HMDS consumption reduction scheme for line-widths above 0.2 micrometer. There are many priming-related modular and system level technical enhancements that can be designed in the next generation photoresist processing tools in order to extend 248 nm lithography towards smaller feature sizes.

Drosophila as an unconventional substrate for microfabrication

NASA Astrophysics Data System (ADS)

Shum, Angela J.; Parviz, Babak A.

2007-02-01

We present the application of Drosophila fruit flies as an unconventional substrate for microfabrication. Drosophila by itself represents a complex system capable of many functions not attainable with current microfabrication technology. By using Drosophila as a substrate, we are able to capitalize on these natural functions while incorporating additional functionality into a superior hybrid system. In the following, development of microfabrication processes for Drosophila substrates is discussed. In particular, results of a study on Drosophila tolerance to vacuum pressure during multiple stages of development are given. A remarkable finding that adult Drosophila may withstand up to 3 hours of exposure to vacuum with measurable survival is noted. This finding opens a number of new opportunities for performing fabrication processes, similar to the ones performed on a silicon wafer, on a fruit fly as a live substrate. As a model microfabrication process, it is shown how a collection of Drosophila can be made to self-assemble into an array of microfabricated recesses on a silicon wafer and how a shadow mask can be used to thermally evaporate 100 nm of indium on flies. The procedure resulted in the production of a number of live flies with a pre-designed metal micropattern on their wings. This demonstration of vacuum microfabrication on a live organism provides the first step towards the development of a hybrid biological/solid-state manufacturing process for complex microsystems.

Process in manufacturing high efficiency AlGaAs/GaAs solar cells by MO-CVD

NASA Technical Reports Server (NTRS)

Yeh, Y. C. M.; Chang, K. I.; Tandon, J.

1984-01-01

Manufacturing technology for mass producing high efficiency GaAs solar cells is discussed. A progress using a high throughput MO-CVD reactor to produce high efficiency GaAs solar cells is discussed. Thickness and doping concentration uniformity of metal oxide chemical vapor deposition (MO-CVD) GaAs and AlGaAs layer growth are discussed. In addition, new tooling designs are given which increase the throughput of solar cell processing. To date, 2cm x 2cm AlGaAs/GaAs solar cells with efficiency up to 16.5% were produced. In order to meet throughput goals for mass producing GaAs solar cells, a large MO-CVD system (Cambridge Instrument Model MR-200) with a susceptor which was initially capable of processing 20 wafers (up to 75 mm diameter) during a single growth run was installed. In the MR-200, the sequencing of the gases and the heating power are controlled by a microprocessor-based programmable control console. Hence, operator errors can be reduced, leading to a more reproducible production sequence.

Study of temperature distributions in wafer exposure process

NASA Astrophysics Data System (ADS)

Lin, Zone-Ching; Wu, Wen-Jang

During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP's standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

Photo-EMF sensitivity of porous silicon thin layer-crystalline silicon heterojunction to ammonia adsorption.

PubMed

Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

2011-01-01

A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

A review of manufacturing metrology for improved reliability of silicon photovoltaic modules

NASA Astrophysics Data System (ADS)

Davis, Kristopher O.; Walters, Joseph; Schneller, Eric; Seigneur, Hubert; Brooker, R. Paul; Scardera, Giuseppe; Rodgers, Marianne P.; Mohajeri, Nahid; Shiradkar, Narendra; Dhere, Neelkanth G.; Wohlgemuth, John; Rudack, Andrew C.; Schoenfeld, Winston V.

2014-10-01

In this work, the use of manufacturing metrology across the supply chain to improve crystalline silicon (c-Si) photovoltaic (PV) module reliability and durability is addressed. Additionally, an overview and summary of a recent extensive literature survey of relevant measurement techniques aimed at reducing or eliminating the probability of field failures is presented. An assessment of potential gaps is also given, wherein the PV community could benefit from new research and demonstration efforts. This review is divided into three primary areas representing different parts of the c-Si PV supply chain: (1) feedstock production, crystallization and wafering; (2) cell manufacturing; and (3) module manufacturing.

A Techno-Economic Look at SiC WBG from Wafer to Motor Drive

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bench Reese, Samantha R; Horowitz, Kelsey A; Remo, Timothy W

Techno-economic analysis helps benchmark and deliver supply chain and manufacturing insights that can be leveraged by decision-makers to inform investment strategies, policy, and other decisions to promote economic growth and competitiveness. Silicon Carbide (SiC) wide-band gap (WBG) technologies is poised to be an integral contributor to the clean energy economy. We use bottoms-up regional manufacturing cost models to show SiC power electronics, manufactured in volume, could result in final product cost parity with those manufactured with silicon. The models are further leveraged to show innovation pathways to lower cost and potentially expanded technology adoption.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

ILT based defect simulation of inspection images accurately predicts mask defect printability on wafer

NASA Astrophysics Data System (ADS)

Deep, Prakash; Paninjath, Sankaranarayanan; Pereira, Mark; Buck, Peter

2016-05-01

At advanced technology nodes mask complexity has been increased because of large-scale use of resolution enhancement technologies (RET) which includes Optical Proximity Correction (OPC), Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO). The number of defects detected during inspection of such mask increased drastically and differentiation of critical and non-critical defects are more challenging, complex and time consuming. Because of significant defectivity of EUVL masks and non-availability of actinic inspection, it is important and also challenging to predict the criticality of defects for printability on wafer. This is one of the significant barriers for the adoption of EUVL for semiconductor manufacturing. Techniques to decide criticality of defects from images captured using non actinic inspection images is desired till actinic inspection is not available. High resolution inspection of photomask images detects many defects which are used for process and mask qualification. Repairing all defects is not practical and probably not required, however it's imperative to know which defects are severe enough to impact wafer before repair. Additionally, wafer printability check is always desired after repairing a defect. AIMSTM review is the industry standard for this, however doing AIMSTM review for all defects is expensive and very time consuming. Fast, accurate and an economical mechanism is desired which can predict defect printability on wafer accurately and quickly from images captured using high resolution inspection machine. Predicting defect printability from such images is challenging due to the fact that the high resolution images do not correlate with actual mask contours. The challenge is increased due to use of different optical condition during inspection other than actual scanner condition, and defects found in such images do not have correlation with actual impact on wafer. Our automated defect simulation tool predicts printability of defects at wafer level and automates the process of defect dispositioning from images captured using high resolution inspection machine. It first eliminates false defects due to registration, focus errors, image capture errors and random noise caused during inspection. For the remaining real defects, actual mask-like contours are generated using the Calibre® ILT solution [1][2], which is enhanced to predict the actual mask contours from high resolution defect images. It enables accurate prediction of defect contours, which is not possible from images captured using inspection machine because some information is already lost due to optical effects. Calibre's simulation engine is used to generate images at wafer level using scanner optical conditions and mask-like contours as input. The tool then analyses simulated images and predicts defect printability. It automatically calculates maximum CD variation and decides which defects are severe to affect patterns on wafer. In this paper, we assess the printability of defects for the mask of advanced technology nodes. In particular, we will compare the recovered mask contours with contours extracted from SEM image of the mask and compare simulation results with AIMSTM for a variety of defects and patterns. The results of printability assessment and the accuracy of comparison are presented in this paper. We also suggest how this method can be extended to predict printability of defects identified on EUV photomasks.

Neural Network Modeling for Gallium Arsenide IC Fabrication Process and Device Characteristics.

NASA Astrophysics Data System (ADS)

Creech, Gregory Lee, I.

This dissertation presents research focused on the utilization of neurocomputing technology to achieve enhanced yield and effective yield prediction in integrated circuit (IC) manufacturing. Artificial neural networks are employed to model complex relationships between material and device characteristics at critical stages of the semiconductor fabrication process. Whole wafer testing was performed on the starting substrate material and during wafer processing at four critical steps: Ohmic or Post-Contact, Post-Recess, Post-Gate and Final, i.e., at completion of fabrication. Measurements taken and subsequently used in modeling include, among others, doping concentrations, layer thicknesses, planar geometries, layer-to-layer alignments, resistivities, device voltages, and currents. The neural network architecture used in this research is the multilayer perceptron neural network (MLPNN). The MLPNN is trained in the supervised mode using the generalized delta learning rule. It has one hidden layer and uses continuous perceptrons. The research focuses on a number of different aspects. First is the development of inter-process stage models. Intermediate process stage models are created in a progressive fashion. Measurements of material and process/device characteristics taken at a specific processing stage and any previous stages are used as input to the model of the next processing stage characteristics. As the wafer moves through the fabrication process, measurements taken at all previous processing stages are used as input to each subsequent process stage model. Secondly, the development of neural network models for the estimation of IC parametric yield is demonstrated. Measurements of material and/or device characteristics taken at earlier fabrication stages are used to develop models of the final DC parameters. These characteristics are computed with the developed models and compared to acceptance windows to estimate the parametric yield. A sensitivity analysis is performed on the models developed during this yield estimation effort. This is accomplished by analyzing the total disturbance of network outputs due to perturbed inputs. When an input characteristic bears no, or little, statistical or deterministic relationship to the output characteristics, it can be removed as an input. Finally, neural network models are developed in the inverse direction. Characteristics measured after the final processing step are used as the input to model critical in-process characteristics. The modeled characteristics are used for whole wafer mapping and its statistical characterization. It is shown that this characterization can be accomplished with minimal in-process testing. The concepts and methodologies used in the development of the neural network models are presented. The modeling results are provided and compared to the actual measured values of each characteristic. An in-depth discussion of these results and ideas for future research are presented.

Advanced excimer laser technologies enable green semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Fukuda, Hitomi; Yoo, Youngsun; Minegishi, Yuji; Hisanaga, Naoto; Enami, Tatsuo

2014-03-01

"Green" has fast become an important and pervasive topic throughout many industries worldwide. Many companies, especially in the manufacturing industries, have taken steps to integrate green initiatives into their high-level corporate strategies. Governments have also been active in implementing various initiatives designed to increase corporate responsibility and accountability towards environmental issues. In the semiconductor manufacturing industry, there are growing concerns over future environmental impact as enormous fabs expand and new generation of equipments become larger and more powerful. To address these concerns, Gigaphoton has implemented various green initiatives for many years under the EcoPhoton™ program. The objective of this program is to drive innovations in technology and services that enable manufacturers to significantly reduce both the financial and environmental "green cost" of laser operations in high-volume manufacturing environment (HVM) - primarily focusing on electricity, gas and heat management costs. One example of such innovation is Gigaphoton's Injection-Lock system, which reduces electricity and gas utilization costs of the laser by up to 50%. Furthermore, to support the industry's transition from 300mm to the next generation 450mm wafers, technologies are being developed to create lasers that offer double the output power from 60W to 120W, but reducing electricity and gas consumption by another 50%. This means that the efficiency of lasers can be improve by up to 4 times in 450mm wafer production environments. Other future innovations include the introduction of totally Heliumfree Excimer lasers that utilize Nitrogen gas as its replacement for optical module purging. This paper discusses these and other innovations by Gigaphoton to enable green manufacturing.

Research and Development Strategies in the Semiconductor Industry

NASA Astrophysics Data System (ADS)

Bowling, Allen

2003-03-01

In the 21st Century semiconductor industry, there is a critical balance between internally funded semiconductor research and development (R) and externally funded R. External R may include jointly-funded research collaborations/partnerships with other device manufacturers, jointly-funded consortia-based R, and individually-funded research programs at universities and other contract research locations. Each of these approaches has merits and each has costs. There is a critical balance between keeping the internal research and development pipeline filled and keeping it from being overspent. To meet both competitive schedule and cost goals, a semiconductor device manufacturer must decide on a model for selection of internal versus external R. Today, one of the most critical decisions is whether or not to do semiconductor research and development on 300 mm silicon wafers. Equipment suppliers are doing first development on 300 mm equipment. So, for the device manufacturer, there is a balance between the cost of doing development on 300 mm wafers and the development time schedule driven by equipment availability. In the face of these cost and schedule elements, device manufacturers are looking to consortia such as SEMATECH, SRC, and SRC MARCO for early development and screening of new materials and device structure approaches. This also causes much more close development collaboration between device manufacturer and equipment supplier. Many device manufacturers are also making use of direct contract research with universities and other contract-research organizations, such as IMEC, LETI, and other government-funded research organizations around the world. To get the most out of these external research interactions, the company must develop a strategy for management and technology integration of external R.

3D interconnect metrology in CMS/ITRI

NASA Astrophysics Data System (ADS)

Ku, Y. S.; Shyu, D. M.; Hsu, W. T.; Chang, P. Y.; Chen, Y. C.; Pang, H. L.

2011-05-01

Semiconductor device packaging technology is rapidly advancing, in response to the demand for thinner and smaller electronic devices. Three-dimensional chip/wafer stacking that uses through-silicon vias (TSV) is a key technical focus area, and the continuous development of this novel technology has created a need for non-contact characterization. Many of these challenges are novel to the industry due to the relatively large variety of via sizes and density, and new processes such as wafer thinning and stacked wafer bonding. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at EOL/ITRI. While there is a variety of metrology and inspection applications for 3D interconnect processing, the main topics covered here are via CD/depth measurement, thinned wafer inspection and wafer warpage measurement.

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

NASA Technical Reports Server (NTRS)

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

Experimental Design For Photoresist Characterization

NASA Astrophysics Data System (ADS)

Luckock, Larry

1987-04-01

In processing a semiconductor product (from discrete devices up to the most complex products produced) we find more photolithographic steps in wafer fabrication than any other kind of process step. Thus, the success of a semiconductor manufacturer hinges on the optimization of their photolithographic processes. Yet, we find few companies that have taken the time to properly characterize this critical operation; they are sitting in the "passenger's seat", waiting to see what will come out, hoping that the yields will improve someday. There is no "black magic" involved in setting up a process at its optimum conditions (i.e. minimum sensitivity to all variables at the same time). This paper gives an example of a real world situation for optimizing a photolithographic process by the use of a properly designed experiment, followed by adequate multidimensional analysis of the data. Basic SPC practices like plotting control charts will not, by themselves, improve yields; the control charts are, however, among the necessary tools used in the determination of the process capability and in the formulation of the problems to be addressed. The example we shall consider is the twofold objective of shifting the process average, while tightening the variance, of polysilicon line widths. This goal was identified from a Pareto analysis of yield-limiting mechanisms, plus inspection of the control charts. A key issue in a characterization of this type of process is the number of interactions between variables; this example rules out two-level full factorial and three-level fractional factorial designs (which cannot detect all of the interactions). We arrive at an experiment with five factors at five levels each. A full factorial design for five factors at three levels would require 3125 wafers. Instead, we will use a design that allows us to run this experiment with only 25 wafers, for a significant reduction in time, materials and manufacturing interruption in order to complete the experiment. An optimum solution is then determined via response surface analysis and a series of 3-D and contour plots are shown. The offset between the mask dimensions and poly CD at the optimum operating conditions is discussed with respect to yield, profits and return-on-investment. The expert system used for process optimization covers all types of process steps, producing the best custom designed experiment based on the actual equipment used. The knowledge base contains parameter lists, by machine make and model, ranked by sensitivity and controllability. One option allows 3-D spatial characterization of equipment. For the purpose of this presentation, we will assume that we want to optimize a photo-lithographic process used for polysilicon pattern definition and that we have determined minimum and maximum line widths, based on electrical yield requirements of the product. For this MOS process, the minimum critical dimension (CD) for the poly gate was determined by punchthrough voltage, threshold voltage, etc., while the maximum CD was determined from other performance factors like access time. We will start with the product engineer's analysis.

Submicron patterned metal hole etching

DOEpatents

McCarthy, Anthony M.; Contolini, Robert J.; Liberman, Vladimir; Morse, Jeffrey

2000-01-01

A wet chemical process for etching submicron patterned holes in thin metal layers using electrochemical etching with the aid of a wetting agent. In this process, the processed wafer to be etched is immersed in a wetting agent, such as methanol, for a few seconds prior to inserting the processed wafer into an electrochemical etching setup, with the wafer maintained horizontal during transfer to maintain a film of methanol covering the patterned areas. The electrochemical etching setup includes a tube which seals the edges of the wafer preventing loss of the methanol. An electrolyte composed of 4:1 water: sulfuric is poured into the tube and the electrolyte replaces the wetting agent in the patterned holes. A working electrode is attached to a metal layer of the wafer, with reference and counter electrodes inserted in the electrolyte with all electrodes connected to a potentiostat. A single pulse on the counter electrode, such as a 100 ms pulse at +10.2 volts, is used to excite the electrochemical circuit and perform the etch. The process produces uniform etching of the patterned holes in the metal layers, such as chromium and molybdenum of the wafer without adversely effecting the patterned mask.

Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

NASA Astrophysics Data System (ADS)

Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

2018-07-01

This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

Results from a first production of enhanced Silicon Sensor Test Structures produced by ITE Warsaw

NASA Astrophysics Data System (ADS)

Bergauer, T.; Dragicevic, M.; Frey, M.; Grabiec, P.; Grodner, M.; Hänsel, S.; Hartmann, F.; Hoffmann, K.-H.; Hrubec, J.; Krammer, M.; Kucharski, K.; Macchiolo, A.; Marczewski, J.

2009-01-01

Monitoring the manufacturing process of silicon sensors is essential to ensure stable quality of the produced detectors. During the CMS silicon sensor production we were utilising small Test Structures (TS) incorporated on the cut-away of the wafers to measure certain process-relevant parameters. Experience from the CMS production and quality assurance led to enhancements of these TS. Another important application of TS is the commissioning of new vendors. The measurements provide us with a good understanding of the capabilities of a vendor's process. A first batch of the new TS was produced at the Institute of Electron Technology in Warsaw Poland. We will first review the improvements to the original CMS test structures and then discuss a selection of important measurements performed on this first batch.

New methodology for dynamic lot dispatching

NASA Astrophysics Data System (ADS)

Tai, Wei-Herng; Wang, Jiann-Kwang; Lin, Kuo-Cheng; Hsu, Yi-Chin

1994-09-01

This paper presents a new dynamic dispatching rule to improve delivery. The dynamic dispatching rule named `SLACK and OTD (on time delivery)' is developed for focusing on due date and target cycle time under the environment of IC manufacturing. This idea uses traditional SLACK policy to control long term due date and new OTD policy to reflect the short term stage queue time. Through the fuzzy theory, these two policies are combined as the dispatching controller to define the lot priority in the entire production line. Besides, the system would automatically update the lot priority according to the current line situation. Since the wafer dispatching used to be controlled by critical ratio that indicates the low customer satisfaction. And the overall slack time in the front end of the process is greater compared to that in the rear end of the process which reveals that the machines in the rear end are overloaded by rush orders. When SLACK and OTD are used the due date control has been gradually improved. The wafer with either a long stage queue time or urgent due date will be pushed through the overall production line instead of jammed in the front end. A demand pull system is also developed to satisfy not only due date but also the quantity of monthly demand. The SLACK and OTD rule has been implemented in Taiwan Semiconductor Manufacturing Company for eight months with beneficial results. In order to clearly monitor the SLACK and OTD policy, a method called box chart is generated to simulate the entire production system. From the box chart, we can not only monitor the result of decision policy but display the production situation on the density figure. The production cycle time and delivery situation can also be investigated.

The Preemptive Stocker Dispatching Rule of Automatic Material Handling System in 300 mm Semiconductor Manufacturing Factories

NASA Astrophysics Data System (ADS)

Wang, C. N.; Lin, H. S.; Hsu, H. P.; Wang, Yen-Hui; Chang, Y. P.

2016-04-01

The integrated circuit (IC) manufacturing industry is one of the biggest output industries in this century. The 300mm wafer fabs is the major fab size of this industry. The automatic material handling system (AMHS) has become one of the most concerned issues among semiconductor manufacturers. The major lot delivery of 300mm fabs is used overhead hoist transport (OHT). The traffic jams are happened frequently due to the wide variety of products and big amount of OHTs moving in the fabs. The purpose of this study is to enhance the delivery performance of automatic material handling and reduce the delay and waiting time of product transportation for both hot lots and normal lots. Therefore, this study proposes an effective OHT dispatching rule: preemptive stocker dispatching (PSD). Simulation experiments are conducted and one of the best differentiated preemptive rule, differentiated preemptive dispatching (DPD), is used for comparison. Compared with DPD, The results indicated that PSD rule can reduce average variable delivery time of normal lots by 13.15%, decreasing average variable delivery time of hot lots by 17.67%. Thus, the PSD rule can effectively reduce the delivery time and enhance productivity in 300 mm wafer fabs.

Making Porous Luminescent Regions In Silicon Wafers

NASA Technical Reports Server (NTRS)

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Matsuoka, Yoichi; Seki, Junichi; Nakayama, Takahiro; Nakagawa, Kazuki; Azuma, Hisanobu; Yamamoto, Kiyohito; Sato, Chiaki; Sakai, Fumio; Takabayashi, Yukio; Aghili, Ali; Mizuno, Makoto; Choi, Jin; Jones, Chris E.

2016-10-01

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. On the mask side, a new replication tool, the FPA-1100 NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control, resolution and image placement accuracy. In this paper we discuss the progress made in both feature resolution and in meeting the image placement specification for replica masks.

Epitaxial thinning process

NASA Technical Reports Server (NTRS)

Siegel, C. M. (Inventor)

1984-01-01

A method is described for thinning an epitaxial layer of a wafer that is to be used in producing diodes having a specified breakdown voltage and which also facilitates the thinning process. Current is passed through the epitaxial layer, by connecting a current source between the substrate of the wafer and an electrolyte in which the wafer is immersed. When the wafer is initially immersed, the voltage across the wafer initially drops and then rises at a steep rate. When light is applied to the wafer the voltage drops, and when the light is interrupted the voltage rises again. These changes in voltage, each indicate the breakdown voltage of a Schottky diode that could be prepared from the wafer at that time. The epitaxial layer is thinned by continuing to apply current through the wafer while it is immersed and light is applied, to form an oxide film and when the oxide film is thick the wafer can then be cleaned of oxide and the testing and thinning continued. Uninterrupted thinning can be achieved by first forming an oxide film, and then using an electrolyte that dissolves the oxide about as fast as it is being formed, to limit the thickness of the oxide layer.

Innovative manufacturing technologies for low-cost, high efficiency PERC-based PV modules

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yelundur, Vijay

2017-04-19

The goal this project was to accelerate the deployment of innovative solar cell and module technologies that reduce the cost of PERC-based modules to best-in-class. New module integration technology was to be used to reduce the cost and reliance on conventional silver bus bar pastes and enhance cell efficiency. On the cell manufacturing front, the cost of PERC solar cells was to be reduced by introducing advanced metallization approaches to increase cell efficiency. These advancements will be combined with process optimization to target cell efficiencies in the range of 21 to 21.5%. This project will also explore the viability ofmore » a bifacial PERC solar cell design to enable cost savings through the use of thin silicon wafers. This project was terminated on 4/30/17 after four months of activity due financial challenges facing the recipient.« less

Advances in III-V based dual-band MWIR/LWIR FPAs at HRL

NASA Astrophysics Data System (ADS)

Delaunay, Pierre-Yves; Nosho, Brett Z.; Gurga, Alexander R.; Terterian, Sevag; Rajavel, Rajesh D.

2017-02-01

Recent advances in superlattice-based infrared detectors have rendered this material system a solid alternative to HgCdTe for dual-band sensing applications. In particular, superlattices are attractive from a manufacturing perspective as the epitaxial wafers can be grown with a high degree of lateral uniformity, low macroscopic defect densities (< 50 cm-2) and achieve dark current levels comparable to HgCdTe detectors. In this paper, we will describe our recent effort on the VISTA program towards producing HD-format (1280x720, 12 μm pitch) superlattice based, dual-band MWIR/LWIR FPAs. We will report results from several multi-wafer fabrication lots of 1280x720, 12 μm pitch FPAs processed over the last two years. To assess the FPA performance, noise equivalent temperature difference (NETD) measurements were conducted at 80K, f/4.21 and using a blackbody range of 22°C to 32°C. For the MWIR band, the NETD was 27.44 mK with a 3x median NETD operability of 99.40%. For the LWIR band, the median NETD was 27.62 mK with a 3x median operability of 99.09%. Over the course of the VISTA program, HRL fabricated over 30 FPAs with similar NETDs and operabilities in excess of 99% for both bands, demonstrating the manufacturability and high uniformity of III-V superlattices. We will also present additional characterization results including blinkers, spatial stability, modulation transfer function and thermal cycles reliability.

The role of printing techniques for large-area dye sensitized solar cells

NASA Astrophysics Data System (ADS)

Mariani, Paolo; Vesce, Luigi; Di Carlo, Aldo

2015-10-01

The versatility of printing technologies and their intrinsic ability to outperform other techniques in large-area deposition gives scope to revolutionize the photovoltaic (PV) manufacturing field. Printing methods are commonly used in conventional silicon-based PVs to cover part of the production process. Screen printing techniques, for example, are applied to deposit electrical contacts on the silicon wafer. However, it is with the advent of third generation PVs that printing/coating techniques have been extensively used in almost all of the manufacturing processes. Among all the third generation PVs, dye sensitized solar cell (DSSC) technology has been developed up to commercialization levels. DSSCs and modules can be fabricated by adopting all of the main printing techniques on both rigid and flexible substrates. This allows an easy tuning of cell/module characteristics to the desired application. Transparency, colour, shape, layout and other DSSC’s features can be easily varied by changing the printing parameters and paste/ink formulations used in the printing process. This review focuses on large-area printing/coating technologies for the fabrication of DSSCs devices. The most used and promising techniques are presented underlining the process parameters and applications.

Silicon direct bonding approach to high voltage power device (insulated gate bipolar transistors)

NASA Astrophysics Data System (ADS)

Cha, Giho; Kim, Youngchul; Jang, Hyungwoo; Kang, Hyunsoon; Song, Changsub

2001-10-01

Silicon direct bonding technique was successfully applied for the fabrication of high voltage IGBT (Insulated Gate Bipolar Transistor). In this work, 5 inch, p-type CZ wafer for handle wafer and n-type FZ wafer for device wafer were used and bonding the two wafers was performed at reduced pressure (1mmTorr) using a modified vacuum bonding machine. Since the breakdown voltage in high voltage device has been determined by the remained thickness of device layer, grinding and CMP steps should be carefully designed in order to acquire better uniformity of device layer. In order to obtain the higher removal rate and the final better uniformity of device layer, the harmony of the two processes must be considered. We found that the concave type of grinding profile and the optimal thickness of ground wafer was able to reduce the process time of CMP step and also to enhance the final thickness uniformity of device layer up to +/- 1%. Finally, when compared epitaxy layer with SDB wafer, the SDB wafer was found to be more favorable in terms of cost and electrical characteristics.

Development and fabrication of a solar cell junction processing system

NASA Technical Reports Server (NTRS)

1984-01-01

A processing system capable of producing solar cell junctions by ion implantation followed by pulsed electron beam annealing was developed and constructed. The machine was to be capable of processing 4-inch diameter single-crystal wafers at a rate of 10(7) wafers per year. A microcomputer-controlled pulsed electron beam annealer with a vacuum interlocked wafer transport system was designed, built and demonstrated to produce solar cell junctions on 4-inch wafers with an AMI efficiency of 12%. Experiments showed that a non-mass-analyzed (NMA) ion beam could implant 10 keV phosphorous dopant to form solar cell junctions which were equivalent to mass-analyzed implants. A NMA ion implanter, compatible with the pulsed electron beam annealer and wafer transport system was designed in detail but was not built because of program termination.

The future of automation for high-volume wafer fabrication and ASIC manufacturing

NASA Astrophysics Data System (ADS)

Hughes, Randall A.; Shott, John D.

1986-12-01

A framework is given to analyze the future trends in semiconductor manufacturing automation systems, focusing specifically on the needs of ASIC (application-specific integrated circuit) or custom integrated circuit manufacturing. Advances in technologies such as gate arrays and standard cells now make it significantly easier to obtain system cost and performance advantages by integrating nonstandard functions on silicon. ASICs are attractive to U.S. manufacturers because they place a premium on sophisticated design tools, familiarity with customer needs and applications, and fast turn-around fabrication. These are areas where U.S. manufacturers believe they have an advantage and, consequently, will not suffer from the severe price/manufacturing competition encountered in conventional high-volume semiconductor products. Previously, automation was often considered viable only for high-volume manufacturing, but automation becomes a necessity in the new ASIC environment.

Capital intensity of photovoltaics manufacturing: Barrier to scale and opportunity for innovation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Powell, Douglas M.; Fu, Ran; Horowitz, Kelsey

In this study, using a bottom-up cost model, we assess the impact of initial factory capital expenditure (capex) on photovoltaic (PV) module minimum sustainable price (MSP) and industry-wide trends. We find capex to have two important impacts on PV manufacturing. First, capex strongly influences the per-unit MSP of a c-Si module: we calculate that the capex-related elements sum to 22% of MSP for an integrated wafer, cell, and module manufacturer. This fraction provides a significant opportunity to reduce MSP toward the U.S. DOE SunShot module price target through capex innovation.

Capital intensity of photovoltaics manufacturing: Barrier to scale and opportunity for innovation

DOE PAGES

Powell, Douglas M.; Fu, Ran; Horowitz, Kelsey; ...

2015-09-07

In this study, using a bottom-up cost model, we assess the impact of initial factory capital expenditure (capex) on photovoltaic (PV) module minimum sustainable price (MSP) and industry-wide trends. We find capex to have two important impacts on PV manufacturing. First, capex strongly influences the per-unit MSP of a c-Si module: we calculate that the capex-related elements sum to 22% of MSP for an integrated wafer, cell, and module manufacturer. This fraction provides a significant opportunity to reduce MSP toward the U.S. DOE SunShot module price target through capex innovation.

Prolonged menstrual cycles in female workers exposed to ethylene glycol ethers in the semiconductor manufacturing industry.

PubMed

Hsieh, G-Y; Wang, J-D; Cheng, T-J; Chen, P-C

2005-08-01

It has been shown that female workers exposed to ethylene glycol ethers (EGEs) in the semiconductor industry have higher risks of spontaneous abortion, subfertility, and menstrual disturbances, and prolonged waiting time to pregnancy. To examine whether EGEs or other chemicals are associated with long menstrual cycles in female workers in the semiconductor manufacturing industry. Cross-sectional questionnaire survey during the annual health examination at a wafer manufacturing company in Taiwan in 1997. A three tiered exposure-assessment strategy was used to analyse the risk. A short menstrual cycle was defined to be a cycle less than 24 days and a long cycle to be more than 35 days. There were 606 valid questionnaires from 473 workers in fabrication jobs and 133 in non-fabrication areas. Long menstrual cycles were associated with workers in fabrication areas compared to those in non-fabrication areas. Using workers in non-fabrication areas as referents, workers in photolithography and diffusion areas had higher risks for long menstrual cycles. Workers exposed to EGEs and isopropanol, and hydrofluoric acid, isopropanol, and phosphorous compounds also showed increased risks of a long menstrual cycle. Exposure to multiple chemicals, including EGEs in photolithography, might be associated with long menstrual cycles, and may play an important role in a prolonged time to pregnancy in the wafer manufacturing industry; however, the prevalence in the design, possible exposure misclassification, and chance should be considered.

Development of megasonic cleaning for silicon wafers

NASA Technical Reports Server (NTRS)

Mayer, A.

1980-01-01

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Precision molding of advanced glass optics: innovative production technology for lens arrays and free form optics

NASA Astrophysics Data System (ADS)

Pongs, Guido; Bresseler, Bernd; Bergs, Thomas; Menke, Gert

2012-10-01

Today isothermal precision molding of imaging glass optics has become a widely applied and integrated production technology in the optical industry. Especially in consumer electronics (e.g. digital cameras, mobile phones, Blu-ray) a lot of optical systems contain rotationally symmetrical aspherical lenses produced by precision glass molding. But due to higher demands on complexity and miniaturization of optical elements the established process chain for precision glass molding is not sufficient enough. Wafer based molding processes for glass optics manufacturing become more and more interesting for mobile phone applications. Also cylindrical lens arrays can be used in high power laser systems. The usage of unsymmetrical free-form optics allows an increase of efficiency in optical laser systems. Aixtooling is working on different aspects in the fields of mold manufacturing technologies and molding processes for extremely high complex optical components. In terms of array molding technologies, Aixtooling has developed a manufacturing technology for the ultra-precision machining of carbide molds together with European partners. The development covers the machining of multi lens arrays as well as cylindrical lens arrays. The biggest challenge is the molding of complex free-form optics having no symmetrical axis. A comprehensive CAD/CAM data management along the entire process chain is essential to reach high accuracies on the molded lenses. Within a national funded project Aixtooling is working on a consistent data handling procedure in the process chain for precision molding of free-form optics.

Mask automation: need a revolution in mask makers and equipment industry

NASA Astrophysics Data System (ADS)

Moon, Seong-yong; Yu, Sang-yong; Noh, Young-hwa; Son, Ki-jung; Lee, Hyun-Joo; Cho, Han-Ku

2013-09-01

As improving device integration for the next generation, high performance and cost down are also required accordingly in semiconductor business. Recently, significant efforts have been given on putting EUV technology into fabrication in order to improve device integration. At the same time, 450mm wafer manufacturing environment has been considered seriously in many ways in order to boost up the productivity. Accordingly, 9-inch mask has been discussed in mask fabrication business recently to support 450mm wafer manufacturing environment successfully. Although introducing 9-inch mask can be crucial for mask industry, multi-beam technology is also expected as another influential turning point to overcome currently the most critical issue in mask industry, electron beam writing time. No matter whether 9-inch mask or multi-beam technology will be employed or not, mask quality and productivity will be the key factors to survive from the device competition. In this paper, the level of facility automation in mask industry is diagnosed and analyzed and the automation guideline is suggested for the next generation.

Possibilities for mixed mode chip manufacturing in EUROPRACTICE

NASA Astrophysics Data System (ADS)

Das, C.

1997-02-01

EUROPRACTICE is an EC initiative under the ESPRIT programme which aims to stimulate the wider exploitation of state-of-the-art microelectronics technologies by European industry and to enhance European industrial competitiveness in the global market-place. Through EUROPRACTICE, the EC has created a range of Basic Services that offer users a cost-effective and flexible means of accessing three main microelectronics-based technologies: Application Specific Integrated Circuit (ASICs), Multi-Chip Modules (MCMs) and Microsystems. EUROPRACTICE Basic Services reduce the cost and risk for companies wishing to begin using these technologies. EUROPRACTICE offers a fully supported, low cost route for companies to design and fabricate ASICs for their individual applications. Low cost is achieved by consolidating designs from many users onto a single semiconductor wafer (MPW: Multi Project Wafer). The EUROPRACTICE IC Manufacturing Service (ICMS) offers a broad range of fabrication technologies including CMOS, BiCMOS and GaAs. The Service extends from enabling users to produce prototype ASICs for testing and evaluation, through to low-volume production runs.

Prediction of ppm level electrical failure by using physical variation analysis

NASA Astrophysics Data System (ADS)

Hou, Hsin-Ming; Kung, Ji-Fu; Hsu, Y.-B.; Yamazaki, Y.; Maruyama, Kotaro; Toyoshima, Yuya; Chen, Chu-en

2016-03-01

The quality of patterns printed on wafer may be attributed to factors such as process window control, pattern fidelity, overlay performance, and metrology. Each of these factors play an important role in making the process more effective by ensuring that certain design- and process-specific parameters are kept within acceptable variation. Since chip size and pattern density are increasing accordingly, in-line real time catching the in-chip weak patterns/defects per million opportunities (WP-DPMO) plays more and more significant role for product yield with high density memory. However, the current in-line inspection tools focus on single layer defect inspection, not effectively and efficiently to catch multi-layer weak patterns/defects even through voltage contrast and/or special test structure design [1]-[2]. In general, the multi-layer weak patterns/defects are escaped easily by using in-line inspection and cause ignorance of product dysfunction until off-line time-consuming final PFA/EFA will be used. To effectively and efficiently in-line real time monitor the potential multi-layer weak patterns, we quantify the bridge electrical metric between contact and gate electrodes into CD physical metric via big data from the larger field of view (FOV: 8k x 16k with 3 nm pixel equalizes to image main field size 34 um x 34 um @ 3 nm pixel) e-beam quality image contour compared to layout GDS database (D2DB) as shown in Fig. 1. Hadoop-based distributed parallel computing is implemented to improve the performance of big data architectures, Fig. 2. Therefore, the state of art in-line real time catching in-chip potential multi-layer weak patterns can be proven and achieved by following some studying cases [3]. Therefore, manufacturing sources of variations can be partitioned to systematic and random variations by applying statistical techniques based on the big data fundamental infrastructures. After big data handling, the in-chip CD and AA variations are distinguished by their spatial correlation distance. For local variations (LV) there is no correlation, whereas for global variations (GV) the correlation distance is very large [7]-[9]. This is the first time to certificate the validation of spatial distribution from the affordable bias contour big data fundamental infrastructures. And then apply statistical techniques to dig out the variation sources. The GV come from systematic issue, which could be compensated by adaptive LT condition or OPC correction. But LV comes from random issue, which being considered as intrinsic problem such as structure, material, tool capability… etc. In this paper studying, we can find out the advanced technology node SRAM contact CD local variation (LV) dominates in total variation, about 70%. It often plays significant in-line real time catching WP-DPMO role of the product yield loss, especially for wafer edge is the worst loss within wafer distribution and causes serious reliability concern. The major root cause of variations comes from the PR material induced burr defect (LV), the second one comes from GV enhanced wafer edge short opportunity, which being attributed to three factors, first one factor is wafer edge CD deliberated enlargement for yield improvement as shown in Fig. 10. Second factor is overlaps/AA shifts due to tool capability dealing with incoming wafer's war page issue and optical periphery layout dependent working pitch issue as shown in Fig. 9 (1)., the last factor comes from wafer edge burr enhanced by wafer edge larger Photo Resistance (PR) spin centrifugal force. After implementing KPIs such as GV related AA/CD indexes as shown in Fig. 9 (1) and 10, respectively, and LV related burr index as shown in Fig. 11., we can construct the parts per million (PPM) level short probability model via multi-variables regression, canonical correlation analysis and logistic transformation. The model provides prediction of PPM level electrical failure by using in-line real time physical variation analysis. However in order to achieve Total Quality Management (TQM), the adaptive Statistical Process Control (SPC) charts can be implemented to in-line real time catch PPM level product malfunction at manufacturing stage. Applying for early stage monitor likes incoming raw material, Photo Resistance (PR) … etc., the LV related burr KPI SPC charts could be a powerful quality inspection vehicle. To sum up the paper's contributions, the state of art in-line real time catching in-chip potential multi-layer physical weak patterns can be proven and achieved effectively and efficiently to associate with PPM level product dysfunction.

Comparing the transient response of a resistive-type sensor with a thin film thermocouple during the post-exposure bake process

NASA Astrophysics Data System (ADS)

Kreider, Kenneth G.; DeWitt, David P.; Fowler, Joel B.; Proctor, James E.; Kimes, William A.; Ripple, Dean C.; Tsai, Benjamin K.

2004-04-01

Recent studies on dynamic temperature profiling and lithographic performance modeling of the post-exposure bake (PEB) process have demonstrated that the rate of heating and cooling may have an important influence on resist lithographic response. Measuring the transient surface temperature during the heating or cooling process with such accuracy can only be assured if the sensors embedded in or attached to the test wafer do not affect the temperature distribution in the bare wafer. In this paper we report on an experimental and analytical study to compare the transient response of embedded platinum resistance thermometer (PRT) sensors with surface-deposited, thin-film thermocouples (TFTC). The TFTCs on silicon wafers have been developed at NIST to measure wafer temperatures in other semiconductor thermal processes. Experiments are performed on a test bed built from a commercial, fab-qualified module with hot and chill plates using wafers that have been instrumented with calibrated type-E (NiCr/CuNi) TFTCs and commercial PRTs. Time constants were determined from an energy-balance analysis fitting the temperature-time derivative to the wafer temperature during the heating and cooling processes. The time constants for instrumented wafers ranged from 4.6 s to 5.1 s on heating for both the TFTC and PRT sensors, with an average difference less than 0.1 s between the TFTCs and PRTs and slightly greater differences on cooling.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

WaferOptics® mass volume production and reliability

NASA Astrophysics Data System (ADS)

Wolterink, E.; Demeyer, K.

2010-05-01

The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Custer, Jonathan S.; Fleming, James G.; Roherty-Osmun, Elizabeth

Refractory ternary nitride films for diffusion barriers in microelectronics have been grown using chemical vapor deposition. Thin films of titanium-silicon-nitride, tungsten-boron-nitride, and tungsten-silicon-nitride of various compositions have been deposited on 150 mm Si wafers. The microstructure of the films are either fully amorphous for the tungsten based films, or nauocrystalline TiN in an amorphous matrix for titanium-silicon-nitride. All films exhibit step coverages suitable for use in future microelectronics generations. Selected films have been tested as diffusion barriers between copper and silicon, and generally perform extremely weH. These fiIms are promising candidates for advanced diffusion barriers for microelectronics applications. The manufacturingmore » of silicon wafers into integrated circuits uses many different process and materials. The manufacturing process is usually divided into two parts: the front end of line (FEOL) and the back end of line (BEOL). In the FEOL the individual transistors that are the heart of an integrated circuit are made on the silicon wafer. The responsibility of the BEOL is to wire all the transistors together to make a complete circuit. The transistors are fabricated in the silicon itself. The wiring is made out of metal, currently aluminum and tungsten, insulated by silicon dioxide, see Figure 1. Unfortunately, silicon will diffuse into aluminum, causing aluminum spiking of junctions, killing transistors. Similarly, during chemical vapor deposition (CVD) of tungsten from ~fj, the reactivity of the fluorine can cause "worn-holes" in the silicon, also destroying transistors. The solution to these problems is a so-called diffusion barrier, which will allow current to pass from the transistors to the wiring, but will prevent reactions between silicon and the metal.« less

Low-cost far infrared bolometer camera for automotive use

NASA Astrophysics Data System (ADS)

Vieider, Christian; Wissmar, Stanley; Ericsson, Per; Halldin, Urban; Niklaus, Frank; Stemme, Göran; Källhammer, Jan-Erik; Pettersson, Håkan; Eriksson, Dick; Jakobsen, Henrik; Kvisterøy, Terje; Franks, John; VanNylen, Jan; Vercammen, Hans; VanHulsel, Annick

2007-04-01

A new low-cost long-wavelength infrared bolometer camera system is under development. It is designed for use with an automatic vision algorithm system as a sensor to detect vulnerable road users in traffic. Looking 15 m in front of the vehicle it can in case of an unavoidable impact activate a brake assist system or other deployable protection system. To achieve our cost target below €100 for the sensor system we evaluate the required performance and can reduce the sensitivity to 150 mK and pixel resolution to 80 x 30. We address all the main cost drivers as sensor size and production yield along with vacuum packaging, optical components and large volume manufacturing technologies. The detector array is based on a new type of high performance thermistor material. Very thin Si/SiGe single crystal multi-layers are grown epitaxially. Due to the resulting valence barriers a high temperature coefficient of resistance is achieved (3.3%/K). Simultaneously, the high quality crystalline material provides very low 1/f-noise characteristics and uniform material properties. The thermistor material is transferred from the original substrate wafer to the read-out circuit using adhesive wafer bonding and subsequent thinning. Bolometer arrays can then be fabricated using industry standard MEMS process and materials. The inherently good detector performance allows us to reduce the vacuum requirement and we can implement wafer level vacuum packaging technology used in established automotive sensor fabrication. The optical design is reduced to a single lens camera. We develop a low cost molding process using a novel chalcogenide glass (GASIR®3) and integrate anti-reflective and anti-erosion properties using diamond like carbon coating.

Long-wave infrared 1 × 2 MMI based on air-gap beneath silicon rib waveguides

NASA Astrophysics Data System (ADS)

Wei, Yuxin; Li, Guoyi; Hao, Yinlei; Li, Yubo; Yang, Jianyi; Wang, Minghua; Jiang, Xiaoqing

2011-08-01

The undercut long-wave infrared (LWIR) waveguide components with air-gap beneath are analyzed and fabricated on the Si-wafer with simple manufacturing process. A 1 × 2 multimode interference (MMI) splitter based on this structure is presented and measured under the 10.6μm wavelength experimental setup. The uniformity of the MMI fabricated is 0.76 dB. The relationship among the output power, slab thickness and air-gap width is also fully discussed. Furthermore, undercut straight waveguides based on SOI platform are fabricated for propagation loss evaluation. Ways to reduce the loss are discussed either.

Laser-Based Production of Metallic Conducting Paths

NASA Astrophysics Data System (ADS)

Vedder, Christian; Stollenwerk, Jochen; Wissenbach, Konrad; Pirch, Norbert

For numerous devices such as OLEDs, solar cells or heated windows conducting paths are needed for collecting or distributing electricity on poorly or non-conducting surfaces. With established techniques the metallic paths can only be produced with a great deal of effort, incurring high costs for plant, equipment and energy. A new laser based process to manufacture conducting paths allows for writing narrow paths (down to 35 μm width) of Al, Cu, Ag or similar materials onto flat surfaces of glass (plain or coated with ITO) and silicon wafers by melting and vaporizing a metal foil through optical energy at high speeds of up to 2.5 m/s.

CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

Photo-EMF Sensitivity of Porous Silicon Thin Layer–Crystalline Silicon Heterojunction to Ammonia Adsorption

PubMed Central

Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

2011-01-01

A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light. PMID:22319353

EUV mask pilot line at Intel Corporation

NASA Astrophysics Data System (ADS)

Stivers, Alan R.; Yan, Pei-Yang; Zhang, Guojing; Liang, Ted; Shu, Emily Y.; Tejnil, Edita; Lieberman, Barry; Nagpal, Rajesh; Hsia, Kangmin; Penn, Michael; Lo, Fu-Chang

2004-12-01

The introduction of extreme ultraviolet (EUV) lithography into high volume manufacturing requires the development of a new mask technology. In support of this, Intel Corporation has established a pilot line devoted to encountering and eliminating barriers to manufacturability of EUV masks. It concentrates on EUV-specific process modules and makes use of the captive standard photomask fabrication capability of Intel Corporation. The goal of the pilot line is to accelerate EUV mask development to intersect the 32nm technology node. This requires EUV mask technology to be comparable to standard photomask technology by the beginning of the silicon wafer process development phase for that technology node. The pilot line embodies Intel's strategy to lead EUV mask development in the areas of the mask patterning process, mask fabrication tools, the starting material (blanks) and the understanding of process interdependencies. The patterning process includes all steps from blank defect inspection through final pattern inspection and repair. We have specified and ordered the EUV-specific tools and most will be installed in 2004. We have worked with International Sematech and others to provide for the next generation of EUV-specific mask tools. Our process of record is run repeatedly to ensure its robustness. This primes the supply chain and collects information needed for blank improvement.

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Non-contact defect diagnostics in Cz-Si wafers using resonance ultrasonic vibrations

NASA Astrophysics Data System (ADS)

Belyaev, A.; Kochelap, V. A.; Tarasov, I.; Ostapenko, S.

2001-01-01

A new resonance effect of generation of sub-harmonic acoustic vibrations was applied to characterize defects in as-grown and processed Cz-Si wafers. Ultrasonic vibrations were generated into standard 8″ wafers using an external ultrasonic transducer and their amplitude recorded in a non-contact mode using a scanning acoustic probe. By tuning the frequency, f, of the transducer we observed generation of intense sub-harmonic acoustic mode ("whistle" or w-mode) with f/2 frequency. The characteristics of the w-mode-amplitude dependence, frequency scans, spatial distribution allow a clear distinction versus harmonic vibrations of the same wafer. The origin of sub-harmonic vibrations observed on 8″ Cz-Si wafers is attributed to a parametric resonance of flexural vibrations in thin silicon circular plates. We present evidence that "whistle" effect shows a strong dependence on the wafer's growth and processing history and can be used for quality assurance purposes.

GaAs Substrates for High-Power Diode Lasers

NASA Astrophysics Data System (ADS)

Mueller, Georg; Berwian, Patrick; Buhrig, Eberhard; Weinert, Berndt

GaAs substrate crystals with low dislocation density (Etch-Pit Density (EPD) < 500,^-2) and Si-doping ( ~10^18,^-3) are required for the epitaxial production of high-power diode-lasers. Large-size wafers (= 3 mathrm{in} -> >=3,) are needed for reducing the manufacturing costs. These requirements can be fulfilled by the Vertical Bridgman (VB) and Vertical Gradient Freeze (VGF) techniques. For that purpose we have developed proper VB/VGF furnaces and optimized the thermal as well as the physico-chemical process conditions. This was strongly supported by extensive numerical process simulation. The modeling of the VGF furnaces and processes was made by using a new computer code called CrysVUN++, which was recently developed in the Crystal Growth Laboratory in Erlangen.GaAs crystals with diameters of 2 and 3in were grown in pyrolytic Boron Nitride (pBN) crucibles having a small-diameter seed section and a conical part. Boric oxide was used to fully encapsulate the crystal and the melt. An initial silicon content in the GaAs melt of c (melt) = 3 x10^19,^-3 has to be used in order to achieve a carrier concentration of n = (0.8- 2) x10^18,^-3, which is the substrate specification of the device manufacturer of the diode-laser. The EPD could be reduced to values between 500,^-2 and 50,^-2 with a Si-doping level of 8 x10^17 to 1 x10^18,^-3. Even the 3in wafers have rather large dislocation-free areas. The lowest EPDs ( <100,^-2) are achieved for long seed wells of the crucible.

Method for synthesis of high quality graphene

DOEpatents

Lanzara, Alessandra [Piedmont, CA; Schmid, Andreas K [Berkeley, CA; Yu, Xiaozhu [Berkeley, CA; Hwang, Choonkyu [Albany, CA; Kohl, Annemarie [Beneditkbeuern, DE; Jozwiak, Chris M [Oakland, CA

2012-03-27

A method is described herein for the providing of high quality graphene layers on silicon carbide wafers in a thermal process. With two wafers facing each other in close proximity, in a first vacuum heating stage, while maintained at a vacuum of around 10.sup.-6 Torr, the wafer temperature is raised to about 1500.degree. C., whereby silicon evaporates from the wafer leaving a carbon rich surface, the evaporated silicon trapped in the gap between the wafers, such that the higher vapor pressure of silicon above each of the wafers suppresses further silicon evaporation. As the temperature of the wafers is raised to about 1530.degree. C. or more, the carbon atoms self assemble themselves into graphene.

Robust, low-noise, polarization-maintaining mode-locked Er-fiber laser with a planar lightwave circuit (PLC) device as a multi-functional element.

PubMed

Kim, Chur; Kwon, Dohyeon; Kim, Dohyun; Choi, Sun Young; Cha, Sang Jun; Choi, Ki Sun; Yeom, Dong-Il; Rotermund, Fabian; Kim, Jungwon

2017-04-15

We demonstrate a new planar lightwave circuit (PLC)-based device, integrated with a 980/1550 wavelength division multiplexer, an evanescent-field-interaction-based saturable absorber, and an output tap coupler, which can be employed as a multi-functional element in mode-locked fiber lasers. Using this multi-functional PLC device, we demonstrate a simple, robust, low-noise, and polarization-maintaining mode-locked Er-fiber laser. The measured full-width at half-maximum bandwidth is 6 nm centered at 1555 nm, corresponding to 217 fs transform-limited pulse duration. The measured RIN and timing jitter are 0.22% [10 Hz-10 MHz] and 6.6 fs [10 kHz-1 MHz], respectively. Our results show that the non-gain section of mode-locked fiber lasers can be easily implemented as a single PLC chip that can be manufactured by a wafer-scale fabrication process. The use of PLC processes in mode-locked lasers has the potential for higher manufacturability of low-cost and robust fiber and waveguide lasers.

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

NASA Astrophysics Data System (ADS)

Mieda, Eiko; Maeda, Tatsuro; Miyata, Noriyuki; Yasuda, Tetsuji; Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki; Aoki, Takeshi; Yamamoto, Taketsugu; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko; Ogawa, Arito; Kikuchi, Toshiyuki; Kunii, Yasuo

2015-03-01

We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

Wafer-scale micro-optics fabrication

NASA Astrophysics Data System (ADS)

Voelkel, Reinhard

2012-07-01

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

Top coat or no top coat for immersion lithography?

NASA Astrophysics Data System (ADS)

Stepanenko, N.; Kim, Hyun-Woo; Kishimura, S.; Van Den Heuvel, D.; Vandenbroeck, N.; Kocsis, M.; Foubert, P.; Maenhoudt, M.; Ercken, M.; Van Roey, F.; Gronheid, R.; Pollentier, I.; Vangoidsenhoven, D.; Delvaux, C.; Baerts, C.; O'Brien, S.; Fyen, W.; Wells, G.

2006-03-01

Since the moment immersion lithography appeared in the roadmaps of IC manufacturers, the question whether to use top coats has become one of the important topics for discussions. The top coats used in immersion lithography have proved to serve as good protectors from leaching of the resist components (PAGs, bases) into the water. However their application complicates the process and may lead to two side effects. First, top coats can affect the process window and resist profile depending on the material's refractive index, thickness, acidity, chemical interaction with the resist and the soaking time. Second, the top coat application may increase the total amount of defects on the wafer. Having an immersion resist which could work without the top coat would be a preferable solution. Still, it is quite challenging to make such a resist as direct water/resist interaction may also result in process window changes, CD variations, generation of additional defects. We have performed a systematic evaluation of a large number of immersion resist and top coat combinations, using the ASML XT:1250Di scanner at IMEC. The samples for the experiments were provided by all the leading resist and top coat suppliers. Particular attention was paid to how the resist and top coat materials from different vendors interacted with each other. Among the factors which could influence the total amount of defects or CD variations on the wafer were: the material's dynamic contact angle and its interaction with the scanner stage speed, top coat thickness and intermixing layer formation, water uptake and leaching. We have examined the importance of all mentioned factors, using such analytical techniques as Resist Development Analyser (RDA), Quartz Crystal Microbalance (QCM), Mass Spectroscopy (MS) and scatterometry. We have also evaluated the influence of the pre- and pos- exposure rinse processes on the defectivity. In this paper we will present the data on imaging and defectivity performance of the resists with and without the use of top coats. So far we can conclude that top coat/resist approach used in immersion lithography needs some more improvements (i.e. process, materials properties) in order to be implemented in high volume manufacturing.

450mm wafer patterning with jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

Logic gate scanner focus control in high-volume manufacturing using scatterometry

NASA Astrophysics Data System (ADS)

Dare, Richard J.; Swain, Bryan; Laughery, Michael

2004-05-01

Tool matching and optimal process control are critical requirements for success in semiconductor manufacturing. It is imperative that a tool"s operating conditions are understood and controlled in order to create a process that is repeatable and produces devices within specifications. Likewise, it is important where possible to match multiple systems using some methodology, so that regardless of which tool is used the process remains in control. Agere Systems is currently using Timbre Technologies" Optical Digital Profilometry (ODP) scatterometry for controlling Nikon scanner focus at the most critical lithography layer; logic gate. By adjusting focus settings and verifying the resultant changes in resist profile shape using ODP, it becomes possible to actively control scanner focus to achieve a desired resist profile. Since many critical lithography processes are designed to produce slightly re-entrant resist profiles, this type of focus control is not possible via Critical Dimension Scanning Electron Microscopy (CDSEM) where reentrant profiles cannot be accurately determined. Additionally, the high throughput and non-destructive nature of this measurement technique saves both cycle time and wafer costs compared to cross-section SEM. By implementing an ODP daily process check and after any maintenance on a scanner, Agere successfully enabled focus drift control, i.e. making necessary focus or equipment changes in order to maintain a desired resist profile.

Non-ARC solution to metal reflective notching: its evaluation and selection

NASA Astrophysics Data System (ADS)

Buffat, Stephen J.

1997-07-01

Patterning photoresists on reflective topography such as aluminum is one of the more difficult problems in device manufacturing. Interference effects caused by reflected light from the substrate/photoresist interface and surface topography result in coupling of additional energy into the film. This leads to linewidth variation known as reflective notching which severely impacts process latitude and increases critical dimension variation. For many years, suppliers approached the problem by adding dyes that absorb in the actinic region to create a larger non-bleachable absorption. In recent years, strongly absorbing intermediate layers or ARC's, both organic and inorganic, have seen widespread implementation to control reflective notching. However, if a fab is not equipped to accommodate the required ARC process, the processing can be very time consuming, cumbersome and costly. This study was undertaken to determine if a non-ARC, i-line photoresist process could be developed to reduce or eliminate aluminum reflective notching and accompanying critical dimension variation. This study was designed to screen, identify, and characterize various resist chemistries. Based on the screening characterization, a final, cost effective resist chemistry without ARC was selected, fully characterized and transferred into production. The selected material is currently being used in a high volume 0.60 micrometers CMOS, 200 mm wafer manufacturing process.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, B.

The 11th Workshop will provide a forum for an informal exchange of technical and scientific information between international researchers in the photovoltaic and non-photovoltaic fields. Discussions will include the various aspects of impurities and defects in silicon--their properties, the dynamics during device processing, and their application for developing low-cost processes for manufacturing high-efficiency silicon solar cells. Sessions and panel discussions will review impurities and defects in crystalline-silicon PV, advanced cell structures, new processes and process characterization techniques, and future manufacturing demands. The workshop will emphasize some of the promising new technologies in Si solar cell fabrication that can lower PVmore » energy costs and meet the throughput demands of the future. The three-day workshop will consist of presentations by invited speakers, followed by discussion sessions. Topics to be discussed are: Si Mechanical properties and Wafer Handling, Advanced Topics in PV Fundamentals, Gettering and Passivation, Impurities and Defects, Advanced Emitters, Crystalline Silicon Growth, and Solar Cell Processing. The workshop will also include presentations by NREL subcontractors who will review the highlights of their research during the current subcontract period. In addition, there will be two poster sessions presenting the latest research and development results. Some presentations will address recent technologies in the microelectronics field that may have a direct bearing on PV.« less

Photovoltaics for the Defense Community through Manufacturing Advances

DTIC Science & Technology

2009-04-27

the mod- ule, the inverter, and the balance of system (BOS) costs. The module is the “solar panel ” component that generates electricity, the inverter...Silicon Key areas Examples Ingot Crystal Structures • Multicrystalline • Monocrystalline Wafering Techniques • Wire sawing • Pulling slices off the ingot

Back-illuminated CCD imager adapted for contrast transfer function measurements thereon

NASA Technical Reports Server (NTRS)

Levine, Peter A. (Inventor)

1987-01-01

Stripe patterns of varying spatial frequency, formed in the top-metalization of a back-illuminated solid-state imager, facilitate on-line measurement of contrast transfer function during wafer-probe testing. The imager may be packaged to allow front-illumination during in-the-field testing after its manufacture.

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2012 CFR

2012-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2013 CFR

2013-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2014 CFR

2014-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

Forming electrical interconnections through semiconductor wafers

NASA Technical Reports Server (NTRS)

Anthony, T. R.

1981-01-01

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

PubMed

Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

2011-04-21

A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

NASA Astrophysics Data System (ADS)

Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

2012-05-01

In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

PubMed

Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

2014-01-09

Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

Computational Modeling in Plasma Processing for 300 mm Wafers

NASA Technical Reports Server (NTRS)

Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

1997-01-01

Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

PubMed

Logan, Andrew; Yeow, John T W

2009-05-01

We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

Wavelength stabilized DBR high power diode laser using EBL optical confining grating technology

NASA Astrophysics Data System (ADS)

Paoletti, R.; Codato, S.; Coriasso, C.; Gotta, P.; Meneghini, G.; Morello, G.; De Melchiorre, P.; Riva, E.; Rosso, M.; Stano, A.; Gattiglio, M.

2018-02-01

This paper reports a DBR High Power Diode Laser (DBR-HPDL) realization, emitting up to 10W in the 920 nm range. High spectral purity (90% power in about 0.5 nm), and wavelength stability versus injected current (about 5 times more than standard FP laser) candidates DBR-HPDL as a suitable device for wavelength stabilized pump source, and high brightness applications exploiting Wavelength Division Multiplexing. Key design aspect is a multiple-orders Electron Beam Lithography (EBL) optical confining grating, stabilizing on same wafer multiple wavelengths by a manufacturable and reliable technology. Present paper shows preliminary demonstration of wafer with 3 pitches, generating DBRHPDLs 2.5 nm spaced.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

2017-06-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

Etching Selectivity of Cr, Fe and Ni Masks on Si & SiO2 Wafers

NASA Astrophysics Data System (ADS)

Garcia, Jorge; Lowndes, Douglas H.

2000-10-01

During this Summer 2000 I joined the Semiconductors and Thin Films group led by Dr. Douglas H. Lowndes at Oak Ridge National Laboratory’s Solid State Division. Our objective was to evaluate the selectivity that Trifluoromethane (CHF3), and Sulfur Hexafluoride (SF6) plasmas have for Si, SiO2 wafers and the Ni, Cr, and Fe masks; being this etching selectivity the ratio of the etching rates of the plasmas for each of the materials. We made use of Silicon and Silicon Dioxide-coated wafers that have Fe, Cr or Ni masks. In the semiconductor field, metal layers are often used as masks to protect layers underneath during processing steps; when these wafers are taken to the dry etching process, both the wafer and the mask layers’ thickness are reduced.

A dynamic scheduling algorithm for singe-arm two-cluster tools with flexible processing times

NASA Astrophysics Data System (ADS)

Li, Xin; Fung, Richard Y. K.

2018-02-01

This article presents a dynamic algorithm for job scheduling in two-cluster tools producing multi-type wafers with flexible processing times. Flexible processing times mean that the actual times for processing wafers should be within given time intervals. The objective of the work is to minimize the completion time of the newly inserted wafer. To deal with this issue, a two-cluster tool is decomposed into three reduced single-cluster tools (RCTs) in a series based on a decomposition approach proposed in this article. For each single-cluster tool, a dynamic scheduling algorithm based on temporal constraints is developed to schedule the newly inserted wafer. Three experiments have been carried out to test the dynamic scheduling algorithm proposed, comparing with the results the 'earliest starting time' heuristic (EST) adopted in previous literature. The results show that the dynamic algorithm proposed in this article is effective and practical.

Noncontacting acoustics-based temperature measurement techniques in rapid thermal processing

NASA Astrophysics Data System (ADS)

Lee, Yong J.; Chou, Ching-Hua; Khuri-Yakub, Butrus T.; Saraswat, Krishna C.

1991-04-01

Temperature measurement of silicon wafers based on the temperature dependence of acoustic waves is studied. The change in the temperature-dependent dispersion relations of the plate modes through the wafer can be exploited to provide a viable temperature monitoring scheme with advantages over both thermocouples and pyrometers. Velocity measurements of acoustic waves through a thin layer of ambient directly above the wafer provides the temperature of the wafer-ambient interface. 1.

High-Efficiency Crystalline Photovoltaics | Photovoltaic Research | NREL

Science.gov Websites

. We are key players in developing low-cost, manufacturable techniques for further increasing the also a driving force in two industry-relevant areas: low-cost III-V photovoltaic cells for 1-sun and are developing a >23%-efficiency, low-cost industrial-size cell on n-Cz wafer by 2018. Silicon

Electron-Tunneling Magnetometer

NASA Technical Reports Server (NTRS)

Kaiser, William J.; Kenny, Thomas W.; Waltman, Steven B.

1993-01-01

Electron-tunneling magnetometer is conceptual solid-state device operating at room temperature, yet offers sensitivity comparable to state-of-art magnetometers such as flux gates, search coils, and optically pumped magnetometers, with greatly reduced volume, power consumption, electronics requirements, and manufacturing cost. Micromachined from silicon wafer, and uses tunneling displacement transducer to detect magnetic forces on cantilever-supported current loop.

Assessment of Present State-of-the-art Sawing Technology of Large Diameter Ingots for Solar Sheet Material

NASA Technical Reports Server (NTRS)

Yoo, H. I.

1978-01-01

Work is reported on: (1) slicing of the ingots with the multiblade slurry saw, the multiwire slurry saw and the I.D. saw, (2) characterization of the sliced wafers, and (3) analysis of add-on slicing cost based on Solar Array Manufacturing Industry Costing Standard.

Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

NASA Astrophysics Data System (ADS)

Kim, Bong-Hwan; Kim, Jong-Bok

2009-06-01

We have developed a microfabrication process for high aspect ratio thick silicon wafer molds and electroplating using flipchip bonding with THB 151N negative photoresist (JSR micro). This fabrication technique includes large area and high thickness silicon wafer mold electroplating. The process consists of silicon deep reactive ion etching (RIE) of the silicon wafer mold, photoresist bonding between the silicon mold and the substrate, nickel electroplating and a silicon removal process. High thickness silicon wafer molds were made by deep RIE and flipchip bonding. In addition, nickel electroplating was developed. Dry film resist (ORDYL MP112, TOK) and thick negative-tone photoresist (THB 151N, JSR micro) were used as bonding materials. In order to measure the bonding strength, the surface energy was calculated using a blade test. The surface energy of the bonding wafers was found to be 0.36-25.49 J m-2 at 60-180 °C for the dry film resist and 0.4-1.9 J m-2 for THB 151N in the same temperature range. Even though ORDYL MP112 has a better value of surface energy than THB 151N, it has a critical disadvantage when it comes to removing residue after electroplating. The proposed process can be applied to high aspect ratio MEMS structures, such as air gap inductors or vertical MEMS probe tips.

ProTEK PSB as Biotechnology Photosensitive Protection Mask on 3C-SiC-on-Si in MEMS Sensor

NASA Astrophysics Data System (ADS)

Marsi, N.; Majlis, B. Y.; Mohd-Yasin, F.; Hamzah, A. A.; Mohd Rus, A. Z.

2016-11-01

This project presents the fabrication of MEMS employing a cubic silicon carbide (3C- SiC) on silicon wafer using newly developed ProTEK PSB as biotechnology photosensitive protection mask. This new biotechnology can reduce the number of processes and simplify the process flow with minimal impact on overall undercut performance. The 680 pm thick wafer is back-etched, leaving the 3C-SiC thin film with a thickness of 1.0 μm as the flexible diaphragm to detect pressure. The effect of the new coating of ProTEK PSB on different KOH solvents were investigated depending on various factors such as development time, final cure temperature and the thickness of the ProTEK PSB deposited layer. It is found that 6.174 μm thickness of ProTEK PSB offers some possibility of reducing the processing time compared to silicon nitride etch masks in KOH (55%wt, 80°C). The new ProTEK PSB biotechnology photosensitive protection mask indicates good stability and sustains its performance in different treatments under KOH and IPA for 8 hours. This work also revealed that the fabrication of MEMS sensors using the new biotechnology photosensitive protection mask provides a simple assembly approach and reduces manufacturing costs. The MEMS sensor can operate up to 500 °C as indicated under the sensitivity of 0.826 pF/MPa with nonlinearity and hysteresis of 0.61% and 3.13%, respectively.

Multi-Functional, Micro Electromechanical Silicon Carbide Accelerometer

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2004-01-01

A method of bulk manufacturing SiC sensors is disclosed and claimed. Materials other than SiC may be used as the substrate material. Sensors requiring that the SiC substrate be pierced are also disclosed and claimed. A process flow reversal is employed whereby the metallization is applied first before the recesses are etched into or through the wafer. Aluminum is deposited on the entire planar surface of the metallization. Photoresist is spun onto the substantially planar surface of the Aluminum which is subsequently masked (and developed and removed). Unwanted Aluminum is etched with aqueous TMAH and subsequently the metallization is dry etched. Photoresist is spun onto the still substantially planar surface of Aluminum and oxide and then masked (and developed and removed) leaving the unimidized photoresist behind. Next, ITO is applied over the still substantially planar surface of Aluminum, oxide and unimidized photoresist. Unimidized and exposed photoresist and ITO directly above it are removed with Acetone. Next, deep reactive ion etching attacks exposed oxide not protected by ITO. Finally, hot phosphoric acid removes the Al and ITO enabling wires to connect with the metallization. The back side of the SiS wafer may be also etched.

Mobil Solar Energy Corporation thin EFG octagons. Semiannual subcontract report, 1 April 1992--30 September 1992

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kalejs, J.P.

1993-09-01

This report describes work carried out for the PVMaT program at Mobil Solar for the period covering April 1, 1992, to September 30, 1992. Mobil Solar is developing advanced technology for growing and cutting 200-{mu}m-thick edge-defined film-fed growth (EFG) octagon tubes that will reduce the manufacturing costs of 10-cm {times} 10-cm polycrystalline EFG silicon wafers. Mobil Solar has made progress in identifying factors that impact on thickness nonuniformity and means to reduce the deleterious impact of ambient-related effects that have caused reduction in crystal growth productivity and wafer yield. The current main obstacle to meeting material yield targets arises duemore » to the buckling produced by thermal stress. Studies of laser cutting of EFG silicon using ND:YAG and dye lasers are underway to develop reduced damage cutting methods. Mobil Solar has carried out design reviews for crystal growth and laser cutting equipment. A task has been initiated to evaluate new online sensors for crystal growth process control and to study implementation of advanced control concepts for productivity and yield improvements.« less

A cMUT probe for ultrasound-guided focused ultrasound targeted therapy.

PubMed

Gross, Dominique; Coutier, Caroline; Legros, Mathieu; Bouakaz, Ayache; Certon, Dominique

2015-06-01

Ultrasound-mediated targeted therapy represents a promising strategy in the arsenal of modern therapy. Capacitive micromachined ultrasonic transducer (cMUT) technology could overcome some difficulties encountered by traditional piezoelectric transducers. In this study, we report on the design, fabrication, and characterization of an ultrasound-guided focused ultrasound (USgFUS) cMUT probe dedicated to preclinical evaluation of targeted therapy (hyperthermia, thermosensitive liposomes activation, and sonoporation) at low frequency (1 MHz) with simultaneous ultrasonic imaging and guidance (15 to 20 MHz). The probe embeds two types of cMUT arrays to perform the modalities of targeted therapy and imaging respectively. The wafer-bonding process flow employed for the manufacturing of the cMUTs is reported. One of its main features is the possibility of implementing two different gap heights on the same wafer. All the design and characterization steps of the devices are described and discussed, starting from the array design up to the first in vitro measurements: optical (microscopy) and electrical (impedance) measurements, arrays' electroacoustic responses, focused pressure field mapping (maximum peak-to-peak pressure = 2.5 MPa), and the first B-scan image of a wire-target phantom.

Industrial implementation of spatial variability control by real-time SPC

NASA Astrophysics Data System (ADS)

Roule, O.; Pasqualini, F.; Borde, M.

2016-10-01

Advanced technology nodes require more and more information to get the wafer process well setup. The critical dimension of components decreases following Moore's law. At the same time, the intra-wafer dispersion linked to the spatial non-uniformity of tool's processes is not capable to decrease in the same proportions. APC systems (Advanced Process Control) are being developed in waferfab to automatically adjust and tune wafer processing, based on a lot of process context information. It can generate and monitor complex intrawafer process profile corrections between different process steps. It leads us to put under control the spatial variability, in real time by our SPC system (Statistical Process Control). This paper will outline the architecture of an integrated process control system for shape monitoring in 3D, implemented in waferfab.

Making Wide-IF SIS Mixers with Suspended Metal-Beam Leads

NASA Technical Reports Server (NTRS)

Kaul, Anupama; Bumble, Bruce; Lee, Karen; LeDuc, Henry; Rice, Frank; Zmuidzinas, Jonas

2005-01-01

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide-intermediate-frequency-band (wide-IF) superconductor/insulator/superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25- m-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections: 1. The front-side process, in which SIS devices with beam leads are formed on a SOI wafer; 2. The backside process, in which the SOI wafer is wax-mounted onto a carrier wafer, then thinned, then partitioned into individual devices; and 3. The release process, in which the individual devices are separated using a lithographic dicing technique. The total thickness of the starting 4-in. (10.16-cm)-diameter SOI wafer includes 25 m for the Si device layer, 0.5 m for the buried oxide (BOX) layer, and 350 m the for Si-handle layer. The front-side process begins with deposition of an etch-stop layer of SiO2 or AlN(x), followed by deposition of a Nb/Al- AlN(x) /Nb trilayer in a load-locked DC magnetron sputtering system. The lithography for four of a total of five layers is performed in a commercial wafer-stepping apparatus. Diagnostic test dies are patterned concurrently at certain locations on the wafer, alongside the mixer devices, using a different mask set. The conventional, self-aligned lift-off process is used to pattern the SIS devices up to the wire level.

A two layer hermetic-like coating process for on-wafer encapsulation of GaAs MMIC`s

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kaleta, T.; Varmazis, C.; Carney, J.P.

1995-12-31

The authors have developed a low-cost, manufacturable, 2-layer coating process for on-wafer encapsulation of GaAs MMICs. This packaging approach takes advantage of the low dielectric permittivity of polymers such as Benzocyclobutene (BCB) and the sealing properties of ceramics such as SiC to provide both mechanical protection to MMICs during handling and also hermetic-like equivalence to moisture with predictable changes in the electrical performance of the coated MMICs. The effects of coatings on FET parameters, spiral inductors and a two stage X-Band LNA have been investigated. Results on FETs indicate that the internode capacitances Cgs and Cgd exhibited the same incrementalmore » change of 0.035 pF/mm (3 and 25 % increase respectively), while Cds changed by 0.051 pF/mm (27% increase) with very minimal changes in the other FET parameters. The only observed change in spiral inductors was a 112% increase in Cp from 0.006 pF to 0.013 pF. The LNA exhibited a 1 GHz shift in frequency response from 7 to 11 GHz to 6 to 11 GHz with no substantial changes in gain and noise figure. Preliminary reliability investigations on coated devices did not show any failures after 150 hours in autoclave (120C, 100% humidity).« less

Molded, wafer level optics for long wave infra-red applications

NASA Astrophysics Data System (ADS)

Franks, John

2016-05-01

For many years, the Thermal Imaging market has been driven by the high volume consumer market. The first signs of this came with the launch of night vision systems for cars, first by Cadillac and Honda and then, more successfully by BMW, Daimler and Audi. For the first time, simple thermal imaging systems were being manufactured at the rate of more than 10,000 units a year. This step change in volumes enabled a step change in system costs, with thermal imaging moving into the consumer's price range. Today we see that the consumer awareness and the consumer market continues to increase with the launch of a number of consumer focused smart phone add-ons. This has brought a further step change in system costs, with the possibility to turn your mobile phone into a thermal imager for under $250. As the detector technology has matured, the pixel pitches have dropped from 50μm in 2002 to 12 μm or even 10μm in today's detectors. This dramatic shrinkage in size has had an equally dramatic effect on the optics required to produce the image on the detector. A moderate field of view that would have required a focal length of 40mm in 2002 now requires a focal length of 8mm. For wide field of view applications and small detector formats, focal lengths in the range 1mm to 5mm are becoming common. For lenses, the quantity manufactured, quality and costs will require a new approach to high volume Infra-Red (IR) manufacturing to meet customer expectations. This, taken with the SwaP-C requirements and the emerging requirement for very small lenses driven by the new detectors, suggests that wafer scale optics are part of the solution. Umicore can now present initial results from an intensive research and development program to mold and coat wafer level optics, using its chalcogenide glass, GASIR®.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1991-01-01

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

1992-01-01

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Residual Stress and Fracture of PECVD Thick Oxide Films for Power MEMS Structures and Devices

DTIC Science & Technology

2007-06-01

Residual stress leads to large overall wafer bow, which makes further processing difficult. For example some microfabrication machines , such as chemical...curvature will be measured across the wafer surface in 12 scans, rotating 24 the wafer by 300 between each scan. In situ wafer curvature will be...SiOx. 4.1. Introduction As introduced earlier (Sec.1), in Power MEMS (micro energy- harvesting devices such as micro heat engines and related components

A spatially resolved retarding field energy analyzer design suitable for uniformity analysis across the surface of a semiconductor wafer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sharma, S., E-mail: shailesh.sharma6@mail.dcu.ie; National Centre for Plasma Science and Technology, Dublin City University, Glasnevin, Dublin 9; Gahan, D., E-mail: david.gahan@impedans.com

2014-04-15

A novel retarding field energy analyzer design capable of measuring the spatial uniformity of the ion energy and ion flux across the surface of a semiconductor wafer is presented. The design consists of 13 individual, compact-sized, analyzers, all of which are multiplexed and controlled by a single acquisition unit. The analyzers were tested to have less than 2% variability from unit to unit due to tight manufacturing tolerances. The main sensor assembly consists of a 300 mm disk to mimic a semiconductor wafer and the plasma sampling orifices of each sensor are flush with disk surface. This device is placedmore » directly on top of the rf biased electrode, at the wafer location, in an industrial capacitively coupled plasma reactor without the need for any modification to the electrode structure. The ion energy distribution, average ion energy, and average ion flux were measured at the 13 locations over the surface of the powered electrode to determine the degree of spatial nonuniformity. The ion energy and ion flux are shown to vary by approximately 20% and 5%, respectively, across the surface of the electrode for the range of conditions investigated in this study.« less

Metrology needs for the semiconductor industry over the next decade

NASA Astrophysics Data System (ADS)

Melliar-Smith, Mark; Diebold, Alain C.

1998-11-01

Metrology will continue to be a key enabler for the development and manufacture of future generations of integrated circuits. During 1997, the Semiconductor Industry Association renewed the National Technology Roadmap for Semiconductors (NTRS) through the 50 nm technology generation and for the first time included a Metrology Roadmap (1). Meeting the needs described in the Metrology Roadmap will be both a technological and financial challenge. In an ideal world, metrology capability would be available at the start of process and tool development, and silicon suppliers would have 450 mm wafer capable metrology tools in time for development of that wafer size. Unfortunately, a majority of the metrology suppliers are small companies that typically can't afford the additional two to three year wait for return on R&D investment. Therefore, the success of the semiconductor industry demands that we expand cooperation between NIST, SEMATECH, the National Labs, SRC, and the entire community. In this paper, we will discuss several critical metrology topics including the role of sensor-based process control, in-line microscopy, focused measurements for transistor and interconnect fabrication, and development needs. Improvements in in-line microscopy must extend existing critical dimension measurements up to 100 nm generations and new methods may be required for sub 100 nm generations. Through development, existing metrology dielectric thickness and dopant dose and junction methods can be extended to 100 nm, but new and possibly in-situ methods are needed beyond 100 nm. Interconnect process control will undergo change before 100 nm due to the introduction of copper metallization, low dielectric constant interlevel dielectrics, and Damascene process flows.

Experiences in flip chip production of radiation detectors

NASA Astrophysics Data System (ADS)

Savolainen-Pulli, Satu; Salonen, Jaakko; Salmi, Jorma; Vähänen, Sami

2006-09-01

Modern imaging devices often require heterogeneous integration of different materials and technologies. Because of yield considerations, material availability, and various technological limitations, an extremely fine pitch is necessary to realize high-resolution images. Thus, there is a need for a hybridization technology that is able to join together readout amplifiers and pixel detectors at a very fine pitch. This paper describes radiation detector flip chip production at VTT. Our flip chip technology utilizes 25-μm diameter tin-lead solder bumps at a 50-μm pitch and is based on flux-free bonding. When preprocessed wafers are used, as is the case here, the total yield is defined only partly by the flip chip process. Wafer preprocessing done by a third-party silicon foundry and the flip chip process create different process defects. Wafer-level yield maps (based on probing) provided by the customer are used to select good readout chips for assembly. Wafer probing is often done outside of a real clean room environment, resulting in particle contamination and/or scratches on the wafers. Factors affecting the total yield of flip chip bonded detectors are discussed, and some yield numbers of the process are given. Ways to improve yield are considered, and finally guidelines for process planning and device design with respect to yield optimization are given.

Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

2016-11-01

The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

Strategy optimization for mask rule check in wafer fab

NASA Astrophysics Data System (ADS)

Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

2015-07-01

Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

Nanoscale x-ray imaging of circuit features without wafer etching.

PubMed

Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S G; Peterka, Tom; Levi, Anthony J F; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

2017-03-01

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules, ideally in a non-destructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions, or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits, with past work delivering 20-40 nm resolution on thinned ICs. We describe a simple model for estimating the required exposure, and use it to estimate the future potential for this technique. Here we show for the first time that this approach can be used to image circuit detail through an unprocessed 300 μ m thick silicon wafer, with sub-20 nm detail clearly resolved after mechanical polishing to 240 μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire non-etched ICs to be imaged to 10 nm resolution or better while maintaining their ability to function in electrical tests.

Nanoscale x-ray imaging of circuit features without wafer etching

DOE PAGES

Deng, Junjing; Hong, Young Pyo; Chen, Si; ...

2017-03-24

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses hasmore » not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20–40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300-μm-thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240-μm thickness was used to eliminate image contrast caused by Si wafer surface scratches. Here, by using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.« less

Nanoscale x-ray imaging of circuit features without wafer etching

NASA Astrophysics Data System (ADS)

Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S. G.; Peterka, Tom; Levi, Anthony J. F.; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

2017-03-01

Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20-40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300 -μ m -thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240 -μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.

Investigation of radiation hardened SOI wafer fabricated by ion-cut technique

NASA Astrophysics Data System (ADS)

Chang, Yongwei; Wei, Xing; Zhu, Lei; Su, Xin; Gao, Nan; Dong, Yemin

2018-07-01

Total ionizing dose (TID) effect on Silicon-on-Insulator (SOI) wafers due to inherent buried oxide (BOX) is a significant concern as it leads to the degradation of electrical properties of SOI-based devices and circuits, even failures of the systems associated with them. This paper reports the radiation hardening implementation of SOI wafer fabricated by ion-cut technique integrated with low-energy Si+ implantation. The electrical properties and radiation response of pseudo-MOS transistors are analyzed. The results demonstrate that the hardening process can significantly improve the TID tolerance of SOI wafers by generating Si nanocrystals (Si-NCs) within the BOX. The presence of Si-NCs created through Si+ implantation is evidenced by high-resolution transmission electron microscopy (HR-TEM). Under the pass gate (PG) irradiation bias, the anti-radiation properties of H-gate SOI nMOSFETs suggest that the radiation hardened SOI wafers with optimized Si implantation dose can perform effectively in a radiation environment. The radiation hardening process provides an excellent way to reinforce the TID tolerance of SOI wafers.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Photolithography and Selective Etching of an Array of Quartz Tuning Fork Resonators with Improved Impact Resistance Characteristics

NASA Astrophysics Data System (ADS)

Lee, Sungkyu

2001-08-01

Quartz tuning fork blanks with improved impact-resistant characteristics for use in Qualcomm mobile station modem (MSM)-3000 central processing unit (CPU) chips for code division multiple access (CDMA), personal communication system (PCS), and global system for mobile communication (GSM) systems were designed using finite element method (FEM) analysis and suitable processing conditions were determined for the reproducible precision etching of a Z-cut quartz wafer into an array of tuning forks. Negative photoresist photolithography for the additive process was used in preference to positive photoresist photolithography for the subtractive process to etch the array of quartz tuning forks. The tuning fork pattern was transferred via a conventional photolithographical chromium/quartz glass template using a standard single-sided aligner and subsequent negative photoresist development. A tightly adhering and pinhole-free 600/2000 Å chromium/gold mask was coated over the developed photoresist pattern which was subsequently stripped in acetone. This procedure was repeated on the back surface of the wafer. With the protective metallization area of the tuning fork geometry thus formed, etching through the quartz wafer was performed at 80°C in a ± 1.5°C controlled bath containing a concentrated solution of ammonium bifluoride to remove the unwanted areas of the quartz wafer. The quality of the quartz wafer surface finish after quartz etching depended primarily on the surface finish of the quartz wafer prior to etching and the quality of quartz crystals used. Selective etching of a 100 μm quartz wafer could be achieved within 90 min at 80°C. A selective etching procedure with reproducible precision has thus been established and enables the photolithographic mass production of miniature tuning fork resonators.

Manufacturability study of masks created by inverse lithography technology (ILT)

NASA Astrophysics Data System (ADS)

Martin, Patrick M.; Progler, C. J.; Xiao, G.; Gray, R.; Pang, L.; Liu, Y.

2005-11-01

As photolithography is pushed to fabricate deep-sub wavelength devices for 90nm, 65nm and smaller technology nodes using available exposure tools (i.e., 248nm, 193nm steppers), photomask capability is becoming extremely critical. For example, PSM masks require more complicated processing; aggressive OPC makes the writing time longer and sometimes unpredictable; and, high MEEF imposes much more stringent demands on mask quality. Therefore, in order for any new lithography technology to be adopted into production, mask manufacturability must be studied thoroughly and carefully. In this paper we will present the mask manufacturability study on mask patterns created using Inverse Lithography Technology (ILT). Unlike conventional OPC methodologies, ILT uses a unique outcome-based technology to mathematically determine the mask features that produce the desired on-wafer results. ILT solves the most critical litho challenges of the deep sub-wavelength era. Potential benefits include: higher yield; expanded litho process windows; superb pattern fidelity at 90, 65 & 45-nm nodes; and reduced time-to-silicon - all without changing the existing lithography infrastructure and design-to-silicon flow. In this study a number of cell structures were selected and used as test patterns. "Luminized patterns" were generated for binary mask and attenuated phase-shift mask. Both conventional OPC patterns and "luminized patterns" were put on a test reticle side by side, and they all have a number of variations in term of correction aggressivity level and mask complexity. Mask manufacturability, including data fracturing, writing time, mask inspection, and metrology were studied. The results demonstrate that, by optimizing the inspection recipe, masks created using ILT technology can be made and qualified using current processes with a reasonable turn-around time.

Forming n/p Junctions With An Excimer Laser

NASA Technical Reports Server (NTRS)

Alexander, Paul, Jr.; Campbell, Robert B.; Wong, David C.; Bottenberg, William L.; Byron, Stanley

1988-01-01

Compact equipment yields high-quality solar cells. Computer controls pulses of excimer laser and movement of silcon wafer. Mirrors direct laser beam to wafer. Lenses focus beam to small spot on surface. Process suitable for silicon made by dendritic-web-growth process.

Recent progress in 1.3- and 1.5-μm waveband wafer-fused VCSELs

NASA Astrophysics Data System (ADS)

Mereuta, A.; Caliman, A.; Sirbu, A.; Iakovlev, V.; Ellafi, D.; Rudra, A.; Wolf, P.; Bimberg, D.; Kapon, E.

2016-11-01

The progress of 1.3- and 1.5-μm waveband wafer-fused VCSELs is reported. The emission of single mode power of 6 - 8 mW at room temperature and up to 3 mW at 80°C were demonstrated. 10-Gb/s full wavelength-set VCSEL devices for CWDM systems with high yield and Telcordia-reliability were industrially manufactured. By increasing the compressive strain in the QWs and reducing the cavity photon life time the modulation bandwidth was increased to 11.5 GHz, and large-signal data transmission experiments show error-free operation and open eye diagrams from 25 to 35 Gb/s in both B2B and after 10-km, respectively.

Silicon sample holder for molecular beam epitaxy on pre-fabricated integrated circuits

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Grunthaner, Paula J. (Inventor); Grunthaner, Frank J. (Inventor)

1994-01-01

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

Method for nanomachining high aspect ratio structures

DOEpatents

Yun, Wenbing; Spence, John; Padmore, Howard A.; MacDowell, Alastair A.; Howells, Malcolm R.

2004-11-09

A nanomachining method for producing high-aspect ratio precise nanostructures. The method begins by irradiating a wafer with an energetic charged-particle beam. Next, a layer of patterning material is deposited on one side of the wafer and a layer of etch stop or metal plating base is coated on the other side of the wafer. A desired pattern is generated in the patterning material on the top surface of the irradiated wafer using conventional electron-beam lithography techniques. Lastly, the wafer is placed in an appropriate chemical solution that produces a directional etch of the wafer only in the area from which the resist has been removed by the patterning process. The high mechanical strength of the wafer materials compared to the organic resists used in conventional lithography techniques with allows the transfer of the precise patterns into structures with aspect ratios much larger than those previously achievable.

Guided ultrasonic wave beam skew in silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2018-04-01

In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

Slicing of Silicon into Sheet Material. Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Solar Array Project

NASA Technical Reports Server (NTRS)

Fleming, J. R.; Holden, S. C.; Wolfson, R. G.

1979-01-01

The use of multiblade slurry sawing to produce silicon wafers from ingots was investigated. The commercially available state of the art process was improved by 20% in terms of area of silicon wafers produced from an ingot. The process was improved 34% on an experimental basis. Economic analyses presented show that further improvements are necessary to approach the desired wafer costs, mostly reduction in expendable materials costs. Tests which indicate that such reduction is possible are included, although demonstration of such reduction was not completed. A new, large capacity saw was designed and tested. Performance comparable with current equipment (in terms of number of wafers/cm) was demonstrated.

Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

NASA Astrophysics Data System (ADS)

Wang, Shing-Dar; Chen, Ting-Wei

2018-06-01

In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in <1 0 0> direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

Advances in SELEX ES infrared detectors for space and astronomy

NASA Astrophysics Data System (ADS)

Knowles, P.; Hipwood, L.; Baker, I.; Weller, H.

2017-11-01

Selex ES produces a wide range of infrared detectors from mercury cadmium telluride (MCT) and triglycine sulfate (TGS), and has supplied both materials into space programmes spanning a period of over 40 years. Current development activities that underpin potential future space missions include large format arrays for near- and short-wave infrared (NIR and SWIR) incorporating radiation-hard designs and suppression of glow. Improved heterostructures are aimed at the reduction of dark currents and avalanche photodiodes (APDs), and parallel studies have been undertaken for low-stress MCT array mounts. Much of this development work has been supported by ESA, UK Space, and ESO, and some has been performed in collaboration with the UK Astronomy Technology Centre and E2V. This paper focuses on MCT heterostructure developments and novel design elements in silicon read-out chips (ROICs). The 2048 x 2048 element, 17um pitch ROIC for ESA's SWIR array development forms the basis for the largest cooled infrared detector manufactured in Europe. Selex ES MCT is grown by metal organic vapour phase epitaxy (MOVPE), currently on 75mm diameter GaAs substrates. The MCT die size of the SWIR array is 35mm square and only a single array can be printed on the 75mm diameter wafer, utilising only 28% of the wafer area. The situation for 100mm substrates is little better, allowing only 2 arrays and 31% utilisation. However, low cost GaAs substrates are readily available in 150mm diameter and the MCT growth is scalable to this size, offering the real possibility of 6 arrays per wafer with 42% utilisation. A similar 2k x 2k ROIC is the goal of ESA's NIR programme, which is currently in phase 2 with a 1k x 1k demonstrator, and a smaller 320 x 256 ROIC (SAPHIRA) has been designed for ESO for the adaptive optics application in the VLT Gravity instrument. All 3 chips have low noise source-follower architecture and are enabled for MCT APD arrays, which have been demonstrated by ESO to be capable of single photon detection. The possibility therefore exists in the near future of demonstrating a photon counting, 2k x 2k SWIR MCT detector manufactured on an affordable wafer scale of 6 arrays per wafer.

Nanoimprint system development and status for high volume semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Hiura, Hiromi; Takabayashi, Yukio; Takashima, Tsuneo; Emoto, Keiji; Choi, Jin; Schumaker, Phil

2016-10-01

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. For imprint lithography, recent attention has been given to the areas of overlay, throughput, defectivity, and mask replication. This paper reviews progress in these critical areas. Recent demonstrations have proven that mix and match overlay of less than 5nm can achieved. Further reductions require a higher order correction system. Modeling and experimental data are presented which provide a path towards reducing the overlay errors to less than 3nm. Throughput is mainly impacted by the fill time of the relief images on the mask. Improvement in resist materials provides a solution that allows 15 wafers per hour per station, or a tool throughput of 60 wafers per hour. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. Finally, on the mask side, a new replication tool, the FPA-1100NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control and IP accuracy. In particular, by improving the specifications on the mask chuck, residual errors of only 1nm can be realized.

Optimal mask characterization by Surrogate Wafer Print (SWaP) method

NASA Astrophysics Data System (ADS)

Kimmel, Kurt R.; Hoellein, Ingo; Peters, Jan Hendrick; Ackmann, Paul; Connolly, Brid; West, Craig

2008-10-01

Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask relative to the specifications is done completely by the mask maker. As the challenges of low-k1 imaging continue to grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers' continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore, improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent and compelling. The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images, rather than the mask's physical attributes, as a technically superior and lower-cost method to characterize a mask. The idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for traditional mask inspections and measurements represents the ultimate method to characterize a mask's performance, which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab mask qualification to validate defect and dimensional performance. In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of SWaP for the characterization of defects as an alternative to traditional mask inspection [1]. It showed that this concept is not only feasible, but, in some cases, desirable. This paper expands on last year's work at AMTC to assess the full implementation of SWaP as an enhancement to mask characterization quality including defectivity, dimensional control, pattern fidelity, and in-plane distortion. We present a thorough analysis of both the technical and logistical challenges coupled with an objective view of the advantages and disadvantages from both the technical and financial perspectives. The analysis and model used by the AMTC will serve to provoke other mask shops to prepare their own analyses then consider this new paradigm for mask characterization and qualification.

Capillary-Driven Microfluidic Chips for Miniaturized Immunoassays: Efficient Fabrication and Sealing of Chips Using a "Chip-Olate" Process.

PubMed

Temiz, Yuksel; Delamarche, Emmanuel

2017-01-01

The fabrication of silicon-based microfluidic chips is invaluable in supporting the development of many microfluidic concepts for research in the life sciences and in vitro diagnostic applications such as the realization of miniaturized immunoassays using capillary-driven chips. While being extremely abundant, the literature covering microfluidic chip fabrication and assay development might not have addressed properly the challenge of fabricating microfluidic chips on a wafer level or the need for dicing wafers to release chips that need then to be further processed, cleaned, rinsed, and dried one by one. Here, we describe the "chip-olate" process wherein microfluidic structures are formed on a silicon wafer, followed by partial dicing, cleaning, and drying steps. Then, integration of reagents (if any) can be done, followed by lamination of a sealing cover. Breaking by hand the partially diced wafer yields individual chips ready for use.

Silicon solar cell process development, fabrication and analysis

NASA Technical Reports Server (NTRS)

Yoo, H. I.; Iles, P. A.; Leung, D. C.

1981-01-01

Solar cells were fabricated from EFG ribbons dendritic webs, cast ingots by heat exchanger method, and cast ingots by ubiquitous crystallization process. Baseline and other process variations were applied to fabricate solar cells. EFG ribbons grown in a carbon-containing gas atmosphere showed significant improvement in silicon quality. Baseline solar cells from dendritic webs of various runs indicated that the quality of the webs under investigation was not as good as the conventional CZ silicon, showing an average minority carrier diffusion length of about 60 um versus 120 um of CZ wafers. Detail evaluation of large cast ingots by HEM showed ingot reproducibility problems from run to run and uniformity problems of sheet quality within an ingot. Initial evaluation of the wafers prepared from the cast polycrystalline ingots by UCP suggested that the quality of the wafers from this process is considerably lower than the conventional CZ wafers. Overall performance was relatively uniform, except for a few cells which showed shunting problems caused by inclusions.

The application of phase grating to CLM technology for the sub-65nm node optical lithography

NASA Astrophysics Data System (ADS)

Yoon, Gi-Sung; Kim, Sung-Hyuck; Park, Ji-Soong; Choi, Sun-Young; Jeon, Chan-Uk; Shin, In-Kyun; Choi, Sung-Woon; Han, Woo-Sung

2005-06-01

As a promising technology for sub-65nm node optical lithography, CLM(Chrome-Less Mask) technology among RETs(Resolution Enhancement Techniques) for low k1 has been researched worldwide in recent years. CLM has several advantages, such as relatively simple manufacturing process and competitive performance compared to phase-edge PSM's. For the low-k1 lithography, we have researched CLM technique as a good solution especially for sub-65nm node. As a step for developing the sub-65nm node optical lithography, we have applied CLM technology in 80nm-node lithography with mesa and trench method. From the analysis of the CLM technology in the 80nm lithography, we found that there is the optimal shutter size for best performance in the technique, the increment of wafer ADI CD varied with pattern's pitch, and a limitation in patterning various shapes and size by OPC dead-zone - OPC dead-zone in CLM technique is the specific region of shutter size that dose not make the wafer CD increased more than a specific size. And also small patterns are easily broken, while fabricating the CLM mask in mesa method. Generally, trench method has better optical performance than mesa. These issues have so far restricted the application of CLM technology to a small field. We approached these issues with 3-D topographic simulation tool and found that the issues could be overcome by applying phase grating in trench-type CLM. With the simulation data, we made some test masks which had many kinds of patterns with many different conditions and analyzed their performance through AIMS fab 193 and exposure on wafer. Finally, we have developed the CLM technology which is free of OPC dead-zone and pattern broken in fabrication process. Therefore, we can apply the CLM technique into sub-65nm node optical lithography including logic devices.

Real-Time Plasma Process Condition Sensing and Abnormal Process Detection

PubMed Central

Yang, Ryan; Chen, Rongshun

2010-01-01

The plasma process is often used in the fabrication of semiconductor wafers. However, due to the lack of real-time etching control, this may result in some unacceptable process performances and thus leads to significant waste and lower wafer yield. In order to maximize the product wafer yield, a timely and accurately process fault or abnormal detection in a plasma reactor is needed. Optical emission spectroscopy (OES) is one of the most frequently used metrologies in in-situ process monitoring. Even though OES has the advantage of non-invasiveness, it is required to provide a huge amount of information. As a result, the data analysis of OES becomes a big challenge. To accomplish real-time detection, this work employed the sigma matching method technique, which is the time series of OES full spectrum intensity. First, the response model of a healthy plasma spectrum was developed. Then, we defined a matching rate as an indictor for comparing the difference between the tested wafers response and the health sigma model. The experimental results showed that this proposal method can detect process faults in real-time, even in plasma etching tools. PMID:22219683

A novel approach of chemical mechanical polishing using environment-friendly slurry for mercury cadmium telluride semiconductors

PubMed Central

Zhang, Zhenyu; Wang, Bo; Zhou, Ping; Guo, Dongming; Kang, Renke; Zhang, Bi

2016-01-01

A novel approach of chemical mechanical polishing (CMP) is developed for mercury cadmium telluride (HgCdTe or MCT) semiconductors. Firstly, fixed-abrasive lapping is used to machine the MCT wafers, and the lapping solution is deionized water. Secondly, the MCT wafers are polished using the developed CMP slurry. The CMP slurry consists of mainly SiO2 nanospheres, H2O2, and malic and citric acids, which are different from previous CMP slurries, in which corrosive and toxic chemical reagents are usually employed. Finally, the polished MCT wafers are cleaned and dried by deionized water and compressed air, respectively. The novel approach of CMP is environment-friendly. Surface roughness Ra, and peak-to-valley (PV) values of 0.45, and 4.74 nm are achieved, respectively on MCT wafers after CMP. The first and second passivating processes are observed in electrochemical measurements on MCT wafers. The fundamental mechanisms of CMP are proposed according to the X-ray photoelectron spectroscopy (XPS) and electrochemical measurements. Malic and citric acids dominate the first passivating process, and the CMP slurry governs the second process. Te4+3d peaks are absent after CMP induced by the developed CMP slurry, indicating the removing of oxidized films on MCT wafers, which is difficult to achieve using single H2O2 and malic and citric acids solutions. PMID:26926622

Novel two channel self-registering integrated macro inspection tool

NASA Astrophysics Data System (ADS)

Aiyer, Arun A.; Meloni, Mark; Kueny, Andrew; Whelan, Mike

2005-05-01

After Develop Inspection (ADI) of every wafer in a lot is quite appealing, since that provides an opportunity to rework defective wafers instead of scrapping them later on. To achieve this level of inspection in manufacturing, automated macro inspection tools with higher throughput, better detection sensitivity and repeatability are needed. Moreover, such an inspector will have to be located within the Coater Developer track. To have a smaller footprint inspector, one might consider spiral-scan of the wafer surface using an off-axis illumination beam. In product wafers, one comes across Manhattan geometry with L/S patterns that are usually smaller than or comparable to the illumination wavelength. Since the reflectance of such a surface depends on the incident polarization and the pattern orientation with respect to the plane of incidence, the acquired wafer surface image will have dark and bright regions. Occurrence of this type of inhomogeneity in the surface image is referred to as the bow tie effect. The bow tie feature degrades S/N ratio of the acquired image and therefore reduces the inspector"s detection sensitivity. In this paper we will describe a macro inspection tool based on a fast spiral-scan technique that eliminates the bow tie effect by propagating the illumination beam in two orthogonal planes of incidence. In addition, by employing two counter-propagating beams, the tool is shown to have the ability to generate real time defect images that are immune to noise from die-to-die thickness variations, die-to-die alignment errors, and under layer contributions.

Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

NASA Astrophysics Data System (ADS)

Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

2015-03-01

A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

PubMed Central

Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

2015-01-01

A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing. PMID:25819285

On-chip copper-dielectric interference filters for manufacturing of ambient light and proximity CMOS sensors.

PubMed

Frey, Laurent; Masarotto, Lilian; D'Aillon, Patrick Gros; Pellé, Catherine; Armand, Marilyn; Marty, Michel; Jamin-Mornet, Clémence; Lhostis, Sandrine; Le Briz, Olivier

2014-07-10

Filter technologies implemented on CMOS image sensors for spectrally selective applications often use a combination of on-chip organic resists and an external substrate with multilayer dielectric coatings. The photopic-like and near-infrared bandpass filtering functions respectively required by ambient light sensing and user proximity detection through time-of-flight can be fully integrated on chip with multilayer metal-dielectric filters. Copper, silicon nitride, and silicon oxide are the materials selected for a technological proof-of-concept on functional wafers, due to their immediate availability in front-end semiconductor fabs. Filter optical designs are optimized with respect to specific performance criteria, and the robustness of the designs regarding process errors are evaluated for industrialization purposes.

A Manufacturing Cost and Supply Chain Analysis of SiC Power Electronics Applicable to Medium-Voltage Motor Drives

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horowitz, Kelsey; Remo, Timothy; Reese, Samantha

Wide bandgap (WBG) semiconductor devices are increasingly being considered for use in certain power electronics applications, where they can improve efficiency, performance, footprint, and, potentially, total system cost compared to systems using traditional silicon (Si) devices. Silicon carbide (SiC) devices in particular -- which are currently more mature than other WBG devices -- are poised for growth in the coming years. Today, the manufacturing of SiC wafers is concentrated in the United States, and chip production is split roughly equally between the United States, Japan, and Europe. Established contract manufacturers located throughout Asia typically carry out manufacturing of WBG powermore » modules. We seek to understand how global manufacturing of SiC components may evolve over time by illustrating the regional cost drivers along the supply chain and providing an overview of other factors that influence where manufacturing is sited. We conduct this analysis for a particular case study where SiC devices are used in a medium-voltage motor drive.« less

Control wafer bow of InGaP on 200 mm Si by strain engineering

NASA Astrophysics Data System (ADS)

Wang, Bing; Bao, Shuyu; Made, Riko I.; Lee, Kwang Hong; Wang, Cong; Eng Kian Lee, Kenneth; Fitzgerald, Eugene A.; Michel, Jurgen

2017-12-01

When epitaxially growing III-V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III-V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III-V semiconductors on large size Si substrates.

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, G.S.

1998-12-15

Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell#

PubMed Central

Poghossian, Arshak; Schumacher, Kerstin; Kloock, Joachim P.; Rosenkranz, Christian; Schultze, Joachim W.; Müller-Veggian, Mattea; Schöning, Michael J.

2006-01-01

A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor) is realised by means of integration of a specifically designed capillary electrochemical micro-droplet cell into a commercial wafer prober-station. The developed system allows the identification and selection of “good” ISFETs at the earliest stage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. The developed system is also feasible for wafer-level characterisation of ISFETs in terms of sensitivity, hysteresis and response time. Additionally, the system might be also utilised for wafer-level testing of further electrochemical sensors.

Environmentally benign processing of YAG transparent wafers

NASA Astrophysics Data System (ADS)

Yang, Yan; Wu, Yiquan

2015-12-01

Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

NASA Astrophysics Data System (ADS)

Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

2010-05-01

Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

Solid State Lighting Program (Falcon)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Meeks, Steven

2012-06-30

Over the past two years, KLA-Tencor and partners successfully developed and deployed software and hardware tools that increase product yield for High Brightness LED (HBLED) manufacturing and reduce product development and factory ramp times. This report summarizes our development effort and details of how the results of the Solid State Light Program (Falcon) have started to help HBLED manufacturers optimize process control by enabling them to flag and correct identified killer defect conditions at any point of origin in the process manufacturing flow. This constitutes a quantum leap in yield management over current practice. Current practice consists of die dispositioningmore » which is just rejection of bad die at end of process based upon probe tests, loosely assisted by optical in-line monitoring for gross process deficiencies. For the first time, and as a result of our Solid State Lighting Program, our LED manufacturing partners have obtained the software and hardware tools that optimize individual process steps to control killer defects at the point in the processes where they originate. Products developed during our two year program enable optimized inspection strategies for many product lines to minimize cost and maximize yield. The Solid State Lighting Program was structured in three phases: i) the development of advanced imaging modes that achieve clear separation between LED defect types, improves signal to noise and scan rates, and minimizes nuisance defects for both front end and back end inspection tools, ii) the creation of defect source analysis (DSA) software that connect the defect maps from back-end and front-end HBLED manufacturing tools to permit the automatic overlay and traceability of defects between tools and process steps, suppress nuisance defects, and identify the origin of killer defects with process step and conditions, and iii) working with partners (Philips Lumileds) on product wafers, obtain a detailed statistical correlation of automated defect and DSA map overlay to failed die identified using end product probe test results. Results from our two year effort have led to “automated end-to-end defect detection” with full defect traceability and the ability to unambiguously correlate device killer defects to optically detected features and their point of origin within the process. Success of the program can be measured by yield improvements at our partner’s facilities and new product orders.« less

Thermo-acousto-photonics for noncontact temperature measurement in silicon wafer processing

NASA Astrophysics Data System (ADS)

Suh, Chii-Der S.; Rabroker, G. Andrew; Chona, Ravinder; Burger, Christian P.

1999-10-01

A non-contact thermometry technique has been developed to characterize the thermal state of silicon wafers during rapid thermal processing. Information on thermal variations is obtained from the dispersion relations of the propagating waveguide mode excited in wafers using a non-contact, broadband optical system referred to as Thermal Acousto- Photonics for Non-Destructive Evaluation. Variations of thermo-mechanical properties in silicon wafers are correlated to temperature changes by performing simultaneous time-frequency analyses on Lamb waveforms acquired with a fiber-tip interferometer sensor. Experimental Lamb wave data collected for cases ranging from room temperature to 400 degrees C is presented. The results show that the temporal progressions of all spectral elements found in the fundamental antisymmetric mode are strong functions of temperature. This particular attribute is exploited to achieve a thermal resolution superior to the +/- 5 degrees C attainable through current pyrometric techniques. By analyzing the temperature-dependent group velocity of a specific frequency component over the temperature range considered and then comparing the results to an analytical model developed for silicon wafers undergoing annealing, excellent agreement was obtained. Presented results demonstrate the feasibility of applying laser-induced stress waves as a temperature diagnostic during rapid thermal processing.

Model based high NA anamorphic EUV RET

NASA Astrophysics Data System (ADS)

Jiang, Fan; Wiaux, Vincent; Fenger, Germain; Clifford, Chris; Liubich, Vlad; Hendrickx, Eric

2018-03-01

With the announcement of the extension of the Extreme Ultraviolet (EUV) roadmap to a high NA lithography tool that utilizes anamorphic optics design, an investigation of design tradeoffs unique to the imaging of anamorphic lithography tool is shown. An anamorphic optical proximity correction (OPC) solution has been developed that models fully the EUV near field electromagnetic effects and the anamorphic imaging using the Domain Decomposition Method (DDM). Clips of imec representative for the N3 logic node were used to demonstrate the OPC solutions on critical layers that will benefit from the increased contrast at high NA using anamorphic imaging. However, unlike isomorphic case, from wafer perspective, OPC needs to treat x and y differently. In the paper, we show a design trade-off seen unique to Anamorphic EUV, namely that using a mask rule of 48nm (mask scale), approaching current state of the art, limitations are observed in the available correction that can be applied to the mask. The metal pattern has a pitch of 24nm and CD of 12nm. During OPC, the correction of the metal lines oriented vertically are being limited by the mask rule of 12nm 1X. The horizontally oriented lines do not suffer from this mask rule limitation as the correction is allowed to go to 6nm 1X. For this example, the masks rules will need to be more aggressive to allow complete correction, or design rules and wafer processes (wafer rotation) would need to be created that utilize the orientation that can image more aggressive features. When considering VIA or block level correction, aggressive polygon corner to corner designs can be handled with various solutions, including applying a 45 degree chop. Multiple solutions are discussed with the metrics of edge placement error (EPE) and Process Variation Bands (PVBands), together with all the mask constrains. Noted in anamorphic OPC, the 45 degree chop is maintained at the mask level to meet mask manufacturing constraints, but results in skewed angle edge in wafer level correction. In this paper, we used both contact (Via/block) patterns and metal patterns for OPC practice. By comparing the EPE of horizontal and vertical patterns with a fixed mask rule check (MRC), and the PVBand, we focus on the challenges and the solutions of OPC with anamorphic High-NA lens.

AutoMOPS- B2B and B2C in mask making: Mask manufacturing performance and customer satisfaction improvement through better information flow management using generic models and standardized languages

NASA Astrophysics Data System (ADS)

Filies, Olaf; de Ridder, Luc; Rodriguez, Ben; Kujiken, Aart

2002-03-01

Semiconductor manufacturing has become a global business, in which companies of different size unite in virtual enterprises to meet new opportunities. Therefore Mask manufacturing is a key business, but mask ordering is a complex process and is always critical regarding design to market time, even though mask complexity and customer base are increasing using a wide variety of different mask order forms which are frequently faulty and very seldom complete. This is effectively blocking agile manufacturing and can tie wafer fabs to a single mask The goal of the project is elimination of the order verification through paperless, electronically linked information sharing/exchange between chip design, mask production and production stages, which will allow automation of the mask preparation. To cover these new techniques and their specifications as well as the common ones with automated tools a special generic Meta-model will be generated, based on the current standards for mask specifications, including the requirements from the involved partners (Alcatel Microelectronics, Altis, Compugraphics, Infineon, Nimble, Sigma-C), the project works out a pre-normative standard. The paper presents the current status of work. This work is partly funded by the Commission of the European Union under the Fifth Framework project IST-1999-10332 AutoMOPS.

Advanced FTIR technology for the chemical characterization of product wafers

NASA Astrophysics Data System (ADS)

Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

2001-01-01

Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers.

Micro-Raman spectroscopy as a tool for the characterization of silicon carbide in power semiconductor material processing

NASA Astrophysics Data System (ADS)

De Biasio, M.; Kraft, M.; Schultz, M.; Goller, B.; Sternig, D.; Esteve, R.; Roesner, M.

2017-05-01

Silicon carbide (SiC) is a wide band-gap semi-conductor material that is used increasingly for high voltage power devices, since it has a higher breakdown field strength and better thermal conductivity than silicon. However, in particular its hardness makes wafer processing difficult and many standard semi-conductor processes have to be specially adapted. We measure the effects of (i) mechanical processing (i.e. grinding of the backside) and (ii) chemical and thermal processing (i.e. doping and annealing), using confocal microscopy to measure the surface roughness of ground wafers and micro-Raman spectroscopy to measure the stresses induced in the wafers by grinding. 4H-SiC wafers with different dopings were studied before and after annealing, using depth-resolved micro-Raman spectroscopy to observe how doping and annealing affect: i.) the damage and stresses induced on the crystalline structure of the samples and ii.) the concentration of free electrical carriers. Our results show that mechanical, chemical and thermal processing techniques have effects on this semiconductor material that can be observed and characterized using confocal microscopy and high resolution micro Raman spectroscopy.

Positioning performance of a maglev fine positioning system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wronosky, J.B.; Smith, T.G.; Jordan, J.D.

1996-12-01

A wafer positioning system was recently developed by Sandia National Laboratories for an Extreme Ultraviolet Lithography (EUVL) research tool. The system, which utilizes a magnetically levitated fine stage to provide ultra-precise positioning in all six degrees of freedom, incorporates technological improvements resulting from four years of prototype development experience. System enhancements, implemented on a second generation design for an ARPA National Center for Advanced Information Component Manufacturing (NCAICM) project, introduced active structural control for the levitated structure of the system. Magnetic levitation (maglev) is emerging as an important technology for wafer positioning systems in advanced lithography applications. The advantages ofmore » maglev stem from the absence of physical contact. The resulting lack of friction enables accurate, fast positioning. Maglev systems are mechanically simple, accomplishing full six degree-of-freedom suspension and control with a minimum of moving parts. Power-efficient designs, which reduce the possibility of thermal distortion of the platen, are achievable. Manufacturing throughput will be improved in future systems with the addition of active structural control of the positioning stages. This paper describes the design, implementation, and functional capability of the maglev fine positioning system. Specifics regarding performance design goals and test results are presented.« less

a Study of Oxygen Precipitation in Heavily Doped Silicon.

NASA Astrophysics Data System (ADS)

Graupner, Robert Kurt

Gettering of impurities with oxygen precipitates is widely used during the fabrication of semiconductors to improve the performance and yield of the devices. Since the effectiveness of the gettering process is largely dependent on the initial interstitial oxygen concentration, accurate measurements of this parameter are of considerable importance. Measurements of interstitial oxygen following thermal cycles are required for development of semiconductor fabrication processes and for research into the mechanisms of oxygen precipitate nucleation and growth. Efforts by industrial associations have led to the development of standard procedures for the measurement of interstitial oxygen in wafers. However practical oxygen measurements often do not satisfy the requirements of such standard procedures. An additional difficulty arises when the silicon wafer has a low resitivity (high dopant concentration). In such cases the infrared light used for the measurement is severely attenuated by the electrons of holes introduced by the dopant. Since such wafers are the substrates used for the production of widely used epitaxial wafers, this measurement problem is economically important. Alternative methods such as Secondary Ion Mass Spectroscopy or Gas Fusion Analysis have been developed to measure oxygen in these cases. However, neither of these methods is capable of distinguishing interstitial oxygen from precipitated oxygen as required for precipitation studies. In addition to the commercial interest in heavily doped silicon substrates, they are also of interest for research into the role of point defects in nucleation and precipitation processes. Despite considerable research effort, there is still disagreement concerning the type of point defect and its role in semiconductor processes. Studies of changes in the interstitial oxygen concentration of heavily doped and lightly doped silicon wafers could help clarify the role of point defects in oxygen nucleation and precipitation processes. This could lead to more effective control and use of oxygen precipitation for gettering. One of the principal purposes of this thesis is the extension of the infrared interstitial oxygen measurement technique to situations outside the measurement capacities of the standard technique. These situations include silicon slices exhibiting interfering precipitate absorption bands and heavily doped n-type silicon wafers. A new method is presented for correcting for the effect of multiple reflections in silicon wafers with optically rough surfaces. The technique for the measurement of interstitial oxygen in heavily doped n-type wafers is then used to perform a comparative study of oxygen precipitation in heavily antimony doped (.035 ohm-cm) silicon and lightly doped p-type silicon. A model is presented to quantitatively explain the observed suppression of defect formation in heavily doped n-type wafers.

In-Line Monitoring of Fab Processing Using X-Ray Diffraction

NASA Astrophysics Data System (ADS)

Gittleman, Bruce; Kozaczek, Kris

2005-09-01

As the materials shift that started with Cu continues to advance in the semiconductor industry, new issues related to materials microstructure have arisen. While x-ray diffraction (XRD) has long been used in development applications, in this paper we show that results generated in real time by a unique, high throughput, fully automated XRD metrology tool can be used to develop metrics for qualification and monitoring of critical processes in current and future manufacturing. It will be shown that these metrics provide a unique set of data that correlate to manufacturing issues. For example, ionized-sputtering is the current deposition method of choice for both the Cu seed and TaNx/Ta barrier layers. The alpha phase of Ta is widely used in production for the upper layer of the barrier stack, but complete elimination of the beta phase requires a TaNx layer with sufficient N content, but not so much as to start poisoning the target and generating particle issues. This is a well documented issue, but traditional monitoring by sheet resistance methods cannot guarantee the absence of the beta phase, whereas XRD can determine the presence of even small amounts of beta. Nickel silicide for gate metallization is another example where monitoring of phase is critical. As well being able to qualify an anneal process that gives only the desired NiSi phase everywhere across the wafer, XRD can be used to determine if full silicidation of the Ni has occurred and characterize the crystallographic microstructure of the Ni to determine any effect of that microstructure on the anneal process. The post-anneal nickel silicide phase and uniformity of the silicide microstructure can all be monitored in production. Other examples of the application of XRD to process qualification and production monitoring are derived from the dependence of certain processes, some types of defect generation, and device performance on crystallographic texture. The data presented will show that CMP dishing problems could be traced to texture of the barrier layer and mitigated by adjusting the barrier process. The density of pits developed during CMP of electrochemically deposited (ECD) Cu depends on the fraction of (111) oriented grains. It must be emphasized that the crystallographic texture is not only a key parameter for qualification of high yielding and reliable processes, but also serves as a critical parameter for monitoring tool health. The texture of Cu and W are sensitive not only to deviations in performance of the tool depositing or annealing a particular film, but also highly sensitive to the texture of the barrier underlayers and thus any performance deviations in those tools. The XRD metrology tool has been designed with production monitoring in mind and has been fully integrated into both 200 mm and 300 mm fabs. Rapid analysis is achieved by using a high intensity fixed x-ray source, coupled with a large area 2D detector. The output metrics from one point are generated while the tool is measuring a subsequent point, giving true on-the-fly analysis; no post-processing of data is necessary. Spatial resolution on the wafer surface ranging from 35 μm to 1 mm is available, making the tool suitable for monitoring of product wafers. Typical analysis times range from 10 seconds to 2 minutes per point, depending on the film thickness and spot size. Current metrics used for process qualification and production monitoring are phase, FWHM of the primary phase peaks (for mean grain size tracking), and crystallographic texture.

Driving imaging and overlay performance to the limits with advanced lithography optimization

NASA Astrophysics Data System (ADS)

Mulkens, Jan; Finders, Jo; van der Laan, Hans; Hinnen, Paul; Kubis, Michael; Beems, Marcel

2012-03-01

Immersion lithography is being extended to 22-nm and even below. Next to generic scanner system improvements, application specific solutions are needed to follow the requirements for CD control and overlay. Starting from the performance budgets, this paper discusses how to improve (in volume manufacturing environment) CDU towards 1-nm and overlay towards 3-nm. The improvements are based on deploying the actuator capabilities of the immersion scanner. The latest generation immersion scanners have extended the correction capabilities for overlay and imaging, offering freeform adjustments of lens, illuminator and wafer grid. In order to determine the needed adjustments the recipe generation per user application is based on a combination wafer metrology data and computational lithography methods. For overlay, focus and CD metrology we use an angle resolved optical scatterometer.

Status, technology and development of silicon solar cells at INER

NASA Astrophysics Data System (ADS)

Jao, S. S.; Tseng, H. H.; Cheng, C.; Tzeng, Y. C.; Chang, H. H.; Hwang, H. L.

Test runs using 200 5-cm-diameter silicon wafers are carried out, yielding 87% with an AM1 conversion efficiency greater than 11.5%. The highest efficiency is 12.7%. Concentrator solar cells of 2 x 2 sq cm are made with an AM1 efficiency of 14%. Solar cells with a diameter of 7.5 cm have attained AM1 efficiencies of more than 11.3%, and texturized solar cells of the same diameter fabricated from rejected wafers show AM1 efficiencies of 9.5-10.5%. It is noted that solar panels comprising 68 cells with a maximum output power of 13.5 W have been manufactured. The results of a 6-month test of a photovoltaic charge station for electric motorcycles are reported.

Heterogeneous integration based on low-temperature bonding for advanced optoelectronic devices

NASA Astrophysics Data System (ADS)

Higurashi, Eiji

2018-04-01

Heterogeneous integration is an attractive approach to manufacturing future optoelectronic devices. Recent progress in low-temperature bonding techniques such as plasma activation bonding (PAB) and surface-activated bonding (SAB) enables a new approach to integrating dissimilar materials for a wide range of photonics applications. In this paper, low-temperature direct bonding and intermediate layer bonding techniques are focused, and their state-of-the-art applications in optoelectronic devices are reviewed. First, we describe the room-temperature direct bonding of Ge/Ge and Ge/Si wafers for photodetectors and of GaAs/SiC wafers for high-power semiconductor lasers. Then, we describe low-temperature intermediate layer bonding using Au and lead-free Sn-3.0Ag-0.5Cu solders for optical sensors and MEMS packaging.

Quantification Of 4H- To 3C-Polymorphism In Silicon Carbide (SiC) Epilayers And An Investigation Of Recombination-Enhanced Dislocation Motion In SiC By Optical Emission Microscopy (Oem) Techniques

NASA Technical Reports Server (NTRS)

Speer, Kevin M.

2004-01-01

Environments that impose operational constraints on conventional silicon-(Si) based semiconductor devices frequently appear in military- and space-grade applications. These constraints include high temperature, high power, and high radiation environments. Silicon carbide (SiC), an alternative type of semiconductor material, has received abundant research attention in the past few years, owing to its radiation-hardened properties as well as its capability to withstand high temperatures and power levels. However, the growth and manufacture of SiC devices is still comparatively immature, and there are severe limitations in present crystal growth and device fabrication processes. Among these limitations is a variety of crystal imperfections known as defects. These imperfections can be point defects (e.g., vacancies and interstitials), line defects (e.g., edge and screw dislocations), or planar defects (e.g., stacking faults and double-positioning boundaries). All of these defects have been experimentally shown to be detrimental to the performance of electron devices made from SiC. As such, it is imperative that these defects are significantly reduced in order for SiC devices to become a viable entity in the electronics world. The NASA Glenn High Temperature Integrated Electronics & Sensors Team (HTIES) is working to identify and eliminate these defects in SiC by implementing improved epitaxial crystal growth procedures. HTIES takes two-inch SiC wafers and etches patterns, producing thousands of mesas into each wafer. Crystal growth is then carried out on top of these mesas in an effort to produce films of improved quality-resulting in electron devices that demonstrate superior performance-as well as fabrication processes that are cost-effective, reliable, and reproducible. In this work, further steps are taken to automate HTIES' SiC wafer inspection system. National Instruments LabVIEW image processing and pattern recognition routines are developed that are capable of quantifying and mapping defects on both the substrate and mesa surfaces, and of quantifying polymorphic changes in the grown materials. In addition, an optical emission microscopy (OEM) system is developed that will facilitate comprehensive study of recombination-enhanced dislocation motion (REDM).

Multijunction high-voltage solar cell

NASA Technical Reports Server (NTRS)

Evans, J. C., Jr.; Goradia, C.; Chai, A. T.

1981-01-01

Multijunction cell allows for fabrication of high-voltage solar cell on single semiconductor wafer. Photovoltaic energy source using cell is combined on wafer with circuit it is to power. Cell consists of many voltage-generating regions internally or externally interconnected to give desired voltage and current combination. For computer applications, module is built on silicon wafer with energy for internal information processing and readouts derived from external light source.

Hybrid enabled thin film metrology using XPS and optical

NASA Astrophysics Data System (ADS)

Vaid, Alok; Iddawela, Givantha; Mahendrakar, Sridhar; Lenahan, Michael; Hossain, Mainul; Timoney, Padraig; Bello, Abner F.; Bozdog, Cornel; Pois, Heath; Lee, Wei Ti; Klare, Mark; Kwan, Michael; Kang, Byung Cheol; Isbester, Paul; Sendelbach, Matthew; Yellai, Naren; Dasari, Prasad; Larson, Tom

2016-03-01

Complexity of process steps integration and material systems for next-generation technology nodes is reaching unprecedented levels, the appetite for higher sampling rates is on the rise, while the process window continues to shrink. Current thickness metrology specifications reach as low as 0.1A for total error budget - breathing new life into an old paradigm with lower visibility for past few metrology nodes: accuracy. Furthermore, for advance nodes there is growing demand to measure film thickness and composition on devices/product instead of surrogate planar simpler pads. Here we extend our earlier work in Hybrid Metrology to the combination of X-Ray based reference technologies (high performance) with optical high volume manufacturing (HVM) workhorse metrology (high throughput). Our stated goal is: put more "eyes" on the wafer (higher sampling) and enable move to films on pattern structure (control what matters). Examples of 1X front-end applications are used to setup and validate the benefits.

Optical proximity correction for anamorphic extreme ultraviolet lithography

NASA Astrophysics Data System (ADS)

Clifford, Chris; Lam, Michael; Raghunathan, Ananthan; Jiang, Fan; Fenger, Germain; Adam, Kostas

2017-10-01

The change from isomorphic to anamorphic optics in high numerical aperture extreme ultraviolet scanners necessitates changes to the mask data preparation flow. The required changes for each step in the mask tape out process are discussed, with a focus on optical proximity correction (OPC). When necessary, solutions to new problems are demonstrated and verified by rigorous simulation. Additions to the OPC model include accounting for anamorphic effects in the optics, mask electromagnetics, and mask manufacturing. The correction algorithm is updated to include awareness of anamorphic mask geometry for mask rule checking. OPC verification through process window conditions is enhanced to test different wafer scale mask error ranges in the horizontal and vertical directions. This work will show that existing models and methods can be updated to support anamorphic optics without major changes. Also, the larger mask size in the Y direction can result in better model accuracy, easier OPC convergence, and designs that are more tolerant to mask errors.

Impedance-based structural health monitoring of additive manufactured structures with embedded piezoelectric wafers

NASA Astrophysics Data System (ADS)

Scheyer, Austin G.; Anton, Steven R.

2017-04-01

Embedding sensors within additive manufactured (AM) structures gives the ability to develop smart structures that are capable of monitoring the mechanical health of a system. AM provides an opportunity to embed sensors within a structure during the manufacturing process. One major limitation of AM technology is the ability to verify the geometric and material properties of fabricated structures. Over the past several years, the electromechanical impedance (EMI) method for structural health monitoring (SHM) has been proven to be an effective method for sensing damage in structurers. The EMI method utilizes the coupling between the electrical and mechanical properties of a piezoelectric transducer to detect a change in the dynamic response of a structure. A piezoelectric device, usually a lead zirconate titanate (PZT) ceramic wafer, is bonded to a structure and the electrical impedance is measured across as range of frequencies. A change in the electrical impedance is directly correlated to changes made to the mechanical condition of the structure. In this work, the EMI method is employed on piezoelectric transducers embedded inside AM parts to evaluate the feasibility of performing SHM on parts fabricated using additive manufacturing. The fused deposition modeling (FDM) method is used to print specimens for this feasibility study. The specimens are printed from polylactic acid (PLA) in the shape of a beam with an embedded monolithic piezoelectric ceramic disc. The specimen is mounted as a cantilever while impedance measurements are taken using an HP 4194A impedance analyzer. Both destructive and nondestructive damage is simulated in the specimens by adding an end mass and drilling a hole near the free end of the cantilever, respectively. The Root Mean Square Deviation (RMSD) method is utilized as a metric for quantifying damage to the system. In an effort to determine a threshold for RMSD, the values are calculated for the variation associated with taking multiple measurements and with re-clamping the cantilever, and determined to be 0.154, and 3.125 respectively. The RMSD value of the cantilever with a 400 g end mass is 11.39, and the RMSD value of the cantilever with a 4 mm hole near the end is 12.15. From these results, it can be determined that the damaged cases have much higher RMSD values than the RMSD values associated with measurements and set up variability of the healthy structure.

Programmable 2-D Addressable Cryogenic Aperture Masks

NASA Technical Reports Server (NTRS)

Kutyrev, A. S.; Moseley, S. H.; Jhabvala, M.; Li, M.; Schwinger, D. S.; Silverberg, R. F.; Wesenberg, R. P.

2004-01-01

We are developing a two-dimensional array of square microshutters (programmable aperture mask) for a multi-object spectrometer for the James Webb Space Telescope (JWST). This device will provide random access selection of the areas in the field to be studied. The device is in essence a close packed array of square slits, each of which can be opened independently to select areas of the sky for detailed study.The device is produced using a 100-micron thick silicon wafer as a substrate with 0.5-micron thick silicon nitride shutters on top of it. Silicon nitride has been selected as the blade and flexure material because its stiffness allows thinner and lighter structures than single crystal Si, the chief alternative, and because of its ease of manufacture. The 100 micron silicon wafer is backetched in a high aspect ratio Deep Reactive Ion Etching (Deep RIE) to leave only a support grid for the shutters and the address electronics. The shutter actuation is done magnetically whereas addressing is electrostatic. 128x128 format microshutter arrays have been produced. Their operation has been demostarted on 32x32 subarrays. Good reliability of the fabrication process and good quality of the microshutters has been achieved. The mechanical behavior and optical performance of the fabricated arrays at cryogenic temperature are being studied.

Progress and challenges for cost effective kerfless Silicon crystal growth for PV application

NASA Astrophysics Data System (ADS)

Serra, J. M.; Alves, J. Maia; Vallera, A. M.

2017-06-01

The major barrier for PV penetration is cost. And the single most important cost factor in silicon technology is the wafer (≈35% of the module cost). Although tremendous progress on cell processing has been reported in recent years, a much smaller evolution is seen on what should be the key point to address - the wafer. The ingot-slicing process is reaching its limits as the wafer thickness is reduced in an effort to lower material costs. Kerf losses of ≈50% and an increase in breakage of a high value added material are putting a lower bound to this approach. New ideas are therefore needed for producing wafers in a way to overcome these limitations. In this paper we present three new concepts being developed in our laboratory that have one thing in common: they all are zero kerf loss processes, aiming at significant reductions in material loss. One explores the concept of exfoliation, the other two aim at the growth of silicon directly into ribbons. These were conceived as continuous processes, based on a floating molten zone concept, to avoid impurity contamination during crystallization.

Semiconductor P-I-N detector

DOEpatents

Sudharsanan, Rengarajan; Karam, Nasser H.

2001-01-01

A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

Modular packaging concept for MEMS and MOEMS

NASA Astrophysics Data System (ADS)

Stenchly, Vanessa; Reinert, Wolfgang; Quenzer, Hans-Joachim

2017-11-01

Wherever technical systems detect objects in their environment or interact with people, optical devices may play an important role. Light can be relatively easily produced and spatially and temporally modulated. Laser can project sharp images over long distances or cut materials in short distances. Depending on the wavelength an invisible scanning in near infrared for gesture recognition is possible as well as a projection of brilliant colour images. For several years, the Fraunhofer ISIT develops Opto-Packaging processes based on the viscous reshaping of glass wafers: First, hermetically sealed laser micro-mirror scanners WLP with inclined windows deflect in the central light reflex of the window out of the image area. Second, housing with lateral light exit permits hermetic sealing of edge-emitting lasers for highest reliability and durability. Such systems are currently experiencing an extremely high interest of the industry in all segments, from consumer to automotive through to materials processing. Our modular Opto-Packaging platform enables fast product developments. Housing for opto mechanical MEMS devices are equipped with inclined windows to minimize distortion, stray light and reflection losses. The hot viscous glass forming technology is also applied to functionalized substrate wafers which possess areas with high heat dissipation in addition to thermally insulating areas. Electrical contacts may be realized with metal filled vias or TGV (Through Glass Vias). The modular system reduces the development times for new, miniaturized optical systems so that manufacturers can focus on the essentials in their development, namely their product functionalities.

HVM die yield improvement as a function of DRSEM ADC

NASA Astrophysics Data System (ADS)

Maheshwary, Sonu; Haas, Terry; McGarvey, Steve

2010-03-01

Given the current manufacturing technology roadmap and the competitiveness of the global semiconductor manufacturing environment in conjunction with the semiconductor manufacturing market dynamics, the market place continues to demand a reduced die manufacturing cost. This continuous pressure on lowering die cost in turn drives an aggressive yield learning curve, a key component of which is defect reduction of manufacturing induced anomalies. In order to meet and even exceed line and die yield targets there is a need to revamp defect classification strategies and place a greater emphasize on increasing the accuracy and purity of the Defect Review Scanning Electron Microscope (DRSEM) Automated Defect Classification (ADC) results while placing less emphasis on the ADC results of patterned/un-patterned wafer inspection systems. The increased emphasis on DRSEM ADC results allows for a high degree of automation and consistency in the classification data and eliminates variance induced by the manufacturing staff. This paper examines the use of SEM based Auto Defect Classification in a high volume manufacturing environment as a key driver in the reduction of defect limited yields.

Design for manufacturability production management activity report

NASA Astrophysics Data System (ADS)

Miyazaki, Norihiko; Sato, T.; Honma, M.; Yoshioka, N.; Hosono, K.; Onodera, T.; Itoh, H.; Suzuki, H.; Uga, T.; Kadota, K.; Iriki, N.

2006-05-01

Design For Manufacturability Production Management (DFM-PM) Subcommittee has been started in succession to Reticle Management Subcommittee (RMS) in Semiconductor Manufacturing Technology Committee for Japan (SMTCJ) from 2005. Our activity focuses on the SoC (System On Chip) Business, and it pursues the improvement of communication in manufacturing technique. The first theme of activity is the investigation and examination of the new trends about production (manufacturer) technology and related information, and proposals of business solution. The second theme is the standardization activity about manufacture technology and the cooperation with related semiconductors' organizations. And the third theme is holding workshop and support for promotion and spread of the standardization technology throughout semiconductor companies. We expand a range of scope from design technology to wafer pattern reliability and we will propose the competition domain, the collaboration area and the standardization technology on DFM. Furthermore, we will be able to make up a SoC business model as the 45nm node technology beyond manufacturing platform in cooperating with the design information and the production information by utilizing EDA technology.

Noncontact Measurement of Doping Profile for Bare Silicon

NASA Astrophysics Data System (ADS)

Kohno, Motohiro; Matsubara, Hideaki; Okada, Hiroshi; Hirae, Sadao; Sakai, Takamasa

1998-10-01

In this study, we evaluate the doping concentrations of bare silicon wafers by noncontact capacitance voltage (C V) measurements. The metal-air-insulator-semiconductor (MAIS) method enables the measurement of C V characteristics of silicon wafers without oxidation and electrode preparation. This method has the advantage that a doping profile close to the wafer surface can be obtained. In our experiment, epitaxial silicon wafers were used to compare the MAIS method with the conventional MIS method. The experimental results obtained from the two methods showed good agreement. Then, doping profiles of boron-doped Czochralski (CZ) wafers were measured by the MAIS method. The result indicated a significant reduction of the doping concentration near the wafer surface. This observation is attributed to the well-known deactivation of boron with atomic hydrogen which permeated the silicon bulk during the polishing process. This deactivation was recovered by annealing in air at 180°C for 120 min.

The reverse laser drilling of transparent materials

NASA Technical Reports Server (NTRS)

Anthony, T. R.; Lindner, P. A.

1980-01-01

Within a limited range of incident laser-beam intensities, laser drilling of a sapphire wafer initiates on the surface of the wafer where the laser beam exits and proceeds upstream in the laser beam to the surface where the laser beam enters the wafer. This reverse laser drilling is the result of the constructive interference between the laser beam and its reflected component on the exit face of the wafer. Constructive interference occurs only at the exit face of the sapphire wafer because the internally reflected laser beam suffers no phase change there. A model describing reverse laser drilling predicts the ranges of incident laser-beam intensity where no drilling, reverse laser drilling, and forward laser drilling can be expected in various materials. The application of reverse laser drilling in fabricating feed-through conductors in silicon-on-sapphire wafers for a massively parallel processer is described.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jankowski, A.F.; Hayes, J.P.; Kanna, R.L.

The formation of high energy density, storage devices is achievable using composite material systems. Alternate layering of carbon aerogel wafers and Ni foils with rnicroporous separators is a prospective composite for capacitor applications. An inherent problem exists to form a physical bond between Ni and the porous carbon wafer. The bonding process must be limited to temperatures less than 1000{degrees}C, at which point the aerogel begins to degrade. The advantage of a low temperature eutectic in the Ni-Ti alloy system solves this problem. Ti, a carbide former, is readily adherent as a sputter deposited thin film onto the carbon wafer.more » A vacuum bonding process is then used to join the Ni foil and Ti coating through eutectic phase formation. The parameters required for successfld bonding are described along with a structural characterization of the Ni foil-carbon aerogel wafer interface.« less

Surface etching technologies for monocrystalline silicon wafer solar cells

NASA Astrophysics Data System (ADS)

Tang, Muzhi

With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

Hybrid Integration of III-V Solar Microcells for High Efficiency Concentrated Photovoltaic Modules

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tauke-Pedretti, Anna; Cederberg, Jeffery; Cruz-Campa, Jose Luis

The design, fabrication and performance of InGaAs and InGaP/GaAs microcells are presented. These cells are integrated with a Si wafer providing a path for insertion in hybrid concentrated photovoltaic modules. Comparisons are made between bonded cells and cells fabricated on their native wafer. The bonded cells showed no evidence of degradation in spite of the integration process which involved significant processing including the removal of the III-V substrate. Results from a number of hybrid cell configurations were reported. These cells employed integration techniques including wafer level bonding of processed cells and solder bonding of the cells. Lastly, the cells themselvesmore » showed evidence of degradation in spite of the integration process, which involved significant processing including the removal of the III-V substrate.« less

Hybrid Integration of III-V Solar Microcells for High Efficiency Concentrated Photovoltaic Modules

DOE PAGES

Tauke-Pedretti, Anna; Cederberg, Jeffery; Cruz-Campa, Jose Luis; ...

2018-03-09

The design, fabrication and performance of InGaAs and InGaP/GaAs microcells are presented. These cells are integrated with a Si wafer providing a path for insertion in hybrid concentrated photovoltaic modules. Comparisons are made between bonded cells and cells fabricated on their native wafer. The bonded cells showed no evidence of degradation in spite of the integration process which involved significant processing including the removal of the III-V substrate. Results from a number of hybrid cell configurations were reported. These cells employed integration techniques including wafer level bonding of processed cells and solder bonding of the cells. Lastly, the cells themselvesmore » showed evidence of degradation in spite of the integration process, which involved significant processing including the removal of the III-V substrate.« less

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, Gary S.

1998-01-01

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

NASA Astrophysics Data System (ADS)

Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

2016-08-01

Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

NASA Technical Reports Server (NTRS)

Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.;

Evaluation and verification of epitaxial process sequence for silicon solar-cell production

NASA Technical Reports Server (NTRS)

Redfield, D.

1981-01-01

To achieve the program goals, 28 minimodules were fabricated and tested, using 600 cells made from three-inch-diameter wafers processed by the sequence chosen for this purpose. Of these 600 cells, half were made from epitaxially grown layers on potentially low-cost substrates. The other half were made from commercial semiconductor-grade (SG), single-crystal silicon wafers that served as controls. Cell processing was normally performed on mixed lots containing significant numbers of each of these two types of wafers. After evaluation of the performance of all cells, they were separated by types for incorporation into modules that were to be tested for electrical performance and response to environmental stress. A simplified flow chart displaying this scheme, for quantities representing half of the planned total to be processed, is presented.

Optima XE Single Wafer High Energy Ion Implanter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Satoh, Shu; Ferrara, Joseph; Bell, Edward

2008-11-03

The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowingmore » the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.« less

The Novel Preparation of P-N Junction Mesa Diodes by Silicon-Wafer Direct Bonding (SDB)

NASA Astrophysics Data System (ADS)

Yeh, Ching-Fa; Hwangleu, Shyang

1992-05-01

The key processes of silicon-wafer direct bonding (SDB), including hydrophilic surface formation and optimal two-step heat treatment, have been developed However, H2SO4/H2O2 solution being a strong oxidized acid solution, native oxide is found to have grown on the wafer surface as soon as a wafer is treated in this solution. In the case of a wafer further treated in diluted HF solution after hydrophilic surface formation, it is shown that the wafer surface can not only be cleaned of its native oxide but also remains hydrophilic, and can provide excellent voidless bonding. The N+/P and N/P combination junction mesa diodes fabricated on the wafers prepared by these novel SDB technologies are examined. The ideality factor n of the N/P mesa diode is 2.4˜2.8 for the voltage range 0.2˜0.3 V; hence, the lowering of the ideality factor n is evidently achieved. As for the N+/P mesa diode, the ideality factor n shows a value of 1.10˜1.30 for the voltage range 0.2˜0.6 V; the low value of n is attributed to an autodoping phenomenon which has caused the junction interface to form in the P-silicon bulk. However, the fact that the sustaining voltage of the N/P mesa diode showed a value greater than 520 V reveals the effectiveness of our novel SDB processes.

Device overlay method for high volume manufacturing

NASA Astrophysics Data System (ADS)

Lee, Honggoo; Han, Sangjun; Kim, Youngsik; Kim, Myoungsoo; Heo, Hoyoung; Jeon, Sanghuck; Choi, DongSub; Nabeth, Jeremy; Brinster, Irina; Pierson, Bill; Robinson, John C.

2016-03-01

Advancing technology nodes with smaller process margins require improved photolithography overlay control. Overlay control at develop inspection (DI) based on optical metrology targets is well established in semiconductor manufacturing. Advances in target design and metrology technology have enabled significant improvements in overlay precision and accuracy. One approach to represent in-die on-device as-etched overlay is to measure at final inspection (FI) with a scanning electron microscope (SEM). Disadvantages to this approach include inability to rework, limited layer coverage due to lack of transparency, and higher cost of ownership (CoO). A hybrid approach is investigated in this report whereby infrequent DI/FI bias is characterized and the results are used to compensate the frequent DI overlay results. The bias characterization is done on an infrequent basis, either based on time or triggered from change points. On a per-device and per-layer basis, the optical target overlay at DI is compared with SEM on-device overlay at FI. The bias characterization results are validated and tracked for use in compensating the DI APC controller. Results of the DI/FI bias characterization and sources of variation are presented, as well as the impact on the DI correctables feeding the APC system. Implementation details in a high volume manufacturing (HVM) wafer fab will be reviewed. Finally future directions of the investigation will be discussed.

New low-cost high heat flux source

NASA Astrophysics Data System (ADS)

Cheng, Dah Yu

1993-11-01

Intense heat sources are needed to address new manufacturing techniques, such as, the Rapid Thermal Process for silicon wafer manufacturing. The current technology of high heat flux sources is the laser for its ability to do welding and cutting is well-known. The laser with its coherent radiation allows an image to be focused down to very small sizes to reach extremely high heat flux. But the laser also has problems: it is inefficient in its use because of its singular wave length and brings up OSHA safety related problems. Also heavy industrial manufacturing requires much higher total energy in addition to the high heat flux which makes the current laser system too slow to be economical. The system I am proposing starts with a parabolic curve. If the curve is rotated about the axis of the parabola, it generates the classical parabolic reflector as we know it. On the other hand, when the curve is rotated about the chord, a line passing through the focal point and perpendicular to the axis, generates a new surface called the Orthogonal Parabolic Surface. A new optical reflector geometry is presented which integrates a linear white light (continuum spectra) source through a coherent path to be focused to a very small area.

Pressure activated interconnection of micro transfer printed components

NASA Astrophysics Data System (ADS)

Prevatte, Carl; Guven, Ibrahim; Ghosal, Kanchan; Gomez, David; Moore, Tanya; Bonafede, Salvatore; Raymond, Brook; Trindade, António Jose; Fecioru, Alin; Kneeburg, David; Meitl, Matthew A.; Bower, Christopher A.

2016-05-01

Micro transfer printing and other forms of micro assembly deterministically produce heterogeneously integrated systems of miniaturized components on non-native substrates. Most micro assembled systems include electrical interconnections to the miniaturized components, typically accomplished by metal wires formed on the non-native substrate after the assembly operation. An alternative scheme establishing interconnections during the assembly operation is a cost-effective manufacturing method for producing heterogeneous microsystems, and facilitates the repair of integrated microsystems, such as displays, by ex post facto addition of components to correct defects after system-level tests. This letter describes pressure-concentrating conductor structures formed on silicon (1 0 0) wafers to establish connections to preexisting conductive traces on glass and plastic substrates during micro transfer printing with an elastomer stamp. The pressure concentrators penetrate a polymer layer to form the connection, and reflow of the polymer layer bonds the components securely to the target substrate. The experimental yield of series-connected test systems with >1000 electrical connections demonstrates the suitability of the process for manufacturing, and robustness of the test systems against exposure to thermal shock, damp heat, and mechanical flexure shows reliability of the resulting bonds.

Development of pulsed processes for the manufacture of solar cells

NASA Technical Reports Server (NTRS)

Minnucci, J. A.

1979-01-01

Low-energy ion implantation processes for the automated production of silicon solar cells were investigated. Phosphorus ions at an energy of 10 keV and dose of 2 x 10 to the 15th power/sq cm were implanted in silicon solar cells to produce junctions, while boron ions at 25 keV and 5 x 10 to the 15th power were implanted in the cells to produce effective back surface fields. An ion implantation facility with a beam current up to 4 mA and a production throughput of 300 wafers per hour was designed and installed. A design was prepared for a 100 mA, automated implanter with a production capacity of 100 MW sub e/sq cm per year. Two process sequences were developed which employ ion implantation and furnace or pulse annealing. A computer program was used to determine costs for junction formation by ion implantation and various furnace annealing cycles to demonstrate cost effectiveness of these methods.

Beam delivery system with a non-digitized diffractive beam splitter for laser-drilling of silicon

NASA Astrophysics Data System (ADS)

Amako, J.; Fujii, E.

2016-02-01

We report a beam-delivery system consisting of a non-digitized diffractive beam splitter and a Fourier transform lens. The system is applied to the deep-drilling of silicon using a nanosecond pulse laser in the manufacture of inkjet printer heads. In this process, a circularly polarized pulse beam is divided into an array of uniform beams, which are then delivered precisely to the process points. To meet these requirements, the splitter was designed to be polarization-independent with an efficiency>95%. The optical elements were assembled so as to allow the fine tuning of the effective overall focal length by adjusting the wavefront curvature of the beam. Using the system, a beam alignment accuracy of<5 μm was achieved for a 12-mm-wide beam array and the throughput was substantially improved (10,000 points on a silicon wafer drilled in ~1 min). This beam-delivery scheme works for a variety of laser applications that require parallel processing.

Dimension Reduction of Multivariable Optical Emission Spectrometer Datasets for Industrial Plasma Processes

PubMed Central

Yang, Jie; McArdle, Conor; Daniels, Stephen

2014-01-01

A new data dimension-reduction method, called Internal Information Redundancy Reduction (IIRR), is proposed for application to Optical Emission Spectroscopy (OES) datasets obtained from industrial plasma processes. For example in a semiconductor manufacturing environment, real-time spectral emission data is potentially very useful for inferring information about critical process parameters such as wafer etch rates, however, the relationship between the spectral sensor data gathered over the duration of an etching process step and the target process output parameters is complex. OES sensor data has high dimensionality (fine wavelength resolution is required in spectral emission measurements in order to capture data on all chemical species involved in plasma reactions) and full spectrum samples are taken at frequent time points, so that dynamic process changes can be captured. To maximise the utility of the gathered dataset, it is essential that information redundancy is minimised, but with the important requirement that the resulting reduced dataset remains in a form that is amenable to direct interpretation of the physical process. To meet this requirement and to achieve a high reduction in dimension with little information loss, the IIRR method proposed in this paper operates directly in the original variable space, identifying peak wavelength emissions and the correlative relationships between them. A new statistic, Mean Determination Ratio (MDR), is proposed to quantify the information loss after dimension reduction and the effectiveness of IIRR is demonstrated using an actual semiconductor manufacturing dataset. As an example of the application of IIRR in process monitoring/control, we also show how etch rates can be accurately predicted from IIRR dimension-reduced spectral data. PMID:24451453

Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

NASA Technical Reports Server (NTRS)

Routh, D. E.; Sharma, G. C. (Inventor)

1984-01-01

An apparatus is disclosed which includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a dc magnetron sputtering system. A gas inlet introduces various gases to the vacuum chamber and creates various gas plasma during the sputtering steps. The rotating turntables insure that the respective wafers are present under the sputtering guns for an average amount of time such that consistency in sputtering and deposition is achieved. By continuous and sequential processing of the wafers in a common vacuum chamber without removal, the adverse affects of exposure to atmospheric conditions are eliminated providing higher quality circuit contacts and functional device.

Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

NASA Technical Reports Server (NTRS)

Routh, D. E.; Sharma, G. C. (Inventor)

1982-01-01

The processing of wafer devices to form multilevel interconnects for microelectronic circuits is described. The method is directed to performing the sequential steps of etching the via, removing the photo resist pattern, back sputtering the entire wafer surface and depositing the next layer of interconnect material under common vacuum conditions without exposure to atmospheric conditions. Apparatus for performing the method includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a DC magnetron sputtering system. A gas inlet is provided in the chamber for the introduction of various gases to the vacuum chamber and the creation of various gas plasma during the sputtering steps.

Mechanics of wafer bonding: Effect of clamping

NASA Astrophysics Data System (ADS)

Turner, K. T.; Thouless, M. D.; Spearing, S. M.

2004-01-01

A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

Contacting graphene in a 200 mm wafer silicon technology environment

NASA Astrophysics Data System (ADS)

Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

2018-06-01

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

Measurement and thermal modeling of sapphire substrate temperature at III-Nitride MOVPE conditions

DOE PAGES

Creighton, J. Randall; Coltrin, Michael E.; Figiel, Jeffrey J.

2017-04-01

Here, growth rates and alloy composition of AlGaN grown by MOVPE is often very temperature dependent due to the presence of gas-phase parasitic chemical processes. These processes make wafer temperature measurement highly important, but in fact such measurements are very difficult because of substrate transparency in the near- IR (~900 nm) where conventional pyrometers detect radiation. The transparency problem can be solved by using a mid-IR pyrometer operating at a wavelength (~7500 nm) where sapphire is opaque. We employ a mid- IR pyrometer to measure the sapphire wafer temperature and simultaneously a near-IR pyrometer to measure wafer pocket temperature, whilemore » varying reactor pressure in both a N 2 and H 2 ambient. Near 1300 °C, as the reactor pressure is lowered from 300 Torr to 10 Torr the wafer temperature drops dramatically, and the ΔT between the pocket and wafer increases from ~20 °C to ~250 °C. Without the mid-IR pyrometer the large wafer temperature change with pressure would not have been noted. In order to explain this behavior we have developed a quasi-2D thermal model that includes a proper accounting of the pressure-dependent thermal contact resistance, and also accounts for sapphire optical transmission. The model and experimental results demonstrate that at most growth conditions the majority of the heat is transported from the wafer pocket to the wafer via gas conduction, in the free molecular flow limit. In this limit gas conductivity is independent of gap size but first order in pressure, and can quantitatively explain results from 20 to 300 Torr. Further analysis yields a measure of the thermal accommodation coefficients; α(H 2) =0.23, α(N 2) =0.50, which are in the range typically measured.« less

Fabricating with crystalline Si to improve superconducting detector performance

NASA Astrophysics Data System (ADS)

Beyer, A. D.; Hollister, M. I.; Sayers, J.; Frez, C. F.; Day, P. K.; Golwala, S. R.

2017-05-01

We built and measured radio-frequency (RF) loss tangent, tan δ, evaluation structures using float-zone quality silicon-on-insulator (SOI) wafers with 5 μm thick device layers. Superconducting Nb components were fabricated on both sides of the SOI Si device layer. Our main goals were to develop a robust fabrication for using crystalline Si (c-Si) dielectric layers with superconducting Nb components in a wafer bonding process and to confirm that tan δ with c-Si dielectric layers was reduced at RF frequencies compared to devices fabricated with amorphous dielectrics, such as SiO2 and SixNy, where tan δ ∼ 10-3. Our primary test structure used a Nb coplanar waveguide (CPW) readout structure capacitively coupled to LC resonators, where the capacitors were defined as parallel-plate capacitors on both sides of a c-Si device layer using a wafer bonding process with benzocyclobutene (BCB) wafer bonding adhesive. Our control experiment, to determine the intrinsic tan δ in the SOI device layer without wafer bonding, also used Nb CPW readout coupled to LC resonators; however, the parallel-plate capacitors were fabricated on both sides of the Si device layer using a deep reactive ion etch (DRIE) to access the c-Si underside through the buried oxide and handle Si layers in the SOI wafers. We found that our wafer bonded devices demonstrated F· δ = (8 ± 2) × 10-5, where F is the filling fraction of two-level states (TLS). For the control experiment, F· δ = (2.0 ± 0.6) × 10-5, and we discuss what may be degrading the performance in the wafer bonded devices as compared to the control devices.

Silicon Wafer Advanced Packaging (SWAP). Multichip Module (MCM) Foundry Study. Version 2

DTIC Science & Technology

1991-04-08

Next Layer Dielectric Spacing - Additional Metal Thickness Impact on Dielectric Uniformity/Adhiesion. The first step in .!Ie EPerimental design would be... design CAM - computer aided manufacturing CAE - computer aided engineering CALCE - computer aided life cycle engineering center CARMA - computer aided...expansion 5 j- CVD - chemical vapor deposition J . ..- j DA - design automation J , DEC - Digital Equipment Corporation --- DFT - design for testability

Method of defining features on materials with a femtosecond laser

DOEpatents

Roos, Edward Victor [Los Altos, CA; Roeske, Franklin [Livermore, CA; Lee, Ronald S [Livermore, CA; Benterou, Jerry J [Livermore, CA

2006-05-23

The invention relates to a pulsed laser ablation method of metals and/or dielectric films from the surface of a wafer, printed circuit board or a hybrid substrate. By utilizing a high-energy ultra-short pulses of laser light, such a method can be used to manufacture electronic circuits and/or electro-mechanical assemblies without affecting the material adjacent to the ablation zone.

Wafer edge overlay control solution for N7 and beyond

NASA Astrophysics Data System (ADS)

van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

2018-03-01

Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

Optical processing furnace with quartz muffle and diffuser plate

DOEpatents

Sopori, B.L.

1996-11-19

An optical furnace for annealing a process wafer is disclosed comprising a source of optical energy, a quartz muffle having a door to hold the wafer for processing, and a quartz diffuser plate to diffuse the light impinging on the quartz muffle; a feedback system with a light sensor located in the wall of the muffle is also provided for controlling the source of optical energy. 5 figs.

Analysis and Evaluation of Processes and Equipment in Tasks 2 and 4 of the Low-cost Solar Array Project

NASA Technical Reports Server (NTRS)

Goldman, H.; Wolf, M.

1978-01-01

The significant economic data for the current production multiblade wafering and inner diameter slicing processes were tabulated and compared to data on the experimental and projected multiblade slurry, STC ID diamond coated blade, multiwire slurry and crystal systems fixed abrasive multiwire slicing methods. Cost calculations were performed for current production processes and for 1982 and 1986 projected wafering techniques.

Cohesive zone model for direct silicon wafer bonding

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2007-05-01

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Vertical and lateral heterogeneous integration

NASA Astrophysics Data System (ADS)

Geske, Jon; Okuno, Yae L.; Bowers, John E.; Jayaraman, Vijay

2001-09-01

A technique for achieving large-scale monolithic integration of lattice-mismatched materials in the vertical direction and the lateral integration of dissimilar lattice-matched structures has been developed. The technique uses a single nonplanar direct-wafer-bond step to transform vertically integrated epitaxial structures into lateral epitaxial variation across the surface of a wafer. Nonplanar wafer bonding is demonstrated by integrating four different unstrained multi-quantum-well active regions lattice matched to InP on a GaAs wafer surface. Microscopy is used to verify the quality of the bonded interface, and photoluminescence is used to verify that the bonding process does not degrade the optical quality of the laterally integrated wells. The authors propose this technique as a means to achieve greater levels of wafer-scale integration in optical, electrical, and micromechanical devices.

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1982-01-01

The investigation of the performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was continued by fabricating a set of minicell wafers on a selection of 10 cm x 10 cm wafers. A minicell wafer consists of an array of small (approximately 0.2 sq cm in area) photodiodes which are isolated from one another by a mesa structure. The junction capacitance of each minicell was used to obtain the dopant concentration, and therefore the resistivity, as a function of position across each wafer. The results indicate that there is no significant variation in resistivity with position for any of the polycrystalline wafers, whether Semix or Wacker. However, the resistivity of Semix brick 71-01E did decrease slightly from bottom to top.

Realize multiple hermetic chamber pressures for system-on-chip process by using the capping wafer with diverse cavity depths

NASA Astrophysics Data System (ADS)

Cheng, Shyh-Wei; Weng, Jui-Chun; Liang, Kai-Chih; Sun, Yi-Chiang; Fang, Weileun

2018-04-01

Many mechanical and thermal characteristics, for example the air damping, of suspended micromachined structures are sensitive to the ambient pressure. Thus, micromachined devices such as the gyroscope and accelerometer have different ambient pressure requirements. Commercially available process platforms could be used to fabricate and integrate devices of various functions to reduce the chip size. However, it remains a challenge to offer different ambient pressures for micromachined devices after sealing them by wafer level capping (WLC). This study exploits the outgassing characteristics of the CMOS chip to fabricate chambers of various pressures after the WLC of the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform. The pressure of the sealed chamber can be modulated by the chamber volume after the outgassing. In other words, the pressure of hermetic sealed chambers can be easily and properly defined by the etching depth of the cavity on an Si capping wafer. In applications, devices sealed with different cavity depths are implemented using the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform to demonstrate the present approach. Measurements show the feasibility of this simple chamber pressure modulation approach on eight-inch wafers.

Advanced process control framework initiative

NASA Astrophysics Data System (ADS)

Hill, Tom; Nettles, Steve

1997-01-01

The semiconductor industry, one the world's most fiercely competitive industries, is driven by increasingly complex process technologies and global competition to improve cycle time, quality, and process flexibility. Due to the complexity of these problems, current process control techniques are generally nonautomated, time-consuming, reactive, nonadaptive, and focused on individual fabrication tools and processes. As the semiconductor industry moves into higher density processes, radical new approaches are required. To address the need for advanced factory-level process control in this environment, Honeywell, Advanced Micro Devices (AMD), and SEMATECH formed the Advanced Process Control Framework Initiative (APCFI) joint research project. The project defines and demonstrates an Advanced Process Control (APC) approach based on SEMATECH's Computer Integrated Manufacturing (CIM) Framework. Its scope includes the coordination of Manufacturing Execution Systems, process control tools, and wafer fabrication equipment to provide necessary process control capabilities. Moreover, it takes advantage of the CIM Framework to integrate and coordinate applications from other suppliers that provide services necessary for the overall system to function. This presentation discusses the key concept of model-based process control that differentiates the APC Framework. This major improvement over current methods enables new systematic process control by linking the knowledge of key process settings to desired product characteristics that reside in models created with commercial model development tools The unique framework-based approach facilitates integration of commercial tools and reuse of their data by tying them together in an object-based structure. The presentation also explores the perspective of each organization's involvement in the APCFI project. Each has complementary goals and expertise to contribute; Honeywell represents the supplier viewpoint, AMD represents the user with 'real customer requirements', and SEMATECH provides a consensus-building organization that widely disseminates technology to suppliers and users in the semiconductor industry that face similar equipment and factory control systems challenges.

Growth of 1.5 micron gallium indium nitrogen arsenic antimonide vertical cavity surface emitting lasers by molecular beam epitaxy

NASA Astrophysics Data System (ADS)

Wistey, Mark Allan

Fiber optics has revolutionized long distance communication and long haul networks, allowing unimaginable data speeds and noise-free telephone calls around the world for mere pennies per hour at the trunk level. But the high speeds of optical fiber generally do not extend to individual workstations or to the home, in large part because it has been difficult and expensive to produce lasers which emitted light at wavelengths which could take advantage of optical fiber. One of the most promising solutions to this problem is the development of a new class of semiconductors known as dilute nitrides. Dilute nitrides such as GaInNAs can be grown directly on gallium arsenide, which allows well-established processing techniques. More important, gallium arsenide allows the growth of vertical-cavity surface-emitting lasers (VCSELs), which can be grown in dense, 2D arrays on each wafer, providing tremendous economies of scale for manufacturing, testing, and packaging. Unfortunately, GaInNAs lasers have suffered from what has been dubbed the "nitrogen penalty," with high thresholds and low efficiency as the fraction of nitrogen in the semiconductor was increased. This thesis describes the steps taken to identify and essentially eliminate the nitrogen penalty. Protecting the wafer surface from plasma ignition, using an arsenic cap, greatly improved material quality. Using a Langmuir probe, we further found that the nitrogen plasma source produced a large number of ions which damaged the wafer during growth. The ions were dramatically reduced using deflection plates. Low voltage deflection plates were found to be preferable to high voltages, and simulations showed low voltages to be adequate for ion removal. The long wavelengths from dilute nitrides can be partly explained by wafer damage during growth. As a result of these studies, we demonstrated the first CW, room temperature lasers at wavelengths beyond 1.5mum on gallium arsenide, and the first GaInNAs(Sb) VCSELs beyond 1.31mum: 1.46mum. These techniques offer the promise of inexpensive, high speed fiber networking.

Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

NASA Technical Reports Server (NTRS)

Budraa, N. K.; Jackson, H. W.; Barmatz, M.

1999-01-01

We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

Low temperature spalling of silicon: A crack propagation study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan

2017-06-08

Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, themore » crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.« less

Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

NASA Astrophysics Data System (ADS)

Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

2018-05-01

A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

Fluxless eutectic bonding of GaAs-on-Si by using Ag/Sn solder

NASA Astrophysics Data System (ADS)

Eo, Sung-Hwa; Kim, Dae-Seon; Jeong, Ho-Jung; Jang, Jae-Hyung

2013-11-01

Fluxless GaAs-on-Si wafer bonding using Ag/Sn solder was investigated to realize uniform and void-free heterogeneous material integration. The effects of the diffusion barrier, Ag/Sn thickness, and Ar plasma treatment were studied to achieve the optimal fluxless bonding process. Pt on a GaAs wafer and Mo on a Si wafer act as diffusion barriers by preventing the flow of Ag/Sn solder into both the wafers. The bonding strength is closely related to the Ag/Sn thickness and Ar plasma treatment. A shear strength test was carried out to investigate the bonding strength. Under identical bonding conditions, the Ag/Sn thickness was optimized to achieve higher bonding strength and to avoid the formation of voids due to thermal stress. An Ar plasma pretreatment process improved the bonding strength because the Ar plasma removed carbon contaminants and metal-oxide bonds from the metal surface.

Advances in process overlay on 300-mm wafers

NASA Astrophysics Data System (ADS)

Staecker, Jens; Arendt, Stefanie; Schumacher, Karl; Mos, Evert C.; van Haren, Richard J. F.; van der Schaar, Maurits; Edart, Remi; Demmerle, Wolfgang; Tolsma, Hoite

2002-07-01

Overlay budgets are getting tighter within 300 mm volume production and as a consequence the process effects on alignment and off-line metrology becomes more important. In a short loop experiment, with cleared reference marks in each image field, the isolated effect of processing was measured with a sub-nanometer accuracy. The examined processes are Shallow Trench Isolation (STI), Tungsten-Chemical Mechanical Processing (W-CMP) and resist spinning. The alignment measurements were done on an ASML TWINSCANT scanner and the off-line metrology measurements on a KLA Tencor. Mark type and mark position dependency of the process effects are analyzed. The mean plus 3 (sigma) of the maximum overlay after correcting batch average wafer parameters is used as an overlay performance indicator (OPI). 3 (sigma) residuals to the wafer-model are used as an indicator of the noise that is added by the process. The results are in agreement with existing knowledge of process effects on 200 mm wafers. The W-CMP process introduces an additional wafer rotation and scaling that is similar for alignment marks and metrology targets. The effects depend on the mark type; in general they get less severe for higher spatial frequencies. For a 7th order alignment mark, the OPI measured about 12 nm and the added noise about 12 nm. For the examined metrology targets the OPI is about 20 nm with an added noise of about 90 nm. Two different types of alignment marks were tested in the STI process, i.e., zero layer marks and marks that were exposed together with the STI product. The overlay contribution due to processing on both types of alignment marks is very low (smaller than 5 nm OPI) and independent on mark type. Some flyers are observed fot the zero layer marks. The flyers can be explained by the residues of oxide and nitride that is left behind in the spaces of the alignment marks. Resist spinning is examined on single layer resist and resist with an organic Bottom Anti-Reflective Coating (BARC) underneath. Single layer resist showed scaling on unsegmented marks that disappears using higher diffraction orders and/or mark segmentation. Resist with a planarizing BARC caused additional effects on the wafer edge for measurements with the red laser signal. The effects disappear using the green laser of ATHENAT.

Using process monitor wafers to understand directed self-assembly defects

NASA Astrophysics Data System (ADS)

Cao, Yi; Her, YoungJun; Delgadillo, Paulina R.; Vandenbroeck, Nadia; Gronheid, Roel; Chan, Boon Teik; Hashimoto, Yukio; Romo, Ainhoa; Somervell, Mark; Nafus, Kathleen; Nealey, Paul F.

2013-03-01

As directed self-assembly (DSA) has gained momentum over the past few years, questions about its application to high volume manufacturing have arisen. One of the major concerns is about the fundamental limits of defectivity that can be attained with the technology. If DSA applications demonstrate defectivity that rivals of traditional lithographic technologies, the pathway to the cost benefits of the technology creates a very compelling case for its large scale implementation. To address this critical question, our team at IMEC has established a process monitor flow to track the defectivity behaviors of an exemplary chemo-epitaxy application for printing line/space patterns. Through establishing this baseline, we have been able to understand both traditional lithographic defect sources in new materials as well as new classes of assembly defects associated with DSA technology. Moreover, we have explored new materials and processing to lower the level of the defectivity baseline. The robustness of the material sets and process is investigated as well. In this paper, we will report the understandings learned from the IMEC DSA process monitor flow.

Process control systems: integrated for future process technologies

NASA Astrophysics Data System (ADS)

Botros, Youssry; Hajj, Hazem M.

2003-06-01

Process Control Systems (PCS) are becoming more crucial to the success of Integrated Circuit makers due to their direct impact on product quality, cost, and Fab output. The primary objective of PCS is to minimize variability by detecting and correcting non optimal performance. Current PCS implementations are considered disparate, where each PCS application is designed, deployed and supported separately. Each implementation targets a specific area of control such as equipment performance, wafer manufacturing, and process health monitoring. With Intel entering the nanometer technology era, tighter process specifications are required for higher yields and lower cost. This requires areas of control to be tightly coupled and integrated to achieve the optimal performance. This requirement can be achieved via consistent design and deployment of the integrated PCS. PCS integration will result in several benefits such as leveraging commonalities, avoiding redundancy, and facilitating sharing between implementations. This paper will address PCS implementations and focus on benefits and requirements of the integrated PCS. Intel integrated PCS Architecture will be then presented and its components will be briefly discussed. Finally, industry direction and efforts to standardize PCS interfaces that enable PCS integration will be presented.

Material electronic quality specifications for polycrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-06-01

As the use of polycrystalline silicon wafers has expanded in the photovoltaic industry, the need grows for monitoring and qualification techniques for as-grown material that can be used to optimize crystal growth and help predict solar cell performance. Particular needs are for obtaining quantitative measures over full wafer areas of the effects of lifetime limiting defects and of the lifetime upgrading taking place during solar cell processing. We review here the approaches being pursued in programs under way to develop material quality specifications for thin Edge-defined Film-fed Growth (EFG) polycrystalline silicon as-grown wafers. These studies involve collaborations between Mobil Solar, and NREL and university-based laboratories.

BCB Bonding Technology of Back-Side Illuminated COMS Device

NASA Astrophysics Data System (ADS)

Wu, Y.; Jiang, G. Q.; Jia, S. X.; Shi, Y. M.

2018-03-01

Back-side illuminated CMOS(BSI) sensor is a key device in spaceborne hyperspectral imaging technology. Compared with traditional devices, the path of incident light is simplified and the spectral response is planarized by BSI sensors, which meets the requirements of quantitative hyperspectral imaging applications. Wafer bonding is the basic technology and key process of the fabrication of BSI sensors. 6 inch bonding of CMOS wafer and glass wafer was fabricated based on the low bonding temperature and high stability of BCB. The influence of different thickness of BCB on bonding strength was studied. Wafer bonding with high strength, high stability and no bubbles was fabricated by changing bonding conditions.

Particle-free microchip processing

DOEpatents

Geller, Anthony S.; Rader, Daniel J.

1996-01-01

Method and apparatus for reducing particulate contamination in microchip processing are disclosed. The method and apparatus comprise means to reduce particle velocity toward the wafer before the particles can be deposited on the wafer surface. A reactor using electric fields to reduce particle velocity and prevent particulate contamination is disclosed. A reactor using a porous showerhead to reduce particle velocities and prevent particulate contamination is disclosed.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE PAGES

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; ...

2015-10-15

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Comparison of line shortening assessed by aerial image and wafer measurements

NASA Astrophysics Data System (ADS)

Ziegler, Wolfram; Pforr, Rainer; Thiele, Joerg; Maurer, Wilhelm

1997-02-01

Increasing number of patterns per area and decreasing linewidth demand enhancement technologies for optical lithography. OPC, the correction of systematic non-linearity in the pattern transfer process by correction of design data is one possibility to tighten process control and to increase the lifetime of existing lithographic equipment. The two most prominent proximity effects to be corrected by OPC are CD variation and line shortening. Line shortening measured on a wafer is up to 2 times larger than full resist simulation results. Therefore, the influence of mask geometry to line shortening is a key item to parameterize lithography. The following paper discusses the effect of adding small serifs to line ends with 0.25 micrometer ground-rule design. For reticles produced on an ALTA 3000 with standard wet etch process, the corner rounding on them mask can be reduced by adding serifs of a certain size. The corner rounding was measured and the effect on line shortening on the wafer is determined. This was investigated by resist measurements on wafer, aerial image plus resist simulation and aerial image measurements on the AIMS microscope.

Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2002-01-01

A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

A fully wafer-level packaged RF MEMS switch with low actuation voltage using a piezoelectric actuator

NASA Astrophysics Data System (ADS)

Park, Jae-Hyoung; Lee, Hee-Chul; Park, Yong-Hee; Kim, Yong-Dae; Ji, Chang-Hyeon; Bu, Jonguk; Nam, Hyo-Jin

2006-11-01

In this paper, a fully wafer-level packaged RF MEMS switch has been demonstrated, which has low operation voltage, using a piezoelectric actuator. The piezoelectric actuator was designed to operate at low actuation voltage for application to advanced mobile handsets. The dc contact type RF switch was packaged using the wafer-level bonding process. The CPW transmission lines and piezoelectric actuators have been fabricated on separate wafers and assembled together by the wafer-level eutectic bonding process. A gold and tin composite was used for eutectic bonding at a low temperature of 300 °C. Via holes interconnecting the electrical contact pads through the wafer were filled completely with electroplated copper. The fully wafer-level packaged RF MEMS switch showed an insertion loss of 0.63 dB and an isolation of 26.4 dB at 5 GHz. The actuation voltage of the switch was 5 V. The resonant frequency of the piezoelectric actuator was 38.4 kHz and the spring constant of the actuator was calculated to be 9.6 N m-1. The size of the packaged SPST (single-pole single-through) switch was 1.2 mm × 1.2 mm including the packaging sealing rim. The effect of the proposed package structure on the RF performance was characterized with a device having CPW through lines and vertical feed lines excluding the RF switches. The measured packaging loss was 0.2 dB and the return loss was 33.6 dB at 5 GHz.

Direct wafer bonding of highly conductive GaSb/GaInAs and GaSb/GaInP heterojunctions prepared by argon-beam surface activation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Predan, Felix, E-mail: felix.predan@ise.fraunhofer.de; Reinwand, Dirk; Cariou, Romain

The authors present a low-temperature wafer bonding process for the formation of electrically conductive n-GaSb/n-Ga{sub 0.79}In{sub 0.21}As and n-GaSb/n-Ga{sub 0.32}In{sub 0.68}P heterojunctions. The surfaces are deoxidized by sputter-etching with an argon-beam and bonded in ultrahigh vacuum. The sputtering behavior was investigated for each material, revealing a distinct selective sputtering characteristic for Ga{sub 0.32}In{sub 0.68}P. According to these findings, the settings for the bonding process were chosen. The mechanical and electrical properties of the wafer bonds were studied. Fully bonded 2 in. wafer pairs were found for both material combinations exhibiting high bond energies, which are comparable to the binding energiesmore » in the semiconductors. Furthermore, bond resistances below 5 mΩ cm{sup 2} could be reached, which are in the range of the lowest resistances that have been reported for wafer bonded heterojunctions. This speaks, together with the high bond energies, for a high amount of covalent bonds at the interfaces. These promising bond characteristics make the integration of antimonides with arsenides or phosphides by wafer bonding attractive for various optoelectronic applications such as multijunction solar cells.« less