Sample records for wafer scale integration

  1. Wafer integrated micro-scale concentrating photovoltaics

    NASA Astrophysics Data System (ADS)

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  2. Silicon Hybrid Wafer Scale Integration Interconnect Evaluation

    DTIC Science & Technology

    1989-12-01

    perform Wafer Scale Integration on a routine basis is being vigorously pursued by a number of interests in military, academic , and commercial sectors...A iliciosi rip1 St -110 illic. (;11ptai / W. -a ;,tcd Ihat Ilesc hybhrid futl liods separiltely soI lie llixiiiul’upw~v~ ielts andl ~il (otii’ie thli

  3. Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

    PubMed Central

    Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

    2014-01-01

    In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

  4. Wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible biomedical platform.

    PubMed

    Maeng, Jimin; Meng, Chuizhou; Irazoqui, Pedro P

    2015-02-01

    We present wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible parylene platform, as progress toward sustainably powering biomedical microsystems suitable for implantable and wearable applications. All-solid-state, low-profile (<30 μm), and high-density (up to ~500 μF/mm(2)) micro-supercapacitors are formed on an ultrathin (~20 μm) freestanding parylene film by a wafer-scale parylene packaging process in combination with a polyaniline (PANI) nanowire growth technique assisted by surface plasma treatment. These micro-supercapacitors are highly flexible and shown to be resilient toward flexural stress. Further, direct integration of micro-supercapacitors into a radio frequency (RF) rectifying circuit is achieved on a single parylene platform, yielding a complete RF energy harvesting microsystem. The system discharging rate is shown to improve by ~17 times in the presence of the integrated micro-supercapacitors. This result suggests that the integrated micro-supercapacitor technology described herein is a promising strategy for sustainably powering biomedical microsystems dedicated to implantable and wearable applications.

  5. Thinning of PLZT ceramic wafers for sensor integration

    NASA Astrophysics Data System (ADS)

    Jin, Na; Liu, Weiguo

    2010-08-01

    Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

  6. Wafer-Scale Integration of Systolic Arrays,

    DTIC Science & Technology

    1985-10-01

    hus wtha rbaiith hig robabili, e aubrbe orutysta mostck b(e)adstotoefwsi the cenofther cnnel thati are connted to (g.The kery ato the alevel of t...problems considered heretofore in this paper also have an interpretation in a purely graph theoretic model. Suppose we are given a two-dimensional...graphs," Magyar 7Td. Akad. Math . Kut. Int. Kozl, Vol. 5, 1960, pp. 17-61. [6] D. Fussell and P. Varman, "Fault-tolerant wafer-scale architectures for

  7. Wafer-scale pixelated detector system

    DOEpatents

    Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

    2017-10-17

    A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

  8. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

    PubMed

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-12-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

  9. Wafer scale oblique angle plasma etching

    DOEpatents

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  10. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    NASA Astrophysics Data System (ADS)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  11. Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

    NASA Astrophysics Data System (ADS)

    Mieda, Eiko; Maeda, Tatsuro; Miyata, Noriyuki; Yasuda, Tetsuji; Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki; Aoki, Takeshi; Yamamoto, Taketsugu; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko; Ogawa, Arito; Kikuchi, Toshiyuki; Kunii, Yasuo

    2015-03-01

    We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

  12. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  13. High throughput wafer defect monitor for integrated metrology applications in photolithography

    NASA Astrophysics Data System (ADS)

    Rao, Nagaraja; Kinney, Patrick; Gupta, Anand

    2008-03-01

    The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

  14. Fabrication of wafer-scale nanopatterned sapphire substrate through phase separation lithography

    NASA Astrophysics Data System (ADS)

    Guo, Xu; Ni, Mengyang; Zhuang, Zhe; Dai, Jiangping; Wu, Feixiang; Cui, Yushuang; Yuan, Changsheng; Ge, Haixiong; Chen, Yanfeng

    2016-04-01

    A phase separation lithography (PSL) based on polymer blend provides an extremely simple, low-cost, and high-throughput way to fabricate wafer-scale disordered nanopatterns. This method was introduced to fabricate nanopatterned sapphire substrates (NPSSs) for GaN-based light-emitting diodes (LEDs). The PSL process only involved in spin-coating of polystyrene (PS)/polyethylene glycol (PEG) polymer blend on sapphire substrate and followed by a development with deionized water to remove PEG moiety. The PS nanoporous network was facilely obtained, and the structural parameters could be effectively tuned by controlling the PS/PEG weight ratio of the spin-coating solution. 2-in. wafer-scale NPSSs were conveniently achieved through the PS nanoporous network in combination with traditional nanofabrication methods, such as O2 reactive ion etching (RIE), e-beam evaporation deposition, liftoff, and chlorine-based RIE. In order to investigate the performance of such NPSSs, typical blue LEDs with emission wavelengths of ~450 nm were grown on the NPSS and a flat sapphire substrate (FSS) by metal-organic chemical vapor deposition, respectively. The integral photoluminescence (PL) intensity of the NPSS LED was enhanced by 32.3 % compared to that of the FSS-LED. The low relative standard deviation of 4.7 % for PL mappings of NPSS LED indicated the high uniformity of PL data across the whole 2-in. wafer. Extremely simple, low cost, and high throughput of the process and the ability to fabricate at the wafer scale make PSL a potential method for production of nanopatterned sapphire substrates.

  15. From magic to technology: materials integration by wafer bonding

    NASA Astrophysics Data System (ADS)

    Dragoi, Viorel

    2006-02-01

    Wafer bonding became in the last decade a very powerful technology for MEMS/MOEMS manufacturing. Being able to offer a solution to overcome some problems of the standard processes used for materials integration (e.g. epitaxy, thin films deposition), wafer bonding is nowadays considered an important item in the MEMS engineer toolbox. Different principles governing the wafer bonding processes will be reviewed in this paper. Various types of applications will be presented as examples.

  16. Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

    NASA Astrophysics Data System (ADS)

    Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

    2015-02-01

    The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

  17. Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics.

    PubMed

    Heo, Jinseong; Byun, Kyung-Eun; Lee, Jaeho; Chung, Hyun-Jong; Jeon, Sanghun; Park, Seongjun; Hwang, Sungwoo

    2013-01-01

    Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.

  18. Wafer-scale plasmonic and photonic crystal sensors

    NASA Astrophysics Data System (ADS)

    George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

    2015-08-01

    200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

  19. 11.72 sq cm SiC Wafer-scale Interconnected 64 kA PiN Diode

    DTIC Science & Technology

    2012-01-30

    drop of 10.3 V. The dissipated energy was 382 J and the calculated action exceeded 1.7 MA2 -s. Preliminary development of high voltage interconnection...scale diode action (surge current integral), a key reliability parameter, exceeded 1.7 MA2 -s. Figure 6: The wafer-scale interconnected diode...scale diode was 382 J and the calculated action exceeded 1.7 MA2 -sec. High voltage operation of PiN diodes, thyristors, and other semiconductor

  20. Simplified nonplanar wafer bonding for heterogeneous device integration

    NASA Astrophysics Data System (ADS)

    Geske, Jon; Bowers, John E.; Riley, Anton

    2004-07-01

    We demonstrate a simplified nonplanar wafer bonding technique for heterogeneous device integration. The improved technique can be used to laterally integrate dissimilar semiconductor device structures on a lattice-mismatched substrate. Using the technique, two different InP-based vertical-cavity surface-emitting laser active regions have been integrated onto GaAs without compromising the quality of the photoluminescence. Experimental and numerical simulation results are presented.

  1. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    NASA Astrophysics Data System (ADS)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  2. Wafer level reliability testing: An idea whose time has come

    NASA Technical Reports Server (NTRS)

    Trapp, O. D.

    1987-01-01

    Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

  3. Wafer-scale growth of VO2 thin films using a combinatorial approach

    PubMed Central

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

    2015-01-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that ‘electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

  4. Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

    NASA Astrophysics Data System (ADS)

    Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

    2017-02-01

    A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (~1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

  5. Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals.

    PubMed

    Carey, Benjamin J; Ou, Jian Zhen; Clark, Rhiannon M; Berean, Kyle J; Zavabeti, Ali; Chesman, Anthony S R; Russo, Salvy P; Lau, Desmond W M; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C; Dickey, Michael D; Kaner, Richard B; Daeneke, Torben; Kalantar-Zadeh, Kourosh

    2017-02-17

    A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

  6. Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

    PubMed Central

    Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kavehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

    2017-01-01

    A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes. PMID:28211538

  7. Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

    PubMed

    Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

    2008-07-30

    Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

  8. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-07

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  9. Wafer-Level Vacuum Packaging of Smart Sensors.

    PubMed

    Hilton, Allan; Temple, Dorota S

    2016-10-31

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  10. Wafer-Level Vacuum Packaging of Smart Sensors

    PubMed Central

    Hilton, Allan; Temple, Dorota S.

    2016-01-01

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology. PMID:27809249

  11. InP-based photonic integrated circuit platform on SiC wafer.

    PubMed

    Takenaka, Mitsuru; Takagi, Shinichi

    2017-11-27

    We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

  12. Wafer level reliability for high-performance VLSI design

    NASA Technical Reports Server (NTRS)

    Root, Bryan J.; Seefeldt, James D.

    1987-01-01

    As very large scale integration architecture requires higher package density, reliability of these devices has approached a critical level. Previous processing techniques allowed a large window for varying reliability. However, as scaling and higher current densities push reliability to its limit, tighter control and instant feedback becomes critical. Several test structures developed to monitor reliability at the wafer level are described. For example, a test structure was developed to monitor metal integrity in seconds as opposed to weeks or months for conventional testing. Another structure monitors mobile ion contamination at critical steps in the process. Thus the reliability jeopardy can be assessed during fabrication preventing defective devices from ever being placed in the field. Most importantly, the reliability can be assessed on each wafer as opposed to an occasional sample.

  13. Layer-by-layer assembly of two-dimensional materials into wafer-scale heterostructures

    NASA Astrophysics Data System (ADS)

    Kang, Kibum; Lee, Kan-Heng; Han, Yimo; Gao, Hui; Xie, Saien; Muller, David A.; Park, Jiwoong

    2017-10-01

    High-performance semiconductor films with vertical compositions that are designed to atomic-scale precision provide the foundation for modern integrated circuitry and novel materials discovery. One approach to realizing such films is sequential layer-by-layer assembly, whereby atomically thin two-dimensional building blocks are vertically stacked, and held together by van der Waals interactions. With this approach, graphene and transition-metal dichalcogenides--which represent one- and three-atom-thick two-dimensional building blocks, respectively--have been used to realize previously inaccessible heterostructures with interesting physical properties. However, no large-scale assembly method exists at present that maintains the intrinsic properties of these two-dimensional building blocks while producing pristine interlayer interfaces, thus limiting the layer-by-layer assembly method to small-scale proof-of-concept demonstrations. Here we report the generation of wafer-scale semiconductor films with a very high level of spatial uniformity and pristine interfaces. The vertical composition and properties of these films are designed at the atomic scale using layer-by-layer assembly of two-dimensional building blocks under vacuum. We fabricate several large-scale, high-quality heterostructure films and devices, including superlattice films with vertical compositions designed layer-by-layer, batch-fabricated tunnel device arrays with resistances that can be tuned over four orders of magnitude, band-engineered heterostructure tunnel diodes, and millimetre-scale ultrathin membranes and windows. The stacked films are detachable, suspendable and compatible with water or plastic surfaces, which will enable their integration with advanced optical and mechanical systems.

  14. Layer-by-layer assembly of two-dimensional materials into wafer-scale heterostructures.

    PubMed

    Kang, Kibum; Lee, Kan-Heng; Han, Yimo; Gao, Hui; Xie, Saien; Muller, David A; Park, Jiwoong

    2017-10-12

    High-performance semiconductor films with vertical compositions that are designed to atomic-scale precision provide the foundation for modern integrated circuitry and novel materials discovery. One approach to realizing such films is sequential layer-by-layer assembly, whereby atomically thin two-dimensional building blocks are vertically stacked, and held together by van der Waals interactions. With this approach, graphene and transition-metal dichalcogenides-which represent one- and three-atom-thick two-dimensional building blocks, respectively-have been used to realize previously inaccessible heterostructures with interesting physical properties. However, no large-scale assembly method exists at present that maintains the intrinsic properties of these two-dimensional building blocks while producing pristine interlayer interfaces, thus limiting the layer-by-layer assembly method to small-scale proof-of-concept demonstrations. Here we report the generation of wafer-scale semiconductor films with a very high level of spatial uniformity and pristine interfaces. The vertical composition and properties of these films are designed at the atomic scale using layer-by-layer assembly of two-dimensional building blocks under vacuum. We fabricate several large-scale, high-quality heterostructure films and devices, including superlattice films with vertical compositions designed layer-by-layer, batch-fabricated tunnel device arrays with resistances that can be tuned over four orders of magnitude, band-engineered heterostructure tunnel diodes, and millimetre-scale ultrathin membranes and windows. The stacked films are detachable, suspendable and compatible with water or plastic surfaces, which will enable their integration with advanced optical and mechanical systems.

  15. Computational Modeling in Plasma Processing for 300 mm Wafers

    NASA Technical Reports Server (NTRS)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  16. SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

    NASA Astrophysics Data System (ADS)

    Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

    2016-10-01

    Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and

  17. Wafer-to-wafer bonding of nonplanarized MEMS surfaces using solder

    NASA Astrophysics Data System (ADS)

    Sparks, D.; Queen, G.; Weston, R.; Woodward, G.; Putty, M.; Jordan, L.; Zarabadi, S.; Jayakar, K.

    2001-11-01

    The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.

  18. I-line stepper based overlay evaluation method for wafer bonding applications

    NASA Astrophysics Data System (ADS)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2018-03-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

  19. Wafer-scale growth of highly textured piezoelectric thin films by pulsed laser deposition for micro-scale sensors and actuators

    NASA Astrophysics Data System (ADS)

    Nguyen, M. D.; Tiggelaar, R.; Aukes, T.; Rijnders, G.; Roelof, G.

    2017-11-01

    Piezoelectric lead-zirconate-titanate (PZT) thin films were deposited on 4-inch (111)Pt/Ti/SiO2/Si(001) wafers using large-area pulsed laser deposition (PLD). This study was focused on the homogeneity in film thickness, microstructure, ferroelectric and piezoelectric properties of PZT thin films. The results indicated that the highly textured (001)-oriented PZT thin films with wafer-scale thickness homogeneity (990 nm ± 0.8%) were obtained. The films were fabricated into piezoelectric cantilevers through a MEMS microfabrication process. The measured longitudinal piezoelectric coefficient (d 33f = 210 pm/V ± 1.6%) and piezoelectric transverse coefficient (e 31f = -18.8 C/m2 ± 2.8%) were high and homogeneity across wafers. The high piezoelectric properties on Si wafers will extend industrial application of PZT thin films and further development of piezoMEMS.

  20. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication.

    PubMed

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-02-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80-100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

  1. Vertical and lateral heterogeneous integration

    NASA Astrophysics Data System (ADS)

    Geske, Jon; Okuno, Yae L.; Bowers, John E.; Jayaraman, Vijay

    2001-09-01

    A technique for achieving large-scale monolithic integration of lattice-mismatched materials in the vertical direction and the lateral integration of dissimilar lattice-matched structures has been developed. The technique uses a single nonplanar direct-wafer-bond step to transform vertically integrated epitaxial structures into lateral epitaxial variation across the surface of a wafer. Nonplanar wafer bonding is demonstrated by integrating four different unstrained multi-quantum-well active regions lattice matched to InP on a GaAs wafer surface. Microscopy is used to verify the quality of the bonded interface, and photoluminescence is used to verify that the bonding process does not degrade the optical quality of the laterally integrated wells. The authors propose this technique as a means to achieve greater levels of wafer-scale integration in optical, electrical, and micromechanical devices.

  2. Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

    NASA Astrophysics Data System (ADS)

    Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

    2016-04-01

    In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

  3. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

    PubMed Central

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-01-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80–100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes. PMID:28145513

  4. A hermetic and room-temperature wafer bonding technique based on integrated reactive multilayer systems

    NASA Astrophysics Data System (ADS)

    Braeuer, J.; Gessner, T.

    2014-11-01

    This paper focuses on direct deposition and patterning of reactive and nano-scale multilayer films at wafer level. These multilayer structures are called integrated reactive material systems (iRMS). In contrast to the typically used nickel (Ni)/ aluminum (Al) systems, in this work we needed to have our total multilayer film thicknesses smaller than 2.5 µm to reduce stress within the multilayer as well as deposition costs. Thus, we introduced new high energetic iRMS. These films were deposited by using alternating magnetron sputtering from high purity Al- and palladium (Pd)-targets to obtain films with a defined Al:Pd atomic ratio. In this paper, we present the result for reaction characteristics and reaction velocities which were up to 72.5 m s-1 for bond frames with lateral dimensions as low as 20 µm. Furthermore, the feasibility of silicon (Si)-Si, Si-glass as well as Si-ceramic hermetic and metallic wafer bonding at room temperature is presented. We show that by using this bond technology, strong (maximum shear strengths of 235 MPa) and hermetically sealed bond interfaces can be achieved without any additional solder material.

  5. Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

    PubMed

    Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

    2012-07-17

    Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

  6. Laser wafering for silicon solar.

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurfacemore » damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.« less

  7. Wafer-scale epitaxial graphene on SiC for sensing applications

    NASA Astrophysics Data System (ADS)

    Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

    2015-12-01

    The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

  8. Infrared spectroscopy of wafer-scale graphene.

    PubMed

    Yan, Hugen; Xia, Fengnian; Zhu, Wenjuan; Freitag, Marcus; Dimitrakopoulos, Christos; Bol, Ageeth A; Tulevski, George; Avouris, Phaedon

    2011-12-27

    We report spectroscopy results from the mid- to far-infrared on wafer-scale graphene, grown either epitaxially on silicon carbide or by chemical vapor deposition. The free carrier absorption (Drude peak) is simultaneously obtained with the universal optical conductivity (due to interband transitions) and the wavelength at which Pauli blocking occurs due to band filling. From these, the graphene layer number, doping level, sheet resistivity, carrier mobility, and scattering rate can be inferred. The mid-IR absorption of epitaxial two-layer graphene shows a less pronounced peak at 0.37 ± 0.02 eV compared to that in exfoliated bilayer graphene. In heavily chemically doped single-layer graphene, a record high transmission reduction due to free carriers approaching 40% at 250 μm (40 cm(-1)) is measured in this atomically thin material, supporting the great potential of graphene in far-infrared and terahertz optoelectronics.

  9. Wafer-scale synthesis of monolayer and few-layer MoS2 via thermal vapor sulfurization

    NASA Astrophysics Data System (ADS)

    Robertson, John; Liu, Xue; Yue, Chunlei; Escarra, Matthew; Wei, Jiang

    2017-12-01

    Monolayer molybdenum disulfide (MoS2) is an atomically thin, direct bandgap semiconductor crystal potentially capable of miniaturizing optoelectronic devices to an atomic scale. However, the development of 2D MoS2-based optoelectronic devices depends upon the existence of a high optical quality and large-area monolayer MoS2 synthesis technique. To address this need, we present a thermal vapor sulfurization (TVS) technique that uses powder MoS2 as a sulfur vapor source. The technique reduces and stabilizes the flow of sulfur vapor, enabling monolayer wafer-scale MoS2 growth. MoS2 thickness is also controlled with great precision; we demonstrate the ability to synthesize MoS2 sheets between 1 and 4 layers thick, while also showing the ability to create films with average thickness intermediate between integer layer numbers. The films exhibit wafer-scale coverage and uniformity, with electrical quality varying depending on the final thickness of the grown MoS2. The direct bandgap of grown monolayer MoS2 is analyzed using internal and external photoluminescence quantum efficiency. The photoluminescence quantum efficiency is shown to be competitive with untreated exfoliated MoS2 monolayer crystals. The ability to consistently grow wafer-scale monolayer MoS2 with high optical quality makes this technique a valuable tool for the development of 2D optoelectronic devices such as photovoltaics, detectors, and light emitters.

  10. Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

    NASA Astrophysics Data System (ADS)

    Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

    2017-08-01

    Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

  11. Influence of Si wafer thinning processes on (sub)surface defects

    NASA Astrophysics Data System (ADS)

    Inoue, Fumihiro; Jourdain, Anne; Peng, Lan; Phommahaxay, Alain; De Vos, Joeri; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik; Beyne, Eric; Uedono, Akira

    2017-05-01

    Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5 μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 μm. For the case of Si thinning towards 5 μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5-2 μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in between grinding and dry etch it is possible to significantly reduce not only the roughness, but also the remaining vacancies at the subsurface. The surface of grinding + CMP + dry etching gives an equivalent mono vacancy result as to that of grinding + CMP. This combination of thinning processes allows development of extremely thin 3D integration devices with minimal roughness and vacancy surface.

  12. Wafer-scale fabrication of polymer-based microdevices via injection molding and photolithographic micropatterning protocols.

    PubMed

    Lee, Dae-Sik; Yang, Haesik; Chung, Kwang-Hyo; Pyo, Hyeon-Bong

    2005-08-15

    Because of their broad applications in biomedical analysis, integrated, polymer-based microdevices incorporating micropatterned metallic and insulating layers are significant in contemporary research. In this study, micropatterns for temperature sensing and microelectrode sets for electroanalysis have been implemented on an injection-molded thin polymer membrane by employing conventional semiconductor processing techniques (i.e., standard photolithographic methods). Cyclic olefin copolymer (COC) is chosen as the polymer substrate because of its high chemical and thermal stability. A COC 5-in. wafer (1-mm thickness) is manufactured using an injection molding method, in which polymer membranes (approximately 130 microm thick and 3 mm x 6 mm in area) are implemented simultaneously in order to reduce local thermal mass around micropatterned heaters and temperature sensors. The highly polished surface (approximately 4 nm within 40 microm x 40 microm area) of the fabricated COC wafer as well as its good resistance to typical process chemicals makes it possible to use the standard photolithographic and etching protocols on the COC wafer. Gold micropatterns with a minimum 5-microm line width are fabricated for making microheaters, temperature sensors, and microelectrodes. An insulating layer of aluminum oxide (Al2O3) is prepared at a COC-endurable low temperature (approximately 120 degrees C) by using atomic layer deposition and micropatterning for the electrode contacts. The fabricated microdevice for heating and temperature sensing shows improved performance of thermal isolation, and microelectrodes display good electrochemical performances for electrochemical sensors. Thus, this novel 5-in. wafer-level microfabrication method is a simple and cost-effective protocol to prepare polymer substrate and demonstrates good potential for application to highly integrated and miniaturized biomedical devices.

  13. Chelant Enhanced Solution Processing for Wafer Scale Synthesis of Transition Metal Dichalcogenide Thin Films.

    PubMed

    Ionescu, Robert; Campbell, Brennan; Wu, Ryan; Aytan, Ece; Patalano, Andrew; Ruiz, Isaac; Howell, Stephen W; McDonald, Anthony E; Beechem, Thomas E; Mkhoyan, K Andre; Ozkan, Mihrimah; Ozkan, Cengiz S

    2017-07-25

    It is of paramount importance to improve the control over large area growth of high quality molybdenum disulfide (MoS 2 ) and other types of 2D dichalcogenides. Such atomically thin materials have great potential for use in electronics, and are thought to make possible the first real applications of spintronics. Here in, a facile and reproducible method of producing wafer scale atomically thin MoS 2 layers has been developed using the incorporation of a chelating agent in a common organic solvent, dimethyl sulfoxide (DMSO). Previously, solution processing of a MoS 2 precursor, ammonium tetrathiomolybdate ((NH 4 ) 2 MoS 4 ), and subsequent thermolysis was used to produce large area MoS 2 layers. Our work here shows that the use of ethylenediaminetetraacetic acid (EDTA) in DMSO exerts superior control over wafer coverage and film thickness, and the results demonstrate that the chelating action and dispersing effect of EDTA is critical in growing uniform films. Raman spectroscopy, photoluminescence (PL), x-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectroscopy (FTIR), atomic force microscopy (AFM) and high-resolution scanning transmission electron microscopy (HR-STEM) indicate the formation of homogenous few layer MoS 2 films at the wafer scale, resulting from the novel chelant-in-solution method.

  14. A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

    NASA Astrophysics Data System (ADS)

    Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

    2013-03-01

    The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

  15. Large scale integration of graphene transistors for potential applications in the back end of the line

    NASA Astrophysics Data System (ADS)

    Smith, A. D.; Vaziri, S.; Rodriguez, S.; Östling, M.; Lemme, M. C.

    2015-06-01

    A chip to wafer scale, CMOS compatible method of graphene device fabrication has been established, which can be integrated into the back end of the line (BEOL) of conventional semiconductor process flows. In this paper, we present experimental results of graphene field effect transistors (GFETs) which were fabricated using this wafer scalable method. The carrier mobilities in these transistors reach up to several hundred cm2 V-1 s-1. Further, these devices exhibit current saturation regions similar to graphene devices fabricated using mechanical exfoliation. The overall performance of the GFETs can not yet compete with record values reported for devices based on mechanically exfoliated material. Nevertheless, this large scale approach is an important step towards reliability and variability studies as well as optimization of device aspects such as electrical contacts and dielectric interfaces with statistically relevant numbers of devices. It is also an important milestone towards introducing graphene into wafer scale process lines.

  16. Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer.

    PubMed

    Yu, Yang; Fong, Patrick W K; Wang, Shifeng; Surya, Charles

    2016-11-29

    High quality wafer-scale free-standing WS 2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS 2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS 2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS 2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS 2 , which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS 2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm 2 at -1 V which shows superior performances compared to the directly grown WS 2 /GaN heterojunctions.

  17. Within-wafer CD variation induced by wafer shape

    NASA Astrophysics Data System (ADS)

    Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

    2016-03-01

    In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer

  18. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  19. Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer

    PubMed Central

    Yu, Yang; Fong, Patrick W. K.; Wang, Shifeng; Surya, Charles

    2016-01-01

    High quality wafer-scale free-standing WS2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS2, which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm2 at −1 V which shows superior performances compared to the directly grown WS2/GaN heterojunctions. PMID:27897210

  20. Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments.

    PubMed

    Bomer, Johan G; Prokofyev, Alexander V; van den Berg, Albert; Le Gac, Séverine

    2014-12-07

    We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the microchannels, and alignment precision. Experiments on lipid bilayers with electrophysiological recordings using a model pore-forming polypeptide are demonstrated.

  1. Fabrication of nano-scale Cu bond pads with seal design in 3D integration applications.

    PubMed

    Chen, K N; Tsang, C K; Wu, W W; Lee, S H; Lu, J Q

    2011-04-01

    A method to fabricate nano-scale Cu bond pads for improving bonding quality in 3D integration applications is reported. The effect of Cu bonding quality on inter-level via structural reliability for 3D integration applications is investigated. We developed a Cu nano-scale-height bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO2 CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes provide the feasibility of reliable nano-scale 3D integration applications.

  2. Resolving critical dimension drift over time in plasma etching through virtual metrology based wafer-to-wafer control

    NASA Astrophysics Data System (ADS)

    Lee, Ho Ki; Baek, Kye Hyun; Shin, Kyoungsub

    2017-06-01

    As semiconductor devices are scaled down to sub-20 nm, process window of plasma etching gets extremely small so that process drift or shift becomes more significant. This study addresses one of typical process drift issues caused by consumable parts erosion over time and provides feasible solution by using virtual metrology (VM) based wafer-to-wafer control. Since erosion of a shower head has center-to-edge area dependency, critical dimensions (CDs) at the wafer center and edge area get reversed over time. That CD trend is successfully estimated on a wafer-to-wafer basis by a partial least square (PLS) model which combines variables from optical emission spectroscopy (OES), VI-probe and equipment state gauges. R 2 of the PLS model reaches 0.89 and its prediction performance is confirmed in a mass production line. As a result, the model can be exploited as a VM for wafer-to-wafer control. With the VM, advanced process control (APC) strategy is implemented to solve the CD drift. Three σ of CD across wafer is improved from the range (1.3-2.9 nm) to the range (0.79-1.7 nm). Hopefully, results introduced in this paper will contribute to accelerating implementation of VM based APC strategy in semiconductor industry.

  3. The Imaging Properties of a Silicon Wafer X-Ray Telescope

    NASA Technical Reports Server (NTRS)

    Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

    1994-01-01

    Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

  4. Wafer-scale aluminum nano-plasmonics

    NASA Astrophysics Data System (ADS)

    George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

    2014-09-01

    The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

  5. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    NASA Astrophysics Data System (ADS)

    Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

    2014-08-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

  6. Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

    NASA Astrophysics Data System (ADS)

    Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

    2014-02-01

    Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

  7. WaferOptics® mass volume production and reliability

    NASA Astrophysics Data System (ADS)

    Wolterink, E.; Demeyer, K.

    2010-05-01

    The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

  8. New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

    NASA Astrophysics Data System (ADS)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2017-06-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

  9. Wafer scale BN on sapphire substrates for improved graphene transport.

    PubMed

    Vangala, Shivashankar; Siegel, Gene; Prusnick, Timothy; Snure, Michael

    2018-06-11

    Wafer scale (2") BN grown by metal organic chemical vapor deposition (MOCVD) on sapphire was examined as a weakly interacting dielectric substrate for graphene, demonstrating improved transport properties over conventional sapphire and SiO 2 /Si substrates. Chemical vapor deposition grown graphene was transferred to BN/sapphire substrates for evaluation of more than 30 samples using Raman and Hall effects measurements. A more than 2x increase in Hall mobility and 10x reduction in sheet carrier density was measured for graphene on BN/sapphire compared to sapphire substrates. Through control of the MOCVD process, BN films with roughness ranging from <0.1 nm to >1 nm were grown and used to study the effects of substrate roughness on graphene transport. Arrays of graphene field effect transistors were fabricated on 2" BN/sapphire substrates demonstrating scalability and device performance enhancement.

  10. HED-TIE: A wafer-scale approach for fabricating hybrid electronic devices with trench isolated electrodes

    NASA Astrophysics Data System (ADS)

    Banerjee, Sreetama; Bülz, Daniel; Solonenko, Dmytro; Reuter, Danny; Deibel, Carsten; Hiller, Karla; Zahn, Dietrich R. T.; Salvan, Georgeta

    2017-05-01

    Organic-inorganic hybrid electronic devices (HEDs) offer opportunities for functionalities that are not easily obtainable with either organic or inorganic materials individually. In the strive for down-scaling the channel length in planar geometry HEDs, the best results were achieved with electron beam lithography or nanoimprint lithography. Their application on the wafer level is, however, cost intensive and time consuming. Here, we propose trench isolated electrode (TIE) technology as a fast, cost effective, wafer-level approach for the fabrication of planar HEDs with electrode gaps in the range of 100 nm. We demonstrate that the formation of the organic channel can be realized by deposition from solution as well as by the thermal evaporation of organic molecules. To underline one key feature of planar HED-TIEs, namely full accessibility of the active area of the devices by external stimuli such as light, 6,13-bis (triisopropylsilylethynyl) (TIPS)-pentacene/Au HED-TIEs are successfully tested for possible application as hybrid photodetectors in the visible spectral range.

  11. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

    PubMed Central

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-01-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

  12. Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures

    DTIC Science & Technology

    2006-11-01

    Chip Level CMOS Chip High resistivity Si Metal Interconnect 25μm 24GHz fully integrated receiver CMOS transimpedance Amplifier (13GHz BW, 52dBΩ...power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating...With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage

  13. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  14. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    NASA Astrophysics Data System (ADS)

    Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  15. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  16. Revealing the Crystalline Integrity of Wafer-Scale Graphene on SiO2/Si: An Azimuthal RHEED Approach.

    PubMed

    Lu, Zonghuan; Sun, Xin; Xiang, Yu; Washington, Morris A; Wang, Gwo-Ching; Lu, Toh-Ming

    2017-07-12

    The symmetry of graphene is usually determined by a low-energy electron diffraction (LEED) method when the graphene is on the conductive substrates, but LEED cannot handle graphene transferred to SiO 2 /Si substrates due to the charging effect. While transmission electron microscopy can generate electron diffraction on post-transferred graphene, this method is too localized. Herein, we employed an azimuthal reflection high-energy electron diffraction (RHEED) method to construct the reciprocal space mapping and determine the symmetry of wafer-size graphene both pre- and post-transfer. In this work, single-crystalline Cu(111) films were prepared on sapphire(0001) and spinel(111) substrates with sputtering. Then the graphene was epitaxially grown on single-crystalline Cu(111) films with a low pressure chemical vapor deposition. The reciprocal space mapping using azimuthal RHEED confirmed that the graphene grown on Cu(111) films was single-crystalline, no matter the form of the monolayer or multilayer structure. While the Cu(111) film grown on sapphire(0001) may occasionally consist of 60° in-plane rotational twinning, the reciprocal space mapping revealed that the in-plane orientation of graphene grown atop was not affected. The proposed method for checking the crystalline integrity of the post-transferred graphene sheets is an important step in the realization of the graphene as a platform to fabricate electronic and optoelectronic devices.

  17. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  18. An Integrated Approach to the Bulk III-Nitride Crystal Growth and Wafering

    DTIC Science & Technology

    2007-06-12

    Integrated Approach to the Bulk III-Nitride Crystal Growth and Wafering GaN powder decomposition - I 2GaN(s) = 2Ga(s) + N2(g) Ga2O3 (s)+Ga = 3GaO(g) GaO(g...Ga(g) = Ga2O(g) Ga(l) = Ga(g) 2GaN(s) = 2Ga(s) + N2(g) Ga(l) = Ga(g) Heterogeneous chemistry GaN(s) Ga2O3 , Ga(l)GaN(s), Ga(l)Condensed phases N2, Ga(g...400ppm; • The commercial GaN powder is converted from Ga2O3 . The powder purity is less than 91% with more than 3% oxygen concentration. • The very

  19. Integration of strained and relaxed silicon thin films on silicon wafers via engineered oxide heterostructures: Experiment and theory

    NASA Astrophysics Data System (ADS)

    Seifarth, O.; Dietrich, B.; Zaumseil, P.; Giussani, A.; Storck, P.; Schroeder, T.

    2010-10-01

    Strained and relaxed single crystalline Si on insulator systems is an important materials science approach for future Si-based nanoelectronics. Layer transfer techniques are the dominating global integration approach over the whole wafer system but are difficult to scale down for local integration purposes limited to the area of the future device. In this respect, the heteroepitaxy approach by two simple subsequent epitaxial deposition steps of the oxide and the Si thin film is a promising way. We introduce tailored (Pr2O3)1-x(Y2O3)x oxide heterostructures on Si(111) as flexible heteroepitaxy concept for the integration of either strained or fully relaxed single crystalline Si thin films. Two different buffer concepts are explored by a combined experimental and theoretical study. First, the growth of fully relaxed single crystalline Si films is achieved by the growth of mixed PrYO3 insulators on Si(111) whose lattice constant is matched to Si. Second, isomorphic oxide-on-oxide epitaxy is exploited to grow strained Si films on lattice mismatched Y2O3/Pr2O3/Si(111) support systems. A thickness dependent multilayer model, based on Matthew's approach for strain relaxation by misfit dislocations, is presented to describe the experimental data.

  20. Integration of an Axcelis Optima HD Single Wafer High Current Implanter for p- and n-S/D Implants in an Existing Batch Implanter Production Line

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Schmeide, Matthias; Kontratenko, Serguei; Krimbacher, Bernhard

    2008-11-03

    This paper is focused on the integration and qualification of an Axcelis Optima HD single wafer high current spot beam implanter in an existing 200 mm production line with different types of Axcelis batch implanters for high current applications. Both the design of the beamline and the beam shape are comparable between single wafer and batch high current spot beam implanters. In contrast to the single wafer high current ribbon beam implanter, energy contamination is not a concern for the considered spot beam tool because the drift mode can be used down to energies in the 2 keV region. Themore » most important difference between single wafer and batch high current implanters is the significantly higher dose rate and, therefore, the higher damage rate for the single wafer tool due to the different scanning architecture. The results of the integration of high dose implantations, mainly for p- and n-S/D formation, for DRAM 110 nm without pre-amorphization implantation (PAI), CMOS Logic from around 250 nm down to 90 nm without and with PAI, are presented and discussed. Dopant concentration profile analysis using SIMS was performed for different technologies and implantation conditions. The impurity activation was measured using sheet resistance and in some cases spreading resistance technique was applied. The amorphous layer thickness was measured using TEM. Finally, device data are presented in combination with dose, energy and beam current variations. The results have shown that the integration of implantation processes into crystalline structure without PAI is more complex and time consuming than implantations into amorphous layer where the damage difference due to the different dose rates is negligible.« less

  1. Wafer-size free-standing single-crystalline graphene device arrays

    NASA Astrophysics Data System (ADS)

    Li, Peng; Jing, Gaoshan; Zhang, Bo; Sando, Shota; Cui, Tianhong

    2014-08-01

    We report an approach of wafer-scale addressable single-crystalline graphene (SCG) arrays growth by using pre-patterned seeds to control the nucleation. The growth mechanism and superb properties of SCG were studied. Large array of free-standing SCG devices were realized. Characterization of SCG as nano switches shows excellent performance with life time (>22 000 times) two orders longer than that of other graphene nano switches reported so far. This work not only shows the possibility of producing wafer-scale high quality SCG device arrays but also explores the superb performance of SCG as nano devices.

  2. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

    PubMed

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-05-13

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

  3. Single-shot optical recorder with sub-picosecond resolution and scalable record length on a semiconductor wafer

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Muir, R.; Heebner, J.

    In this study, we demonstrate a novel, single-shot recording technology for transient optical signals. A resolution of 0.4 ps over a record length of 54 ps was demonstrated. Here, a pump pulse crossing through a signal samples a diagonal “slice” of space–time, enabling a camera to record spatially the time content of the signal. Unlike related X (2)-based cross-correlation techniques, here the signal is sampled through optically pumped carriers that modify the refractive index of a silicon wafer. Surrounding the wafer with birefringent retarders enables two time-staggered, orthogonally polarized signal copies to probe the wafer. Recombining the copies at amore » final crossed polarizer destructively interferes with them, except during the brief stagger window, where a differential phase shift is incurred. This enables the integrating response of the rapidly excited but persistent carriers to be optically differentiated. Lastly, this sampling mechanism has several advantages that enable scaling to long record lengths, including making use of large, inexpensive semiconductor wafers, eliminating the need for phase matching, broad insensitivity to the spectral and angular properties of the pump, and overall hardware simplicity.« less

  4. Single-shot optical recorder with sub-picosecond resolution and scalable record length on a semiconductor wafer

    DOE PAGES

    Muir, R.; Heebner, J.

    2017-10-24

    In this study, we demonstrate a novel, single-shot recording technology for transient optical signals. A resolution of 0.4 ps over a record length of 54 ps was demonstrated. Here, a pump pulse crossing through a signal samples a diagonal “slice” of space–time, enabling a camera to record spatially the time content of the signal. Unlike related X (2)-based cross-correlation techniques, here the signal is sampled through optically pumped carriers that modify the refractive index of a silicon wafer. Surrounding the wafer with birefringent retarders enables two time-staggered, orthogonally polarized signal copies to probe the wafer. Recombining the copies at amore » final crossed polarizer destructively interferes with them, except during the brief stagger window, where a differential phase shift is incurred. This enables the integrating response of the rapidly excited but persistent carriers to be optically differentiated. Lastly, this sampling mechanism has several advantages that enable scaling to long record lengths, including making use of large, inexpensive semiconductor wafers, eliminating the need for phase matching, broad insensitivity to the spectral and angular properties of the pump, and overall hardware simplicity.« less

  5. Micro-scale heat-exchangers for Joule-Thomson cooling.

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Gross, Andrew John

    2014-01-01

    This project focused on developing a micro-scale counter flow heat exchangers for Joule-Thomson cooling with the potential for both chip and wafer scale integration. This project is differentiated from previous work by focusing on planar, thin film micromachining instead of bulk materials. A process will be developed for fabricating all the devices mentioned above, allowing for highly integrated micro heat exchangers. The use of thin film dielectrics provides thermal isolation, increasing efficiency of the coolers compared to designs based on bulk materials, and it will allow for wafer-scale fabrication and integration. The process is intended to implement a CFHX asmore » part of a Joule-Thomson cooling system for applications with heat loads less than 1mW. This report presents simulation results and investigation of a fabrication process for such devices.« less

  6. Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

    PubMed

    Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

    2014-01-09

    Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

  7. Wafer-scale production of highly uniform two-dimensional MoS2 by metal-organic chemical vapor deposition

    NASA Astrophysics Data System (ADS)

    Kim, TaeWan; Mun, Jihun; Park, Hyeji; Joung, DaeHwa; Diware, Mangesh; Won, Chegal; Park, Jonghoo; Jeong, Soo-Hwan; Kang, Sang-Woo

    2017-05-01

    Semiconducting two-dimensional (2D) materials, particularly extremely thin molybdenum disulfide (MoS2) films, are attracting considerable attention from academia and industry owing to their distinctive optical and electrical properties. Here, we present the direct growth of a MoS2 monolayer with unprecedented spatial and structural uniformity across an entire 8 inch SiO2/Si wafer. The influences of growth pressure, ambient gases (Ar, H2), and S/Mo molar flow ratio on the MoS2 layered growth were explored by considering the domain size, nucleation sites, morphology, and impurity incorporation. Monolayer MoS2-based field effect transistors achieve an electron mobility of 0.47 cm2 V-1 s-1 and on/off current ratio of 5.4 × 104. This work demonstrates the potential for reliable wafer-scale production of 2D MoS2 for practical applications in next-generation electronic and optical devices.

  8. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  9. Structured wafer for device processing

    DOEpatents

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  10. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    PubMed Central

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  11. Transfer of InP epilayers by wafer bonding

    NASA Astrophysics Data System (ADS)

    Hjort, Klas

    2004-08-01

    Wafer bonding increases the freedom of design in the integration of dissimilar materials. For example, it is interesting to combine III-V compounds that have direct band gap and high mobility with silicon (Si) that is extensively used in microelectronic applications. The interest to integrate III-V-based materials with Si arises primarily from two types of applications: smart pixels for optical intra- and inter-chip interconnects in the so-called optoelectronic integrated circuits, and optoelectronic devices using some material advantages of combining III-V with Si. Also, in the III-V industry larger substrates are crucial for higher efficiency in high-volume production, and especially so for monolithic microwave integrated circuits (MMIC). For indium phosphide (InP) the development of large-area substrates has not been able to keep up with market demands. One way to circumvent this problem is to use silicon substrates that are large-area, low-cost, and mechanically strong with high thermal conductivity. In addition, silicon is transparent at the emission wavelengths most often used in InP-based optoelectronics. Unfortunately, the large lattice-mismatch, 8.1%, between silicon and InP, has limited the success of heteroepitaxial growth. Hence, one alternative to be reviewed is InP-to-Si wafer bonding. When a direct semiconductor interface is not needed there are several other means of wafer bonding, e.g. adhesive, eutectic, and solid-state. These processes can be used for direct integration of small islets of epitaxially thin InP microelectronics onto other substrates, e.g. by transferring of InP-based epilayers to a Si-based microwave circuit by pick-and-place, BCB resist adhesive bonding and sacrificing of the InP substrate.

  12. Wafer-shape metrics based foundry lithography

    NASA Astrophysics Data System (ADS)

    Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

    2017-03-01

    As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

  13. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  14. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  15. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

    DOE PAGES

    Berman, Diana; Deshmukh, Sanket; Narayanan, Badri; ...

    2016-07-04

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here in this article, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the processmore » can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. Additionally, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.« less

  16. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Berman, Diana; Deshmukh, Sanket; Narayanan, Badri

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here in this article, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the processmore » can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. Additionally, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.« less

  17. Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

    NASA Astrophysics Data System (ADS)

    Turner, K. T.; Spearing, S. M.

    2002-12-01

    Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

  18. Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

    NASA Astrophysics Data System (ADS)

    Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

    2015-07-01

    Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

  19. Investigation of radiation hardened SOI wafer fabricated by ion-cut technique

    NASA Astrophysics Data System (ADS)

    Chang, Yongwei; Wei, Xing; Zhu, Lei; Su, Xin; Gao, Nan; Dong, Yemin

    2018-07-01

    Total ionizing dose (TID) effect on Silicon-on-Insulator (SOI) wafers due to inherent buried oxide (BOX) is a significant concern as it leads to the degradation of electrical properties of SOI-based devices and circuits, even failures of the systems associated with them. This paper reports the radiation hardening implementation of SOI wafer fabricated by ion-cut technique integrated with low-energy Si+ implantation. The electrical properties and radiation response of pseudo-MOS transistors are analyzed. The results demonstrate that the hardening process can significantly improve the TID tolerance of SOI wafers by generating Si nanocrystals (Si-NCs) within the BOX. The presence of Si-NCs created through Si+ implantation is evidenced by high-resolution transmission electron microscopy (HR-TEM). Under the pass gate (PG) irradiation bias, the anti-radiation properties of H-gate SOI nMOSFETs suggest that the radiation hardened SOI wafers with optimized Si implantation dose can perform effectively in a radiation environment. The radiation hardening process provides an excellent way to reinforce the TID tolerance of SOI wafers.

  20. Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

    NASA Astrophysics Data System (ADS)

    Chen, Po-Ying

    2008-12-01

    Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

  1. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  2. Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

    PubMed

    Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

    2017-10-01

    Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

  3. Wafer-scale design of lightweight and transparent electronics that wraps around hairs

    NASA Astrophysics Data System (ADS)

    Salvatore, Giovanni A.; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

    2014-01-01

    Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

  4. New optoelectronic methodology for nondestructive evaluation of MEMS at the wafer level

    NASA Astrophysics Data System (ADS)

    Furlong, Cosme; Ferguson, Curtis F.; Melson, Michael J.

    2004-02-01

    One of the approaches to fabrication of MEMS involves surface micromachining to define dies on single crystal silicon wafers, dicing of the wafers to separate the dies, and electronic packaging of the individual dies. Dicing and packaging of MEMS accounts for a large fraction of the fabrication costs, therefore, nondestructive evaluation at the wafer level, before dicing, can have significant implications on improving production yield and costs. In this paper, advances in development of optoelectronic holography (OEH) techniques for nondestructive, noninvasive, full-field of view evaluation of MEMS at the wafer level are described. With OEH techniques, quantitative measurements of shape and deformation of MEMS, as related to their performance and integrity, are obtained with sub-micrometer spatial resolution and nanometer measuring accuracy. To inspect an entire wafer with OEH methodologies, measurements of overlapping regions of interest (ROI) on a wafer are recorded and adjacent ROIs are stitched together through efficient 3D correlation analysis algorithms. Capabilities of the OEH techniques are illustrated with representative applications, including determination of optimal inspection conditions to minimize inspection time while achieving sufficient levels of accuracy and resolution.

  5. Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress

    NASA Astrophysics Data System (ADS)

    Chen, Po-Ying; Kung, Heng-Yu; Lai, Yi-Shao; Hsiung Tsai, Ming; Yeh, Wen-Kuan

    2008-02-01

    In this work, we present a novel approach and method for elucidating the characteristics of wafer-level chip-scale packages (WLCSPs) for electromigration (EM) tests. The die in WLCSP was directly attached to the substrate via a soldered interconnect. The shrinking of the area of the die that is available for power, and the solder bump also shrinks the volume and increases the density of electrons for interconnect efficiency. The bump current density now approaches to 106 A/cm2, at which point the EM becomes a significant reliability issue. As known, the EM failure depends on numerous factors, including the working temperature and the under bump metallization (UBM) thickness. A new interconnection geometry is adopted extensively with moderate success in overcoming larger mismatches between the displacements of components during current and temperature changes. Both environments and testing parameters for WLCSP are increasingly demanded. Although failure mechanisms are considered to have been eliminated or at least made manageable, new package technologies are again challenging its process, integrity and reliability. WLCSP technology was developed to eliminate the need for encapsulation to ensure compatibility with smart-mount technology (SMT). The package has good handing properties but is now facing serious reliability problems. In this work, we investigated the reliability of a WLCSP subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 °C. A very strong correlation exists between the mean time to failure (MTTF) of the WLCSP test vehicle and the mean current density that is carried by a solder joint. A series of current densities were applied to the WLCSP architecture; Black's power law was employed in a failure mode simulation. Additionally, scanning electron microscopy (SEM) was adopted to determine the differences existing between high- and low-current-density failure modes.

  6. Consequences of atomic layer etching on wafer scale uniformity in inductively coupled plasmas

    NASA Astrophysics Data System (ADS)

    Huard, Chad M.; Lanham, Steven J.; Kushner, Mark J.

    2018-04-01

    Atomic layer etching (ALE) typically divides the etching process into two self-limited reactions. One reaction passivates a single layer of material while the second preferentially removes the passivated layer. As such, under ideal conditions the wafer scale uniformity of ALE should be independent of the uniformity of the reactant fluxes onto the wafers, provided all surface reactions are saturated. The passivation and etch steps should individually asymptotically saturate after a characteristic fluence of reactants has been delivered to each site. In this paper, results from a computational investigation are discussed regarding the uniformity of ALE of Si in Cl2 containing inductively coupled plasmas when the reactant fluxes are both non-uniform and non-ideal. In the parameter space investigated for inductively coupled plasmas, the local etch rate for continuous processing was proportional to the ion flux. When operated with saturated conditions (that is, both ALE steps are allowed to self-terminate), the ALE process is less sensitive to non-uniformities in the incoming ion flux than continuous etching. Operating ALE in a sub-saturation regime resulted in less uniform etching. It was also found that ALE processing with saturated steps requires a larger total ion fluence than continuous etching to achieve the same etch depth. This condition may result in increased resist erosion and/or damage to stopping layers using ALE. While these results demonstrate that ALE provides increased etch depth uniformity, they do not show an improved critical dimension uniformity in all cases. These possible limitations to ALE processing, as well as increased processing time, will be part of the process optimization that includes the benefits of atomic resolution and improved uniformity.

  7. Radiation-Hardened Wafer Scale Integration

    DTIC Science & Technology

    1989-10-25

    unlimited. LEXINGTON MASSACHUSETTS EXECUTIVE SUMMARY A focal plane processor (FPP) for a large array of LWIR photodetectors on a space platform must...It seems certain that large. scanning LWIR arrays will once again be of interest in the future, though their specifications will differ from those... nonuniformity and defects in the ZMR material, but films of good quality produced by this technique are now available commercially from Kopin Corporation. Such

  8. Control wafer bow of InGaP on 200 mm Si by strain engineering

    NASA Astrophysics Data System (ADS)

    Wang, Bing; Bao, Shuyu; Made, Riko I.; Lee, Kwang Hong; Wang, Cong; Eng Kian Lee, Kenneth; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-12-01

    When epitaxially growing III-V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III-V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III-V semiconductors on large size Si substrates.

  9. Sidewall patterning—a new wafer-scale method for accurate patterning of vertical silicon structures

    NASA Astrophysics Data System (ADS)

    Westerik, P. J.; Vijselaar, W. J. C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G. E.

    2018-01-01

    For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that allows for reproducible sub-micrometer resolution local modification along vertical silicon sidewalls. Instead of optical lithography, this method makes smart use of inclined ion beam etching to selectively etch the top parts of structures, and controlled retraction of a conformal layer to define a hard mask in the vertical direction. The top, bottom or middle part of a structure could be selectively exposed, and it was shown that these exposed regions can, for example, be selectively covered with a catalyst, doped, or structured further.

  10. Impurity engineering of Czochralski silicon used for ultra large-scaled-integrated circuits

    NASA Astrophysics Data System (ADS)

    Yang, Deren; Chen, Jiahe; Ma, Xiangyang; Que, Duanlin

    2009-01-01

    Impurities in Czochralski silicon (Cz-Si) used for ultra large-scaled-integrated (ULSI) circuits have been believed to deteriorate the performance of devices. In this paper, a review of the recent processes from our investigation on internal gettering in Cz-Si wafers which were doped with nitrogen, germanium and/or high content of carbon is presented. It has been suggested that those impurities enhance oxygen precipitation, and create both denser bulk microdefects and enough denuded zone with the desirable width, which is benefit of the internal gettering of metal contamination. Based on the experimental facts, a potential mechanism of impurity doping on the internal gettering structure is interpreted and, a new concept of 'impurity engineering' for Cz-Si used for ULSI is proposed.

  11. Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

    PubMed

    Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

    2013-03-25

    n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

  12. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  13. Wafer-Scale and Wrinkle-Free Epitaxial Growth of Single-Orientated Multilayer Hexagonal Boron Nitride on Sapphire.

    PubMed

    Jang, A-Rang; Hong, Seokmo; Hyun, Chohee; Yoon, Seong In; Kim, Gwangwoo; Jeong, Hu Young; Shin, Tae Joo; Park, Sung O; Wong, Kester; Kwak, Sang Kyu; Park, Noejung; Yu, Kwangnam; Choi, Eunjip; Mishchenko, Artem; Withers, Freddie; Novoselov, Kostya S; Lim, Hyunseob; Shin, Hyeon Suk

    2016-05-11

    Large-scale growth of high-quality hexagonal boron nitride has been a challenge in two-dimensional-material-based electronics. Herein, we present wafer-scale and wrinkle-free epitaxial growth of multilayer hexagonal boron nitride on a sapphire substrate by using high-temperature and low-pressure chemical vapor deposition. Microscopic and spectroscopic investigations and theoretical calculations reveal that synthesized hexagonal boron nitride has a single rotational orientation with AA' stacking order. A facile method for transferring hexagonal boron nitride onto other target substrates was developed, which provides the opportunity for using hexagonal boron nitride as a substrate in practical electronic circuits. A graphene field effect transistor fabricated on our hexagonal boron nitride sheets shows clear quantum oscillation and highly improved carrier mobility because the ultraflatness of the hexagonal boron nitride surface can reduce the substrate-induced degradation of the carrier mobility of two-dimensional materials.

  14. Through-wafer interrogation of microstructure motion for MEMS feedback control

    NASA Astrophysics Data System (ADS)

    Dawson, Jeremy M.; Chen, Jingdong; Brown, Kolin S.; Famouri, Parviz F.; Hornak, Lawrence A.

    1999-09-01

    Closed-loop MEMS control enables mechanical microsystems to adapt to the demands of the environment which they are actuating opening a new window of opportunity for future MEMS applications. Planar diffractive optical microsystems have the potential to enable the integrated optical interrogation of MEMS microstructure position fully decoupled from the means of mechanical actuation which is central to realization of feedback control. This paper presents the results of initial research evaluating through-wafer optical microsystems for MEMS integrated optical monitoring. Positional monitoring results obtained from a 1.3 micrometer wavelength through- wafer free-space optical probe of a lateral comb resonator fabricated using the Multi-User MEMS Process Service (MUMPS) are presented. Given the availability of positional information via probe signal feedback, a simulation of the application of nonlinear sliding control is presented illustrating position control of the lateral comb resonator structure.

  15. Wafer characteristics via reflectometry

    DOEpatents

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  16. Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell#

    PubMed Central

    Poghossian, Arshak; Schumacher, Kerstin; Kloock, Joachim P.; Rosenkranz, Christian; Schultze, Joachim W.; Müller-Veggian, Mattea; Schöning, Michael J.

    2006-01-01

    A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor) is realised by means of integration of a specifically designed capillary electrochemical micro-droplet cell into a commercial wafer prober-station. The developed system allows the identification and selection of “good” ISFETs at the earliest stage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. The developed system is also feasible for wafer-level characterisation of ISFETs in terms of sensitivity, hysteresis and response time. Additionally, the system might be also utilised for wafer-level testing of further electrochemical sensors.

  17. Effect of wafer geometry on lithography chucking processes

    NASA Astrophysics Data System (ADS)

    Turner, Kevin T.; Sinha, Jaydeep K.

    2015-03-01

    Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

  18. New getter configuration at wafer level for assuring long term stability of MEMs

    NASA Astrophysics Data System (ADS)

    Moraja, Marco; Amiotti, Marco; Kullberg, Richard C.

    2003-01-01

    The evolution from ceramic packages to wafer to wafer hermetic sealing poses tremendous technical challenges to integrate a proper getter inside the MEMs to assure a long term stability and reliability of the devices. The state of the art solution to integrate a getter inside the MEMs of the last generation consists in patterning the getter material with a specific geometry onto the Si cap wafer. The practical implementation of this solution consists in a 4" or 6" Si wafers with grooves or particular incisures, where the getter material is placed in form of a thick film. The typical thickness of these thick films is in the range of few microns, depending on the gas load to be handled during the lifetime of the device. The structure of the thick getter film is highly porous in order to improve sorption performances, but at the same time there are no loose particles thanks to a proprietary manufacturing method. The getter thick film is composed of a Zr special alloy with a proper composition to optimize the sorption performances. The getter thick film can be placed selectively into grooves without affecting the lateral regions, surrounding the grooves where the hermetic sealing is performed.

  19. Wafer-scale self-organized InP nanopillars with controlled orientation for photovoltaic devices.

    PubMed

    Sanatinia, Reza; Berrier, Audrey; Dhaka, Veer; Perros, Alexander P; Huhtio, Teppo; Lipsanen, Harri; Anand, Srinivasan

    2015-10-16

    A unique wafer-scale self-organization process for generation of InP nanopillars is demonstrated, which is based on maskless ion-beam etching (IBE) of InP developed to obtain the nanopillars, where the height, shape, and orientation of the nanopillars can be varied by controlling the processing parameters. The fabricated InP nanopillars exhibit broadband suppression of the reflectance, 'black InP,' a property useful for solar cells. The realization of a conformal p-n junction for carrier collection, in the fabricated solar cells, is achieved by a metalorganic vapor phase epitaxy (MOVPE) overgrowth step on the fabricated pillars. The conformal overgrowth retains the broadband anti-reflection property of the InP nanopillars, indicating the feasibility of this technology for solar cells. Surface passivation of the formed InP nanopillars using sulfur-oleylamine solution resulted in improved solar-cell characteristics. An open-circuit voltage of 0.71 V and an increase of 0.13 V compared to the unpassivated device were achieved.

  20. Low-Temperature Wafer-Scale Deposition of Continuous 2D SnS2 Films.

    PubMed

    Mattinen, Miika; King, Peter J; Khriachtchev, Leonid; Meinander, Kristoffer; Gibbon, James T; Dhanak, Vin R; Räisänen, Jyrki; Ritala, Mikko; Leskelä, Markku

    2018-04-19

    Semiconducting 2D materials, such as SnS 2 , hold immense potential for many applications ranging from electronics to catalysis. However, deposition of few-layer SnS 2 films has remained a great challenge. Herein, continuous wafer-scale 2D SnS 2 films with accurately controlled thickness (2 to 10 monolayers) are realized by combining a new atomic layer deposition process with low-temperature (250 °C) postdeposition annealing. Uniform coating of large-area and 3D substrates is demonstrated owing to the unique self-limiting growth mechanism of atomic layer deposition. Detailed characterization confirms the 1T-type crystal structure and composition, smoothness, and continuity of the SnS 2 films. A two-stage deposition process is also introduced to improve the texture of the films. Successful deposition of continuous, high-quality SnS 2 films at low temperatures constitutes a crucial step toward various applications of 2D semiconductors. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  1. Carbon dioxide capture using resin-wafer electrodeionization

    DOEpatents

    Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

    2015-09-08

    The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

  2. High-κ Al2O3 material in low temperature wafer-level bonding for 3D integration application

    NASA Astrophysics Data System (ADS)

    Fan, J.; Tu, L. C.; Tan, C. S.

    2014-03-01

    This work systematically investigated a high-κ Al2O3 material for low temperature wafer-level bonding for potential applications in 3D microsystems. A clean Si wafer with an Al2O3 layer thickness of 50 nm was applied as our experimental approach. Bonding was initiated in a clean room ambient after surface activation, followed by annealing under inert ambient conditions at 300 °C for 3 h. The investigation consisted of three parts: a mechanical support study using the four-point bending method, hermeticity measurements using the helium bomb test, and thermal conductivity analysis for potential heterogeneous bonding. Compared with samples bonded using a conventional oxide bonding material (SiO2), a higher interfacial adhesion energy (˜11.93 J/m2) and a lower helium leak rate (˜6.84 × 10-10 atm.cm3/sec) were detected for samples bonded using Al2O3. More importantly, due to the excellent thermal conductivity performance of Al2O3, this technology can be used in heterogeneous direct bonding, which has potential applications for enhancing the performance of Si photonic integrated devices.

  3. Methane production using resin-wafer electrodeionization

    DOEpatents

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  4. Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers

    NASA Technical Reports Server (NTRS)

    Anthony, Thomas R. (Inventor)

    1983-01-01

    Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.

  5. 1.3-microm optically-pumped semiconductor disk laser by wafer fusion.

    PubMed

    Lyytikäinen, Jari; Rautiainen, Jussi; Toikkanen, Lauri; Sirbu, Alexei; Mereuta, Alexandru; Caliman, Andrei; Kapon, Eli; Okhotnikov, Oleg G

    2009-05-25

    We report a wafer-fused high power optically-pumped semiconductor disk laser operating at 1.3 microm. An InP-based active medium was fused with a GaAs/AlGaAs distributed Bragg reflector, resulting in an integrated monolithic gain mirror. Over 2.7 W of output power, obtained at temperature of 15 degrees C, represents the best achievement reported to date for this type of lasers. The results reveal an essential advantage of the wafer fusing technique over both monolithically grown AlGaInAs/GaInAsP- and GaInNAs-based structures.

  6. Advances in process overlay on 300-mm wafers

    NASA Astrophysics Data System (ADS)

    Staecker, Jens; Arendt, Stefanie; Schumacher, Karl; Mos, Evert C.; van Haren, Richard J. F.; van der Schaar, Maurits; Edart, Remi; Demmerle, Wolfgang; Tolsma, Hoite

    2002-07-01

    Overlay budgets are getting tighter within 300 mm volume production and as a consequence the process effects on alignment and off-line metrology becomes more important. In a short loop experiment, with cleared reference marks in each image field, the isolated effect of processing was measured with a sub-nanometer accuracy. The examined processes are Shallow Trench Isolation (STI), Tungsten-Chemical Mechanical Processing (W-CMP) and resist spinning. The alignment measurements were done on an ASML TWINSCANT scanner and the off-line metrology measurements on a KLA Tencor. Mark type and mark position dependency of the process effects are analyzed. The mean plus 3 (sigma) of the maximum overlay after correcting batch average wafer parameters is used as an overlay performance indicator (OPI). 3 (sigma) residuals to the wafer-model are used as an indicator of the noise that is added by the process. The results are in agreement with existing knowledge of process effects on 200 mm wafers. The W-CMP process introduces an additional wafer rotation and scaling that is similar for alignment marks and metrology targets. The effects depend on the mark type; in general they get less severe for higher spatial frequencies. For a 7th order alignment mark, the OPI measured about 12 nm and the added noise about 12 nm. For the examined metrology targets the OPI is about 20 nm with an added noise of about 90 nm. Two different types of alignment marks were tested in the STI process, i.e., zero layer marks and marks that were exposed together with the STI product. The overlay contribution due to processing on both types of alignment marks is very low (smaller than 5 nm OPI) and independent on mark type. Some flyers are observed fot the zero layer marks. The flyers can be explained by the residues of oxide and nitride that is left behind in the spaces of the alignment marks. Resist spinning is examined on single layer resist and resist with an organic Bottom Anti-Reflective Coating (BARC

  7. 450mm wafer patterning with jet and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  8. Interferometric thickness calibration of 300 mm silicon wafers

    NASA Astrophysics Data System (ADS)

    Wang, Quandou; Griesmann, Ulf; Polvani, Robert

    2005-12-01

    The "Improved Infrared Interferometer" (IR 3) at the National Institute of Standards and Technology (NIST) is a phase-measuring interferometer, operating at a wavelength of 1550 nm, which is being developed for measuring the thickness and thickness variation of low-doped silicon wafers with diameters up to 300 mm. The purpose of the interferometer is to produce calibrated silicon wafers, with a certified measurement uncertainty, which can be used as reference wafers by wafer manufacturers and metrology tool manufacturers. We give an overview of the design of the interferometer and discuss its application to wafer thickness measurements. The conversion of optical thickness, as measured by the interferometer, to the wafer thickness requires knowledge of the refractive index of the material of the wafer. We describe a method for measuring the refractive index which is then used to establish absolute thickness and thickness variation maps for the wafer.

  9. Temperature Dependent Electrical Properties of PZT Wafer

    NASA Astrophysics Data System (ADS)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  10. Porous solid ion exchange wafer for immobilizing biomolecules

    DOEpatents

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  11. Wafer-level colinearity monitoring for TFH applications

    NASA Astrophysics Data System (ADS)

    Moore, Patrick; Newman, Gary; Abreau, Kelly J.

    2000-06-01

    a method of quickly estimating colinearity at the wafer-level with a test reticle and metrology equipment routinely found in TFH facilities. Colinearity results are correlated to slider-fab measurements on production devices. Stepper contributions to colinearity are estimated, and compared across multiple steppers and stepper generations. Multiple techniques of integrating this diagnostic into production are investigated and discussed.

  12. Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

    NASA Astrophysics Data System (ADS)

    Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

    2012-05-01

    In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

  13. Contacting graphene in a 200 mm wafer silicon technology environment

    NASA Astrophysics Data System (ADS)

    Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

    2018-06-01

    Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

  14. The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line

    NASA Astrophysics Data System (ADS)

    Lee, Jeffrey; McGarvey, Steve

    2013-04-01

    The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the

  15. A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

    PubMed

    Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

    2012-07-01

    We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

  16. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y.; James, Ralph B.

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  17. Post exposure bake unit equipped with wafer-shape compensation technology

    NASA Astrophysics Data System (ADS)

    Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

    2007-03-01

    In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

  18. "Performance Of A Wafer Stepper With Automatic Intra-Die Registration Correction."

    NASA Astrophysics Data System (ADS)

    van den Brink, M. A.; Wittekoek, S.; Linders, H. F. D.; van Hout, F. J.; George, R. A.

    1987-01-01

    An evaluation of a wafer stepper with the new improved Philips/ASM-L phase grating alignment system is reported. It is shown that an accurate alignment system needs an accurate X-Y-0 wafer stage and an accurate reticle Z stage to realize optimum overlay accuracy. This follows from a discussion of the overlay budget and an alignment procedure model. The accurate wafer stage permits high overlay accuracy using global alignment only, thus eliminating the throughput penalty of align-by-field schemes. The accurate reticle Z stage enables an intra-die magnification control with respect to the wafer scale. Various overlay data are reported, which have been measured with the automatic metrology program of the stepper. It is demonstrated that the new dual alignment system (with the external spatial filter) has improved the ability to align to weakly reflecting layers. The results are supported by a Fourier analysis of the alignment signal. Resolution data are given for the PAS 2500 projection lenses, which show that the high overlay accuracy of the system is properly matched with submicron linewidth control. The results of a recently introduced 20mm i-line lens with a numerical aperture of 0.4 (Zeiss 10-78-58) are included.

  19. Forming electrical interconnections through semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Anthony, T. R.

    1981-01-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  20. Evaluation of a cyanoacrylate dressing to manage peristomal skin alterations under ostomy skin barrier wafers.

    PubMed

    Milne, Catherine T; Saucier, Darlene; Trevellini, Chenel; Smith, Juliet

    2011-01-01

    Peristomal skin alterations under ostomy barrier wafers are a commonly reported problem. While a number of interventions to manage this issue have been reported, the use of a topically applied cyanoacrylate has received little attention. This case series describes the use of a topical cyanoacrylate for the management of peristomal skin alterations in persons living with an ostomy. Using a convenience sample, the topical cyanoacrylate dressing was applied to 11 patients with peristomal skin disruption under ostomy wafers in acute care and outpatient settings. The causes of barrier function interruption were also addressed to enhance outcomes. Patients were assessed for wound discomfort using a Likert Scale, time to healing, and number of appliance changes. Patient satisfaction was also examined. Average reported discomfort levels were 9.5 out of 10 at the initial peristomal irritation assessment visit decreased to 3.5 at the first wafer change and were absent by the second wafer change. Wafers had increasing wear time between changes in both settings with acute care patients responding faster. Epidermal resurfacing occurred within 10.2 days in outpatients and within 7 days in acute care patients. Because of the skin sealant action of this dressing, immediate adherence of the wafer was reported at all pouch changes.

  1. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R.

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  2. Wafer defect detection by a polarization-insensitive external differential interference contrast module.

    PubMed

    Nativ, Amit; Feldman, Haim; Shaked, Natan T

    2018-05-01

    We present a system that is based on a new external, polarization-insensitive differential interference contrast (DIC) module specifically adapted for detecting defects in semiconductor wafers. We obtained defect signal enhancement relative to the surrounding wafer pattern when compared with bright-field imaging. The new DIC module proposed is based on a shearing interferometer that connects externally at the output port of an optical microscope and enables imaging thin samples, such as wafer defects. This module does not require polarization optics (such as Wollaston or Nomarski prisms) and is insensitive to polarization, unlike traditional DIC techniques. In addition, it provides full control of the DIC shear and orientation, which allows obtaining a differential phase image directly on the camera (with no further digital processing) while enhancing defect detection capabilities, even if the size of the defect is smaller than the resolution limit. Our technique has the potential of future integration into semiconductor production lines.

  3. Noncontact sheet resistance measurement technique for wafer inspection

    NASA Astrophysics Data System (ADS)

    Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

    1995-12-01

    A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

  4. Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage.

    PubMed

    Rack, Alexander; Scheel, Mario; Danilewsky, Andreas N

    2016-03-01

    Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1-2 ms followed by jumps faster than 2-6 m s(-1), leading to a macroscopically observed average velocity of 0.028-0.055 m s(-1). The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound.

  5. Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

    NASA Technical Reports Server (NTRS)

    Buehler, M. G. (Inventor)

    1985-01-01

    An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

  6. Wafer-scale Fabrication of Non-Polar Mesoporous GaN Distributed Bragg Reflectors via Electrochemical Porosification.

    PubMed

    Zhu, Tongtong; Liu, Yingjun; Ding, Tao; Fu, Wai Yuen; Jarman, John; Ren, Christopher Xiang; Kumar, R Vasant; Oliver, Rachel A

    2017-03-27

    Distributed Bragg reflectors (DBRs) are essential components for the development of optoelectronic devices. For many device applications, it is highly desirable to achieve not only high reflectivity and low absorption, but also good conductivity to allow effective electrical injection of charges. Here, we demonstrate the wafer-scale fabrication of highly reflective and conductive non-polar gallium nitride (GaN) DBRs, consisting of perfectly lattice-matched non-polar (11-20) GaN and mesoporous GaN layers that are obtained by a facile one-step electrochemical etching method without any extra processing steps. The GaN/mesoporous GaN DBRs exhibit high peak reflectivities (>96%) across the entire visible spectrum and wide spectral stop-band widths (full-width at half-maximum >80 nm), while preserving the material quality and showing good electrical conductivity. Such mesoporous GaN DBRs thus provide a promising and scalable platform for high performance GaN-based optoelectronic, photonic, and quantum photonic devices.

  7. Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy

    PubMed Central

    Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

    2013-01-01

    The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (“metasurfaces”) can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

  8. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  9. Switchable static friction of piezoelectric composite—silicon wafer contacts

    NASA Astrophysics Data System (ADS)

    van den Ende, D. A.; Fischer, H. R.; Groen, W. A.; van der Zwaag, S.

    2013-04-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and a silicon wafer counter surface rests solely on the matrix region of the piezocomposite surface. When actuated, the piezoelectric ceramic fibers protrude from the surface and the wafer rests solely on these protrusions. A threefold decrease in engineering static friction coefficient upon actuation of the piezocomposite was observed: from μ* = 1.65 to μ* = 0.50. These experimental results could be linked to the change in contact surface area and roughness using capillary adhesion theory, which relates the adhesive force to the number and size of the contacting asperities for the different surface states.

  10. Through-wafer optical probe characterization for microelectromechanical systems positional state monitoring and feedback control

    NASA Astrophysics Data System (ADS)

    Dawson, Jeremy M.; Chen, Jingdong; Brown, Kolin S.; Famouri, Parviz F.; Hornak, Lawrence A.

    2000-12-01

    Implementation of closed-loop microelectromechanical system (MEMS) control enables mechanical microsystems to adapt to the demands of the environment that they are actuating, opening a broad range of new opportunities for future MEMS applications. Integrated optical microsystems have the potential to enable continuous in situ optical interrogation of MEMS microstructure position fully decoupled from the means of mechanical actuation that is necessary for realization of feedback control. We present the results of initial research evaluating through-wafer optical microprobes for surface micromachined MEMS integrated optical position monitoring. Results from the through-wafer free-space optical probe of a lateral comb resonator fabricated using the multiuser MEMS process service (MUMPS) indicate significant positional information content with an achievable return probe signal dynamic range of up to 80% arising from film transmission contrast. Static and dynamic deflection analysis and experimental results indicate a through-wafer probe positional signal sensitivity of 40 mV/micrometers for the present setup or 10% signal change per micrometer. A simulation of the application of nonlinear sliding control is presented illustrating position control of the lateral comb resonator structure given the availability of positional state information.

  11. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  12. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; hide

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  13. Patterned wafer geometry grouping for improved overlay control

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Han, Sangjun; Woo, Jaeson; Park, Junbeom; Song, Changrock; Anis, Fatima; Vukkadala, Pradeep; Jeon, Sanghuck; Choi, DongSub; Huang, Kevin; Heo, Hoyoung; Smith, Mark D.; Robinson, John C.

    2017-03-01

    Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

  14. Highly Transparent Wafer-Scale Synthesis of Crystalline WS2 Nanoparticle Thin Film for Photodetector and Humidity-Sensing Applications.

    PubMed

    Pawbake, Amit S; Waykar, Ravindra G; Late, Dattatray J; Jadkar, Sandesh R

    2016-02-10

    In the present investigation, we report a one-step synthesis method of wafer-scale highly crystalline tungsten disulfide (WS2) nanoparticle thin film by using a modified hot wire chemical vapor deposition (HW-CVD) technique. The average size of WS2 nanoparticle is found to be 25-40 nm over an entire 4 in. wafer of quartz substrate. The low-angle XRD data of WS2 nanoparticle shows the highly crystalline nature of sample along with orientation (002) direction. Furthermore, Raman spectroscopy shows two prominent phonon vibration modes of E(1)2g and A1g at ∼356 and ∼420 cm(-1), respectively, indicating high purity of material. The TEM analysis shows good crystalline quality of sample. The synthesized WS2 nanoparticle thin film based device shows good response to humidity and good photosensitivity along with good long-term stability of the device. It was found that the resistance of the films decreases with increasing relative humidity (RH). The maximum humidity sensitivity of 469% along with response time of ∼12 s and recovery time of ∼13 s were observed for the WS2 thin film humidity sensor device. In the case of photodetection, the response time of ∼51 s and recovery time of ∼88 s were observed with sensitivity ∼137% under white light illumination. Our results open up several avenues to grow other transition metal dichalcogenide nanoparticle thin film for large-area nanoelectronics as well as industrial applications.

  15. Heterogeneously integrated microsystem-on-a-chip

    DOEpatents

    Chanchani, Rajen [Albuquerque, NM

    2008-02-26

    A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

  16. Wafer hot spot identification through advanced photomask characterization techniques

    NASA Astrophysics Data System (ADS)

    Choi, Yohan; Green, Michael; McMurran, Jeff; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

    2016-10-01

    As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that the classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced characterization methods in order to optimize the mask process to meet the wafer lithographer's needs. These advanced characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled wafer performance.

  17. Optima XE Single Wafer High Energy Ion Implanter

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Satoh, Shu; Ferrara, Joseph; Bell, Edward

    2008-11-03

    The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowingmore » the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.« less

  18. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M.

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  19. Optical surface analysis: a new technique for the inspection and metrology of optoelectronic films and wafers

    NASA Astrophysics Data System (ADS)

    Bechtler, Laurie; Velidandla, Vamsi

    2003-04-01

    In response to demand for higher volumes and greater product capability, integrated optoelectronic device processing is rapidly increasing in complexity, benefiting from techniques developed for conventional silicon integrated circuit processing. The needs for high product yield and low manufacturing cost are also similar to the silicon wafer processing industry. This paper discusses the design and use of an automated inspection instrument called the Optical Surface Analyzer (OSA) to evaluate two critical production issues in optoelectronic device manufacturing: (1) film thickness uniformity, and (2) defectivity at various process steps. The OSA measurement instrument is better suited to photonics process development than most equipment developed for conventional silicon wafer processing in two important ways: it can handle both transparent and opaque substrates (unlike most inspection and metrology tools), and it is a full-wafer inspection method that captures defects and film variations over the entire substrate surface (unlike most film thickness measurement tools). Measurement examples will be provided in the paper for a variety of films and substrates used for optoelectronics manufacturing.

  20. Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

    NASA Astrophysics Data System (ADS)

    Syed, Ahmed Rashid

    Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

  1. Characterization of silicon-on-insulator wafers

    NASA Astrophysics Data System (ADS)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  2. Wafer-level packaging with compression-controlled seal ring bonding

    DOEpatents

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  3. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

  4. Applications of the silicon wafer direct-bonding technique to electron devices

    NASA Astrophysics Data System (ADS)

    Furukawa, K.; Nakagawa, A.

    1990-01-01

    A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

  5. Wafer-level vacuum/hermetic packaging technologies for MEMS

    NASA Astrophysics Data System (ADS)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  6. Laser furnace and method for zone refining of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

    1988-01-01

    A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

  7. Atomic mechanism for the growth of wafer-scale single-crystal graphene: theoretical perspective and scanning tunneling microscopy investigations

    NASA Astrophysics Data System (ADS)

    Niu, Tianchao; Zhang, Jialin; Chen, Wei

    2017-12-01

    Chemical vapor deposition (CVD) is the most promising approach for producing low-cost, high-quality, and large area graphene. Revealing the graphene growth mechanism at the atomic-scale is of great importance for realizing single crystal graphene (SCG) over wafer scale. Density functional theoretical (DFT) calculations are playing an increasingly important role in revealing the structure of the most stable carbon species, understanding the evolution processes, and disclosing the active sites. Scanning tunneling microscopy (STM) is a powerful surface characterization tool to illustrate the real space distribution and atomic structures of growth intermediates during the CVD process. Combining them together can provide valuable information to improve the atomically controlled growth of SCG. Starting from a basic concept of the substrate effect on realizing SCG, this review covers the progress made in theoretical investigations on various carbon species during graphene growth on different transition metal substrates, in the STM study of the structural intermediates on transition metal surfaces, and in synthesizing graphene nanoribbons with atomic-precise width and edge structure, ending with a perspective on the future development of 2D materials beyond graphene.

  8. Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

    2018-03-01

    It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

  9. Novel wafer stepper with violet LED light source

    NASA Astrophysics Data System (ADS)

    Ting, Yung-Chiang; Shy, Shyi-Long

    2014-03-01

    Novel wafer stepper by using contact or proximity printing will be developed, using violet LED light source to replace Hg Arc. lamp or laser. Mirror, filter and condenser lens for Hg Arc. Lamp or laser and reduction lens for projection printing can be discarded. Reliability and manufacturing cost of wafer stepper can be improved. Exposure result by using IP3600 resist and wafer stepper with violet LED light source (wave-length 360nm to 410 nm) will be obtained. This novel wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist with sub-micron to 100 micron thickness.

  10. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  11. Quantitative phase measurement for wafer-level optics

    NASA Astrophysics Data System (ADS)

    Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

    2015-07-01

    Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

  12. Wave-front propagation of rinsing flows on rotating semiconductor wafers

    NASA Astrophysics Data System (ADS)

    Frostad, John M.; Ylitalo, Andy; Walls, Daniel J.; Mui, David S. L.; Fuller, Gerald G.

    2016-11-01

    The semiconductor manufacturing industry is migrating to a cleaning technology that involves dispersing cleaning solutions onto a rotating wafer, similar to spin-coating. Advantages include a more continuous overall fabrication process, lower particle level, no cross contamination from the back side of a wafer, and less usage of harsh chemicals for a lower environmental impact. Rapid rotation of the wafer during rinsing can be more effective, but centrifugal forces can pull spiral-like ribbons of liquid radially outward from the advancing wave-front where particles can build up, causing higher instances of device failure at these locations. A better understanding of the rinsing flow is essential for reducing yield losses while taking advantage of the benefits of rotation. In the present work, high-speed video and image processing are used to study the dynamics of the advancing wave-front from an impinging jet on a rotating substrate. The flow-rate and rotation-speed are varied for substrates coated with a thin layer of a second liquid that has a different surface tension than the jet liquid. The difference in surface tension of the two fluids gives rise to Marangoni stresses at the interface that have a significant impact on the rinsing process, despite the extremely short time-scales involved.

  13. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, Theodoer F.

    1995-01-01

    Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

  14. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  15. Study of temperature distributions in wafer exposure process

    NASA Astrophysics Data System (ADS)

    Lin, Zone-Ching; Wu, Wen-Jang

    During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

  16. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  17. Ultra-high heat flux cooling characteristics of cryogenic micro-solid nitrogen particles and its application to semiconductor wafer cleaning technology

    NASA Astrophysics Data System (ADS)

    Ishimoto, Jun; Oh, U.; Guanghan, Zhao; Koike, Tomoki; Ochiai, Naoya

    2014-01-01

    The ultra-high heat flux cooling characteristics and impingement behavior of cryogenic micro-solid nitrogen (SN2) particles in relation to a heated wafer substrate were investigated for application to next generation semiconductor wafer cleaning technology. The fundamental characteristics of cooling heat transfer and photoresist removal-cleaning performance using micro-solid nitrogen particulate spray impinging on a heated substrate were numerically investigated and experimentally measured by a new type of integrated computational-experimental technique. This study contributes not only advanced cryogenic cooling technology for high thermal emission devices, but also to the field of nano device engineering including the semiconductor wafer cleaning technology.

  18. Wafer edge overlay control solution for N7 and beyond

    NASA Astrophysics Data System (ADS)

    van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

    2018-03-01

    Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

  19. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2008-10-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  20. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  1. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-03-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  2. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    NASA Astrophysics Data System (ADS)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

    2016-08-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

  3. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    NASA Technical Reports Server (NTRS)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; hide

    2016-01-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN(sub x)) materials and microwave structures, and the resulting performance improvements.

  4. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  5. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  6. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  7. Modelling deformation and fracture in confectionery wafers

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which wasmore » then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.« less

  8. Controllable laser thermal cleavage of sapphire wafers

    NASA Astrophysics Data System (ADS)

    Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

    2018-03-01

    Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

  9. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, Gary S.

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  10. Guided ultrasonic wave beam skew in silicon wafers

    NASA Astrophysics Data System (ADS)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2018-04-01

    In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

  11. High-throughput automatic defect review for 300mm blank wafers with atomic force microscope

    NASA Astrophysics Data System (ADS)

    Zandiatashbar, Ardavan; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

    2015-03-01

    While feature size in lithography process continuously becomes smaller, defect sizes on blank wafers become more comparable to device sizes. Defects with nm-scale characteristic size could be misclassified by automated optical inspection (AOI) and require post-processing for proper classification. Atomic force microscope (AFM) is known to provide high lateral and the highest vertical resolution by mechanical probing among all techniques. However, its low throughput and tip life in addition to the laborious efforts for finding the defects have been the major limitations of this technique. In this paper we introduce automatic defect review (ADR) AFM as a post-inspection metrology tool for defect study and classification for 300 mm blank wafers and to overcome the limitations stated above. The ADR AFM provides high throughput, high resolution, and non-destructive means for obtaining 3D information for nm-scale defect review and classification.

  12. Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene

    DTIC Science & Technology

    2014-08-01

    Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene by Eugene Zakar, Wayne Churaman, Collin Becker, Bernard Rod, Luke...Laboratory Adelphi, MD 20783-1138 ARL-TR-7025 August 2014 Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene...Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6

  13. On the design of GaN vertical MESFETs on commercial LED sapphire wafers

    NASA Astrophysics Data System (ADS)

    Atalla, Mahmoud R. M.; Noor Elahi, Asim M.; Mo, Chen; Jiang, Zhenyu; Liu, Jie; Ashok, S.; Xu, Jian

    2016-12-01

    Design of GaN-based vertical metal-semiconductor field-effect transistors (MESFETs) on commercial light-emitting-diode (LED) epi-wafers has been proposed and proof of principle devices have been fabricated. In order to better understand the IV curves, these devices have been simulated using the charge transport model. It was found that shrinking the drain pillar size would significantly help in reaching cut-off at much lower gate bias even at high carrier concentration of unintentionally doped GaN and considerable leakage current caused by the Schottky barrier lowering. The realization of these vertical MESFETs on LED wafers would allow their chip-level integration. This would open a way to many intelligent lighting applications like on-chip current regulator and signal regulation/communication in display technology.

  14. Cohesive zone model for direct silicon wafer bonding

    NASA Astrophysics Data System (ADS)

    Kubair, D. V.; Spearing, S. M.

    2007-05-01

    Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

  15. Large scale integration of CVD-graphene based NEMS with narrow distribution of resonance parameters

    NASA Astrophysics Data System (ADS)

    Arjmandi-Tash, Hadi; Allain, Adrien; (Vitto Han, Zheng; Bouchiat, Vincent

    2017-06-01

    We present a novel method for the fabrication of the arrays of suspended micron-sized membranes, based on monolayer pulsed-CVD graphene. Such devices are the source of an efficient integration of graphene nano-electro-mechanical resonators, compatible with production at the wafer scale using standard photolithography and processing tools. As the graphene surface is continuously protected by the same polymer layer during the whole process, suspended graphene membranes are clean and free of imperfections such as deposits, wrinkles and tears. Batch fabrication of 100 μm-long multi-connected suspended ribbons is presented. At room temperature, mechanical resonance of electrostatically-actuated devices show narrow distribution of their characteristic parameters with high quality factor and low effective mass and resonance frequencies, as expected for low stress and adsorbate-free membranes. Upon cooling, a sharp increase of both resonant frequency and quality factor is observed, enabling to extract the thermal expansion coefficient of CVD graphene. Comparison with state-of-the-art graphene NEMS is presented.

  16. Integrating Carbon Nanotubes For Atomic Force Microscopy Imaging Applications

    NASA Technical Reports Server (NTRS)

    Ye, Qi; Cassell, Alan M.; Liu, Hongbing; Han, Jie; Meyyappan, Meyya

    2004-01-01

    Carbon nanotube (CNT) related nanostructures possess remarkable electrical, mechanical, and thermal properties. To produce these nanostructures for real world applications, a large-scale controlled growth of carbon nanotubes is crucial for the integration and fabrication of nanodevices and nanosensors. We have taken the approach of integrating nanopatterning and nanomaterials synthesis with traditional silicon micro fabrication techniques. This integration requires a catalyst or nanomaterial protection scheme. In this paper, we report our recent work on fabricating wafer-scale carbon nanotube AFM cantilever probe tips. We will address the design and fabrication considerations in detail, and present the preliminary scanning probe test results. This work may serve as an example of rational design, fabrication, and integration of nanomaterials for advanced nanodevice and nanosensor applications.

  17. Wafer hot spot identification through advanced photomask characterization techniques: part 2

    NASA Astrophysics Data System (ADS)

    Choi, Yohan; Green, Michael; Cho, Young; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

    2017-03-01

    Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.

  18. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  19. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  20. Development of parametric material, energy, and emission inventories for wafer fabrication in the semiconductor industry.

    PubMed

    Murphy, Cynthia F; Kenig, George A; Allen, David T; Laurent, Jean-Philippe; Dyer, David E

    2003-12-01

    Currently available data suggest that most of the energy and material consumption related to the production of an integrated circuit is due to the wafer fabrication process. The complexity of wafer manufacturing, requiring hundreds of steps that vary from product to product and from facility to facility and which change every few years, has discouraged the development of material, energy, and emission inventory modules for the purpose of insertion into life cycle assessments. To address this difficulty, a flexible, process-based system for estimating material requirements, energy requirements, and emissions in wafer fabrication has been developed. The method accounts for mass and energy use atthe unit operation level. Parametric unit operation modules have been developed that can be used to predict changes in inventory as the result of changes in product design, equipment selection, or process flow. A case study of the application of the modules is given for energy consumption, but a similar methodology can be used for materials, individually or aggregated.

  1. Flexible metal-semiconductor-metal device prototype on wafer-scale thick boron nitride layers grown by MOVPE.

    PubMed

    Li, Xin; Jordan, Matthew B; Ayari, Taha; Sundaram, Suresh; El Gmili, Youssef; Alam, Saiful; Alam, Muhbub; Patriarche, Gilles; Voss, Paul L; Paul Salvestrini, Jean; Ougazzaden, Abdallah

    2017-04-11

    Practical boron nitride (BN) detector applications will require uniform materials over large surface area and thick BN layers. To report important progress toward these technological requirements, 1~2.5 µm-thick BN layers were grown on 2-inch sapphire substrates by metal-organic vapor phase epitaxy (MOVPE). The structural and optical properties were carefully characterized and discussed. The thick layers exhibited strong band-edge absorption near 215 nm. A highly oriented two-dimensional h-BN structure was formed at the film/sapphire interface, which permitted an effective exfoliation of the thick BN film onto other adhesive supports. And this structure resulted in a metal-semiconductor-metal (MSM) device prototype fabricated on BN membrane delaminating from the substrate. MSM photodiode prototype showed low dark current of 2 nA under 100 V, and 100 ± 20% photoconductivity yield for deep UV light illumination. These wafer-scale MOVPE-grown thick BN layers present great potential for the development of deep UV photodetection applications, and even for flexible (opto-) electronics in the future.

  2. Compensating measured intra-wafer ring oscillator stage delay with intra-wafer exposure dose corrections

    NASA Astrophysics Data System (ADS)

    Verhaegen, Staf; Nackaerts, Axel; Dusa, Mircea; Carpaij, Rene; Vandenberghe, Geert; Finders, Jo

    2006-03-01

    The purpose of this paper is to use measurements on real working devices to derive more information than typically measured by the classic line-width measurement techniques. The first part of the paper will discuss the principle of the measurements with a ring oscillator, a circuit used to measure the speed of elementary logic gates. These measurements contribute to the understanding of the exact timing dependencies in circuits, which is of utmost importance for the design and simulation of these circuits. When connecting an odd number of digital inverting stages in a ring, the circuit has no stable digital state but acts as an analog oscillator with the oscillation frequency dependent on the analog propagation delay of the signals through the stages. By varying some conditions during a litho step, the delay change caused by the process condition change can be measured very accurately. The response of the ring oscillator delay to exposure dose is measured and presented in this paper together with a comparison of measured line-width values of the poly gate lines. The second part of the paper will focus on improving the intra-wafer variation of the stage delay. A number of ring oscillators are put in a design at different slit and scan locations. 200mm wafers are processed with 48 full dies present. From the intra-wafer delay fingerprint and the dose sensitivity of the delay an intra-wafer dose correction, also called a dose recipe, is calculated. This dose recipe is used on the scanner to compensate for effects that are the root cause for the delay profile; including reticle and processing such as track, etch and annealing.

  3. A novel patterning control strategy based on real-time fingerprint recognition and adaptive wafer level scanner optimization

    NASA Astrophysics Data System (ADS)

    Cekli, Hakki Ergun; Nije, Jelle; Ypma, Alexander; Bastani, Vahid; Sonntag, Dag; Niesing, Henk; Zhang, Linmiao; Ullah, Zakir; Subramony, Venky; Somasundaram, Ravin; Susanto, William; Matsunobu, Masazumi; Johnson, Jeff; Tabery, Cyrus; Lin, Chenxi; Zou, Yi

    2018-03-01

    In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a `fingerprint', on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching <3nm, requiring the allowable budget for process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel `computational process control strategy' which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each

  4. Wafer level fabrication of single cell dispenser chips with integrated electrodes for particle detection

    NASA Astrophysics Data System (ADS)

    Schoendube, Jonas; Yusof, Azmi; Kalkandjiev, Kiril; Zengerle, Roland; Koltay, Peter

    2015-02-01

    This work presents the microfabrication and experimental evaluation of a dispenser chip, designed for isolation and printing of single cells by combining impedance sensing and drop-on-demand dispensing. The dispenser chip features 50  ×  55 µm (width × height) microchannels, a droplet generator and microelectrodes for impedance measurements. The chip is fabricated by sandwiching a dry film photopolymer (TMMF) between a silicon and a Pyrex wafer. TMMF has been used to define microfluidic channels, to serve as low temperature (75 °C) bonding adhesive and as etch mask during 300 µm deep HF etching of the Pyrex wafer. Due to the novel fabrication technology involving the dry film resist, it became possible to fabricate facing electrodes at the top and bottom of the channel and to apply electrical impedance sensing for particle detection with improved performance. The presented microchip is capable of dispensing liquid and detecting microparticles via impedance measurement. Single polystyrene particles of 10 µm size could be detected with a mean signal amplitude of 0.39  ±  0.13 V (n=439 ) at particle velocities of up to 9.6 mm s-1 inside the chip.

  5. Reticle variation influence on manufacturing line and wafer device performance

    NASA Astrophysics Data System (ADS)

    Nistler, John L.; Spurlock, Kyle

    1994-01-01

    Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

  6. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    NASA Astrophysics Data System (ADS)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  7. Characterization of wafer-level bonded hermetic packages using optical leak detection

    NASA Astrophysics Data System (ADS)

    Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

    2009-07-01

    For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

  8. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

    PubMed

    Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

    2008-07-24

    The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of

  9. A Fully Integrated Quartz MEMS VHF TCXO.

    PubMed

    Kubena, Randall L; Stratton, Frederic P; Nguyen, Hung D; Kirby, Deborah J; Chang, David T; Joyce, Richard J; Yong, Yook-Kong; Garstecki, Jeffrey F; Cross, Matthew D; Seman, S E

    2018-06-01

    We report on a 32-MHz quartz temperature compensated crystal oscillator (TCXO) fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate, thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ±0.2 parts per million over temperature using on-chip third-order compensation circuitry. The TCXO operates at low power of 2.5 mW and can be thinned to as part of the wafer-level eutectic encapsulation. Full integration with large state-of-the-art CMOS wafers is possible using carrier wafer techniques.

  10. Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

    2014-01-01

    This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

  11. Strategy For Yield Control And Enhancement In VLSI Wafer Manufacturing

    NASA Astrophysics Data System (ADS)

    Neilson, B.; Rickey, D.; Bane, R. P.

    1988-01-01

    In most fully utilized integrated circuit (IC) production facilities, profit is very closely linked with yield. In even the most controlled manufacturing environments, defects due to foreign material are a still major contributor to yield loss. Ideally, an IC manufacturer will have ample engineering resources to address any problem that arises. In the real world, staffing limitations require that some tasks must be left undone and potential benefits left unrealized. Therefore, it is important to prioritize problems in a manner that will give the maximum benefit to the manufacturer. When offered a smorgasbord of problems to solve, most people (engineers included) will start with what is most interesting or the most comfortable to work on. By providing a system that accurately predicts the impact of a wide variety of defect types, a rational method of prioritizing engineering effort can be made. To that effect, a program was developed to determine and rank the major yield detractors in a mixed analog/digital FET manufacturing line. The two classical methods of determining yield detractors are chip failure analysis and defect monitoring on drop in test die. Both of these methods have short comings: 1) Chip failure analysis is painstaking and very time consuming. As a result, the sample size is very small. 2) Drop in test die are usually designed for device parametric analysis rather than defect analysis. To provide enough wafer real estate to do meaningful defect analysis would render the wafer worthless for production. To avoid these problems, a defect monitor was designed that provided enough area to detect defects at the same rate or better than the NMOS product die whose yield was to be optimized. The defect monitor was comprehensive and electrically testable using such equipment as the Prometrix LM25 and other digital testers. This enabled the quick accumulation of data which could be handled statistically and mapped individually. By scaling the defect densities

  12. Mask-to-wafer alignment system

    DOEpatents

    Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

    2003-11-04

    A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

  13. Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

    NASA Astrophysics Data System (ADS)

    Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

    2018-01-01

    Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

  14. Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

    PubMed

    Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

    2014-06-01

    Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

  15. Integral resonator gyroscope

    NASA Technical Reports Server (NTRS)

    Shcheglov, Kirill V. (Inventor); Challoner, A. Dorian (Inventor); Hayworth, Ken J. (Inventor); Wiberg, Dean V. (Inventor); Yee, Karl Y. (Inventor)

    2008-01-01

    The present invention discloses an inertial sensor having an integral resonator. A typical sensor comprises a planar mechanical resonator for sensing motion of the inertial sensor and a case for housing the resonator. The resonator and a wall of the case are defined through an etching process. A typical method of producing the resonator includes etching a baseplate, bonding a wafer to the etched baseplate, through etching the wafer to form a planar mechanical resonator and the wall of the case and bonding an end cap wafer to the wall to complete the case.

  16. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  17. P/N InP solar cells on Ge wafers

    NASA Technical Reports Server (NTRS)

    Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

    1994-01-01

    Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented

  18. Material electronic quality specifications for polycrystalline silicon wafers

    NASA Astrophysics Data System (ADS)

    Kalejs, J. P.

    1994-06-01

    As the use of polycrystalline silicon wafers has expanded in the photovoltaic industry, the need grows for monitoring and qualification techniques for as-grown material that can be used to optimize crystal growth and help predict solar cell performance. Particular needs are for obtaining quantitative measures over full wafer areas of the effects of lifetime limiting defects and of the lifetime upgrading taking place during solar cell processing. We review here the approaches being pursued in programs under way to develop material quality specifications for thin Edge-defined Film-fed Growth (EFG) polycrystalline silicon as-grown wafers. These studies involve collaborations between Mobil Solar, and NREL and university-based laboratories.

  19. Low cost back contact heterojunction solar cells on thin c-Si wafers. integrating laser and thin film processing for improved manufacturability

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Hegedus, Steven S.

    2015-09-08

    An interdigitated back contact (IBC) Si wafer solar cell with deposited a-Si heterojunction (HJ) emitter and contacts is considered the ultimate single junction Si solar cell design. This was confirmed in 2014 by both Panasonic and Sharp Solar producing IBC-HJ cells breaking the previous record Si solar cell efficiency of 25%. But manufacturability at low cost is a concern for the complex IBC-HJ device structure. In this research program, our goals were to addressed the broad industry need for a high-efficiency c-Si cell that overcomes the dominant module cost barriers by 1) developing thin Si wafers synthesized by innovative, kerflessmore » techniques; 2) integrating laser-based processing into most aspects of solar cell fabrication, ensuring high speed and low thermal budgets ; 3) developing an all back contact cell structure compatible with thin wafers using a simplified, low-temperature fabrication process; and 4) designing the contact patterning to enable simplified module assembly. There were a number of significant achievements from this 3 year program. Regarding the front surface, we developed and applied new method to characterize critical interface recombination parameters including interface defect density Dit and hole and electron capture cross-section for use as input for 2D simulation of the IBC cell to guide design and loss analysis. We optimized the antireflection and passivation properties of the front surface texture and a-Si/a-SiN/a-SiC stack depositions to obtain a very low (< 6 mA/cm2) front surface optical losses (reflection and absorption) while maintaining excellent surface passivation (SRV<5 cm/s). We worked with kerfless wafer manufacturers to apply defect-engineering techniques to improve bulk minority-carrier lifetime of thin kerfless wafers by both reducing initial impurities during growth and developing post-growth gettering techniques. This led insights about the kinetics of nickel, chromium, and dislocations in PV-grade silicon and

  20. Evaluation of anti-sticking layers performances for 200mm wafer scale Smart NILTM process through surface and defectivity characterizations

    NASA Astrophysics Data System (ADS)

    Delachat, F.; Phillipe, J.-C.; Larrey, V.; Fournel, F.; Bos, S.; Teyssèdre, H.; Chevalier, Xavier; Nicolet, Célia; Navarro, Christophe; Cayrefourcq, Ian

    2018-03-01

    In this work, an evaluation of various ASL processes for 200 mm wafer scale in the HERCULES® NIL equipment platform available at the CEA-Leti through the INSPIRE program is reported. The surface and adherence energies were correlated to the AFM and defectivity results in order to select the most promising ASL process for high resolution etch mask applications. The ASL performances of the selected process were evaluated by multiple working stamp fabrication using unpatterned and patterned masters though defectivity monitoring on optical based-inspection tools. Optical and SEM defect reviews were systematically performed. Multiple working stamps fabrication without degradation of the master defectivity was witnessed. This evaluation enabled to benchmark several ASL solutions based on the grafted technology develop by ARKEMA in order to reduce and optimize the soft stamp defectivity prior to its replication and therefore considerably reduce the final imprint defectivity for the Smart NIL process.

  1. Characterizing SOI Wafers By Use Of AOTF-PHI

    NASA Technical Reports Server (NTRS)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  2. Centimeter-Scale 2D van der Waals Vertical Heterostructures Integrated on Deformable Substrates Enabled by Gold Sacrificial Layer-Assisted Growth.

    PubMed

    Islam, Md Ashraful; Kim, Jung Han; Schropp, Anthony; Kalita, Hirokjyoti; Choudhary, Nitin; Weitzman, Dylan; Khondaker, Saiful I; Oh, Kyu Hwan; Roy, Tania; Chung, Hee-Suk; Jung, Yeonwoong

    2017-10-11

    Two-dimensional (2D) transition metal dichalcogenides (TMDs) such as molybdenum or tungsten disulfides (MoS 2 or WS 2 ) exhibit extremely large in-plane strain limits and unusual optical/electrical properties, offering unprecedented opportunities for flexible electronics/optoelectronics in new form factors. In order for them to be technologically viable building-blocks for such emerging technologies, it is critically demanded to grow/integrate them onto flexible or arbitrary-shaped substrates on a large wafer-scale compatible with the prevailing microelectronics processes. However, conventional approaches to assemble them on such unconventional substrates via mechanical exfoliations or coevaporation chemical growths have been limited to small-area transfers of 2D TMD layers with uncontrolled spatial homogeneity. Moreover, additional processes involving a prolonged exposure to strong chemical etchants have been required for the separation of as-grown 2D layers, which is detrimental to their material properties. Herein, we report a viable strategy to universally combine the centimeter-scale growth of various 2D TMD layers and their direct assemblies on mechanically deformable substrates. By exploring the water-assisted debonding of gold (Au) interfaced with silicon dioxide (SiO 2 ), we demonstrate the direct growth, transfer, and integration of 2D TMD layers and heterostructures such as 2D MoS 2 and 2D MoS 2 /WS 2 vertical stacks on centimeter-scale plastic and metal foil substrates. We identify the dual function of the Au layer as a growth substrate as well as a sacrificial layer which facilitates 2D layer transfer. Furthermore, we demonstrate the versatility of this integration approach by fabricating centimeter-scale 2D MoS 2 /single walled carbon nanotube (SWNT) vertical heterojunctions which exhibit current rectification and photoresponse. This study opens a pathway to explore large-scale 2D TMD van der Waals layers as device building blocks for emerging

  3. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  4. Intrinsic Gettering in Nitrogen-Doped and Hydrogen-Annealed Czochralski-Grown Silicon Wafers

    NASA Astrophysics Data System (ADS)

    Goto, Hiroyuki; Pan, Lian-Sheng; Tanaka, Masafumi; Kashima, Kazuhiko

    2001-06-01

    The properties of nitrogen-doped and hydrogen-annealed Czochralski-grown silicon (NHA-CZ-Si) wafers were investigated in this study. The quality of the subsurface was investigated by monitoring the generation lifetime of minority carriers, as measured by the capacitance-time measurements of a metal oxide silicon capacitor (MOS C-t). The intrinsic gettering (IG) ability was investigated by determining the nickel concentration on the surface and in the subsurface as measured by graphite furnace atomic absorption spectrometry (GFAAS) after the wafer was deliberately contaminated with nickel. From the results obtained, the generation lifetimes of these NHA-CZ-Si wafers were determined to be almost the same as, or a little longer than those of epitaxial wafers, and the IG ability was proportional to the total volume of oxygen precipitates [i.e., bulk micro defects (BMDs)], which was influenced by the oxygen and nitrogen concentrations in the wafers. Therefore, it is suggested that the subsurface of the NHA-CZ-Si wafers is of good quality and the IG capacity is controllable by the nitrogen and oxygen concentrations in the wafers.

  5. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  6. Strategy optimization for mask rule check in wafer fab

    NASA Astrophysics Data System (ADS)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  7. Wafer plane inspection for advanced reticle defects

    NASA Astrophysics Data System (ADS)

    Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

    2008-05-01

    Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

  8. Ultrathin, wafer-scale hexagonal boron nitride on dielectric surfaces by diffusion and segregation mechanism

    NASA Astrophysics Data System (ADS)

    Sonde, Sushant; Dolocan, Andrei; Lu, Ning; Corbet, Chris; Kim, Moon J.; Tutuc, Emanuel; Banerjee, Sanjay K.; Colombo, Luigi

    2017-06-01

    Chemical vapor deposition (CVD) of two-dimensional (2D) hexagonal boron nitride (h-BN) is at the center of numerous studies for its applications in novel electronic devices. However, a clear understanding of the growth mechanism is lacking for its wider industrial adoption on technologically relevant substrates such as SiO2. Here, we demonstrate a controllable growth method of thin, wafer scale h-BN films on arbitrary substrates. We also clarify the growth mechanism to be diffusion and surface segregation (D-SS) of boron (B) and nitrogen (N) in Ni and Co thin films on SiO2/Si substrates after exposure to diborane and ammonia precursors at high temperature. The segregation was found to be independent of the cooling rates employed in this report, and to our knowledge has not been found nor reported for 2D h-BN growth so far, and thus provides an important direction for controlled growth of h-BN. This unique segregation behavior is a result of a combined effect of high diffusivity, small film thickness and the inability to achieve extremely high cooling rates in CVD systems. The resulting D-SS h-BN films exhibit excellent electrical insulating behavior with an optical bandgap of about 5.8 eV. Moreover, graphene-on-h-BN field effect transistors using the as-grown D-SS h-BN films show a mobility of about 6000 cm2 V-1 s-1 at room temperature.

  9. The uses of Man-Made diamond in wafering applications

    NASA Technical Reports Server (NTRS)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  10. Developing quartz wafer mold manufacturing process for patterned media

    NASA Astrophysics Data System (ADS)

    Chiba, Tsuyoshi; Fukuda, Masaharu; Ishikawa, Mikio; Itoh, Kimio; Kurihara, Masaaki; Hoga, Morihisa

    2009-04-01

    Recently, patterned media have gained attention as a possible candidate for use in the next generation of hard disk drives (HDD). Feature sizes on media are predicted to be 20-25 nm half pitch (hp) for discrete-track media in 2010. One method of fabricating such a fine pattern is by using a nanoimprint. The imprint mold for the patterned media is created from a 150-millimeter, rounded, quartz wafer. The purpose of the process introduced here was to construct a quartz wafer mold and to fabricate line and space (LS) patterns at 24 nmhp for DTM. Additionally, we attempted to achieve a dense hole (HOLE) pattern at 12.5 nmhp for BPM for use in 2012. The manufacturing process of molds for patterned media is almost the same as that for semiconductors, with the exception of the dry-etching process. A 150-millimeter quartz wafer was etched on a special tray made from carving a 6025 substrate, by using the photo-mask tool. We also optimized the quartz etching conditions. As a result, 24 nmhp LS and HOLE patterns were manufactured on the quartz wafer. In conclusion, the quartz wafer mold manufacturing process was established. It is suggested that the etching condition should be further optimized to achieve a higher resolution of HOLE patterns.

  11. All silicon electrode photocapacitor for integrated energy storage and conversion.

    PubMed

    Cohn, Adam P; Erwin, William R; Share, Keith; Oakes, Landon; Westover, Andrew S; Carter, Rachel E; Bardhan, Rizia; Pint, Cary L

    2015-04-08

    We demonstrate a simple wafer-scale process by which an individual silicon wafer can be processed into a multifunctional platform where one side is adapted to replace platinum and enable triiodide reduction in a dye-sensitized solar cell and the other side provides on-board charge storage as an electrochemical supercapacitor. This builds upon electrochemical fabrication of dual-sided porous silicon and subsequent carbon surface passivation for silicon electrochemical stability. The utilization of this silicon multifunctional platform as a combined energy storage and conversion system yields a total device efficiency of 2.1%, where the high frequency discharge capability of the integrated supercapacitor gives promise for dynamic load-leveling operations to overcome current and voltage fluctuations during solar energy harvesting.

  12. Process Performance of Optima XEx Single Wafer High Energy Implanter

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Kim, J. H.; Yoon, Jongyoon; Kondratenko, S.

    2011-01-07

    To meet the process requirements for well formation in future CMOS memory production, high energy implanters require more robust angle, dose, and energy control while maintaining high productivity. The Optima XEx high energy implanter meets these requirements by integrating a traditional LINAC beamline with a robust single wafer handling system. To achieve beam angle control, Optima XEx can control both the horizontal and vertical beam angles to within 0.1 degrees using advanced beam angle measurement and correction. Accurate energy calibration and energy trim functions accelerate process matching by eliminating energy calibration errors. The large volume process chamber and UDC (upstreammore » dose control) using faraday cups outside of the process chamber precisely control implant dose regardless of any chamber pressure increase due to PR (photoresist) outgassing. An optimized RF LINAC accelerator improves reliability and enables singly charged phosphorus and boron energies up to 1200 keV and 1500 keV respectively with higher beam currents. A new single wafer endstation combined with increased beam performance leads to overall increased productivity. We report on the advanced performance of Optima XEx observed during tool installation and volume production at an advanced memory fab.« less

  13. A High-Q Resonant Pressure Microsensor with Through-Glass Electrical Interconnections Based on Wafer-Level MEMS Vacuum Packaging

    PubMed Central

    Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

    2014-01-01

    This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in “H” type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than −0.01% F.S/°C in the range of −40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S. PMID:25521385

  14. A high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging.

    PubMed

    Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

    2014-12-16

    This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in "H" type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than -0.01% F.S/°C in the range of -40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S.

  15. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Johnston, S.; Yan, F.; Zaunbracher, K.

    2011-07-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finishedmore » cell performance.« less

  16. Edge printability: techniques used to evaluate and improve extreme wafer edge printability

    NASA Astrophysics Data System (ADS)

    Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

    2004-05-01

    The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

  17. Recent Results on Gridpix Detectors:. AN Integrated Micromegas Grid and a Micromegas Ageing Test

    NASA Astrophysics Data System (ADS)

    Chefdeville, M.; Aarts, A.; van der Graaf, H.; van der Putten, S.

    2006-04-01

    A new gas-filled detector combining a Micromegas with a CMOS pixel chip has been recently tested. A procedure to integrate the Micromegas grid onto silicon wafers (‘wafer post processing’) has been developed. We aim to eventually integrate the grid on top of wafers of CMOS pixel chips. The first part of this contribution describes an application in vertex detection (GOSSIP). Then tests of the first detector prototype of a grid integrated on a bare silicon wafer are shown. Finally an ageing test of a Micromegas chamber is presented. After verifying the chambers' proportionality at a very high dose rates, the device was irradiated until ageing became apparent.

  18. Reduction of across-wafer CDU via constrained optimization of a multichannel PEB plate controller based on in-situ measurements of thermal time constants

    NASA Astrophysics Data System (ADS)

    Tiffany, Jason E.; Cohen, Barney M.

    2004-05-01

    As line widths approach 90nm node in volume production, post exposure bake (PEB) uniformity becomes a much larger component of the across wafer critical dimension uniformity (CDU). In production, the need for PEB plate matching has led to novel solutions such as plate specific dose offsets. This type of correction does not help across wafer CDU. Due to unequal activation energies of the critical PEB processes, any thermal history difference can result in a corresponding CD variation. The rise time of the resist to the target temperature has been shown to affect CD, with the most critical time being the first 5-7 seconds. A typical PEB plate has multi-zone thermal control with one thermal sensor per zone. The current practice is to setup each plate to match the steady-state target temperature, ignoring any dynamic performance. Using an in-situ wireless RTD wafer, it is possible to characterize the dynamic performance, or time constant, of each RTD location on the sensing wafer. Constrained by the zone structure of the PEB plate, the proportional, integral and derivative (PID) settings of each controller channel could be optimized to reduce the variations in rise time across the RTD wafer, thereby reducing the PEB component of across wafer CDU.

  19. Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

    NASA Astrophysics Data System (ADS)

    Ostapenko, S.; Tarasov, I.

    2000-04-01

    A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

  20. Reduction of B-integral accumulation in lasers

    DOEpatents

    Meyerhofer, David D.; Konoplev, Oleg A.

    2000-01-01

    A pulsed laser is provided wherein the B-integral accumulated in the laser pulse is reduced using a semiconductor wafer. A laser pulse is generated by a laser pulse source. The laser pulse passes through a semiconductor wafer that has a negative nonlinear index of refraction. Thus, the laser pulse accumulates a negative B-integral. The laser pulse is then fed into a laser amplification medium, which has a positive nonlinear index of refraction. The laser pulse may make a plurality of passes through the laser amplification medium and accumulate a positive B-integral during a positive non-linear phase change. The semiconductor and laser pulse wavelength are chosen such that the negative B-integral accumulated in the semiconductor wafer substantially cancels the positive B-integral accumulated in the laser amplification medium. There may be additional accumulation of positive B-integral if the laser pulse passes through additional optical mediums such as a lens or glass plates. Thus, the effects of self-phase modulation in the laser pulse are substantially reduced.

  1. System for slicing wafers

    NASA Technical Reports Server (NTRS)

    1982-01-01

    A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

  2. Design of an integrated aerial image sensor

    NASA Astrophysics Data System (ADS)

    Xue, Jing; Spanos, Costas J.

    2005-05-01

    The subject of this paper is a novel integrated aerial image sensor (IAIS) system suitable for integration within the surface of an autonomous test wafer. The IAIS could be used as a lithography processing monitor, affording a "wafer's eye view" of the process, and therefore facilitating advanced process control and diagnostics without integrating (and dedicating) the sensor to the processing equipment. The IAIS is composed of an aperture mask and an array of photo-detectors. In order to retrieve nanometer scale resolution of the aerial image with a practical photo-detector pixel size, we propose a design of an aperture mask involving a series of spatial phase "moving" aperture groups. We demonstrate a design example aimed at the 65nm technology node through TEMPEST simulation. The optimized, key design parameters include an aperture width in the range of 30nm, aperture thickness in the range of 70nm, and offer a spatial resolution of about 5nm, all with comfortable fabrication tolerances. Our preliminary simulation work indicates the possibility of the IAIS being applied to the immersion lithography. A bench-top far-field experiment verifies that our approach of the spatial frequency down-shift through forming large Moire patterns is feasible.

  3. Imaging ATUM ultrathin section libraries with WaferMapper: a multi-scale approach to EM reconstruction of neural circuits

    PubMed Central

    Hayworth, Kenneth J.; Morgan, Josh L.; Schalek, Richard; Berger, Daniel R.; Hildebrand, David G. C.; Lichtman, Jeff W.

    2014-01-01

    The automated tape-collecting ultramicrotome (ATUM) makes it possible to collect large numbers of ultrathin sections quickly—the equivalent of a petabyte of high resolution images each day. However, even high throughput image acquisition strategies generate images far more slowly (at present ~1 terabyte per day). We therefore developed WaferMapper, a software package that takes a multi-resolution approach to mapping and imaging select regions within a library of ultrathin sections. This automated method selects and directs imaging of corresponding regions within each section of an ultrathin section library (UTSL) that may contain many thousands of sections. Using WaferMapper, it is possible to map thousands of tissue sections at low resolution and target multiple points of interest for high resolution imaging based on anatomical landmarks. The program can also be used to expand previously imaged regions, acquire data under different imaging conditions, or re-image after additional tissue treatments. PMID:25018701

  4. Wafer chamber having a gas curtain for extreme-UV lithography

    DOEpatents

    Kanouff, Michael P.; Ray-Chaudhuri, Avijit K.

    2001-01-01

    An EUVL device includes a wafer chamber that is separated from the upstream optics by a barrier having an aperture that is permeable to the inert gas. Maintaining an inert gas curtain in the proximity of a wafer positioned in a chamber of an extreme ultraviolet lithography device can effectively prevent contaminants from reaching the optics in an extreme ultraviolet photolithography device even though solid window filters are not employed between the source of reflected radiation, e.g., the camera, and the wafer. The inert gas removes the contaminants by entrainment.

  5. In-situ wafer bowing measurements of GaN grown on Si (111) substrate by reflectivity mapping in metal organic chemical vapor deposition system

    NASA Astrophysics Data System (ADS)

    Yang, Yi-Bin; Liu, Ming-Gang; Chen, Wei-Jie; Han, Xiao-Biao; Chen, Jie; Lin, Xiu-Qi; Lin, Jia-Li; Luo, Hui; Liao, Qiang; Zang, Wen-Jie; Chen, Yin-Song; Qiu, Yun-Ling; Wu, Zhi-Sheng; Liu, Yang; Zhang, Bai-Jun

    2015-09-01

    In this work, the wafer bowing during growth can be in-situ measured by a reflectivity mapping method in the 3×2″ Thomas Swan close coupled showerhead metal organic chemical vapor deposition (MOCVD) system. The reflectivity mapping method is usually used to measure the film thickness and growth rate. The wafer bowing caused by stresses (tensile and compressive) during the epitaxial growth leads to a temperature variation at different positions on the wafer, and the lower growth temperature leads to a faster growth rate and vice versa. Therefore, the wafer bowing can be measured by analyzing the discrepancy of growth rates at different positions on the wafer. Furthermore, the wafer bowings were confirmed by the ex-situ wafer bowing measurement. High-resistivity and low-resistivity Si substrates were used for epitaxial growth. In comparison with low-resistivity Si substrate, GaN grown on high-resistivity substrate shows a larger wafer bowing caused by the highly compressive stress introduced by compositionally graded AlGaN buffer layer. This transition of wafer bowing can be clearly in-situ measured by using the reflectivity mapping method. Project supported by the National Natural Science Foundation of China (Grant Nos. 61274039 and 51177175), the National Basic Research Program of China (Grant No. 2011CB301903), the Ph.D. Programs Foundation of Ministry of Education of China (Grant No. 20110171110021), the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260), the International Science and Technology Collaboration Program of Guangdong Province, China (Grant No. 2013B051000041), the Science and Technology Plan of Guangdong Province, China (Grant No. 2013B010401013), the National High Technology Research and Development Program of China (Grant No. 2014AA032606), and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics, China (Grant No. IOSKL2014KF17).

  6. Wafer-scale controlled exfoliation of metal organic vapor phase epitaxy grown InGaN/GaN multi quantum well structures using low-tack two-dimensional layered h-BN

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Ayari, Taha; Li, Xin; Voss, Paul L.

    Recent advances in epitaxial growth have led to the growth of III-nitride devices on 2D layered h-BN. This advance has the potential for wafer-scale transfer to arbitrary substrates, which could improve the thermal management and would allow III-N devices to be used more flexibly in a broader range of applications. We report wafer scale exfoliation of a metal organic vapor phase epitaxy grown InGaN/GaN Multi Quantum Well (MQW) structure from a 5 nm thick h-BN layer that was grown on a 2-inch sapphire substrate. The weak van der Waals bonds between h-BN atomic layers break easily, allowing the MQW structure tomore » be mechanically lifted off from the sapphire substrate using a commercial adhesive tape. This results in the surface roughness of only 1.14 nm on the separated surface. Structural characterizations performed before and after the lift-off confirm the conservation of structural properties after lift-off. Cathodoluminescence at 454 nm was present before lift-off and 458 nm was present after. Electroluminescence near 450 nm from the lifted-off structure has also been observed. These results show that the high crystalline quality ultrathin h-BN serves as an effective sacrificial layer—it maintains performance, while also reducing the GaN buffer thickness and temperature ramps as compared to a conventional two-step growth method. These results support the use of h-BN as a low-tack sacrificial underlying layer for GaN-based device structures and demonstrate the feasibility of large area lift-off and transfer to any template, which is important for industrial scale production.« less

  7. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In thismore » manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented« less

  8. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    PubMed Central

    Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

    2013-01-01

    Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

  9. Heterogeneous integration of lithium niobate and silicon nitride waveguides for wafer-scale photonic integrated circuits on silicon.

    PubMed

    Chang, Lin; Pfeiffer, Martin H P; Volet, Nicolas; Zervas, Michael; Peters, Jon D; Manganelli, Costanza L; Stanton, Eric J; Li, Yifei; Kippenberg, Tobias J; Bowers, John E

    2017-02-15

    An ideal photonic integrated circuit for nonlinear photonic applications requires high optical nonlinearities and low loss. This work demonstrates a heterogeneous platform by bonding lithium niobate (LN) thin films onto a silicon nitride (Si3N4) waveguide layer on silicon. It not only provides large second- and third-order nonlinear coefficients, but also shows low propagation loss in both the Si3N4 and the LN-Si3N4 waveguides. The tapers enable low-loss-mode transitions between these two waveguides. This platform is essential for various on-chip applications, e.g., modulators, frequency conversions, and quantum communications.

  10. Robust wafer identification recognition based on asterisk-shape filter and high-low score comparison method.

    PubMed

    Hsu, Wei-Chih; Yu, Tsan-Ying; Chen, Kuan-Liang

    2009-12-10

    Wafer identifications (wafer ID) can be used to identify wafers from each other so that wafer processing can be traced easily. Wafer ID recognition is one of the problems of optical character recognition. The process to recognize wafer IDs is similar to that used in recognizing car license-plate characters. However, due to some unique characteristics, such as the irregular space between two characters and the unsuccessive strokes of wafer ID, it will not get a good result to recognize wafer ID by directly utilizing the approaches used in car license-plate character recognition. Wafer ID scratches are engraved by a laser scribe almost along the following four fixed directions: horizontal, vertical, plus 45 degrees , and minus 45 degrees orientations. The closer to the center line of a wafer ID scratch, the higher the gray level will be. These and other characteristics increase the difficulty to recognize the wafer ID. In this paper a wafer ID recognition scheme based on an asterisk-shape filter and a high-low score comparison method is proposed to cope with the serious influence of uneven luminance and make recognition more efficiently. Our proposed approach consists of some processing stages. Especially in the final recognition stage, a template-matching method combined with stroke analysis is used as a recognizing scheme. This is because wafer IDs are composed of Semiconductor Equipment and Materials International (SEMI) standard Arabic numbers and English alphabets, and thus the template ID images are easy to obtain. Furthermore, compared with the approach that requires prior training, such as a support vector machine, which often needs a large amount of training image samples, no prior training is required for our approach. The testing results show that our proposed scheme can efficiently and correctly segment out and recognize the wafer ID with high performance.

  11. Hybrid Integrated Platforms for Silicon Photonics

    PubMed Central

    Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

    2010-01-01

    A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

  12. W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

    NASA Technical Reports Server (NTRS)

    Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

    1997-01-01

    Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

  13. Method for photolithographic definition of recessed features on a semiconductor wafer utilizing auto-focusing alignment

    DOEpatents

    Farino, A.J.; Montague, S.; Sniegowski, J.J.; Smith, J.H.; McWhorter, P.J.

    1998-07-21

    A method is disclosed for photolithographically defining device features up to the resolution limit of an auto-focusing projection stepper when the device features are to be formed in a wafer cavity at a depth exceeding the depth of focus of the stepper. The method uses a focusing cavity located in a die field at the position of a focusing light beam from the auto-focusing projection stepper, with the focusing cavity being of the same depth as one or more adjacent cavities wherein a semiconductor device is to be formed. The focusing cavity provides a bottom surface for referencing the focusing light beam and focusing the stepper at a predetermined depth below the surface of the wafer, whereat the device features are to be defined. As material layers are deposited in each device cavity to build up a semiconductor structure such as a microelectromechanical system (MEMS) device, the same material layers are deposited in the focusing cavity, raising the bottom surface and re-focusing the stepper for accurately defining additional device features in each succeeding material layer. The method is especially applicable for forming MEMS devices within a cavity or trench and integrating the MEMS devices with electronic circuitry fabricated on the wafer surface. 15 figs.

  14. Method for photolithographic definition of recessed features on a semiconductor wafer utilizing auto-focusing alignment

    DOEpatents

    Farino, Anthony J.; Montague, Stephen; Sniegowski, Jeffry J.; Smith, James H.; McWhorter, Paul J.

    1998-01-01

    A method is disclosed for photolithographically defining device features up to the resolution limit of an auto-focusing projection stepper when the device features are to be formed in a wafer cavity at a depth exceeding the depth of focus of the stepper. The method uses a focusing cavity located in a die field at the position of a focusing light beam from the auto-focusing projection stepper, with the focusing cavity being of the same depth as one or more adjacent cavities wherein a semiconductor device is to be formed. The focusing cavity provides a bottom surface for referencing the focusing light beam and focusing the stepper at a predetermined depth below the surface of the wafer, whereat the device features are to be defined. As material layers are deposited in each device cavity to build up a semiconductor structure such as a microelectromechanical system (MEMS) device, the same material layers are deposited in the focusing cavity, raising the bottom surface and re-focusing the stepper for accurately defining additional device features in each succeeding material layer. The method is especially applicable for forming MEMS devices within a cavity or trench and integrating the MEMS devices with electronic circuitry fabricated on the wafer surface.

  15. Multi-wire slurry wafering demonstrations. [slicing silicon ingots for solar arrays

    NASA Technical Reports Server (NTRS)

    Chen, C. P.

    1978-01-01

    Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

  16. High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

    PubMed

    Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

    2017-04-25

    Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

  17. High frequency guided wave propagation in monocrystalline silicon wafers

    NASA Astrophysics Data System (ADS)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2017-04-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

  18. Cryogenic probe station for on-wafer characterization of electrical devices

    NASA Astrophysics Data System (ADS)

    Russell, Damon; Cleary, Kieran; Reeves, Rodrigo

    2012-04-01

    A probe station, suitable for the electrical characterization of integrated circuits at cryogenic temperatures is presented. The unique design incorporates all moving components inside the cryostat at room temperature, greatly simplifying the design and allowing automated step and repeat testing. The system can characterize wafers up to 100 mm in diameter, at temperatures <20 K. It is capable of highly repeatable measurements at millimeter-wave frequencies, even though it utilizes a Gifford McMahon cryocooler which typically imposes limits due to vibration. Its capabilities are illustrated by noise temperature and S-parameter measurements on low noise amplifiers for radio astronomy, operating at 75-116 GHz.

  19. Non-contact defect diagnostics in Cz-Si wafers using resonance ultrasonic vibrations

    NASA Astrophysics Data System (ADS)

    Belyaev, A.; Kochelap, V. A.; Tarasov, I.; Ostapenko, S.

    2001-01-01

    A new resonance effect of generation of sub-harmonic acoustic vibrations was applied to characterize defects in as-grown and processed Cz-Si wafers. Ultrasonic vibrations were generated into standard 8″ wafers using an external ultrasonic transducer and their amplitude recorded in a non-contact mode using a scanning acoustic probe. By tuning the frequency, f, of the transducer we observed generation of intense sub-harmonic acoustic mode ("whistle" or w-mode) with f/2 frequency. The characteristics of the w-mode-amplitude dependence, frequency scans, spatial distribution allow a clear distinction versus harmonic vibrations of the same wafer. The origin of sub-harmonic vibrations observed on 8″ Cz-Si wafers is attributed to a parametric resonance of flexural vibrations in thin silicon circular plates. We present evidence that "whistle" effect shows a strong dependence on the wafer's growth and processing history and can be used for quality assurance purposes.

  20. A front-end wafer-level microsystem packaging technique with micro-cap array

    NASA Astrophysics Data System (ADS)

    Chiang, Yuh-Min

    2002-09-01

    The back-end packaging process is the remaining challenge for the micromachining industry to commercialize microsystem technology (MST) devices at low cost. This dissertation presents a novel wafer level protection technique as a final step of the front-end fabrication process for MSTs. It facilitates improved manufacturing throughput and automation in package assembly, wafer level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized micro-cap array, which consists of an assortment of small caps micro-molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments during packaging. The micro-cap array is first constructed by a micromachining process with micro-molding technique, then sealed to the device wafer at wafer level. Epoxy-based wafer-level micro cap array has been successfully fabricated and showed good compatibility with conventional back-end packaging processes. An adhesive transfer technique was demonstrated to seal the micro cap array with a MEMS device wafer. No damage or gross leak was observed while wafer dicing or later during a gross leak test. Applications of the micro cap array are demonstrated on MEMS, microactuators fabricated using CRONOS MUMPS process. Depending on the application needs, the micro-molded cap can be designed and modified to facilitate additional component functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. Successful fabrication of a micro cap array comprised with microlenses can provide active functions as well as passive protection. An optical tweezer array could be one possibility for applications of a micro cap with microlenses. The micro cap itself could serve as micro well for DNA or bacteria amplification as well.

  1. Very Large Scale Integration (VLSI).

    ERIC Educational Resources Information Center

    Yeaman, Andrew R. J.

    Very Large Scale Integration (VLSI), the state-of-the-art production techniques for computer chips, promises such powerful, inexpensive computing that, in the future, people will be able to communicate with computer devices in natural language or even speech. However, before full-scale VLSI implementation can occur, certain salient factors must be…

  2. Lamb wave propagation in monocrystalline silicon wafers.

    PubMed

    Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

  3. A 45° saw-dicing process applied to a glass substrate for wafer-level optical splitter fabrication for optical coherence tomography

    NASA Astrophysics Data System (ADS)

    Maciel, M. J.; Costa, C. G.; Silva, M. F.; Gonçalves, S. B.; Peixoto, A. C.; Ribeiro, A. Fernando; Wolffenbuttel, R. F.; Correia, J. H.

    2016-08-01

    This paper reports on the development of a technology for the wafer-level fabrication of an optical Michelson interferometer, which is an essential component in a micro opto-electromechanical system (MOEMS) for a miniaturized optical coherence tomography (OCT) system. The MOEMS consists on a titanium dioxide/silicon dioxide dielectric beam splitter and chromium/gold micro-mirrors. These optical components are deposited on 45° tilted surfaces to allow the horizontal/vertical separation of the incident beam in the final micro-integrated system. The fabrication process consists of 45° saw dicing of a glass substrate and the subsequent deposition of dielectric multilayers and metal layers. The 45° saw dicing is fully characterized in this paper, which also includes an analysis of the roughness. The optimum process results in surfaces with a roughness of 19.76 nm (rms). The actual saw dicing process for a high-quality final surface results as a compromise between the dicing blade’s grit size (#1200) and the cutting speed (0.3 mm s-1). The proposed wafer-level fabrication allows rapid and low-cost processing, high compactness and the possibility of wafer-level alignment/assembly with other optical micro components for OCT integrated imaging.

  4. 1 million-Q optomechanical microdisk resonators for sensing with very large scale integration

    NASA Astrophysics Data System (ADS)

    Hermouet, M.; Sansa, M.; Banniard, L.; Fafin, A.; Gely, M.; Allain, P. E.; Santos, E. Gil; Favero, I.; Alava, T.; Jourdan, G.; Hentz, S.

    2018-02-01

    Cavity optomechanics have become a promising route towards the development of ultrasensitive sensors for a wide range of applications including mass, chemical and biological sensing. In this study, we demonstrate the potential of Very Large Scale Integration (VLSI) with state-of-the-art low-loss performance silicon optomechanical microdisks for sensing applications. We report microdisks exhibiting optical Whispering Gallery Modes (WGM) with 1 million quality factors, yielding high displacement sensitivity and strong coupling between optical WGMs and in-plane mechanical Radial Breathing Modes (RBM). Such high-Q microdisks with mechanical resonance frequencies in the 102 MHz range were fabricated on 200 mm wafers with Variable Shape Electron Beam lithography. Benefiting from ultrasensitive readout, their Brownian motion could be resolved with good Signal-to-Noise ratio at ambient pressure, as well as in liquid, despite high frequency operation and large fluidic damping: the mechanical quality factor reduced from few 103 in air to 10's in liquid, and the mechanical resonance frequency shifted down by a few percent. Proceeding one step further, we performed an all-optical operation of the resonators in air using a pump-probe scheme. Our results show our VLSI process is a viable approach for the next generation of sensors operating in vacuum, gas or liquid phase.

  5. Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

    NASA Technical Reports Server (NTRS)

    Okojie, Robert S. (Inventor)

    2002-01-01

    A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

  6. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  7. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

    1979-01-01

    A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

  8. Warpage Measurement of Thin Wafers by Reflectometry

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand Krishna

    To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

  9. Engineering Controlled Spalling in (100)-Oriented GaAs for Wafer Reuse

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Sweet, Cassi A.; McNeely, Joshua E.; Gorman, Brian

    Controlled spalling offers a way to cleave thin, single-crystal films or devices from wafers, particularly if the fracture planes in the material are oriented parallel to the wafer surface. Unfortunately, misalignment between the favored fracture planes and the wafer surface preferred for photovoltaic growth in (100)-oriented GaAs produces a highly faceted surface when subject to controlled spalling. This highly faceted cleavage surface is problematic in several ways: (1) it can result in large variations of spall depth due to unstable crack propagation; (2) it may introduce defects into the device zone or underlying substrate; and (3) it consumes many micronsmore » of material outside of the device zone. We present the ways in which we have engineered controlled spalling for (100)-oriented GaAs to minimize these effects. We expand the operational window for controlled spalling to avoid spontaneous spalling, find no evidence of dislocation activity in the spalled film or the parent wafer, and reduce facet height and facet height irregularity. Resolving these issues provides a viable path forward for reducing III-V device cost through the controlled spalling of (100)-oriented GaAs devices and subsequent wafer reuse when these processes are combined with a high-throughput growth method such as Hydride Vapor Phase Epitaxy.« less

  10. Direct wafer bonding of highly conductive GaSb/GaInAs and GaSb/GaInP heterojunctions prepared by argon-beam surface activation

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Predan, Felix, E-mail: felix.predan@ise.fraunhofer.de; Reinwand, Dirk; Cariou, Romain

    The authors present a low-temperature wafer bonding process for the formation of electrically conductive n-GaSb/n-Ga{sub 0.79}In{sub 0.21}As and n-GaSb/n-Ga{sub 0.32}In{sub 0.68}P heterojunctions. The surfaces are deoxidized by sputter-etching with an argon-beam and bonded in ultrahigh vacuum. The sputtering behavior was investigated for each material, revealing a distinct selective sputtering characteristic for Ga{sub 0.32}In{sub 0.68}P. According to these findings, the settings for the bonding process were chosen. The mechanical and electrical properties of the wafer bonds were studied. Fully bonded 2 in. wafer pairs were found for both material combinations exhibiting high bond energies, which are comparable to the binding energiesmore » in the semiconductors. Furthermore, bond resistances below 5 mΩ cm{sup 2} could be reached, which are in the range of the lowest resistances that have been reported for wafer bonded heterojunctions. This speaks, together with the high bond energies, for a high amount of covalent bonds at the interfaces. These promising bond characteristics make the integration of antimonides with arsenides or phosphides by wafer bonding attractive for various optoelectronic applications such as multijunction solar cells.« less

  11. Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

    NASA Astrophysics Data System (ADS)

    Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

    2018-04-01

    Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

  12. Coaxial twin-shaft magnetic fluid seals applied in vacuum wafer-handling robot

    NASA Astrophysics Data System (ADS)

    Cong, Ming; Wen, Haiying; Du, Yu; Dai, Penglei

    2012-07-01

    Compared with traditional mechanical seals, magnetic fluid seals have unique characters of high airtightness, minimal friction torque requirements, pollution-free and long life-span, widely used in vacuum robots. With the rapid development of Integrate Circuit (IC), there is a stringent requirement for sealing wafer-handling robots when working in a vacuum environment. The parameters of magnetic fluid seals structure is very important in the vacuum robot design. This paper gives a magnetic fluid seal device for the robot. Firstly, the seal differential pressure formulas of magnetic fluid seal are deduced according to the theory of ferrohydrodynamics, which indicate that the magnetic field gradient in the sealing gap determines the seal capacity of magnetic fluid seal. Secondly, the magnetic analysis model of twin-shaft magnetic fluid seals structure is established. By analyzing the magnetic field distribution of dual magnetic fluid seal, the optimal value ranges of important parameters, including parameters of the permanent magnetic ring, the magnetic pole tooth, the outer shaft, the outer shaft sleeve and the axial relative position of two permanent magnetic rings, which affect the seal differential pressure, are obtained. A wafer-handling robot equipped with coaxial twin-shaft magnetic fluid rotary seals and bellows seal is devised and an optimized twin-shaft magnetic fluid seals experimental platform is built. Test result shows that when the speed of the two rotational shafts ranges from 0-500 r/min, the maximum burst pressure is about 0.24 MPa. Magnetic fluid rotary seals can provide satisfactory performance in the application of wafer-handling robot. The proposed coaxial twin-shaft magnetic fluid rotary seal provides the instruction to design high-speed vacuum robot.

  13. Enhanced capture rate for haze defects in production wafer inspection

    NASA Astrophysics Data System (ADS)

    Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

    2010-03-01

    Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure

  14. Reduction of wafer-edge overlay errors using advanced correction models, optimized for minimal metrology requirements

    NASA Astrophysics Data System (ADS)

    Kim, Min-Suk; Won, Hwa-Yeon; Jeong, Jong-Mun; Böcker, Paul; Vergaij-Huizer, Lydia; Kupers, Michiel; Jovanović, Milenko; Sochal, Inez; Ryan, Kevin; Sun, Kyu-Tae; Lim, Young-Wan; Byun, Jin-Moo; Kim, Gwang-Gon; Suh, Jung-Joon

    2016-03-01

    In order to optimize yield in DRAM semiconductor manufacturing for 2x nodes and beyond, the (processing induced) overlay fingerprint towards the edge of the wafer needs to be reduced. Traditionally, this is achieved by acquiring denser overlay metrology at the edge of the wafer, to feed field-by-field corrections. Although field-by-field corrections can be effective in reducing localized overlay errors, the requirement for dense metrology to determine the corrections can become a limiting factor due to a significant increase of metrology time and cost. In this study, a more cost-effective solution has been found in extending the regular correction model with an edge-specific component. This new overlay correction model can be driven by an optimized, sparser sampling especially at the wafer edge area, and also allows for a reduction of noise propagation. Lithography correction potential has been maximized, with significantly less metrology needs. Evaluations have been performed, demonstrating the benefit of edge models in terms of on-product overlay performance, as well as cell based overlay performance based on metrology-to-cell matching improvements. Performance can be increased compared to POR modeling and sampling, which can contribute to (overlay based) yield improvement. Based on advanced modeling including edge components, metrology requirements have been optimized, enabling integrated metrology which drives down overall metrology fab footprint and lithography cycle time.

  15. Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

    PubMed Central

    Kazior, Thomas E.

    2014-01-01

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  16. Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

    PubMed

    Kazior, Thomas E

    2014-03-28

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

  17. ILT based defect simulation of inspection images accurately predicts mask defect printability on wafer

    NASA Astrophysics Data System (ADS)

    Deep, Prakash; Paninjath, Sankaranarayanan; Pereira, Mark; Buck, Peter

    2016-05-01

    At advanced technology nodes mask complexity has been increased because of large-scale use of resolution enhancement technologies (RET) which includes Optical Proximity Correction (OPC), Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO). The number of defects detected during inspection of such mask increased drastically and differentiation of critical and non-critical defects are more challenging, complex and time consuming. Because of significant defectivity of EUVL masks and non-availability of actinic inspection, it is important and also challenging to predict the criticality of defects for printability on wafer. This is one of the significant barriers for the adoption of EUVL for semiconductor manufacturing. Techniques to decide criticality of defects from images captured using non actinic inspection images is desired till actinic inspection is not available. High resolution inspection of photomask images detects many defects which are used for process and mask qualification. Repairing all defects is not practical and probably not required, however it's imperative to know which defects are severe enough to impact wafer before repair. Additionally, wafer printability check is always desired after repairing a defect. AIMSTM review is the industry standard for this, however doing AIMSTM review for all defects is expensive and very time consuming. Fast, accurate and an economical mechanism is desired which can predict defect printability on wafer accurately and quickly from images captured using high resolution inspection machine. Predicting defect printability from such images is challenging due to the fact that the high resolution images do not correlate with actual mask contours. The challenge is increased due to use of different optical condition during inspection other than actual scanner condition, and defects found in such images do not have correlation with actual impact on wafer. Our automated defect simulation tool predicts

  18. Big data driven cycle time parallel prediction for production planning in wafer manufacturing

    NASA Astrophysics Data System (ADS)

    Wang, Junliang; Yang, Jungang; Zhang, Jie; Wang, Xiaoxi; Zhang, Wenjun Chris

    2018-07-01

    Cycle time forecasting (CTF) is one of the most crucial issues for production planning to keep high delivery reliability in semiconductor wafer fabrication systems (SWFS). This paper proposes a novel data-intensive cycle time (CT) prediction system with parallel computing to rapidly forecast the CT of wafer lots with large datasets. First, a density peak based radial basis function network (DP-RBFN) is designed to forecast the CT with the diverse and agglomerative CT data. Second, the network learning method based on a clustering technique is proposed to determine the density peak. Third, a parallel computing approach for network training is proposed in order to speed up the training process with large scaled CT data. Finally, an experiment with respect to SWFS is presented, which demonstrates that the proposed CTF system can not only speed up the training process of the model but also outperform the radial basis function network, the back-propagation-network and multivariate regression methodology based CTF methods in terms of the mean absolute deviation and standard deviation.

  19. Silicon wafer temperature monitoring using all-fiber laser ultrasonics

    NASA Astrophysics Data System (ADS)

    Alcoz, Jorge J.; Duffer, Charles E.

    1998-03-01

    Laser-ultrasonics is a very attractive technique for in-line process control in the semiconductor industry as it is compatible with the clean room environment and offers the capability to inspect parts at high-temperature. We describe measurements of the velocity of laser-generated Lamb waves in silicon wafers as a function of temperature using fiber- optic laser delivery and all-fiber interferometric sensing. Fundamental anti-symmetric Lamb-wave modes were generated in 5 inches < 111 > silicon wafers using a Nd:YAG laser coupled to a large-core multimode fiber. Generation was also performed using an array of sources created with a diffraction grating. For detection a compact fiber-optic sensor was used which is well suited for industrial environments as it is compact, rugged, stable, and low-cost. The wafers were heated up to 1000 degrees C and the temperature correlated with ultrasonic velocity measurements.

  20. Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

    NASA Astrophysics Data System (ADS)

    Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

    2018-05-01

    Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

  1. Intentional defect array wafers: their practical use in semiconductor control and monitoring systems

    NASA Astrophysics Data System (ADS)

    Emami, Iraj; McIntyre, Michael; Retersdorf, Michael

    2003-07-01

    In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.

  2. Contactless measurement of electrical conductivity of semiconductor wafers using the reflection of millimeter waves

    NASA Astrophysics Data System (ADS)

    Ju, Yang; Inoue, Kojiro; Saka, Masumi; Abe, Hiroyuki

    2002-11-01

    We present a method for quantitative measurement of electrical conductivity of semiconductor wafers in a contactless fashion by using millimeter waves. A focusing sensor was developed to focus a 110 GHz millimeter wave beam on the surface of a silicon wafer. The amplitude and the phase of the reflection coefficient of the millimeter wave signal were measured by which electrical conductivity of the wafer was determined quantitatively, independent of the permittivity and thickness of the wafers. The conductivity obtained by this method agrees well with that measured by the conventional four-point-probe method.

  3. 1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Lorenz, Adam

    For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10more » billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).« less

  4. Surface etching technologies for monocrystalline silicon wafer solar cells

    NASA Astrophysics Data System (ADS)

    Tang, Muzhi

    With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

  5. Probing photo-carrier collection efficiencies of individual silicon nanowire diodes on a wafer substrate.

    PubMed

    Schmitt, S W; Brönstrup, G; Shalev, G; Srivastava, S K; Bashouti, M Y; Döhler, G H; Christiansen, S H

    2014-07-21

    Vertically aligned silicon nanowire (SiNW) diodes are promising candidates for the integration into various opto-electronic device concepts for e.g. sensing or solar energy conversion. Individual SiNW p-n diodes have intensively been studied, but to date an assessment of their device performance once integrated on a silicon substrate has not been made. We show that using a scanning electron microscope (SEM) equipped with a nano-manipulator and an optical fiber feed-through for tunable (wavelength, power using a tunable laser source) sample illumination, the dark and illuminated current-voltage (I-V) curve of individual SiNW diodes on the substrate wafer can be measured. Surprisingly, the I-V-curve of the serially coupled system composed of SiNW/wafers is accurately described by an equivalent circuit model of a single diode and diode parameters like series and shunting resistivity, diode ideality factor and photocurrent can be retrieved from a fit. We show that the photo-carrier collection efficiency (PCE) of the integrated diode illuminated with variable wavelength and intensity light directly gives insight into the quality of the device design at the nanoscale. We find that the PCE decreases for high light intensities and photocurrent densities, due to the fact that considerable amounts of photo-excited carriers generated within the substrate lead to a decrease in shunting resistivity of the SiNW diode and deteriorate its rectification. The PCE decreases systematically for smaller wavelengths of visible light, showing the possibility of monitoring the effectiveness of the SiNW device surface passivation using the shown measurement technique. The integrated device was pre-characterized using secondary ion mass spectrometry (SIMS), TCAD simulations and electron beam induced current (EBIC) measurements to validate the properties of the characterized material at the single SiNW diode level.

  6. Printable Single-Crystal Silicon Micro/Nanoscale Ribbons, Platelets and Bars Generated from Bulk Wafers

    DTIC Science & Technology

    2007-08-28

    enables high yield integration onto wafers, glass plates, plastic sheets, rubber slabs or other surfaces. As one application example, bottom gate thin... EPDMS 1m2Si ESi 1m2PDMS 23 is the critical strain for buck- ling, epre is the degree of prestrain, k0 and A0 are...Young’s modulus of Si and PDMS. The following values were used to yield the calcualted value of it (i.e., 84 lm): ESi = 160 GPa, EPDMS = 2 MPa, mPDMS

  7. Advanced FTIR technology for the chemical characterization of product wafers

    NASA Astrophysics Data System (ADS)

    Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

    2001-01-01

    Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers.

  8. Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

    NASA Astrophysics Data System (ADS)

    Altan, Hakan

    All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on

  9. Hybrid Integration of III-V Solar Microcells for High Efficiency Concentrated Photovoltaic Modules

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Tauke-Pedretti, Anna; Cederberg, Jeffery; Cruz-Campa, Jose Luis

    The design, fabrication and performance of InGaAs and InGaP/GaAs microcells are presented. These cells are integrated with a Si wafer providing a path for insertion in hybrid concentrated photovoltaic modules. Comparisons are made between bonded cells and cells fabricated on their native wafer. The bonded cells showed no evidence of degradation in spite of the integration process which involved significant processing including the removal of the III-V substrate. Results from a number of hybrid cell configurations were reported. These cells employed integration techniques including wafer level bonding of processed cells and solder bonding of the cells. Lastly, the cells themselvesmore » showed evidence of degradation in spite of the integration process, which involved significant processing including the removal of the III-V substrate.« less

  10. Hybrid Integration of III-V Solar Microcells for High Efficiency Concentrated Photovoltaic Modules

    DOE PAGES

    Tauke-Pedretti, Anna; Cederberg, Jeffery; Cruz-Campa, Jose Luis; ...

    2018-03-09

    The design, fabrication and performance of InGaAs and InGaP/GaAs microcells are presented. These cells are integrated with a Si wafer providing a path for insertion in hybrid concentrated photovoltaic modules. Comparisons are made between bonded cells and cells fabricated on their native wafer. The bonded cells showed no evidence of degradation in spite of the integration process which involved significant processing including the removal of the III-V substrate. Results from a number of hybrid cell configurations were reported. These cells employed integration techniques including wafer level bonding of processed cells and solder bonding of the cells. Lastly, the cells themselvesmore » showed evidence of degradation in spite of the integration process, which involved significant processing including the removal of the III-V substrate.« less

  11. Mechanics of wafer bonding: Effect of clamping

    NASA Astrophysics Data System (ADS)

    Turner, K. T.; Thouless, M. D.; Spearing, S. M.

    2004-01-01

    A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

  12. X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

    NASA Technical Reports Server (NTRS)

    Park, Yeonjoon (Inventor); Kim, Hyun Jung (Inventor); Skuza, Jonathan R. (Inventor); Lee, Kunik (Inventor); Choi, Sang Hyouk (Inventor); King, Glen C. (Inventor)

    2017-01-01

    An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

  13. Hybrid integrated single-wavelength laser with silicon micro-ring reflector

    NASA Astrophysics Data System (ADS)

    Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

    2018-02-01

    A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

  14. Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

    NASA Astrophysics Data System (ADS)

    Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

    2018-04-01

    In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

  15. An Integrated Scale for Measuring an Organizational Learning System

    ERIC Educational Resources Information Center

    Jyothibabu, C.; Farooq, Ayesha; Pradhan, Bibhuti Bhusan

    2010-01-01

    Purpose: The purpose of this paper is to develop an integrated measurement scale for an organizational learning system by capturing the learning enablers, learning results and performance outcome in an organization. Design/methodology/approach: A new measurement scale was developed by integrating and modifying two existing scales, identified…

  16. Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

    NASA Astrophysics Data System (ADS)

    Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

    2015-03-01

    A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

  17. Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

    PubMed Central

    Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

    2015-01-01

    A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing. PMID:25819285

  18. Techniques for control of long-term reliability of complex integrated circuits. I - Reliability assurance by test vehicle qualification.

    NASA Technical Reports Server (NTRS)

    Van Vonno, N. W.

    1972-01-01

    Development of an alternate approach to the conventional methods of reliability assurance for large-scale integrated circuits. The product treated is a large-scale T squared L array designed for space applications. The concept used is that of qualification of product by evaluation of the basic processing used in fabricating the product, providing an insight into its potential reliability. Test vehicles are described which enable evaluation of device characteristics, surface condition, and various parameters of the two-level metallization system used. Evaluation of these test vehicles is performed on a lot qualification basis, with the lot consisting of one wafer. Assembled test vehicles are evaluated by high temperature stress at 300 C for short time durations. Stressing at these temperatures provides a rapid method of evaluation and permits a go/no go decision to be made on the wafer lot in a timely fashion.

  19. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

    PubMed

    Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

    2015-12-16

    In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  20. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    PubMed Central

    Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

    2015-01-01

    In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction. PMID:26694407

  1. Crystallographic Orientation Identification in Multicrystalline Silicon Wafers Using NIR Transmission Intensity

    NASA Astrophysics Data System (ADS)

    Skenes, Kevin; Kumar, Arkadeep; Prasath, R. G. R.; Danyluk, Steven

    2018-02-01

    Near-infrared (NIR) polariscopy is a technique used for the non-destructive evaluation of the in-plane stresses in photovoltaic silicon wafers. Accurate evaluation of these stresses requires correct identification of the stress-optic coefficient, a material property which relates photoelastic parameters to physical stresses. The material stress-optic coefficient of silicon varies with crystallographic orientation. This variation poses a unique problem when measuring stresses in multicrystalline silicon (mc-Si) wafers. This paper concludes that the crystallographic orientation of silicon can be estimated by measuring the transmission of NIR light through the material. The transmission of NIR light through monocrystalline wafers of known orientation were compared with the transmission of NIR light through various grains in mc-Si wafers. X-ray diffraction was then used to verify the relationship by obtaining the crystallographic orientations of these assorted mc-Si grains. Variation of transmission intensity for different crystallographic orientations is further explained by using planar atomic density. The relationship between transmission intensity and planar atomic density appears to be linear.

  2. Accurate characterization of wafer bond toughness with the double cantilever specimen

    NASA Astrophysics Data System (ADS)

    Turner, Kevin T.; Spearing, S. Mark

    2008-01-01

    The displacement loaded double cantilever test, also referred to as the "Maszara test" and the "crack opening method" by the wafer bonding community, is a common technique used to evaluate the interface toughness or surface energy of direct wafer bonds. While the specimen is widely used, there has been a persistent question as to the accuracy of the method since the actual specimen geometry differs from the ideal beam geometry assumed in the expression used for data reduction. The effect of conducting the test on whole wafer pairs, in which the arms of cantilevers are wide plates rather than slender beams, is examined in this work using finite element analysis. A model is developed to predict the equilibrium shape of the crack front and to develop a corrected expression for calculating interface toughness from crack length measurements obtained in tests conducted on whole wafer pairs. The finite element model, which is validated through comparison to experiments, demonstrates that using the traditional beam theory-based expressions for data reduction can lead to errors of up to 25%.

  3. Scatterometry on pelliclized masks: an option for wafer fabs

    NASA Astrophysics Data System (ADS)

    Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

    2007-03-01

    Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

  4. Chip-scale sensor system integration for portable health monitoring.

    PubMed

    Jokerst, Nan M; Brooke, Martin A; Cho, Sang-Yeon; Shang, Allan B

    2007-12-01

    The revolution in integrated circuits over the past 50 yr has produced inexpensive computing and communications systems that are powerful and portable. The technologies for these integrated chip-scale sensing systems, which will be miniature, lightweight, and portable, are emerging with the integration of sensors with electronics, optical systems, micromachines, microfluidics, and the integration of chemical and biological materials (soft/wet material integration with traditional dry/hard semiconductor materials). Hence, we stand at a threshold for health monitoring technology that promises to provide wearable biochemical sensing systems that are comfortable, inauspicious, wireless, and battery-operated, yet that continuously monitor health status, and can transmit compressed data signals at regular intervals, or alarm conditions immediately. In this paper, we explore recent results in chip-scale sensor integration technology for health monitoring. The development of inexpensive chip-scale biochemical optical sensors, such as microresonators, that are customizable for high sensitivity coupled with rapid prototyping will be discussed. Ground-breaking work in the integration of chip-scale optical systems to support these optical sensors will be highlighted, and the development of inexpensive Si complementary metal-oxide semiconductor circuitry (which makes up the vast majority of computational systems today) for signal processing and wireless communication with local receivers that lie directly on the chip-scale sensor head itself will be examined.

  5. Wafer plane inspection with soft resist thresholding

    NASA Astrophysics Data System (ADS)

    Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

    2008-10-01

    Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

  6. Particle detection for patterned wafers of 100nm design rule by evanescent light illumination: analysis of evanescent light scattering using Finite-Difference Time-Domain (FDTD) method

    NASA Astrophysics Data System (ADS)

    Yoshioka, Toshie; Miyoshi, Takashi; Takaya, Yasuhiro

    2005-12-01

    To realize high productivity and reliability of the semiconductor, patterned wafers inspection technology to maintain high yield becomes essential in modern semiconductor manufacturing processes. As circuit feature is scaled below 100nm, the conventional imaging and light scattering methods are impossible to apply to the patterned wafers inspection technique, because of diffraction limit and lower S/N ratio. So, we propose a new particle detection method using annular evanescent light illumination. In this method, a converging annular light used as a light source is incident on a micro-hemispherical lens. When the converging angle is larger than critical angle, annular evanescent light is generated under the bottom surface of the hemispherical lens. Evanescent light is localized near by the bottom surface and decays exponentially away from the bottom surface. So, the evanescent light selectively illuminates the particles on the patterned wafer surface, because it can't illuminate the patterned wafer surface. The proposed method evaluates particles on a patterned wafer surface by detecting scattered evanescent light distribution from particles. To analyze the fundamental characteristics of the proposed method, the computer simulation was performed using FDTD method. The simulation results show that the proposed method is effective for detecting 100nm size particle on patterned wafer of 100nm lines and spaces, particularly under the condition that the evanescent light illumination with p-polarization and parallel incident to the line orientation. Finally, the experiment results suggest that 220nm size particle on patterned wafer of about 200nm lines and spaces can be detected.

  7. MiRNA-181d Expression Significantly Affects Treatment Responses to Carmustine Wafer Implantation.

    PubMed

    Sippl, Christoph; Ketter, Ralf; Bohr, Lisa; Kim, Yoo Jin; List, Markus; Oertel, Joachim; Urbschat, Steffi

    2018-05-26

    Standard therapeutic protocols for glioblastoma, the most aggressive type of brain cancer, include surgery followed by chemoradiotherapy. Additionally, carmustine-eluting wafers can be implanted locally into the resection cavity. To evaluate microRNA (miRNA)-181d as a prognostic marker of responses to carmustine wafer implantation. A total of 80 glioblastoma patients (40/group) were included in a matched pair analysis. One group (carmustine wafer group) received concomitant chemoradiotherapy with carmustine wafer implantation (Stupp protocol). The second group (control group) received only concomitant chemoradiotherapy. All tumor specimens were subjected to evaluations of miRNA-181d expression, results were correlated with further individual clinical data. The Cancer Genome Atlas (TCGA) dataset of 149 patients was used as an independent cohort to validate the results. Patients in the carmustine wafer group with low miRNA-181d expression had significantly longer overall (hazard ratio [HR], 35.03, [95% confidence interval (CI): 3.50-350.23], P = .002) and progression-free survival (HR, 20.23, [95% CI: 2.19-186.86], P = .008) than patients of the same group with a high miRNA-181d expression. These correlations were not observed in the control group. The nonsignificance in the control group was confirmed in the independent TCGA dataset. The carmustine wafer group patients with low miRNA-181d expression also had a significantly longer progression-free (P = .049) and overall survival (OS) (P = .034), compared with control group patients. Gross total resection correlated significantly with longer OS (P = .023). MiRNA-181d expression significantly affects treatment responses to carmustine wafer implantation.

  8. Grain-boundary type and distribution in silicon carbide coatings and wafers

    NASA Astrophysics Data System (ADS)

    Cancino-Trejo, Felix; López-Honorato, Eddie; Walker, Ross C.; Ferrer, Romelia Salomon

    2018-03-01

    Silicon carbide is the main diffusion barrier against metallic fission products in TRISO (tristructural isotropic) coated fuel particles. The explanation of the accelerated diffusion of silver through SiC has remained a challenge for more than four decades. Although, it is now well accepted that silver diffuse through SiC by grain boundary diffusion, little is known about the characteristics of the grain boundaries in SiC and how these change depending on the type of sample. In this work five different types (coatings and wafers) of SiC produced by chemical vapor deposition were characterized by electron backscatter diffraction (EBSD). The SiC in TRISO particles had a higher concentration of high angle grain boundaries (aprox. 70%) compared to SiC wafers, which ranged between 30 and 60%. Similarly, SiC wafers had a higher concentration of low angle grain boundaries ranging between 15 and 30%, whereas TRISO particles only reached values of around 7%. The same trend remained when comparing the content of coincidence site lattice (CSL) boundaries, since SiC wafers showed a concentration of more than 30%, whilst TRISO particles had contents of around 20%. In all samples the largest fractions of CSL boundaries (3 ≤ Σ ≤ 17) were the Σ3 boundaries. We show that there are important differences between the SiC in TRISO particles and SiC wafers which could explain some of the differences observed in diffusion experiments in the literature.

  9. Integrated simulation of continuous-scale and discrete-scale radiative transfer in metal foams

    NASA Astrophysics Data System (ADS)

    Xia, Xin-Lin; Li, Yang; Sun, Chuang; Ai, Qing; Tan, He-Ping

    2018-06-01

    A novel integrated simulation of radiative transfer in metal foams is presented. It integrates the continuous-scale simulation with the direct discrete-scale simulation in a single computational domain. It relies on the coupling of the real discrete-scale foam geometry with the equivalent continuous-scale medium through a specially defined scale-coupled zone. This zone holds continuous but nonhomogeneous volumetric radiative properties. The scale-coupled approach is compared to the traditional continuous-scale approach using volumetric radiative properties in the equivalent participating medium and to the direct discrete-scale approach employing the real 3D foam geometry obtained by computed tomography. All the analyses are based on geometrical optics. The Monte Carlo ray-tracing procedure is used for computations of the absorbed radiative fluxes and the apparent radiative behaviors of metal foams. The results obtained by the three approaches are in tenable agreement. The scale-coupled approach is fully validated in calculating the apparent radiative behaviors of metal foams composed of very absorbing to very reflective struts and that composed of very rough to very smooth struts. This new approach leads to a reduction in computational time by approximately one order of magnitude compared to the direct discrete-scale approach. Meanwhile, it can offer information on the local geometry-dependent feature and at the same time the equivalent feature in an integrated simulation. This new approach is promising to combine the advantages of the continuous-scale approach (rapid calculations) and direct discrete-scale approach (accurate prediction of local radiative quantities).

  10. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu

  11. Steel bridge fatigue crack detection with piezoelectric wafer active sensors

    NASA Astrophysics Data System (ADS)

    Yu, Lingyu; Giurgiutiu, Victor; Ziehl, Paul; Ozevin, Didem; Pollock, Patrick

    2010-04-01

    Piezoelectric wafer active sensors (PWAS) are well known for its dual capabilities in structural health monitoring, acting as either actuators or sensors. Due to the variety of deterioration sources and locations of bridge defects, there is currently no single method that can detect and address the potential sources globally. In our research, our use of the PWAS based sensing has the novelty of implementing both passive (as acoustic emission) and active (as ultrasonic transducers) sensing with a single PWAS network. The combined schematic is using acoustic emission to detect the presence of fatigue cracks in steel bridges in their early stage since methods such as ultrasonics are unable to quantify the initial condition of crack growth since most of the fatigue life for these details is consumed while the fatigue crack is too small to be detected. Hence, combing acoustic emission with ultrasonic active sensing will strengthen the damage detection process. The integration of passive acoustic emission detection with active sensing will be a technological leap forward from the current practice of periodic and subjective visual inspection, and bridge management based primarily on history of past performance. In this study, extensive laboratory investigation is performed supported by theoretical modeling analysis. A demonstration system will be presented to show how piezoelectric wafer active sensor is used for acoustic emission. Specimens representing complex structures are tested. The results will also be compared with traditional acoustic emission transducers to identify the application barriers.

  12. Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

    NASA Astrophysics Data System (ADS)

    Miki, N.; Spearing, S. M.

    2003-11-01

    Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

  13. Fabrication of Total-Dose-Radiation-Hardened (TDRH) SOI wafer with embedded silicon nanoclusters

    NASA Astrophysics Data System (ADS)

    Wu, Aimin; Wang, Xi; Wei, Xing; Chen, Jing; Chen, Ming; Zhang, Zhengxuan

    2009-05-01

    Si ion-implantation and post annealing of silicon wafers prior to wafer bonding were used to radiation-harden the thermal oxide layer of Silicon on Insulator structures. After grinding and polishing, Total-Dose-Radiation-Hardened SOI (TDRH-SOI) wafers with several-micron-thick device layers were prepared. Electrical characterization before and after X-ray irradiation showed that the flatband voltage shift induced by irradiation was reduced by this preprocessing. Photoluminescence Spectroscopy (PL), Transmission Electron Microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) results indicated that the improvement of the total dose response of the TDRH-SOI wafer was associated with formation of Si nanoclusters in the implanted oxide layer, suggesting that these were the likely candidates for electron and proton trapping centers that reduce the positive charge buildup effect in the buried oxide.

  14. Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

    PubMed

    Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

    2013-11-22

    Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

  15. Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Johnston, S.; Yan, F.; Dorn, D.

    2012-06-01

    Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect bandmore » images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.« less

  16. Smoother Scribing of Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Danyluk, S.

    1986-01-01

    Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

  17. Commercial production of QWIP wafers by molecular beam epitaxy

    NASA Astrophysics Data System (ADS)

    Fastenau, J. M.; Liu, W. K.; Fang, X. M.; Lubyshev, D. I.; Pelzel, R. I.; Yurasits, T. R.; Stewart, T. R.; Lee, J. H.; Li, S. S.; Tidrow, M. Z.

    2001-06-01

    As the performance of quantum well infrared photodetectors (QWIPs) and QWIP-based imaging systems continues to improve, their demand will undoubtedly grow. This points to the importance of a reliable commercial supplier of semiconductor QWIP material on three inch and, in the near future, four-inch substrates. Molecular beam epitaxy (MBE) is the preferred technique for growing the demanding QWIP structure, as tight control is required over the material composition and layer thickness. We report the current status of MBE-grown GaAs-based QWIP structures in a commercial production environment at IQE. Uniformity data and run-to-run reproducibility on both three-inch and four-inch GaAs substrates are quantified using alloy composition and QW thickness. Initial results on growth technology transfer to a multi-wafer MBE reactor are also presented. High-resolution X-ray diffraction measurements demonstrate GaAs QW thickness variations and AlGaAs barrier compositions changes to be less than 4% and 1% Al, respectively, across four-inch QWIP wafers from both single- and multiple-wafer MBE platforms.

  18. Graphene-Si heterogeneous nanotechnology

    NASA Astrophysics Data System (ADS)

    Akinwande, Deji; Tao, Li

    2013-05-01

    It is widely envisioned that graphene, an atomic sheet of carbon that has generated very broad interest has the largest prospects for flexible smart systems and for integrated graphene-silicon (G-Si) heterogeneous very large-scale integrated (VLSI) nanoelectronics. In this work, we focus on the latter and elucidate the research progress that has been achieved for integration of graphene with Si-CMOS including: wafer-scale graphene growth by chemical vapor deposition on Cu/SiO2/Si substrates, wafer-scale graphene transfer that afforded the fabrication of over 10,000 devices, wafer-scalable mitigation strategies to restore graphene's device characteristics via fluoropolymer interaction, and demonstrations of graphene integrated with commercial Si- CMOS chips for hybrid nanoelectronics and sensors. Metrology at the wafer-scale has led to the development of custom Raman processing software (GRISP) now available on the nanohub portal. The metrology reveals that graphene grown on 4-in substrates have monolayer quality comparable to exfoliated flakes. At room temperature, the high-performance passivated graphene devices on SiO2/Si can afford average mobilities 3000cm2/V-s and gate modulation that exceeds an order of magnitude. The latest growth research has yielded graphene with high mobilities greater than 10,000cm2/V-s on oxidized silicon. Further progress requires track compatible graphene-Si integration via wafer bonding in order to translate graphene research from basic to applied research in commercial R and D laboratories to ultimately yield a viable nanotechnology.

  19. Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

    NASA Astrophysics Data System (ADS)

    Matsuoka, Yoichi; Seki, Junichi; Nakayama, Takahiro; Nakagawa, Kazuki; Azuma, Hisanobu; Yamamoto, Kiyohito; Sato, Chiaki; Sakai, Fumio; Takabayashi, Yukio; Aghili, Ali; Mizuno, Makoto; Choi, Jin; Jones, Chris E.

    2016-10-01

    Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. On the mask side, a new replication tool, the FPA-1100 NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control, resolution and image placement accuracy. In this paper we discuss the progress made in both feature resolution and in meeting the image placement specification for replica masks.

  20. Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

    NASA Astrophysics Data System (ADS)

    Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

    2017-10-01

    Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

  1. Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

    NASA Astrophysics Data System (ADS)

    Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

    2018-03-01

    The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

  2. Thermo-acousto-photonics for noncontact temperature measurement in silicon wafer processing

    NASA Astrophysics Data System (ADS)

    Suh, Chii-Der S.; Rabroker, G. Andrew; Chona, Ravinder; Burger, Christian P.

    1999-10-01

    A non-contact thermometry technique has been developed to characterize the thermal state of silicon wafers during rapid thermal processing. Information on thermal variations is obtained from the dispersion relations of the propagating waveguide mode excited in wafers using a non-contact, broadband optical system referred to as Thermal Acousto- Photonics for Non-Destructive Evaluation. Variations of thermo-mechanical properties in silicon wafers are correlated to temperature changes by performing simultaneous time-frequency analyses on Lamb waveforms acquired with a fiber-tip interferometer sensor. Experimental Lamb wave data collected for cases ranging from room temperature to 400 degrees C is presented. The results show that the temporal progressions of all spectral elements found in the fundamental antisymmetric mode are strong functions of temperature. This particular attribute is exploited to achieve a thermal resolution superior to the +/- 5 degrees C attainable through current pyrometric techniques. By analyzing the temperature-dependent group velocity of a specific frequency component over the temperature range considered and then comparing the results to an analytical model developed for silicon wafers undergoing annealing, excellent agreement was obtained. Presented results demonstrate the feasibility of applying laser-induced stress waves as a temperature diagnostic during rapid thermal processing.

  3. Pre-stressed piezoelectric bimorph micro-actuators based on machined 40 µm PZT thick films: batch scale fabrication and integration with MEMS

    NASA Astrophysics Data System (ADS)

    Wilson, S. A.; Jourdain, R. P.; Owens, S.

    2010-09-01

    The projected force-displacement capability of piezoelectric ceramic films in the 20-50 µm thickness range suggests that they are well suited to many micro-fluidic and micro-pneumatic applications. Furthermore when they are configured as bending actuators and operated at ~ 1 V µm - 1 they do not necessarily conform to the high-voltage, very low-displacement piezoelectric stereotype. Even so they are rarely found today in commercial micro-electromechanical devices, such as micro-pumps and micro-valves, and the main barriers to making them much more widely available would appear to be processing incompatibilities rather than commercial desirability. In particular, the issues associated with integration of these devices into MEMS at the production level are highly significant and they have perhaps received less attention in the mainstream than they deserve. This paper describes a fabrication route based on ultra-precision ceramic machining and full-wafer bonding for cost-effective batch scale production of thick film PZT bimorph micro-actuators and their integration with MEMS. The resulting actuators are pre-stressed (ceramic in compression) which gives them added performance, they are true bimorphs with bi-directional capability and they exhibit full bulk piezoelectric ceramic properties. The devices are designed to integrate with ancillary systems components using transfer-bonding techniques. The work forms part of the European Framework 6 Project 'Q2M—Quality to Micro'.

  4. Method for wafer edge profile extraction using optical images obtained in edge defect inspection process

    NASA Astrophysics Data System (ADS)

    Okamoto, Hiroaki; Sakaguchi, Naoshi; Hayano, Fuminori

    2010-03-01

    It is becoming increasingly important to monitor wafer edge profiles in the immersion lithography era. A Nikon edge defect inspection tool acquires the circumferential optical images of the wafer edge during its inspection process. Nikon's unique illumination system and optics make it possible to then convert the brightness data of the captured images to quantifiable edge profile information. During this process the wafer's outer shape is also calculated. Test results show that even newly shipped bare wafers may not have a constant shape over 360 degree. In some cases repeated deformations with 90 degree pitch are observed.

  5. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    NASA Astrophysics Data System (ADS)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  6. Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

    PubMed

    Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

    2015-11-01

    Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. Copyright © 2015 Elsevier B.V. All rights reserved.

  7. Method of producing an integral resonator sensor and case

    NASA Technical Reports Server (NTRS)

    Challoner, A. Dorian (Inventor); Yee, Karl Y. (Inventor); Shcheglov, Kirill V. (Inventor); Hayworth, Ken J. (Inventor); Wiberg, Dean V. (Inventor)

    2005-01-01

    The present invention discloses an inertial sensor having an integral resonator. A typical sensor comprises a planar mechanical resonator for sensing motion of the inertial sensor and a case for housing the resonator. The resonator and a wall of the case are defined through an etching process. A typical method of producing the resonator includes etching a baseplate, bonding a wafer to the etched baseplate, through etching the wafer to form a planar mechanical resonator and the wall of the case and bonding an end cap wafer to the wall to complete the case.

  8. Integrated layout based Monte-Carlo simulation for design arc optimization

    NASA Astrophysics Data System (ADS)

    Shao, Dongbing; Clevenger, Larry; Zhuang, Lei; Liebmann, Lars; Wong, Robert; Culp, James

    2016-03-01

    Design rules are created considering a wafer fail mechanism with the relevant design levels under various design cases, and the values are set to cover the worst scenario. Because of the simplification and generalization, design rule hinders, rather than helps, dense device scaling. As an example, SRAM designs always need extensive ground rule waivers. Furthermore, dense design also often involves "design arc", a collection of design rules, the sum of which equals critical pitch defined by technology. In design arc, a single rule change can lead to chain reaction of other rule violations. In this talk we present a methodology using Layout Based Monte-Carlo Simulation (LBMCS) with integrated multiple ground rule checks. We apply this methodology on SRAM word line contact, and the result is a layout that has balanced wafer fail risks based on Process Assumptions (PAs). This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533

  9. Epitaxial gallium arsenide wafers

    NASA Technical Reports Server (NTRS)

    Black, J. F.; Robinson, L. B.

    1971-01-01

    The preparation of GaAs epitaxial layers by a vapor transport process using AsCl3, Ga and H2 was pursued to provide epitaxial wafers suitable for the fabrication of transferred electron oscillators and amplifiers operating in the subcritical region. Both n-n(+) structures, and n(++)-n-n(+) sandwich structures were grown using n(+) (Si-doped) GaAs substrates. Process variables such as the input AsCl3 concentration, gallium temperature, and substrate temperature and temperature gradient and their effects on properties are presented and discussed.

  10. Silicon sample holder for molecular beam epitaxy on pre-fabricated integrated circuits

    NASA Technical Reports Server (NTRS)

    Hoenk, Michael E. (Inventor); Grunthaner, Paula J. (Inventor); Grunthaner, Frank J. (Inventor)

    1994-01-01

    The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

  11. Length separation of single-walled carbon nanotubes and its impact on structural and electrical properties of wafer-level fabricated carbon nanotube-field-effect transistors

    NASA Astrophysics Data System (ADS)

    Böttger, Simon; Hermann, Sascha; Schulz, Stefan E.; Gessner, Thomas

    2016-10-01

    For an industrial realization of devices based on single-walled carbon nanotube (SWCNTs) such as field-effect transistors (FETs) it becomes increasingly important to consider technological aspects such as intrinsic device structure, integration process controllability as well as yield. From the perspective of a wafer-level integration technology, the influence of SWCNT length on the performance of short-channel CNT-FETs is demonstrated by means of a statistical and comparative study. Therefore, a methodological development of a length separation process based on size-exclusion chromatography was conducted in order to extract well-separated SWCNT dispersions with narrowed length distribution. It could be shown that short SWCNTs adversely affect integrability and reproducibility, underlined by a 25% decline of the integration yield with respect to long SWCNTs. Furthermore, it turns out that the significant changes in electrical performance are directly linked to a SWCNT chain formation in the transistor channel. In particular, CNT-FETs with long SWCNTs outperform reference and short SWCNTs with respect to hole mobility and subthreshold controllability by up to 300% and up to 140%, respectively. As a whole, this study provides a statistical and comparative analysis towards chain-less CNT-FETs fabricated with a wafer-level technology.

  12. Laser treatment of plasma-hydrogenated silicon wafers for thin layer exfoliation

    NASA Astrophysics Data System (ADS)

    Ghica, Corneliu; Nistor, Leona Cristina; Teodorescu, Valentin Serban; Maraloiu, Adrian; Vizireanu, Sorin; Scarisoreanu, Nae Doinel; Dinescu, Maria

    2011-03-01

    We have studied by transmission electron microscopy the microstructural effects induced by pulsed laser annealing in comparison with thermal treatments of RF plasma hydrogenated Si wafers aiming for further application in the smart-cut procedure. While thermal annealing mainly produces a slight decrease of the density of plasma-induced planar defects and an increase of the size and number of plasma-induced nanocavities in the Si matrix, pulsed laser annealing of RF plasma hydrogenated Si wafers with a 355 nm wavelength radiation results in both the healing of defects adjacent to the wafer surface and the formation of a well defined layer of nanometric cavities at a depth of 25-50 nm. In this way, a controlled fracture of single crystal layers of Si thinner than 50 nm is favored.

  13. Overlay Tolerances For VLSI Using Wafer Steppers

    NASA Astrophysics Data System (ADS)

    Levinson, Harry J.; Rice, Rory

    1988-01-01

    In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his

  14. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, C.M.; Hui, W.C.

    1996-11-19

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

  15. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, Conrad M.; Hui, Wing C.

    1996-01-01

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

  16. Resonance ultrasonic diagnostics of defects in full-size silicon wafers

    NASA Astrophysics Data System (ADS)

    Belyaev, A.; Ostapenko, S.

    2001-12-01

    A resonance acoustic effect was observed recently in full-size 200 mm Cz-Si wafers and applied to characterize as-grown and process-induced defects. Ultrasonic vibrations can be excited into wafers using an external ultrasonic transducer and their amplitude is recorded using a scanning air-coupled acoustic probe operated in a non-contact mode. By sweeping driving frequency, f, of the transducer, we observed an amplification of a specific acoustic mode referred to as ‘whistle’. In this paper, we performed theoretical modeling of the whistle which allowed in attributing this mode to resonant flexural vibrations in a thin circular plate. We calculated normal frequencies of the flexural vibrations of a circular plate of radius ρ in the case of the free edge. The model gives an excellent fit to experimental data with regard to whistle spatial distribution. The results of calculation allow the evaluation of resonance acoustic effect in wafers of different geometries employed in the industry.

  17. Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

    NASA Astrophysics Data System (ADS)

    Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

    2014-12-01

    We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

  18. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    NASA Astrophysics Data System (ADS)

    Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

    2016-02-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

  19. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  20. Scaling of graphene integrated circuits.

    PubMed

    Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

    2015-05-07

    The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

  1. Etching Selectivity of Cr, Fe and Ni Masks on Si & SiO2 Wafers

    NASA Astrophysics Data System (ADS)

    Garcia, Jorge; Lowndes, Douglas H.

    2000-10-01

    During this Summer 2000 I joined the Semiconductors and Thin Films group led by Dr. Douglas H. Lowndes at Oak Ridge National Laboratory’s Solid State Division. Our objective was to evaluate the selectivity that Trifluoromethane (CHF3), and Sulfur Hexafluoride (SF6) plasmas have for Si, SiO2 wafers and the Ni, Cr, and Fe masks; being this etching selectivity the ratio of the etching rates of the plasmas for each of the materials. We made use of Silicon and Silicon Dioxide-coated wafers that have Fe, Cr or Ni masks. In the semiconductor field, metal layers are often used as masks to protect layers underneath during processing steps; when these wafers are taken to the dry etching process, both the wafer and the mask layers’ thickness are reduced.

  2. Realize multiple hermetic chamber pressures for system-on-chip process by using the capping wafer with diverse cavity depths

    NASA Astrophysics Data System (ADS)

    Cheng, Shyh-Wei; Weng, Jui-Chun; Liang, Kai-Chih; Sun, Yi-Chiang; Fang, Weileun

    2018-04-01

    Many mechanical and thermal characteristics, for example the air damping, of suspended micromachined structures are sensitive to the ambient pressure. Thus, micromachined devices such as the gyroscope and accelerometer have different ambient pressure requirements. Commercially available process platforms could be used to fabricate and integrate devices of various functions to reduce the chip size. However, it remains a challenge to offer different ambient pressures for micromachined devices after sealing them by wafer level capping (WLC). This study exploits the outgassing characteristics of the CMOS chip to fabricate chambers of various pressures after the WLC of the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform. The pressure of the sealed chamber can be modulated by the chamber volume after the outgassing. In other words, the pressure of hermetic sealed chambers can be easily and properly defined by the etching depth of the cavity on an Si capping wafer. In applications, devices sealed with different cavity depths are implemented using the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform to demonstrate the present approach. Measurements show the feasibility of this simple chamber pressure modulation approach on eight-inch wafers.

  3. Nanoscale x-ray imaging of circuit features without wafer etching

    NASA Astrophysics Data System (ADS)

    Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S. G.; Peterka, Tom; Levi, Anthony J. F.; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

    2017-03-01

    Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20-40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300 -μ m -thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240 -μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.

  4. Nanoscale x-ray imaging of circuit features without wafer etching.

    PubMed

    Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S G; Peterka, Tom; Levi, Anthony J F; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

    2017-03-01

    Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules, ideally in a non-destructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions, or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits, with past work delivering 20-40 nm resolution on thinned ICs. We describe a simple model for estimating the required exposure, and use it to estimate the future potential for this technique. Here we show for the first time that this approach can be used to image circuit detail through an unprocessed 300 μ m thick silicon wafer, with sub-20 nm detail clearly resolved after mechanical polishing to 240 μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire non-etched ICs to be imaged to 10 nm resolution or better while maintaining their ability to function in electrical tests.

  5. Nanoscale x-ray imaging of circuit features without wafer etching

    DOE PAGES

    Deng, Junjing; Hong, Young Pyo; Chen, Si; ...

    2017-03-24

    Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules ideally in a nondestructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses hasmore » not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits with past work delivering 20–40-nm resolution on thinned ICs. We describe a simple model for estimating the required exposure and use it to estimate the future potential for this technique. Here we show that this approach can be used to image circuit detail through an unprocessed 300-μm-thick silicon wafer with sub-20-nm detail clearly resolved after mechanical polishing to 240-μm thickness was used to eliminate image contrast caused by Si wafer surface scratches. Here, by using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire nonetched ICs to be imaged to 10-nm resolution or better while maintaining their ability to function in electrical tests.« less

  6. Dissolution of Oxygen Precipitate Nuclei in n-Type CZ-Si Wafers to Improve Their Material Quality: Experimental Results

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Sopori, Bhushan; Basnyat, Prakash; Devayajanam, Srinivas

    2017-01-01

    We present experimental results which show that oxygen-related precipitate nuclei (OPN) present in p-doped, n-type, Czochralski wafers can be dissolved using a flash-annealing process, yielding very high quality wafers for high-efficiency solar cells. Flash annealing consists of heating a wafer in an optical furnace to temperature between 1150 and 1250 degrees C for a short time. This process produces a large increase in the minority carrier lifetime (MCLT) and homogenizes each wafer. We have tested wafers from different axial locations of two ingots. All wafers reach nearly the same high value of MCLT. The OPN dissolution is confirmed by oxygenmore » analysis using Fourier transform infrared spectra and injection-level dependence of MCLT.« less

  7. Graphene-Decorated Nanocomposites for Printable Electrodes in Thin Wafer Devices

    NASA Astrophysics Data System (ADS)

    Bakhshizadeh, N.; Sivoththaman, S.

    2017-12-01

    Printable electrodes that induce less stress and require lower curing temperatures compared to traditional screen-printed metal pastes are needed in thin wafer devices such as future solar cells, and in flexible electronics. The synthesis of nanocomposites by incorporating graphene nanopowders as well as silver nanowires into epoxy-based electrically conductive adhesives (ECA) is examined to improve electrical conductivity and to develop alternate printable electrode materials that induce less stress on the wafer. For the synthesized graphene and Ag nanowire-decorated ECA nanocomposites, the curing kinetics were studied by dynamic and isothermal differential scanning calorimetry measurements. Thermogravimetric analysis on ECA, ECA-AG and ECA/graphene nanopowder nanocomposites showed that the temperatures for onset of decomposition are higher than their corresponding glass transition temperature ( T g) indicating an excellent thermal resistance. Printed ECA/Ag nanowire nanocomposites showed 90% higher electrical conductivity than ECA films, whereas the ECA/graphene nanocomposites increased the conductivity by over two orders of magnitude. Scanning electron microscopy results also revealed the effect of fillers morphology on the conductivity improvement and current transfer mechanisms in nanocomposites. Residual stress analysis performed on Si wafers showed that the ECA and nanocomposite printed wafers are subjected to much lower stress compared to those printed with metallic pastes. The observed parameters of low curing temperature, good thermal resistance, reasonably high conductivity, and low residual stress in the ECA/graphene nanocomposite makes this material a promising alternative in screen-printed electrode formation in thin substrates.

  8. Chemical method for producing smooth surfaces on silicon wafers

    DOEpatents

    Yu, Conrad

    2003-01-01

    An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

  9. Polarized Optical Scattering Measurements of Metallic Nanoparticles on a Thin Film Silicon Wafer

    NASA Astrophysics Data System (ADS)

    Liu, Cheng-Yang; Liu, Tze-An; Fu, Wei-En

    2009-09-01

    Light scattering has shown its powerful diagnostic capability to characterize optical quality surfaces. In this study, the theory of bidirectional reflectance distribution function (BRDF) was used to analyze the metallic nanoparticles' sizes on wafer surfaces. The BRDF of a surface is defined as the angular distribution of radiance scattered by the surface normalized by the irradiance incident on the surface. A goniometric optical scatter instrument has been developed to perform the BRDF measurements on polarized light scattering on wafer surfaces for the diameter and distribution measurements of metallic nanoparticles. The designed optical scatter instrument is capable of distinguishing various types of optical scattering characteristics, which are corresponding to the diameters of the metallic nanoparticles, near surfaces by using the Mueller matrix calculation. The metallic nanoparticle diameter of measurement is 60 nm on 2 inch thin film wafers. These measurement results demonstrate that the polarization of light scattered by metallic particles can be used to determine the size of metallic nanoparticles on silicon wafers.

  10. Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response

    PubMed Central

    Brito, Nuno; Ferreira, Carlos; Alves, Filipe; Cabral, Jorge; Gaspar, João; Monteiro, João; Rocha, Luís

    2016-01-01

    The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr), quality factor (Q), and pull-in voltage (Vpi) within 1.5 s with repeatability better than 5 ppt (parts per thousand). A full-wafer with 420 devices under test (DUTs) has been evaluated detecting the faulty devices and providing important design specification feedback to the designers. PMID:27657087

  11. Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response.

    PubMed

    Brito, Nuno; Ferreira, Carlos; Alves, Filipe; Cabral, Jorge; Gaspar, João; Monteiro, João; Rocha, Luís

    2016-09-21

    The uniqueness of microelectromechanical system (MEMS) devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC) manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr), quality factor (Q), and pull-in voltage (Vpi) within 1.5 s with repeatability better than 5 ppt (parts per thousand). A full-wafer with 420 devices under test (DUTs) has been evaluated detecting the faulty devices and providing important design specification feedback to the designers.

  12. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    NASA Astrophysics Data System (ADS)

    Qiusheng, Y.; Senkai, C.; Jisheng, P.

    2015-03-01

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  13. Terahertz Array Receivers with Integrated Antennas

    NASA Technical Reports Server (NTRS)

    Chattopadhyay, Goutam; Llombart, Nuria; Lee, Choonsup; Jung, Cecile; Lin, Robert; Cooper, Ken B.; Reck, Theodore; Siles, Jose; Schlecht, Erich; Peralta, Alessandro; hide

    2011-01-01

    Highly sensitive terahertz heterodyne receivers have been mostly single-pixel. However, now there is a real need of multi-pixel array receivers at these frequencies driven by the science and instrument requirements. In this paper we explore various receiver font-end and antenna architectures for use in multi-pixel integrated arrays at terahertz frequencies. Development of wafer-level integrated terahertz receiver front-end by using advanced semiconductor fabrication technologies has progressed very well over the past few years. Novel stacking of micro-machined silicon wafers which allows for the 3-dimensional integration of various terahertz receiver components in extremely small packages has made it possible to design multi-pixel heterodyne arrays. One of the critical technologies to achieve fully integrated system is the antenna arrays compatible with the receiver array architecture. In this paper we explore different receiver and antenna architectures for multi-pixel heterodyne and direct detector arrays for various applications such as multi-pixel high resolution spectrometer and imaging radar at terahertz frequencies.

  14. Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs

    NASA Astrophysics Data System (ADS)

    Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.

    2015-03-01

    This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.

  15. A manufacturable process integration approach for graphene devices

    NASA Astrophysics Data System (ADS)

    Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

    2013-06-01

    In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

  16. Scale-adaptive compressive tracking with feature integration

    NASA Astrophysics Data System (ADS)

    Liu, Wei; Li, Jicheng; Chen, Xiao; Li, Shuxin

    2016-05-01

    Numerous tracking-by-detection methods have been proposed for robust visual tracking, among which compressive tracking (CT) has obtained some promising results. A scale-adaptive CT method based on multifeature integration is presented to improve the robustness and accuracy of CT. We introduce a keypoint-based model to achieve the accurate scale estimation, which can additionally give a prior location of the target. Furthermore, by the high efficiency of data-independent random projection matrix, multiple features are integrated into an effective appearance model to construct the naïve Bayes classifier. At last, an adaptive update scheme is proposed to update the classifier conservatively. Experiments on various challenging sequences demonstrate substantial improvements by our proposed tracker over CT and other state-of-the-art trackers in terms of dealing with scale variation, abrupt motion, deformation, and illumination changes.

  17. Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

    NASA Astrophysics Data System (ADS)

    Pa, Pai-Shan

    2010-01-01

    A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

  18. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    PubMed

    Zhao, C; Konstantinidis, A C; Zheng, Y; Anaxagoras, T; Speller, R D; Kanicki, J

    2015-12-07

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm(-1) and a DQE of around 0.5 at spatial frequencies  <1 mm(-1). In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered.

  19. Correlation of 150-mm silicon wafer site flatness with stepper performance for deep submicron applications

    NASA Astrophysics Data System (ADS)

    Huff, Howard R.; Vigil, Joseph C.; Kuyel, Birol; Chan, David Y.; Nguyen, Long P.

    1992-06-01

    An experimental study was conducted to correlate wafer site flatness SFQD with stepper performance for half-micron lines and spaces. CD measurements were taken on wafers patterned on both GCA pre-production XLS i-line and SVGL Micrascan-90 DUV steppers as well as focus measurements on the Micrascan-90. Wafer site flatness SFQD less than 0.3 micrometers was observed to be a sufficiently small variable in CD non-uniformities for these initial half-micron stepper applications.

  20. ArF scanner performance improvement by using track integrated CD optimization

    NASA Astrophysics Data System (ADS)

    Huang, Jacky; Yu, Shinn-Sheng; Ke, Chih-Ming; Wu, Timothy; Wang, Yu-Hsi; Gau, Tsai-Sheng; Wang, Dennis; Li, Allen; Yang, Wenge; Kaoru, Araki

    2006-03-01

    In advanced semiconductor processing, shrinking CD is one of the main objectives when moving to the next generation technology. Improving CD uniformity (CDU) with shrinking CD is one of the biggest challenges. From ArF lithography CD error budget analysis, PEB (post exposure bake) contributes more than 40% CD variations. It turns out that hot plate performance such as CD matching and within-plate temperature control play key roles in litho cell wafer per hour (WPH). Traditionally wired or wireless thermal sensor wafers were used to match and optimize hot plates. However, sensor-to-sensor matching and sensor data quality vs. sensor lifetime or sensor thermal history are still unknown. These concerns make sensor wafers more suitable for coarse mean-temperature adjustment. For precise temperature adjustment, especially within-hot-plate temperature uniformity, using CD instead of sensor wafer temperature is a better and more straightforward metrology to calibrate hot plates. In this study, we evaluated TEL clean track integrated optical CD metrology (IM) combined with TEL CD Optimizer (CDO) software to improve 193-nm resist within-wafer and wafer-to-wafer CD uniformity. Within-wafer CD uniformity is mainly affected by the temperature non-uniformity on the PEB hot plate. Based on CD and PEB sensitivity of photo resists, a physical model has been established to control the CD uniformity through fine-tuning PEB temperature settings. CD data collected by track integrated CD metrology was fed into this model, and the adjustment of PEB setting was calculated and executed through track internal APC system. This auto measurement, auto feed forward, auto calibration and auto adjustment system can reduce the engineer key-in error and improve the hot plate calibration cycle time. And this PEB auto calibration system can easily bring hot-plate-to-hot-plate CD matching to within 0.5nm and within-wafer CDU (3σ) to less than 1.5nm.

  1. Wafer-Scale Hierarchical Nanopillar Arrays Based on Au Masks and Reactive Ion Etching for Effective 3D SERS Substrate.

    PubMed

    Men, Dandan; Wu, Yingyi; Wang, Chu; Xiang, Junhuai; Yang, Ganlan; Wan, Changjun; Zhang, Honghua

    2018-02-04

    Two-dimensional (2D) periodic micro/nanostructured arrays as SERS substrates have attracted intense attention due to their excellent uniformity and good stability. In this work, periodic hierarchical SiO₂ nanopillar arrays decorated with Ag nanoparticles (NPs) with clean surface were prepared on a wafer-scale using monolayer Au NP arrays as masks, followed by reactive ion etching (RIE), depositing Ag layer and annealing. For the prepared SiO₂ nanopillar arrays decorated with Ag NPs, the size of Ag NPs was tuned from ca. 24 to 126 nanometers by controlling the deposition thickness of Ag film. Importantly, the SiO₂ nanopillar arrays decorated with Ag NPs could be used as highly sensitive SERS substrate for the detection of 4-aminothiophenol (4-ATP) and rhodamine 6G (R6G) due to the high loading of Ag NPs and a very uniform morphology. With a deposition thickness of Ag layer of 30 nm, the SiO₂ nanopillar arrays decorated with Ag NPs exhibited the best sensitive SERS activity. The excellent SERS performance of this substrate is mainly attributed to high-density "hotspots" derived from nanogaps between Ag NPs. Furthermore, this strategy might be extended to synthesize other nanostructured arrays with a large area, which are difficult to be prepared only via conventional wet-chemical or physical methods.

  2. Local interstitial delivery of z-butylidenephthalide by polymer wafers against malignant human gliomas

    PubMed Central

    Harn, Horng-Jyh; Lin, Shinn-Zong; Lin, Po-Cheng; Liu, Cyong-Yue; Liu, Po-Yen; Chang, Li-Fu; Yen, Ssu-Yin; Hsieh, Dean-Kuo; Liu, Fu-Chen; Tai, Dar-Fu; Chiou, Tzyy-Wen

    2011-01-01

    We have shown that the natural compound z-butylidenephthalide (Bdph), isolated from the chloroform extract of Angelica sinensis, has antitumor effects. Because of the limitation of the blood-brain barrier, the Bdph dosage required for treatment of glioma is relatively high. To solve this problem, we developed a local-release system with Bdph incorporated into a biodegradable polyanhydride material, p(CPP-SA; Bdph-Wafer), and investigated its antitumor effects. On the basis of in vitro release kinetics, we demonstrated that the Bdph-Wafer released 50% of the available Bdph by the sixth day, and the release reached a plateau phase (90% of Bdph) by the 30th day. To investigate the in situ antitumor effects of the Bdph-Wafer on glioblastoma multiforme (GBM), we used 2 xenograft animal models—F344 rats (for rat GBM) and nude mice (for human GBM)—which were injected with RG2 and DBTRG-05MG cells, respectively, for tumor formation and subsequently treated subcutaneously with Bdph-Wafers. We observed a significant inhibitory effect on tumor growth, with no significant adverse effects on the rodents. Moreover, we demonstrated that the antitumor effect of Bdph on RG2 cells was via the PKC pathway, which upregulated Nurr77 and promoted its translocation from the nucleus to the cytoplasm. Finally, to study the effect of the interstitial administration of Bdph in cranial brain tumor, Bdph-Wafers were surgically placed in FGF-SV40 transgenic mice. Our Bdph-Wafer significantly reduced tumor size in a dose-dependent manner. In summary, our study showed that p(CPP-SA) containing Bdph delivered a sufficient concentration of Bdph to the tumor site and effectively inhibited the tumor growth in the glioma. PMID:21565841

  3. Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

    NASA Astrophysics Data System (ADS)

    Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

    2004-08-01

    The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

  4. Evaluation of the Technical Feasibility and Effective Cost of Various Wafer Thicknesses for the Manufacture of Solar Cells

    NASA Technical Reports Server (NTRS)

    1979-01-01

    Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.

  5. Evaluation of the technical feasibility and effective cost of various wafer thicknesses for the manufacture of solar cells

    NASA Technical Reports Server (NTRS)

    1978-01-01

    Three wafering demonstration runs were completed on the Yasunaga wire saw. Wafer thickness/taper uniformity is excellent. Many small problems were encountered with Yasunaga accessories, slowing the effort. A wafer characterization cycle was defined and will be initiated during the next period.

  6. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    NASA Astrophysics Data System (ADS)

    Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

    2017-04-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

  7. Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

    NASA Astrophysics Data System (ADS)

    Wang, Shing-Dar; Chen, Ting-Wei

    2018-06-01

    In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in <1 0 0> direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

  8. Non-Reciprocal on Wafer Microwave Devices

    DTIC Science & Technology

    2015-05-27

    filter uses a barium hexagonal ferrite film incorporated into the dielectric layer of a microstrip transmission line. The zero-field operational...Fal,, Robert E. Camley. Millimeter wave phase shifter based on ferromagnetic resonancein a hexagonal barium ferrite thin film, Applied Physics...materials for on-wafer microwave devices concentrated on barium hexagonal ferrite (BaM) films grown on Si because these material is a good candidate

  9. Packaged integrated opto-fluidic solution for harmful fluid analysis

    NASA Astrophysics Data System (ADS)

    Allenet, T.; Bucci, D.; Geoffray, F.; Canto, F.; Couston, L.; Jardinier, E.; Broquin, J.-E.

    2016-02-01

    Advances in nuclear fuel reprocessing have led to a surging need for novel chemical analysis tools. In this paper, we present a packaged lab-on-chip approach with co-integration of optical and micro-fluidic functions on a glass substrate as a solution. A chip was built and packaged to obtain light/fluid interaction in order for the entire device to make spectral measurements using the photo spectroscopy absorption principle. The interaction between the analyte solution and light takes place at the boundary between a waveguide and a fluid micro-channel thanks to the evanescent part of the waveguide's guided mode that propagates into the fluid. The waveguide was obtained via ion exchange on a glass wafer. The input and the output of the waveguides were pigtailed with standard single mode optical fibers. The micro-scale fluid channel was elaborated with a lithography procedure and hydrofluoric acid wet etching resulting in a 150+/-8 μm deep channel. The channel was designed with fluidic accesses, in order for the chip to be compatible with commercial fluidic interfaces/chip mounts. This allows for analyte fluid in external capillaries to be pumped into the device through micro-pipes, hence resulting in a fully packaged chip. In order to produce this co-integrated structure, two substrates were bonded. A study of direct glass wafer-to-wafer molecular bonding was carried-out to improve detector sturdiness and durability and put forward a bonding protocol with a bonding surface energy of γ>2.0 J.m-2. Detector viability was shown by obtaining optical mode measurements and detecting traces of 1.2 M neodymium (Nd) solute in 12+/-1 μL of 0.01 M and pH 2 nitric acid (HNO3) solvent by obtaining an absorption peak specific to neodymium at 795 nm.

  10. Integrated otpical monitoring of MEMS for closed-loop control

    NASA Astrophysics Data System (ADS)

    Dawson, Jeremy M.; Wang, Limin; McCormick, W. B.; Rittenhouse, S. A.; Famouri, Parviz F.; Hornak, Lawrence A.

    2003-01-01

    Robust control and failure assessment of MEMS employed in physically demanding, mission critical applications will allow for higher degrees of quality assurance in MEMS operation. Device fault detection and closed-loop control require detailed knowledge of the operational states of MEMS over the lifetime of the device, obtained by a means decoupled from the system. Preliminary through-wafer optical monitoring research efforts have shown that through-wafer optical probing is suitable for characterizing and monitoring the behavior of MEMS, and can be implemented in an integrated optical monitoring package for continuous in-situ device monitoring. This presentation will discuss research undertaken to establish integrated optical device metrology for closed-loop control of a MUMPS fabricated lateral harmonic oscillator. Successful linear closed-loop control results using a through-wafer optical microprobe position feedback signal will be presented. A theoretical optical output field intensity study of grating structures, fabricated on the shuttle of the resonator, was performed to improve the position resolution of the optical microprobe position signal. Through-wafer microprobe signals providing a positional resolution of 2 μm using grating structures will be shown, along with initial binary Fresnel diffractive optical microelement design layout, process development, and testing results. Progress in the design, fabrication, and test of integrated optical elements for multiple microprobe signal delivery and recovery will be discussed, as well as simulation of device system model parameter changes for failure assessment.

  11. Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

    NASA Astrophysics Data System (ADS)

    Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

    2018-04-01

    Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

  12. The Novel Preparation of P-N Junction Mesa Diodes by Silicon-Wafer Direct Bonding (SDB)

    NASA Astrophysics Data System (ADS)

    Yeh, Ching-Fa; Hwangleu, Shyang

    1992-05-01

    The key processes of silicon-wafer direct bonding (SDB), including hydrophilic surface formation and optimal two-step heat treatment, have been developed However, H2SO4/H2O2 solution being a strong oxidized acid solution, native oxide is found to have grown on the wafer surface as soon as a wafer is treated in this solution. In the case of a wafer further treated in diluted HF solution after hydrophilic surface formation, it is shown that the wafer surface can not only be cleaned of its native oxide but also remains hydrophilic, and can provide excellent voidless bonding. The N+/P and N/P combination junction mesa diodes fabricated on the wafers prepared by these novel SDB technologies are examined. The ideality factor n of the N/P mesa diode is 2.4˜2.8 for the voltage range 0.2˜0.3 V; hence, the lowering of the ideality factor n is evidently achieved. As for the N+/P mesa diode, the ideality factor n shows a value of 1.10˜1.30 for the voltage range 0.2˜0.6 V; the low value of n is attributed to an autodoping phenomenon which has caused the junction interface to form in the P-silicon bulk. However, the fact that the sustaining voltage of the N/P mesa diode showed a value greater than 520 V reveals the effectiveness of our novel SDB processes.

  13. SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

    NASA Astrophysics Data System (ADS)

    Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

    2010-05-01

    Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

  14. External self-gettering of nickel in float zone silicon wafers

    NASA Astrophysics Data System (ADS)

    Gay, N.; Martinuzzi, S.

    1997-05-01

    During indiffusion of Ni atoms in silicon crystals at 950 °C from a nickel layer source, Ni-Si alloys can be formed close to the surface. Metal solubility in these alloys is higher than in silicon, which induces a marked segregation gettering of the Ni atoms which have diffused in the bulk of the wafers. Consequently, the regions of the wafers covered with the Ni layer are less contaminated than adjacent regions in which Ni atoms have also penetrated, as shown by the absence of precipitates and the higher diffusion length of minority carriers. The results suggest the existence of external self-gettering of Ni atoms by the nickel source.

  15. Scale relativity theory and integrative systems biology: 1. Founding principles and scale laws.

    PubMed

    Auffray, Charles; Nottale, Laurent

    2008-05-01

    In these two companion papers, we provide an overview and a brief history of the multiple roots, current developments and recent advances of integrative systems biology and identify multiscale integration as its grand challenge. Then we introduce the fundamental principles and the successive steps that have been followed in the construction of the scale relativity theory, and discuss how scale laws of increasing complexity can be used to model and understand the behaviour of complex biological systems. In scale relativity theory, the geometry of space is considered to be continuous but non-differentiable, therefore fractal (i.e., explicitly scale-dependent). One writes the equations of motion in such a space as geodesics equations, under the constraint of the principle of relativity of all scales in nature. To this purpose, covariant derivatives are constructed that implement the various effects of the non-differentiable and fractal geometry. In this first review paper, the scale laws that describe the new dependence on resolutions of physical quantities are obtained as solutions of differential equations acting in the scale space. This leads to several possible levels of description for these laws, from the simplest scale invariant laws to generalized laws with variable fractal dimensions. Initial applications of these laws to the study of species evolution, embryogenesis and cell confinement are discussed.

  16. Bulk lifetime characterization of corona charged silicon wafers with high resistivity by means of microwave detected photoconductivity

    NASA Astrophysics Data System (ADS)

    Engst, C. R.; Rommel, M.; Bscheid, C.; Eisele, I.; Kutter, C.

    2017-12-01

    Minority carrier lifetime (lifetime) measurements are performed on corona-charged silicon wafers by means of Microwave Detected Photoconductivity (MDP). The corona charge is deposited on the front and back sides of oxidized wafers in order to adjust accumulation conditions. Once accumulation is established, interface recombination is suppressed and bulk lifetimes are obtained. Neither contacts nor non-CMOS compatible preparation techniques are required in order to achieve accumulation conditions, which makes the method ideally suited for inline characterization. The novel approach, termed ChargedMDP (CMDP), is used to investigate neutron transmutation doped (NTD) float zone silicon with resistivities ranging from 6.0 to 8.2 kΩ cm. The bulk properties of 150 mm NTD wafers are analyzed in detail by performing measurements of the carrier lifetime and the steady-state photoconductivity at various injection levels. The results are compared with MDP measurements of uncharged wafers as well as to the established charged microwave detected Photoconductance Decay (charge-PCD) method. Besides analyzing whole wafers, CMDP measurements are performed on oxide test-structures on a patterned wafer. Finally, the oxide properties are characterized by means of charge-PCD as well as capacitance-voltage measurements. With CMDP, average bulk lifetimes up to 33.1 ms are measured, whereby significant variations are observed among wafers, which are produced out of the same ingot but oxidized in different furnaces. The observed lifetime variations are assumed to be caused by contaminations, which are introduced during the oxidation process. The results obtained by CMDP were neither accessible by means of conventional MDP measurements of uncharged wafers nor with the established charge-PCD method.

  17. Integrated Arrays on Silicon at Terahertz Frequencies

    NASA Technical Reports Server (NTRS)

    Chattopadhayay, Goutam; Lee, Choonsup; Jung, Cecil; Lin, Robert; Peralta, Alessandro; Mehdi, Imran; Llombert, Nuria; Thomas, Bertrand

    2011-01-01

    In this paper we explore various receiver font-end and antenna architecture for use in integrated arrays at terahertz frequencies. Development of wafer-level integrated terahertz receiver front-end by using advanced semiconductor fabrication technologies and use of novel integrated antennas with silicon micromachining are reported. We report novel stacking of micromachined silicon wafers which allows for the 3-dimensional integration of various terahertz receiver components in extremely small packages which easily leads to the development of 2- dimensioanl multi-pixel receiver front-ends in the terahertz frequency range. We also report an integrated micro-lens antenna that goes with the silicon micro-machined front-end. The micro-lens antenna is fed by a waveguide that excites a silicon lens antenna through a leaky-wave or electromagnetic band gap (EBG) resonant cavity. We utilized advanced semiconductor nanofabrication techniques to design, fabricate, and demonstrate a super-compact, low-mass submillimeter-wave heterodyne frontend. When the micro-lens antenna is integrated with the receiver front-end we will be able to assemble integrated heterodyne array receivers for various applications such as multi-pixel high resolution spectrometer and imaging radar at terahertz frequencies.

  18. Degradation of bare and silanized silicon wafer surfaces by constituents of biological fluids.

    PubMed

    Dekeyser, C M; Buron, C C; Derclaye, S R; Jonas, A M; Marchand-Brynaert, J; Rouxhet, P G

    2012-07-15

    The 24 h stability of bare silicon wafers as such or silanized with CH(3)O-(CH(2)-CH(2)-O)(n)-C(3)H(6)-trichlorosilane (n=6-9) was investigated in water, NaCl, phosphate and carbonate solutions, and in phosphate buffered saline (PBS) at 37 °C (close to biological conditions regarding temperature, high ionic strength, and pH). The resulting surfaces were analyzed using ellipsometry, X-ray Reflectometry (XRR), X-ray Photoelectron Spectroscopy (XPS), and Atomic Force Microscopy (AFM). Incubation of the silanized wafers in phosphate solution and PBS provokes a detachment of the silane layer. This is due to a hydrolysis of Si-O bonds which is favored by the action of phosphate, also responsible for a corrosion of non-silanized wafers. The surface alteration (detachment of silane layer and corrosion of the non-silanized wafer) is also important with carbonate solution, due to a higher pH (8.3). The protection of the silicon oxide layer brought by silane against the action of the salts is noticeable for phosphate but not for carbonate. Copyright © 2012 Elsevier Inc. All rights reserved.

  19. Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

    PubMed

    Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

    2011-04-21

    A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

  20. Proceedings of the Low-Cost Solar Array Wafering Workshop

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1982-01-01

    The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

  1. Mems: Platform for Large-Scale Integrated Vacuum Electronic Circuits

    DTIC Science & Technology

    2017-03-20

    SECURITY CLASSIFICATION OF: The objective of the LIVEC advanced study project was to develop a platform for large-scale integrated vacuum electronic ...Distribution Unlimited UU UU UU UU 20-03-2017 1-Jul-2014 30-Jun-2015 Final Report: MEMS Platform for Large-Scale Integrated Vacuum Electronic ... Electronic Circuits (LIVEC) Contract No: W911NF-14-C-0093 COR Dr. James Harvey U.S. ARO RTP, NC 27709-2211 Phone: 702-696-2533 e-mail

  2. Method for protecting chip corners in wet chemical etching of wafers

    DOEpatents

    Hui, Wing C.

    1994-01-01

    The present invention is a corner protection mask design that protects chip corners from undercutting during anisotropic etching of wafers. The corner protection masks abut the chip corner point and extend laterally from segments along one or both corner sides of the corner point, forming lateral extensions. The protection mask then extends from the lateral extensions, parallel to the direction of the corner side of the chip and parallel to scribe lines, thus conserving wafer space. Unmasked bomb regions strategically formed in the protection mask facilitate the break-up of the protection mask during etching. Corner protection masks are useful for chip patterns with deep grooves and either large or small chip mask areas. Auxiliary protection masks form nested concentric frames that etch from the center outward are useful for small chip mask patterns. The protection masks also form self-aligning chip mask areas. The present invention is advantageous for etching wafers with thin film windows, microfine and micromechanical structures, and for forming chip structures more elaborate than presently possible.

  3. Method for protecting chip corners in wet chemical etching of wafers

    DOEpatents

    Hui, W.C.

    1994-02-15

    The present invention is a corner protection mask design that protects chip corners from undercutting during anisotropic etching of wafers. The corner protection masks abut the chip corner point and extend laterally from segments along one or both corner sides of the corner point, forming lateral extensions. The protection mask then extends from the lateral extensions, parallel to the direction of the corner side of the chip and parallel to scribe lines, thus conserving wafer space. Unmasked bomb regions strategically formed in the protection mask facilitate the break-up of the protection mask during etching. Corner protection masks are useful for chip patterns with deep grooves and either large or small chip mask areas. Auxiliary protection masks form nested concentric frames that etch from the center outward are useful for small chip mask patterns. The protection masks also form self-aligning chip mask areas. The present invention is advantageous for etching wafers with thin film windows, microfine and micromechanical structures, and for forming chip structures more elaborate than presently possible. 63 figures.

  4. Comparison of line shortening assessed by aerial image and wafer measurements

    NASA Astrophysics Data System (ADS)

    Ziegler, Wolfram; Pforr, Rainer; Thiele, Joerg; Maurer, Wilhelm

    1997-02-01

    Increasing number of patterns per area and decreasing linewidth demand enhancement technologies for optical lithography. OPC, the correction of systematic non-linearity in the pattern transfer process by correction of design data is one possibility to tighten process control and to increase the lifetime of existing lithographic equipment. The two most prominent proximity effects to be corrected by OPC are CD variation and line shortening. Line shortening measured on a wafer is up to 2 times larger than full resist simulation results. Therefore, the influence of mask geometry to line shortening is a key item to parameterize lithography. The following paper discusses the effect of adding small serifs to line ends with 0.25 micrometer ground-rule design. For reticles produced on an ALTA 3000 with standard wet etch process, the corner rounding on them mask can be reduced by adding serifs of a certain size. The corner rounding was measured and the effect on line shortening on the wafer is determined. This was investigated by resist measurements on wafer, aerial image plus resist simulation and aerial image measurements on the AIMS microscope.

  5. Wafer-scale, massively parallel carbon nanotube arrays for realizing field effect transistors with current density exceeding silicon and gallium arsenide

    NASA Astrophysics Data System (ADS)

    Arnold, Michael

    Calculations have indicated that aligned arrays of semiconducting carbon nanotubes (CNTs) promise to outperform conventional semiconducting materials in short-channel, aggressively scaled field effect transistors (FETs) like those used in semiconductor logic and high frequency amplifier technologies. These calculations have been based on extrapolation of measurements of FETs based on one CNT, in which ballistic transport approaching the quantum conductance limit of 2Go = 4e2/h has been achieved. However, constraints in CNT sorting, processing, alignment, and contacts give rise to non-idealities when CNTs are implemented in densely-packed parallel arrays, which has resulted in a conductance per CNT far from 2Go. The consequence has been that it has been very difficult to create high performance CNT array FETs, and CNT array FETs have not outperformed but rather underperformed channel materials such as Si by 6 x or more. Here, we report nearly ballistic CNT array FETs at a density of 50 CNTs um-1, created via CNT sorting, wafer-scale alignment and assembly, and treatment. The on-state conductance in the arrays is as high as 0.46 Go per CNT, and the conductance of the arrays reaches 1.7 mS um-1, which is 7 x higher than previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density reaches 900 uA um-1 and is similar to or exceeds that of Si FETs when compared at equivalent gate oxide thickness, off-state current density, and channel length. The on-state current density exceeds that of GaAs FETs, as well. This leap in CNT FET array performance is a significant advance towards the exploitation of CNTs in high-performance semiconductor electronics technologies.

  6. Monolithically integrated tri-axis shock accelerometers with MHz-level high resonant-frequency

    NASA Astrophysics Data System (ADS)

    Zou, Hongshuo; Wang, Jiachou; Chen, Fang; Bao, Haifei; Jiao, Ding; Zhang, Kun; Song, Zhaohui; Li, Xinxin

    2017-07-01

    This paper reports a novel monolithically integrated tri-axis high-shock accelerometer with high resonant-frequency for the detection of a broad frequency-band shock signal. For the first time, a resonant-frequency as high as about 1.4 MHz is designed for all the x-, y- and z-axis accelerometers of the integrated tri-axis sensor. In order to achieve a wide frequency-band detection performance, all the three sensing structures are designed into an axially compressed/stretched tiny-beam sensing scheme, where the p  +  -doped tiny-beams are connected into a Wheatstone bridge for piezoresistive output. By using ordinary (1 1 1) silicon wafer (i.e. non-SOI wafer), a single-wafer based fabrication technique is developed to monolithically integrate the three sensing structures for the tri-axis sensor. Testing results under high-shock acceleration show that each of the integrated three-axis accelerometers exhibit about 1.4 MHz resonant-frequency and 0.2-0.4 µV/V/g sensitivity. The achieved high frequencies for all the three sensing units make the tri-axis sensor promising in high fidelity 3D high-shock detection applications.

  7. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Powell, J. Anthony (Inventor)

    1991-01-01

    This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  8. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

    1992-01-01

    A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  9. Surface quality of silicon wafer improved by hydrodynamic effect polishing

    NASA Astrophysics Data System (ADS)

    Peng, Wenqiang; Guan, Chaoliang; Li, Shengyi

    2014-08-01

    Differing from the traditional pad polishing, hydrodynamic effect polishing (HEP) is non-contact polishing with the wheel floated on the workpiece. A hydrodynamic lubricated film is established between the wheel and the workpiece when the wheel rotates at a certain speed in HEP. Nanoparticles mixed with deionized water are employed as the polishing slurry, and with action of the dynamic pressure, nanoparticles with high chemisorption due to the high specific surface area can easily reacted with the surface atoms forming a linkage with workpiece surface. The surface atoms are dragged away when nanoparticles are transported to separate by the flow shear stress. The development of grand scale integration put extremely high requirements on the surface quality on the silicon wafer with surface roughness at subnanometer and extremely low surface damage. In our experiment a silicon sample was processed by HEP, and the surface topography before and after polishing was observed by the atomic force microscopy. Experiment results show that plastic pits and bumpy structures on the initial surface have been removed away clearly with the removal depth of 140nm by HEP process. The processed surface roughness has been improved from 0.737nm RMS to 0.175nm RMS(10μm×10μm) and the section profile shows peaks of the process surface are almost at the same height. However, the machining ripples on the wheel surface will duplicate on the silicon surface under the action of the hydrodynamic effect. Fluid dynamic simulation demonstrated that the coarse surface on the wheel has greatly influence on the distribution of shear stress and dynamic pressure on the workpiece surface.

  10. Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

    NASA Astrophysics Data System (ADS)

    Kubair, D. V.; Spearing, S. M.

    2006-03-01

    Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

  11. Hybrid Silicon Photonic Integration using Quantum Well Intermixing

    NASA Astrophysics Data System (ADS)

    Jain, Siddharth R.

    With the push for faster data transfer across all domains of telecommunication, optical interconnects are transitioning into shorter range applications such as in data centers and personal computing. Silicon photonics, with its economic advantages of leveraging well-established silicon manufacturing facilities, is considered the most promising approach to further scale down the cost and size of optical interconnects for chip-to-chip communication. Intrinsic properties of silicon however limit its ability to generate and modulate light, both of which are key to realizing on-chip optical data transfer. The hybrid silicon approach directly addresses this problem by using molecularly bonded III-V epitaxial layers on silicon for optical gain and absorption. This technology includes direct transfer of III-V wafer to a pre-patterned silicon-on-insulator wafer. Several discrete devices for light generation, modulation, amplification and detection have already been demonstrated on this platform. As in the case of electronics, multiple photonic elements can be integrated on a single chip to improve performance and functionality. However, scalable photonic integration requires the ability to control the bandgap for individual devices along with design changes to simplify fabrication. In the research presented here, quantum well intermixing is used as a technique to define multiple bandgaps for integration on the hybrid silicon platform. Implantation enhanced disordering is used to generate four bandgaps spread over 120+ nm. By combining these selectively intermixed III-V layers with pre-defined gratings and waveguides on silicon, we fabricate distributed feedback, distributed Bragg reflector, Fabry-Perot and mode-locked lasers along with photodetectors, electro-absorption modulators and other test structures, all on a single chip. We demonstrate a broadband laser source with continuous-wave operational lasers over a 200 nm bandwidth. Some of these lasers are integrated with

  12. Design and pitch scaling for affordable node transition and EUV insertion scenario

    NASA Astrophysics Data System (ADS)

    Kim, Ryoung-han; Ryckaert, Julien; Raghavan, Praveen; Sherazi, Yasser; Debacker, Peter; Trivkovic, Darko; Gillijns, Werner; Tan, Ling Ee; Drissi, Youssef; Blanco, Victor; Bekaert, Joost; Mao, Ming; Larivière, Stephane; McIntyre, Greg

    2017-04-01

    imec's DTCO and EUV achievement toward imec 7nm (iN7) technology node which is industry 5nm node equivalent is reported with a focus on cost and scaling. Patterning-aware design methodology supports both iArF multiple patterning and EUV under one compliant design rule. FinFET device with contacted poly pitch of 42nm and metal pitch of 32nm with 7.5-track, 6.5-track, and 6-track standard cell library are explored. Scaling boosters are used to provide additional scaling and die cost benefit while lessening pitch shrink burden, and it makes EUV insertion more affordable. EUV pattern fidelity is optimized through OPC, SMO, M3D, mask sizing and SRAF. Processed wafers were characterized and edge-placement-error (EPE) variability is validated for EUV insertion. Scale-ability and cost of ownership of EUV patterning in aligned with iN7 standard cell design, integration and patterning specification are discussed.

  13. Differences between wafer and bake plate temperature uniformity in proximity bake: a theoretical and experimental study

    NASA Astrophysics Data System (ADS)

    Ramanan, Natarajan; Kozman, Austin; Sims, James B.

    2000-06-01

    As the lithography industry moves toward finer features, specifications on temperature uniformity of the bake plates are expected to become more stringent. Consequently, aggressive improvements are needed to conventional bake station designs to make them perform significantly better than current market requirements. To this end, we have conducted a rigorous study that combines state-of-the-art simulation tools and experimental methods to predict the impact of the parameters that influence the uniformity of the wafer in proximity bake. The key observation from this detailed study is that the temperature uniformity of the wafer in proximity mode depends on a number of parameters in addition to the uniformity of the bake plate itself. These parameters include the lid design, the air flow distribution around the bake chamber, bake plate design and flatness of the bake plate and wafer. By performing careful experimental studies that were guided by extensive numerical simulations, we were able to understand the relative importance of each of these parameters. In an orderly fashion, we made appropriate design changes to curtail or eliminate the nonuniformity caused by each of these parameters. After implementing all these changes, we have now been able to match or improve the temperature uniformity of the wafer in proximity with that of a contact measurement on the bake plate. The wafer temperature uniformity is also very close to the theoretically predicted uniformity of the wafer.

  14. Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

    NASA Astrophysics Data System (ADS)

    Sun, Q. M.; Melnikov, A.; Mandelis, A.

    2015-06-01

    Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

  15. Sulfur passivation techniques for III-V wafer bonding

    NASA Astrophysics Data System (ADS)

    Jackson, Michael James

    The use of direct wafer bonding in a multijunction III-V solar cell structure requires the formation of a low resistance bonded interface with minimal thermal treatment. A wafer bonded interface behaves as two independent surfaces in close proximity, hence a major source of resistance is Fermi level pinning common in III-V surfaces. This study demonstrates the use of sulfur passivation in III-V wafer bonding to reduce the energy barrier at the interface. Two different sulfur passivation processes are addressed. A dry sulfur passivation method that utilizes elemental sulfur vapor activated by ultraviolet light in vacuum is compared with aqueous sulfide and native oxide etch treatments. Through the addition of a sulfur desorption step in vacuum, the UV-S treatment achieves bondable surfaces free of particles contamination or surface roughening. X-ray photoelectron spectroscopy measurements of the sulfur treated GaAs surfaces find lower levels of oxide and the appearance of sulfide species. After 4 hrs of air exposure, the UV-S treated GaAs actually showed an increase in the amount of sulfide bonded to the semiconductor, resulting in less oxidation compared to the aqueous sulfide treatment. Large area bonding is achieved for sulfur treated GaAs / GaAs and InP / InP with bulk fracture strength achieved after annealing at 400 °C and 300 °C respectively, without large compressive forces. The electrical conductivity across a sulfur treated 400 °C bonded n-GaAs/n-GaAs interface significantly increased with a short anneal (1-2 minutes) at elevated temperatures (50--600 °C). Interfaces treated with the NH4OH oxide etch, on the other hand, exhibited only mild improvement in accordance with previously published studies in this area. TEM and STEM images revealed similar interfacial microstructure changes with annealing for both sulfur treated and NH4OH interfaces, whereby some areas have direct semiconductor-semiconductor contact without any interfacial layer. Fitting the

  16. Stress analysis in tungsten and Si 3N 4 coated silicon wafers

    NASA Astrophysics Data System (ADS)

    Ogilvie, Robert E.; Nicolich, Jeffrey

    2009-08-01

    A paper by G. Gerald Stoney [Gerald Stoney, The Tension of Metallic Films Deposited by Electrolysis, Proc. R. Soc. Lond. A 82 (1909) 172-175], entitled "The Tension of Metallic Films deposited by Electrolysis," was presented to the Royal Society of London by the Hon. C. A. Parsons. It was well known at that time that films deposited electrolytically were liable to peel off when exceeding a certain thickness. After examining many thin Steel rules of thickness d which have a thin, t, deposit of Nickel, which curved the Rule to a radius r. Taking the moments about the point b for the steel, Stoney then arrived at the following equation where the integral must be equal to zero; ∫d0(E/r)(b-x)xdx=0sothat b=2/3d From the solution of Eq. (1), we obtain the important fact that the neutral plane is at 2/3 the thickness of the rule from film surface. This also implies that the absolute value of the stress on the film side is twice that on the opposite side of the steel rule. The important point is that if the absolute stress in the silicon on the film side is twice that on the opposite side then the position of the neutral plane must be at 2/3 d. The purpose of this paper is to show that the neutral plane in silicon wafers, which have a thin film (~ 3 μm) of tungsten or Si 3N 4 is indeed at 2/3 the thickness of the wafer.

  17. Improving predictions of large scale soil carbon dynamics: Integration of fine-scale hydrological and biogeochemical processes, scaling, and benchmarking

    NASA Astrophysics Data System (ADS)

    Riley, W. J.; Dwivedi, D.; Ghimire, B.; Hoffman, F. M.; Pau, G. S. H.; Randerson, J. T.; Shen, C.; Tang, J.; Zhu, Q.

    2015-12-01

    Numerical model representations of decadal- to centennial-scale soil-carbon dynamics are a dominant cause of uncertainty in climate change predictions. Recent attempts by some Earth System Model (ESM) teams to integrate previously unrepresented soil processes (e.g., explicit microbial processes, abiotic interactions with mineral surfaces, vertical transport), poor performance of many ESM land models against large-scale and experimental manipulation observations, and complexities associated with spatial heterogeneity highlight the nascent nature of our community's ability to accurately predict future soil carbon dynamics. I will present recent work from our group to develop a modeling framework to integrate pore-, column-, watershed-, and global-scale soil process representations into an ESM (ACME), and apply the International Land Model Benchmarking (ILAMB) package for evaluation. At the column scale and across a wide range of sites, observed depth-resolved carbon stocks and their 14C derived turnover times can be explained by a model with explicit representation of two microbial populations, a simple representation of mineralogy, and vertical transport. Integrating soil and plant dynamics requires a 'process-scaling' approach, since all aspects of the multi-nutrient system cannot be explicitly resolved at ESM scales. I will show that one approach, the Equilibrium Chemistry Approximation, improves predictions of forest nitrogen and phosphorus experimental manipulations and leads to very different global soil carbon predictions. Translating model representations from the site- to ESM-scale requires a spatial scaling approach that either explicitly resolves the relevant processes, or more practically, accounts for fine-resolution dynamics at coarser scales. To that end, I will present recent watershed-scale modeling work that applies reduced order model methods to accurately scale fine-resolution soil carbon dynamics to coarse-resolution simulations. Finally, we

  18. [Development of a scale to measure Korean ego-integrity in older adults].

    PubMed

    Chang, Sung Ok; Kong, Eun Sook; Kim, Kwuy Bun; Kim, Nam Cho; Kim, Ju Hee; Kim, Chun Gill; Kim, Hee Kyung; Song, Mi Soon; Ahn, Soo Yeon; Lee, Kyung Ja; Lee, Young Whee; Chon, Si Ja; Cho, Nam Ok; Cho, Myung Ok; Choi, Kyung Sook

    2007-04-01

    Ego-integrity in older adults is the central concept related to quality of life in later life. Therefore, for effective interventions to enhance the quality of later life, a scale to measure ego-integrity in older adults is necessary. This study was carried out to develop a scale to measure ego-integrity in older adults. This study utilized cronbach's alpha in analyzing the reliability of the collected data and expert group, and factor analysis and item analysis to analyze validity. Seventeen items were selected from a total of 21 items. Cronbach's alpha coefficient for internal consistency was .88 for the 17 items of ego-integrity in the older adults scale. Three factors evolved by factor analysis, which explained 50.71% of the total variance. The scale for measuring ego-integrity in Korean older adults in this study was evaluated as a tool with a high degree of reliability and validity.

  19. Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

    PubMed

    Logan, Andrew; Yeow, John T W

    2009-05-01

    We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

  20. Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine

    PubMed Central

    Dey, Surajit; Parcha, Versha; Bhattacharya, Shiv Sankar; Ghosh, Amitava

    2013-01-01

    Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR). Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A), and lactose monohydrate as ingredient, of hydrophilic matrix former (B) on the bioadhesive force, disintegration time, percent (%) swelling index, and time taken for 70% drug release (t 70%). The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD) analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design. PMID:23781498

  1. Controlling Wafer Contamination Using Automated On-Line Metrology during Wet Chemical Cleaning

    NASA Astrophysics Data System (ADS)

    Wang, Jason; Kingston, Skip; Han, Ye; Saini, Harmesh; McDonald, Robert; Mui, Rudy

    2003-09-01

    The capabilities of a trace contamination analyzer are discussed and demonstrated. This analytical tool utilizes an electrospray, time-of-flight mass spectrometer (ES-TOF-MS) for fully automated on-line monitoring of wafer cleaning solutions. The analyzer provides rich information on metallic, anionic, cationic, elemental, and organic species through its ability to provide harsh (elemental) and soft (molecular) ionization under both positive and negative modes. It is designed to meet semiconductor process control and yield management needs for the ever increasing complex new chemistries present in wafer fabrication.

  2. Automatic vision-based grain optimization and analysis of multi-crystalline solar wafers using hierarchical region growing

    NASA Astrophysics Data System (ADS)

    Fan, Shu-Kai S.; Tsai, Du-Ming; Chuang, Wei-Che

    2017-04-01

    Solar power has become an attractive alternative source of energy. The multi-crystalline solar cell has been widely accepted in the market because it has a relatively low manufacturing cost. Multi-crystalline solar wafers with larger grain sizes and fewer grain boundaries are higher quality and convert energy more efficiently than mono-crystalline solar cells. In this article, a new image processing method is proposed for assessing the wafer quality. An adaptive segmentation algorithm based on region growing is developed to separate the closed regions of individual grains. Using the proposed method, the shape and size of each grain in the wafer image can be precisely evaluated. Two measures of average grain size are taken from the literature and modified to estimate the average grain size. The resulting average grain size estimate dictates the quality of the crystalline solar wafers and can be considered a viable quantitative indicator of conversion efficiency.

  3. Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

    DOE PAGES

    Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; ...

    2015-10-15

    Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

  4. Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes

    Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

  5. Organic printed photonics: From microring lasers to integrated circuits

    PubMed Central

    Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

    2015-01-01

    A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices. PMID:26601256

  6. Organic printed photonics: From microring lasers to integrated circuits.

    PubMed

    Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

    2015-09-01

    A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 10(5), which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

  7. Chemical etching for automatic processing of integrated circuits

    NASA Technical Reports Server (NTRS)

    Kennedy, B. W.

    1981-01-01

    Chemical etching for automatic processing of integrated circuits is discussed. The wafer carrier and loading from a receiving air track into automatic furnaces and unloading onto a sending air track are included.

  8. A fully wafer-level packaged RF MEMS switch with low actuation voltage using a piezoelectric actuator

    NASA Astrophysics Data System (ADS)

    Park, Jae-Hyoung; Lee, Hee-Chul; Park, Yong-Hee; Kim, Yong-Dae; Ji, Chang-Hyeon; Bu, Jonguk; Nam, Hyo-Jin

    2006-11-01

    In this paper, a fully wafer-level packaged RF MEMS switch has been demonstrated, which has low operation voltage, using a piezoelectric actuator. The piezoelectric actuator was designed to operate at low actuation voltage for application to advanced mobile handsets. The dc contact type RF switch was packaged using the wafer-level bonding process. The CPW transmission lines and piezoelectric actuators have been fabricated on separate wafers and assembled together by the wafer-level eutectic bonding process. A gold and tin composite was used for eutectic bonding at a low temperature of 300 °C. Via holes interconnecting the electrical contact pads through the wafer were filled completely with electroplated copper. The fully wafer-level packaged RF MEMS switch showed an insertion loss of 0.63 dB and an isolation of 26.4 dB at 5 GHz. The actuation voltage of the switch was 5 V. The resonant frequency of the piezoelectric actuator was 38.4 kHz and the spring constant of the actuator was calculated to be 9.6 N m-1. The size of the packaged SPST (single-pole single-through) switch was 1.2 mm × 1.2 mm including the packaging sealing rim. The effect of the proposed package structure on the RF performance was characterized with a device having CPW through lines and vertical feed lines excluding the RF switches. The measured packaging loss was 0.2 dB and the return loss was 33.6 dB at 5 GHz.

  9. Electro-optical Probing Of Terahertz Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Romanofsky, R.; Whitaker, J. F.; Valdmanis, J. A.; Mourou, G.; Jackson, T. A.

    1990-01-01

    Electro-optical probe developed to perform noncontact, nondestructive, and relatively noninvasive measurements of electric fields over broad spectrum at millimeter and shorter wavelengths in integrated circuits. Manipulated with conventional intregrated-circuit-wafer-probing equipment and operated without any special preparation of integrated circuits. Tip of probe small electro-optical crystal serving as proximity electric-field sensor.

  10. Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

    NASA Astrophysics Data System (ADS)

    Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

    2018-02-01

    We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

  11. A method for determining average damage depth of sawn crystalline silicon wafers

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Sopori, B.; Devayajanam, S.; Basnyat, P.

    2016-04-01

    The depth of surface damage (or simply, damage) in crystalline silicon wafers, caused by wire sawing of ingots, is determined by performing a series of minority carrier lifetime (MCLT) measurements. Samples are sequentially etched to remove thin layers from each surface and MCLT is measured after each etch step. The thickness-removed (..delta..t) at which the lifetime reaches a peak value corresponds to the damage depth. This technique also allows the damage to be quantified in terms of effective surface recombination velocity (Seff). To accomplish this, the MCLT data are converted into an Seff vs ..delta..t plot, which represents a quantitativemore » distribution of the degree of damage within the surface layer. We describe a wafer preparation procedure to attain reproducible etching and MCLT measurement results. We also describe important characteristics of an etchant used for controllably removing thin layers from the wafer surfaces. Some typical results showing changes in the MCLT vs ..delta..t plots for different cutting parameters are given.« less

  12. Optimization of corn, rice and buckwheat formulations for gluten-free wafer production.

    PubMed

    Dogan, Ismail Sait; Yildiz, Onder; Meral, Raciye

    2016-07-01

    Gluten-free baked products for celiac sufferers are essential for healthy living. Cereals having gluten such as wheat and rye must be removed from the diet for the clinical and histological improvement. The variety of gluten-free foods should be offered for the sufferers. In the study, gluten-free wafer formulas were optimized using corn, rice and buckwheat flours, xanthan and guar gum blend as an alternative product for celiac sufferers. Wafer sheet attributes and textural properties were investigated. Considering all wafer sheet properties in gluten-free formulas, better results were obtained by using 163.5% water, 0.5% guar and 0.1% xanthan in corn formula; 173.3% water, 0.45% guar and 0.15% xanthan gum in rice formula; 176% water, 0.1% guar and 0.5% xanthan gum in buckwheat formula. Average desirability values in gluten-free formulas were between 0.86 and 0.91 indicating they had similar visual and textural profiles to control sheet made with wheat flour. © The Author(s) 2015.

  13. Fabricating a Microcomputer on a Single Silicon Wafer

    NASA Technical Reports Server (NTRS)

    Evanchuk, V. L.

    1983-01-01

    Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

  14. Dislocation-free Ge Nano-crystals via Pattern Independent Selective Ge Heteroepitaxy on Si Nano-Tip Wafers.

    PubMed

    Niu, Gang; Capellini, Giovanni; Schubert, Markus Andreas; Niermann, Tore; Zaumseil, Peter; Katzer, Jens; Krause, Hans-Michael; Skibitzki, Oliver; Lehmann, Michael; Xie, Ya-Hong; von Känel, Hans; Schroeder, Thomas

    2016-03-04

    The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications.

  15. Dislocation-free Ge Nano-crystals via Pattern Independent Selective Ge Heteroepitaxy on Si Nano-Tip Wafers

    PubMed Central

    Niu, Gang; Capellini, Giovanni; Schubert, Markus Andreas; Niermann, Tore; Zaumseil, Peter; Katzer, Jens; Krause, Hans-Michael; Skibitzki, Oliver; Lehmann, Michael; Xie, Ya-Hong; von Känel, Hans; Schroeder, Thomas

    2016-01-01

    The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications. PMID:26940260

  16. Improving scanner wafer alignment performance by target optimization

    NASA Astrophysics Data System (ADS)

    Leray, Philippe; Jehoul, Christiane; Socha, Robert; Menchtchikov, Boris; Raghunathan, Sudhar; Kent, Eric; Schoonewelle, Hielke; Tinnemans, Patrick; Tuffy, Paul; Belen, Jun; Wise, Rich

    2016-03-01

    In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML's Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

  17. Towards a uniform and large-scale deposition of MoS2 nanosheets via sulfurization of ultra-thin Mo-based solid films.

    PubMed

    Vangelista, Silvia; Cinquanta, Eugenio; Martella, Christian; Alia, Mario; Longo, Massimo; Lamperti, Alessio; Mantovan, Roberto; Basset, Francesco Basso; Pezzoli, Fabio; Molle, Alessandro

    2016-04-29

    Large-scale integration of MoS2 in electronic devices requires the development of reliable and cost-effective deposition processes, leading to uniform MoS2 layers on a wafer scale. Here we report on the detailed study of the heterogeneous vapor-solid reaction between a pre-deposited molybdenum solid film and sulfur vapor, thus resulting in a controlled growth of MoS2 films onto SiO2/Si substrates with a tunable thickness and cm(2)-scale uniformity. Based on Raman spectroscopy and photoluminescence, we show that the degree of crystallinity in the MoS2 layers is dictated by the deposition temperature and thickness. In particular, the MoS2 structural disorder observed at low temperature (<750 °C) and low thickness (two layers) evolves to a more ordered crystalline structure at high temperature (1000 °C) and high thickness (four layers). From an atomic force microscopy investigation prior to and after sulfurization, this parametrical dependence is associated with the inherent granularity of the MoS2 nanosheet that is inherited by the pristine morphology of the pre-deposited Mo film. This work paves the way to a closer control of the synthesis of wafer-scale and atomically thin MoS2, potentially extendable to other transition metal dichalcogenides and hence targeting massive and high-volume production for electronic device manufacturing.

  18. Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

    NASA Astrophysics Data System (ADS)

    Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

    This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

  19. Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

    NASA Astrophysics Data System (ADS)

    Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

    2018-06-01

    We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

  20. Detection and characterization of microdefects and microprecipitates in Si wafers by Brewster angle illumination using an optical fiber system

    NASA Astrophysics Data System (ADS)

    Taijing, Lu; Toyoda, Koichi; Nango, Nobuhito; Ogawa, Tomoya

    1991-10-01

    Microdefects and microprecipitates were non-destructively detected in bulk and near surface of a Si wafer by Brewster angle illumination using an optical fiber system, because the p-component of the illumination enters completely into the wafer and then makes scattering from the defects while the other s-component reflects on the wafer surface so as to deviate from an objective lens for the detection of the scattering. Some results of observations and discussions will be done here about the scatterers in epitaxially grown Si layers, denuded zones of Si wafers, annealed amorphous SiC films, SIMOX specimens and slip bands in Si crystals.

  1. Wafer-scale Thermodynamically Stable GaN Nanorods via Two-Step Self-Limiting Epitaxy for Optoelectronic Applications

    NASA Astrophysics Data System (ADS)

    Kum, Hyun; Seong, Han-Kyu; Lim, Wantae; Chun, Daemyung; Kim, Young-Il; Park, Youngsoo; Yoo, Geonwook

    2017-01-01

    We present a method of epitaxially growing thermodynamically stable gallium nitride (GaN) nanorods via metal-organic chemical vapor deposition (MOCVD) by invoking a two-step self-limited growth (TSSLG) mechanism. This allows for growth of nanorods with excellent geometrical uniformity with no visible extended defects over a 100 mm sapphire (Al2O3) wafer. An ex-situ study of the growth morphology as a function of growth time for the two self-limiting steps elucidate the growth dynamics, which show that formation of an Ehrlich-Schwoebel barrier and preferential growth in the c-plane direction governs the growth process. This process allows monolithic formation of dimensionally uniform nanowires on templates with varying filling matrix patterns for a variety of novel electronic and optoelectronic applications. A color tunable phosphor-free white light LED with a coaxial architecture is fabricated as a demonstration of the applicability of these nanorods grown by TSSLG.

  2. First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

    NASA Technical Reports Server (NTRS)

    Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; hide

    2008-01-01

    Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.

  3. Ultra-wideband WDM VCSEL arrays by lateral heterogeneous integration

    NASA Astrophysics Data System (ADS)

    Geske, Jon

    Advancements in heterogeneous integration are a driving factor in the development of evermore sophisticated and functional electronic and photonic devices. Such advancements will merge the optical and electronic capabilities of different material systems onto a common integrated device platform. This thesis presents a new lateral heterogeneous integration technology called nonplanar wafer bonding. The technique is capable of integrating multiple dissimilar semiconductor device structures on the surface of a substrate in a single wafer bond step, leaving different integrated device structures adjacent to each other on the wafer surface. Material characterization and numerical simulations confirm that the material quality is not compromised during the process. Nonplanar wafer bonding is used to fabricate ultra-wideband wavelength division multiplexed (WDM) vertical-cavity surface-emitting laser (VCSEL) arrays. The optically-pumped VCSEL arrays span 140 nm from 1470 to 1610 nm, a record wavelength span for devices operating in this wavelength range. The array uses eight wavelength channels to span the 140 nm with all channels separated by precisely 20 nm. All channels in the array operate single mode to at least 65°C with output power uniformity of +/- 1 dB. The ultra-wideband WDM VCSEL arrays are a significant first step toward the development of a single-chip source for optical networks based on coarse WDM (CWDM), a low-cost alternative to traditional dense WDM. The CWDM VCSEL arrays make use of fully-oxidized distributed Bragg reflectors (DBRs) to provide the wideband reflectivity required for optical feedback and lasing across 140 rim. In addition, a novel optically-pumped active region design is presented. It is demonstrated, with an analytical model and experimental results, that the new active-region design significantly improves the carrier uniformity in the quantum wells and results in a 50% lasing threshold reduction and a 20°C improvement in the peak

  4. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto

    2006-12-10

    To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 {mu}m wide (111) sidewalls was fabricated using a 220 {mu}m thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

  5. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

    PubMed

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-12-10

    To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

  6. Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

    NASA Astrophysics Data System (ADS)

    Kubis, Michael; Wise, Rich; Reijnen, Liesbeth; Viatkina, Katja; Jaenen, Patrick; Luca, Melisa; Mernier, Guillaume; Chahine, Charlotte; Hellin, David; Kam, Benjamin; Sobieski, Daniel; Vertommen, Johan; Mulkens, Jan; Dusa, Mircea; Dixit, Girish; Shamma, Nader; Leray, Philippe

    2016-03-01

    With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

  7. Output blue light evaluation for phosphor based smart white LED wafer level packages.

    PubMed

    Kolahdouz, Zahra; Rostamian, Ali; Kolahdouz, Mohammadreza; Ma, Teng; van Zeijl, Henk; Zhang, Kouchi

    2016-02-22

    This study presents a blue light detector for evaluating the output light of phosphor based white LED package. It is composed of a silicon stripe-shaped photodiode designed and implemented in a 2 μm BiCMOS process which can be used for wafer level integration of different passive and active devices all in just 5 lithography steps. The final device shows a high selectivity to blue light. The maximum responsivity at 480 nm is matched with the target blue LED illumination. The designed structure have better responsivity compared to simple photodiode structure due to reducing the effect of dead layer formation close to the surface because of implantation. It has also a two-fold increase in the responsivity and quantum efficiency compared to previously similar published sensors.

  8. Development of a plan for automating integrated circuit processing

    NASA Technical Reports Server (NTRS)

    1971-01-01

    The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

  9. Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Tiriolo, Raffaele; Rangnekar, Neel; Zhang, Han

    A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservationmore » of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.« less

  10. Integration of a UV curable polymer lens and MUMPs structures on a SOI optical bench

    NASA Astrophysics Data System (ADS)

    Hsieh, Jerwei; Hsiao, Sheng-Yi; Lai, Chun-Feng; Fang, Weileun

    2007-08-01

    This work presents the design concept of integrating a polymer lens, poly-Si MUMPs and single-crystal-silicon HARM structures on a SOI wafer to form a silicon optical bench. This approach enables the monolithic integration of various optical components on the wafer so as to improve the design flexibility of the silicon optical bench. Fabrication processes, including surface and bulk micromachining on the SOI wafer, have been established to realize bi-convex spherical polymer lenses with in-plane as well as out-of-plane optical axes. In addition, a micro device consisting of an in-plane polymer lens, a thick fiber holder and a mechanical shutter driven by an electrothermal actuator is also demonstrated using the present approach. In summary, this study significantly improves the design flexibility as well as the functions of SiOBs.

  11. Contamination-Free Manufacturing: Tool Component Qualification, Verification and Correlation with Wafers

    NASA Astrophysics Data System (ADS)

    Tan, Samantha H.; Chen, Ning; Liu, Shi; Wang, Kefei

    2003-09-01

    As part of the semiconductor industry "contamination-free manufacturing" effort, significant emphasis has been placed on reducing potential sources of contamination from process equipment and process equipment components. Process tools contain process chambers and components that are exposed to the process environment or process chemistry and in some cases are in direct contact with production wafers. Any contamination from these sources must be controlled or eliminated in order to maintain high process yields, device performance, and device reliability. This paper discusses new nondestructive analytical methods for quantitative measurement of the cleanliness of metal, quartz, polysilicon and ceramic components that are used in process equipment tools. The goal of these new procedures is to measure the effectiveness of cleaning procedures and to verify whether a tool component part is sufficiently clean for installation and subsequent routine use in the manufacturing line. These procedures provide a reliable "qualification method" for tool component certification and also provide a routine quality control method for reliable operation of cleaning facilities. Cost advantages to wafer manufacturing include higher yields due to improved process cleanliness and elimination of yield loss and downtime resulting from the installation of "bad" components in process tools. We also discuss a representative example of wafer contamination having been linked to a specific process tool component.

  12. Large-Scale Fabrication of Carbon Nanotube Probe Tips For Atomic Force Microscopy Critical Dimension Imaging Applications

    NASA Technical Reports Server (NTRS)

    Ye, Qi Laura; Cassell, Alan M.; Stevens, Ramsey M.; Meyyappan, Meyya; Li, Jun; Han, Jie; Liu, Hongbing; Chao, Gordon

    2004-01-01

    Carbon nanotube (CNT) probe tips for atomic force microscopy (AFM) offer several advantages over Si/Si3N4 probe tips, including improved resolution, shape, and mechanical properties. This viewgraph presentation discusses these advantages, and the drawbacks of existing methods for fabricating CNT probe tips for AFM. The presentation introduces a bottom up wafer scale fabrication method for CNT probe tips which integrates catalyst nanopatterning and nanomaterials synthesis with traditional silicon cantilever microfabrication technology. This method makes mass production of CNT AFM probe tips feasible, and can be applied to the fabrication of other nanodevices with CNT elements.

  13. Resource integration and shared outcomes at the watershed scale

    Treesearch

    Eleanor S. Towns

    2000-01-01

    Shared resources are universal resources that are vital for sustaining communities, enhancing our quality of life and preserving ecosystem health. We have a shared responsibility to conserve shared resources and preserve their integrity for future generations. Resource integration is accomplished through ecosystem management, often at a watershed scale. The shared...

  14. Reliable four-point flexion test and model for die-to-wafer direct bonding

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Tabata, T., E-mail: toshiyuki.tabata@cea.fr; Sanchez, L.; Fournel, F.

    2015-07-07

    For many years, wafer-to-wafer (W2W) direct bonding has been very developed particularly in terms of bonding energy measurement and bonding mechanism comprehension. Nowadays, die-to-wafer (D2W) direct bonding has gained significant attention, for instance, in photonics and microelectro-mechanics, which supposes controlled and reliable fabrication processes. So, whatever the stuck materials may be, it is not obvious whether bonded D2W structures have the same bonding strength as bonded W2W ones, because of possible edge effects of dies. For that reason, it has been strongly required to develop a bonding energy measurement technique which is suitable for D2W structures. In this paper, bothmore » D2W- and W2W-type standard SiO{sub 2}-to-SiO{sub 2} direct bonding samples are fabricated from the same full-wafer bonding. Modifications of the four-point flexion test (4PT) technique and applications for measuring D2W direct bonding energies are reported. Thus, the comparison between the modified 4PT and the double-cantilever beam techniques is drawn, also considering possible impacts of the conditions of measures such as the water stress corrosion at the debonding interface and the friction error at the loading contact points. Finally, reliability of a modified technique and a new model established for measuring D2W direct bonding energies is demonstrated.« less

  15. A micro-scale plasma spectrometer for space and plasma edge applications (invited)

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Scime, E. E., E-mail: escime@wvu.edu; Keesee, A. M.; Elliott, D.

    2016-11-15

    A plasma spectrometer design based on advances in lithography and microchip stacking technologies is described. A series of curved plate energy analyzers, with an integrated collimator, is etched into a silicon wafer. Tests of spectrometer elements, the energy analyzer and collimator, were performed with a 5 keV electron beam. The measured collimator transmission and energy selectivity were in good agreement with design targets. A single wafer element could be used as a plasma processing or fusion first wall diagnostic.

  16. Pain assessment scales in newborns: integrative review

    PubMed Central

    de Melo, Gleicia Martins; Lélis, Ana Luíza Paula de Aguiar; de Moura, Alline Falconieri; Cardoso, Maria Vera Lúcia Moreira Leitão; da Silva, Viviane Martins

    2014-01-01

    OBJECTIVE: To analyze studies on methods used to assess pain in newborns. DATA SOURCES: Integrative review study of articles published from 2001 to 2012, carried out in the following databases: Scopus, PubMed, CINAHL, LILACS and Cochrane. The sample consisted of 13 articles with level of evidence 5. DATA SYNTHESIS: 29 pain assessment scales in newborns, including 13 one-dimensional and 16 multidimensional, that assess acute and prolonged pain in preterm and full-term infants were available in scientific publications. CONCLUSION: Based on the characteristics of scales, one cannot choose a single one as the most appropriate scale, as this choice will depend on gestational age, type of painful stimulus and the environment in which the infant is inserted. It is suggested the use of multidimensional or one-dimensional scales; however, they must be reliable and validated. PMID:25511005

  17. MoS2 synthesis by gas source MBE for transition metal dichalcogenides integration on large scale substrates

    NASA Astrophysics Data System (ADS)

    El Kazzi, S.; Mortelmans, W.; Nuytten, T.; Meersschaut, J.; Carolan, P.; Landeloos, L.; Conard, T.; Radu, I.; Heyns, M.; Merckling, C.

    2018-04-01

    We present in this paper the use of Gas Source Molecular Beam Epitaxy for the large-scale growth of transition metal dichalcogenides. Fiber-textured MoS2 co-deposited thin films (down to 1 MLs) are grown on commercially 200 mm wafer size templates where MX2 crystalline layers are achieved at temperatures ranging from RT to 550 °C. Raman Spectroscopy and photoluminescence measurements along with X-Ray Photoelectron Spectroscopy show that a low growth rate is essential for complete Mo sulfurization during MoS2 co-deposition. Finally, cross-section Transmission Electron Microscopy investigations are discussed to highlight the influence of SiO2 and Al2O3 used surfaces on MoS2 deposition.

  18. Wafer Scale Union.

    DTIC Science & Technology

    1992-05-31

    configuration. 25 We have tested it electronically to 26 GHz and found that the microwave loss is under 10 dB over the entire range. Our initial phase...UNION EFFORT 32 IEEE MICROWAVE AND GUIDED WAVE LETTERS. VOL. I. NO. 2. FEBRUARY 1991 Wide-Band Millimeter Wave Characterization of Sub-0.2 Micrometer...transistors (HEMT’s) ar nra- (over the frequency range of 1-26 GHz) and a network analyzer H ingly replacing GaAs MESFET’s in microwave and rail- als(ove r

  19. Interactions of double patterning technology with wafer processing, OPC and design flows

    NASA Astrophysics Data System (ADS)

    Lucas, Kevin; Cork, Chris; Miloslavsky, Alex; Luk-Pat, Gerry; Barnes, Levi; Hapli, John; Lewellen, John; Rollins, Greg; Wiaux, Vincent; Verhaegen, Staf

    2008-03-01

    Double patterning technology (DPT) is one of the main options for printing logic devices with half-pitch less than 45nm; and flash and DRAM memory devices with half-pitch less than 40nm. DPT methods decompose the original design intent into two individual masking layers which are each patterned using single exposures and existing 193nm lithography tools. The results of the individual patterning layers combine to re-create the design intent pattern on the wafer. In this paper we study interactions of DPT with lithography, masks synthesis and physical design flows. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step which will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons where required; and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals such as: reduce circuit area; minimize rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure symmetric wafer results; and create uniform wafer density for the individual patterning layers.

  20. X-Ray Diffraction Wafer Mapping Method for Rhombohedral Super-Hetero-Epitaxy

    NASA Technical Reports Server (NTRS)

    Park, Yoonjoon; Choi, Sang Hyouk; King, Glen C.; Elliott, James R.; Dimarcantonio, Albert L.

    2010-01-01

    A new X-ray diffraction (XRD) method is provided to acquire XY mapping of the distribution of single crystals, poly-crystals, and twin defects across an entire wafer of rhombohedral super-hetero-epitaxial semiconductor material. In one embodiment, the method is performed with a point or line X-ray source with an X-ray incidence angle approximating a normal angle close to 90 deg, and in which the beam mask is preferably replaced with a crossed slit. While the wafer moves in the X and Y direction, a narrowly defined X-ray source illuminates the sample and the diffracted X-ray beam is monitored by the detector at a predefined angle. Preferably, the untilted, asymmetric scans are of {440} peaks, for twin defect characterization.

  1. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    DOEpatents

    Lin, YuPo J [Naperville, IL; Henry, Michael P [Batavia, IL; Snyder, Seth W [Lincolnwood, IL

    2011-07-12

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  2. Production of Optical Quality Free Standing Diamond Wafer

    DTIC Science & Technology

    2008-05-19

    Title : Production of Optical Quality Free Standing Diamond Wafer Prime Contractor : Onyx Optics, Inc. 6551 Sierra Lane Dublin, Ca 94568...www.onyxoptics.com Program Manager : Helmuth Meissner Onyx Optics, Inc. 6551 Sierra Lane Dublin, CA 94568 Email: hmeissner@onyxoptics.com Ph: 925...PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) Onyx Optics, Inc. 6551 Sierra Lane Dublin, Ca 94568 8. PERFORMING ORGANIZATION REPORT NUMBER 9. SPONSORING

  3. Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Sumant, A.V.; Auciello, O.; Yuan, H.-C

    2009-05-01

    Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materialsmore » integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.« less

  4. Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

    NASA Astrophysics Data System (ADS)

    Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

    2018-05-01

    Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

  5. Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

    NASA Astrophysics Data System (ADS)

    Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

    2018-05-01

    A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

  6. Molded, wafer level optics for long wave infra-red applications

    NASA Astrophysics Data System (ADS)

    Franks, John

    2016-05-01

    For many years, the Thermal Imaging market has been driven by the high volume consumer market. The first signs of this came with the launch of night vision systems for cars, first by Cadillac and Honda and then, more successfully by BMW, Daimler and Audi. For the first time, simple thermal imaging systems were being manufactured at the rate of more than 10,000 units a year. This step change in volumes enabled a step change in system costs, with thermal imaging moving into the consumer's price range. Today we see that the consumer awareness and the consumer market continues to increase with the launch of a number of consumer focused smart phone add-ons. This has brought a further step change in system costs, with the possibility to turn your mobile phone into a thermal imager for under $250. As the detector technology has matured, the pixel pitches have dropped from 50μm in 2002 to 12 μm or even 10μm in today's detectors. This dramatic shrinkage in size has had an equally dramatic effect on the optics required to produce the image on the detector. A moderate field of view that would have required a focal length of 40mm in 2002 now requires a focal length of 8mm. For wide field of view applications and small detector formats, focal lengths in the range 1mm to 5mm are becoming common. For lenses, the quantity manufactured, quality and costs will require a new approach to high volume Infra-Red (IR) manufacturing to meet customer expectations. This, taken with the SwaP-C requirements and the emerging requirement for very small lenses driven by the new detectors, suggests that wafer scale optics are part of the solution. Umicore can now present initial results from an intensive research and development program to mold and coat wafer level optics, using its chalcogenide glass, GASIR®.

  7. 2-dimensional ion velocity distributions measured by laser-induced fluorescence above a radio-frequency biased silicon wafer

    NASA Astrophysics Data System (ADS)

    Moore, Nathaniel B.; Gekelman, Walter; Pribyl, Patrick; Zhang, Yiting; Kushner, Mark J.

    2013-08-01

    The dynamics of ions traversing sheaths in low temperature plasmas are important to the formation of the ion energy distribution incident onto surfaces during microelectronics fabrication. Ion dynamics have been measured using laser-induced fluorescence (LIF) in the sheath above a 30 cm diameter, 2.2 MHz-biased silicon wafer in a commercial inductively coupled plasma processing reactor. The velocity distribution of argon ions was measured at thousands of positions above and radially along the surface of the wafer by utilizing a planar laser sheet from a pulsed, tunable dye laser. Velocities were measured both parallel and perpendicular to the wafer over an energy range of 0.4-600 eV. The resulting fluorescence was recorded using a fast CCD camera, which provided resolution of 0.4 mm in space and 30 ns in time. Data were taken at eight different phases during the 2.2 MHz cycle. The ion velocity distributions (IVDs) in the sheath were found to be spatially non-uniform near the edge of the wafer and phase-dependent as a function of height. Several cm above the wafer the IVD is Maxwellian and independent of phase. Experimental results were compared with simulations. The experimental time-averaged ion energy distribution function as a function of height compare favorably with results from the computer model.

  8. Multiproject wafers: not just for million-dollar mask sets

    NASA Astrophysics Data System (ADS)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

  9. Oxygen precipitation and bulk microdefects induced by the pre- and postepitaxial annealing in N/N + (100) silicon wafers

    NASA Astrophysics Data System (ADS)

    Wijaranakula, W.; Matlock, J. H.; Mollenkopf, H.

    1987-12-01

    Substrate wafers used for fabrication of epitaxial silicon wafers heavily doped with antimony at the concentration of 1020 atoms/cm3 were preannealed at a temperature between 500 and 900 °C prior to epitaxial deposition. Device fabrication thermal simulation was performed by heat treating the preannealed epitaxial wafers at 1050 °C in dry oxygen ambient for 16 h. Postepitaxial nucleation heat treatment at 750 °C for 4 h prior to the 1050 °C heat treament cycle was also applied on some epitaxial wafers for the purpose of enhancing the oxygen precipitation in silicon. It was observed that morphology and density of the bulk defects induced by the thermal treatment are affected by the preannealing temperature. The results also indicate that nucleation and growth kinetics of oxygen precipitates in preannealed n+ degenerate silicon substrate is strongly governed by oxygen and point defect diffusion.

  10. A novel approach: high resolution inspection with wafer plane defect detection

    NASA Astrophysics Data System (ADS)

    Hess, Carl; Wihl, Mark; Shi, Rui-fang; Xiong, Yalin; Pang, Song

    2008-05-01

    High Resolution reticle inspection is well-established as a proven, effective, and efficient means of detecting yield-limiting mask defects as well as defects which are not immediately yield-limiting yet can enable manufacturing process improvements. Historically, RAPID products have enabled detection of both classes of these defects. The newly-developed Wafer Plane Inspection (WPI) detector technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. Wafer Plane Inspection accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. This has the effect of reducing sensitivity to non-printing defects while enabling higher sensitivity focused in high MEEF areas where small reticle defects still yield significant printing defects on wafers. WPI is a new inspection mode that has been developed by KLA-Tencor and is currently under test with multiple customers. It employs the same transmitted and reflected-light high-resolution images as the industry-standard high-resolution inspections, but with much more sophisticated processing involved. A rigorous mask pattern recovery algorithm is used to convert the transmitted and reflected light images into a modeled representation of the reticle. Lithographic modeling of the scanner is then used to generate an aerial image of the mask. This is followed by resist modeling to determine the exposure of the photoresist. The defect detectors are then applied on this photoresist plane so that only printing defects are detected. Note that no hardware modifications to the inspection system are required to enable this detector. The same tool will be able to perform both our standard High Resolution inspections and the Wafer Plane Inspection detector. This approach has several important features. The ability to ignore non

  11. Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Calaway, Michael J.; Rodriquez, M. C.; Allton, J. H.; Stansbery, E. K.

    2009-01-01

    The Genesis sample return capsule, though broken during the landing impact, contained most of the shattered ultra-pure solar wind collectors comprised of silicon and other semiconductor wafers materials. Post-flight analysis revealed that all wafer fragments were littered with surface particle contamination from spacecraft debris as well as soil from the impact site. This particulate contamination interferes with some analyses of solar wind. In early 2005, the Genesis science team decided to investigate methods for removing the surface particle contamination prior to solar wind analysis.

  12. Heterogeneous integration based on low-temperature bonding for advanced optoelectronic devices

    NASA Astrophysics Data System (ADS)

    Higurashi, Eiji

    2018-04-01

    Heterogeneous integration is an attractive approach to manufacturing future optoelectronic devices. Recent progress in low-temperature bonding techniques such as plasma activation bonding (PAB) and surface-activated bonding (SAB) enables a new approach to integrating dissimilar materials for a wide range of photonics applications. In this paper, low-temperature direct bonding and intermediate layer bonding techniques are focused, and their state-of-the-art applications in optoelectronic devices are reviewed. First, we describe the room-temperature direct bonding of Ge/Ge and Ge/Si wafers for photodetectors and of GaAs/SiC wafers for high-power semiconductor lasers. Then, we describe low-temperature intermediate layer bonding using Au and lead-free Sn-3.0Ag-0.5Cu solders for optical sensors and MEMS packaging.

  13. Homogeneous transparent conductive ZnO:Ga by ALD for large LED wafers

    NASA Astrophysics Data System (ADS)

    Szabó, Zoltán; Baji, Zsófia; Basa, Péter; Czigány, Zsolt; Bársony, István; Wang, Hsin-Ying; Volk, János

    2016-08-01

    Highly conductive and uniform Ga doped ZnO (GZO) films were prepared by atomic layer deposition (ALD) as transparent conductive layers for InGaN/GaN LEDs. The optimal Ga doping concentration was found to be 3 at%. Even for 4" wafers, the TCO layer shows excellent homogeneity of film resistivity (0.8 %) according to Eddy current and spectroscopic ellipsometry mapping. This makes ALD a favourable technique over concurrent methods like MBE and PLD where the up-scaling is problematic. In agreement with previous studies, it was found that by an annealing treatment the quality of the GZO/p-GaN interface can be improved, although it causes the degradation of TCO conductivity. Therefore, a two-step ALD deposition technique was proposed and demonstrated: a "buffer layer" deposited and annealed first was followed by a second deposition step to maintain the high conductivity of the top layer.

  14. Graphene photodetectors with a bandwidth  >76 GHz fabricated in a 6″ wafer process line

    NASA Astrophysics Data System (ADS)

    Schall, Daniel; Porschatis, Caroline; Otto, Martin; Neumaier, Daniel

    2017-03-01

    In recent years, the data traffic has grown exponentially and the forecasts indicate a huge market that could be addressed by communication infrastructure and service providers. However, the processing capacity, space, and energy consumption of the available technology is a serious bottleneck for the exploitation of these markets. Chip-integrated optical communication systems hold the promise of significantly improving these issues related to the current technology. At the moment, the answer to the question which material is best suited for ultrafast chip integrated communication systems is still open. In this manuscript we report on ultrafast graphene photodetectors with a bandwidth of more than 76 GHz well suitable for communication links faster than 100 GBit s-1 per channel. We extract an upper value of 7.2 ps for the timescale in which the bolometric photoresponse in graphene is generated. The photodetectors were fabricated on 6″ silicon-on-insulator wafers in a semiconductor pilot line, demonstrating the scalable fabrication of high-performance graphene based devices.

  15. Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

    NASA Astrophysics Data System (ADS)

    Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

    2018-07-01

    This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

  16. Fractionaly Integrated Flux model and Scaling Laws in Weather and Climate

    NASA Astrophysics Data System (ADS)

    Schertzer, Daniel; Lovejoy, Shaun

    2013-04-01

    The Fractionaly Integrated Flux model (FIF) has been extensively used to model intermittent observables, like the velocity field, by defining them with the help of a fractional integration of a conservative (i.e. strictly scale invariant) flux, such as the turbulent energy flux. It indeed corresponds to a well-defined modelling that yields the observed scaling laws. Generalised Scale Invariance (GSI) enables FIF to deal with anisotropic fractional integrations and has been rather successful to define and model a unique regime of scaling anisotropic turbulence up to planetary scales. This turbulence has an effective dimension of 23/9=2.55... instead of the classical hypothesised 2D and 3D turbulent regimes, respectively for large and small spatial scales. It therefore theoretically eliminates a non plausible "dimension transition" between these two regimes and the resulting requirement of a turbulent energy "mesoscale gap", whose empirical evidence has been brought more and more into question. More recently, GSI-FIF was used to analyse climate, therefore at much larger time scales. Indeed, the 23/9-dimensional regime necessarily breaks up at the outer spatial scales. The corresponding transition range, which can be called "macroweather", seems to have many interesting properties, e.g. it rather corresponds to a fractional differentiation in time with a roughly flat frequency spectrum. Furthermore, this transition yields the possibility to have at much larger time scales scaling space-time climate fluctuations with a much stronger scaling anisotropy between time and space. Lovejoy, S. and D. Schertzer (2013). The Weather and Climate: Emergent Laws and Multifractal Cascades. Cambridge Press (in press). Schertzer, D. et al. (1997). Fractals 5(3): 427-471. Schertzer, D. and S. Lovejoy (2011). International Journal of Bifurcation and Chaos 21(12): 3417-3456.

  17. Opportunities of CMOS-MEMS integration through LSI foundry and open facility

    NASA Astrophysics Data System (ADS)

    Mita, Yoshio; Lebrasseur, Eric; Okamoto, Yuki; Marty, Frédéfic; Setoguchi, Ryota; Yamada, Kentaro; Mori, Isao; Morishita, Satoshi; Imai, Yoshiaki; Hosaka, Kota; Hirakawa, Atsushi; Inoue, Shu; Kubota, Masanori; Denoual, Matthieu

    2017-06-01

    Since the 2000s, several countries have established micro- and nanofabrication platforms for the research and education community as national projects. By combining such platforms with VLSI multichip foundry services, various integrated devices, referred to as “CMOS-MEMS”, can be realized without constructing an entire cleanroom. In this paper, we summarize MEMS-last postprocess schemes for CMOS devices on a bulk silicon wafer as well as on a silicon-on-insulator (SOI) wafer using an open-access cleanroom of the Nanotechnology Platform of MEXT Japan. The integration devices presented in this article are free-standing structures and postprocess isolated LSI devices. Postprocess issues are identified with their solutions, such as the reactive ion etching (RIE) lag for dry release and the impact of the deep RIE (DRIE) postprocess on transistor characteristics. Integration with nonsilicon materials is proposed as one of the future directions.

  18. Stability of laser-propelled wafer satellites

    NASA Astrophysics Data System (ADS)

    Srinivasan, Prashant; Hughes, Gary B.; Lubin, Philip; Zhang, Qicheng; Madajian, Jonathan; Brashears, Travis; Kulkarni, Neeraj; Cohen, Alexander; Griswold, Janelle

    2016-09-01

    For interstellar missions, directed energy is envisioned to drive wafer-scale spacecraft to relativistic speeds. Spacecraft propulsion is provided by a large array of phase-locked lasers, either in Earth orbit or stationed on the ground. The directed-energy beam is focused on the spacecraft, which includes a reflective sail that propels the craft by reflecting the beam. Fluctuations and asymmetry in the beam will create rotational forces on the sail, so the sail geometry must possess an inherent, passive stabilizing effect. A hyperboloid shape is proposed, since changes in the incident beam angle due to yaw will passively counteract rotational forces. This paper explores passive stability properties of a hyperboloid reflector being bombarded by directed-energy beam. A 2D cross-section is analyzed for stability under simulated asymmetric loads. Passive stabilization is confirmed over a range of asymmetries. Realistic values of radiation pressure magnitude are drawn from the physics of light-mirror interaction. Estimates of beam asymmetry are drawn from optical modeling of a laser array far-field intensity using fixed and stochastic phase perturbations. A 3D multi-physics model is presented, using boundary conditions and forcing terms derived from beam simulations and lightmirror interaction models. The question of optimal sail geometry can be pursued, using concepts developed for the baseline hyperboloid. For example, higher curvature of the hyperboloid increases stability, but reduces effective thrust. A hyperboloid sail could be optimized by seeking the minimum curvature that is stable over the expected range of beam asymmetries.

  19. Compliant heterogeneous assemblies of micro-VCSELs as a new materials platform for integrated optoelectronics

    NASA Astrophysics Data System (ADS)

    Kang, Dongseok; Lee, Sung-Min; Kwong, Anthony; Yoon, Jongseung

    2015-03-01

    Despite many unique advantages, vertical cavity surface emitting lasers (VCSELs) have been available mostly on rigid, planar wafers over restricted areas, thereby limiting their usage for applications that can benefit from large-scale, programmable assemblies, hybrid integration with dissimilar materials and devices, or mechanically flexible constructions. Here, materials design and fabrication strategies that address these limitations of conventional VCSELs are presented. Specialized design of epitaxial materials and etching processes, together with printing-based deterministic assemblies and substrate thermal engineering, enabled defect-free release of microscale VCSELs and their device- and circuit-level implementation on non-native, flexible substrates with performance comparable to devices on the growth substrate.

  20. Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

    NASA Astrophysics Data System (ADS)

    Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

    2016-11-01

    The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

  1. High-wafer-yield, high-performance vertical cavity surface-emitting lasers

    NASA Astrophysics Data System (ADS)

    Li, Gabriel S.; Yuen, Wupen; Lim, Sui F.; Chang-Hasnain, Constance J.

    1996-04-01

    Vertical cavity surface emitting lasers (VCSELs) with very low threshold current and voltage of 340 (mu) A and 1.5 V is achieved. The molecular beam epitaxially grown wafers are grown with a highly accurate, low cost and versatile pre-growth calibration technique. One- hundred percent VCSEL wafer yield is obtained. Low threshold current is achieved with a native oxide confined structure with excellent current confinement. Single transverse mode with stable, predetermined polarization direction up to 18 times threshold is also achieved, due to stable index guiding provided by the structure. This is the highest value reported to data for VCSELs. We have established that p-contact annealing in these devices is crucial for low voltage operation, contrary to the general belief. Uniform doping in the mirrors also appears not to be inferior to complicated doping engineering. With these design rules, very low threshold voltage VCSELs are achieved with very simple growth and fabrication steps.

  2. Resonance ultrasonic vibrations in Cz-Si wafers as a possible diagnostic technique in ion implantation

    NASA Astrophysics Data System (ADS)

    Zhao, Z. Y.; Ostapenko, S.; Anundson, R.; Tvinnereim, M.; Belyaev, A.; Anthony, M.

    2001-07-01

    The semiconductor industry does not have effective metrology for well implants. The ability to measure such deep level implants will become increasingly important as we progress along the technology road map. This work explores the possibility of using the acoustic whistle effect on ion implanted silicon wafers. The technique detects the elastic stress and defects in silicon wafers by measuring the sub-harmonic f/2 resonant vibrations on a wafer induced via backside contact to create standing waves, which are measured by a non-contact ultrasonic probe. Preliminary data demonstrates that it is sensitive to implant damage, and there is a direct correlation between this sub-harmonic acoustic mode and some of the implant and anneal conditions. This work presents the results of a feasibility study to assess and quantify the correspondent whistle effect to implant damage, residual damage after annealing and intrinsic defects.

  3. Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

    NASA Astrophysics Data System (ADS)

    Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

    2018-06-01

    Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

  4. Traits Without Borders: Integrating Functional Diversity Across Scales.

    PubMed

    Carmona, Carlos P; de Bello, Francesco; Mason, Norman W H; Lepš, Jan

    2016-05-01

    Owing to the conceptual complexity of functional diversity (FD), a multitude of different methods are available for measuring it, with most being operational at only a small range of spatial scales. This causes uncertainty in ecological interpretations and limits the potential to generalize findings across studies or compare patterns across scales. We solve this problem by providing a unified framework expanding on and integrating existing approaches. The framework, based on trait probability density (TPD), is the first to fully implement the Hutchinsonian concept of the niche as a probabilistic hypervolume in estimating FD. This novel approach could revolutionize FD-based research by allowing quantification of the various FD components from organismal to macroecological scales, and allowing seamless transitions between scales. Copyright © 2016 Elsevier Ltd. All rights reserved.

  5. Investigation of diffusion length distribution on polycrystalline silicon wafers via photoluminescence methods

    PubMed Central

    Lou, Shishu; Zhu, Huishi; Hu, Shaoxu; Zhao, Chunhua; Han, Peide

    2015-01-01

    Characterization of the diffusion length of solar cells in space has been widely studied using various methods, but few studies have focused on a fast, simple way to obtain the quantified diffusion length distribution on a silicon wafer. In this work, we present two different facile methods of doing this by fitting photoluminescence images taken in two different wavelength ranges or from different sides. These methods, which are based on measuring the ratio of two photoluminescence images, yield absolute values of the diffusion length and are less sensitive to the inhomogeneity of the incident laser beam. A theoretical simulation and experimental demonstration of this method are presented. The diffusion length distributions on a polycrystalline silicon wafer obtained by the two methods show good agreement. PMID:26364565

  6. A Wafer-Bonded, Floating Element Shear-Stress Sensor Using a Geometric Moire Optical Transduction Technique

    NASA Technical Reports Server (NTRS)

    Horowitz, Stephen; Chen, Tai-An; Chandrasekaran, Venkataraman; Tedjojuwono, Ken; Cattafesta, Louis; Nishida, Toshikazu; Sheplak, Mark

    2004-01-01

    This paper presents a geometric Moir optical-based floating-element shear stress sensor for wind tunnel turbulence measurements. The sensor was fabricated using an aligned wafer-bond/thin-back process producing optical gratings on the backside of a floating element and on the top surface of the support wafer. Measured results indicate a static sensitivity of 0.26 microns/Pa, a resonant frequency of 1.7 kHz, and a noise floor of 6.2 mPa/(square root)Hz.

  7. Surface characteristics and damage distributions of diamond wire sawn wafers for silicon solar cells

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Sopori, Bhushan; Devayajanam, Srinivas; Basnyat, Prakash

    2016-01-01

    This paper describes surface characteristics, in terms of its morphology, roughness and near-surface damage of Si wafers cut by diamond wire sawing (DWS) of Si ingots under different cutting conditions. Diamond wire sawn Si wafers exhibit nearly-periodic surface features of different spatial wavelengths, which correspond to kinematics of various movements during wafering, such as ingot feed, wire reciprocation, and wire snap. The surface damage occurs in the form of frozen-in dislocations, phase changes, and microcracks. The in-depth damage was determined by conventional methods such as TEM, SEM and angle-polishing/defect-etching. However, because these methods only provide local information, we have alsomore » applied a new technique that determines average damage depth over a large area. This technique uses sequential measurement of the minority carrier lifetime after etching thin layers from the surfaces. The lateral spatial damage variations, which seem to be mainly related to wire reciprocation process, were observed by photoluminescence and minority carrier lifetime mapping. Our results show a strong correlation of damage depth on the diamond grit size and wire usage.« less

  8. Virtual overlay metrology for fault detection supported with integrated metrology and machine learning

    NASA Astrophysics Data System (ADS)

    Lee, Hong-Goo; Schmitt-Weaver, Emil; Kim, Min-Suk; Han, Sang-Jun; Kim, Myoung-Soo; Kwon, Won-Taik; Park, Sung-Ki; Ryan, Kevin; Theeuwes, Thomas; Sun, Kyu-Tae; Lim, Young-Wan; Slotboom, Daan; Kubis, Michael; Staecker, Jens

    2015-03-01

    While semiconductor manufacturing moves toward the 7nm node for logic and 15nm node for memory, an increased emphasis has been placed on reducing the influence known contributors have toward the on product overlay budget. With a machine learning technique known as function approximation, we use a neural network to gain insight to how known contributors, such as those collected with scanner metrology, influence the on product overlay budget. The result is a sufficiently trained function that can approximate overlay for all wafers exposed with the lithography system. As a real world application, inline metrology can be used to measure overlay for a few wafers while using the trained function to approximate overlay vector maps for the entire lot of wafers. With the approximated overlay vector maps for all wafers coming off the track, a process engineer can redirect wafers or lots with overlay signatures outside the standard population to offline metrology for excursion validation. With this added flexibility, engineers will be given more opportunities to catch wafers that need to be reworked, resulting in improved yield. The quality of the derived corrections from measured overlay metrology feedback can be improved using the approximated overlay to trigger, which wafers should or shouldn't be, measured inline. As a development or integration engineer the approximated overlay can be used to gain insight into lots and wafers used for design of experiments (DOE) troubleshooting. In this paper we will present the results of a case study that follows the machine learning function approximation approach to data analysis, with production overlay measured on an inline metrology system at SK hynix.

  9. Optimal mask characterization by Surrogate Wafer Print (SWaP) method

    NASA Astrophysics Data System (ADS)

    Kimmel, Kurt R.; Hoellein, Ingo; Peters, Jan Hendrick; Ackmann, Paul; Connolly, Brid; West, Craig

    2008-10-01

    Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask relative to the specifications is done completely by the mask maker. As the challenges of low-k1 imaging continue to grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers' continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore, improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent and compelling. The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images, rather than the mask's physical attributes, as a technically superior and lower-cost method to characterize a mask. The idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for traditional mask inspections and measurements represents the ultimate method to characterize a mask's performance, which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab mask qualification to validate defect and dimensional performance. In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of SWaP for the characterization of defects as an alternative to traditional mask inspection [1]. It showed that this concept is not only feasible, but, in some cases, desirable. This paper expands on last year's work at AMTC to assess the full implementation of SWaP as an

  10. Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

    NASA Astrophysics Data System (ADS)

    Kim, Bong-Hwan; Kim, Jong-Bok

    2009-06-01

    We have developed a microfabrication process for high aspect ratio thick silicon wafer molds and electroplating using flipchip bonding with THB 151N negative photoresist (JSR micro). This fabrication technique includes large area and high thickness silicon wafer mold electroplating. The process consists of silicon deep reactive ion etching (RIE) of the silicon wafer mold, photoresist bonding between the silicon mold and the substrate, nickel electroplating and a silicon removal process. High thickness silicon wafer molds were made by deep RIE and flipchip bonding. In addition, nickel electroplating was developed. Dry film resist (ORDYL MP112, TOK) and thick negative-tone photoresist (THB 151N, JSR micro) were used as bonding materials. In order to measure the bonding strength, the surface energy was calculated using a blade test. The surface energy of the bonding wafers was found to be 0.36-25.49 J m-2 at 60-180 °C for the dry film resist and 0.4-1.9 J m-2 for THB 151N in the same temperature range. Even though ORDYL MP112 has a better value of surface energy than THB 151N, it has a critical disadvantage when it comes to removing residue after electroplating. The proposed process can be applied to high aspect ratio MEMS structures, such as air gap inductors or vertical MEMS probe tips.

  11. Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

    NASA Astrophysics Data System (ADS)

    Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

    2018-03-01

    A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

  12. SEMICONDUCTOR TECHNOLOGY A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    NASA Astrophysics Data System (ADS)

    Baohong, Gao; Yuling, Liu; Chenwei, Wang; Yadong, Zhu; Shengli, Wang; Qiang, Zhou; Baimei, Tan

    2010-10-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection.

  13. Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

    NASA Astrophysics Data System (ADS)

    Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

    2018-06-01

    Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

  14. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  15. Silicon-on-insulator with hybrid orientations for heterogeneous integration of GaN on Si (100) substrate

    NASA Astrophysics Data System (ADS)

    Zhang, Runchun; Zhao, Beiji; Huang, Kai; You, Tiangui; Jia, Qi; Lin, Jiajie; Zhang, Shibin; Yan, Youquan; Yi, Ailun; Zhou, Min; Ou, Xin

    2018-05-01

    Heterogeneous integration of materials pave a new way for the development of the microsystem with miniaturization and complex functionalities. Two types of hybrid silicon on insulator (SOI) structures, i.e., Si (100)-on-Si (111) and Si (111)-on-Si (100), were prepared by the smart-cut technique, which is consist of ion-slicing and wafer bonding. The precise calculation of the lattice strain of the transferred films without the epitaxial matching relationship to the substrate was demonstrated based on X-ray diffraction (XRD) measurements. The XRD and Raman measurement results suggest that the transferred films possess single crystalline quality. With a chemical mechanical polishing (CMP) process, the surface roughness of the transferred thin films can be reduced from 5.57 nm to 0.30 nm. The 4-inch GaN thin film epitaxially grown on the as-prepared hybrid SOI of Si (111)-on-Si (100) by metalorganic chemical vapor deposition (MOCVD) is of improved quality with a full width at half maximum (FWHM) of 672.54 arcsec extracted from the XRD rocking curve and small surface roughness of 0.40 nm. The wafer-scale GaN on Si (111)-on-Si (100) can serve as a potential platform for the one chip integration of GaN-based high electron mobility transistors (HEMT) or photonics with the Si (100)-based complementary metal oxide semiconductor (CMOS).

  16. Timing of Formal Phase Safety Reviews for Large-Scale Integrated Hazard Analysis

    NASA Technical Reports Server (NTRS)

    Massie, Michael J.; Morris, A. Terry

    2010-01-01

    Integrated hazard analysis (IHA) is a process used to identify and control unacceptable risk. As such, it does not occur in a vacuum. IHA approaches must be tailored to fit the system being analyzed. Physical, resource, organizational and temporal constraints on large-scale integrated systems impose additional direct or derived requirements on the IHA. The timing and interaction between engineering and safety organizations can provide either benefits or hindrances to the overall end product. The traditional approach for formal phase safety review timing and content, which generally works well for small- to moderate-scale systems, does not work well for very large-scale integrated systems. This paper proposes a modified approach to timing and content of formal phase safety reviews for IHA. Details of the tailoring process for IHA will describe how to avoid temporary disconnects in major milestone reviews and how to maintain a cohesive end-to-end integration story particularly for systems where the integrator inherently has little to no insight into lower level systems. The proposal has the advantage of allowing the hazard analysis development process to occur as technical data normally matures.

  17. Chemical vapor deposition for automatic processing of integrated circuits

    NASA Technical Reports Server (NTRS)

    Kennedy, B. W.

    1980-01-01

    Chemical vapor deposition for automatic processing of integrated circuits including the wafer carrier and loading from a receiving air track into automatic furnaces and unloading on to a sending air track is discussed. Passivation using electron beam deposited quartz is also considered.

  18. Damage free integration of ultralow-k dielectrics by template replacement approach

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Zhang, L.; De Gendt, S.; Department of Chemistry, Katholieke Universiteit Leuven, 3000 Leuven

    2015-08-31

    Cu/low-k integration by conventional damascene approach is becoming increasingly difficult as critical dimensions scale down. An alternative integration scheme is studied based on the replacement of a sacrificial template by ultralow-k dielectric. A metal structure is first formed by patterning a template material. After template removal, a k = 2.31 spin-on type of porous low-k dielectric is deposited onto the patterned metal lines. The chemical and electrical properties of spin-on dielectrics are studied on blanket wafers, indicating that during hard bake, most porogen is removed within few minutes, but 120 min are required to achieve the lowest k-value. The effective dielectric constantmore » of the gap-fill low-k is investigated on a 45 nm ½ pitch Meander-Fork structure, leading to k{sub eff} below 2.4. The proposed approach solves the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous materials.« less

  19. Emissivity properties of silicon wafers and their application to radiation thermometry

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Iuchi, T.; Seo, T.

    We studied the spectral and directional emissivities of silicon wafers using an optical polarization technique. Based on the simulation and experimental results, we developed two different radiation thermometry methods for silicon wafers, the first based on a polarized emissivity-invariant condition, and the second based on the relationship between the ratio of the p-to s-polarized radiance and the polarized emissivity. These methods can be performed at temperatures above 600 °C and over a wide wavelength range (0.9∼5 μm), irrespective of dielectric film thickness and substrate resistivity due to the dopant concentrations. Temperature measurements were estimated to have expanded uncertainties (k=2) ofmore » less than 5 °C. A radiometer system with wavelengths above 4.5 μm was successfully developed because the system was not influenced by background noise caused by a high-intensity heating lamp.« less

  20. Model-Based Infrared Metrology for Advanced Technology Nodes and 300 mm Wafer Processing

    NASA Astrophysics Data System (ADS)

    Rosenthal, Peter A.; Duran, Carlos; Tower, Josh; Mazurenko, Alex; Mantz, Ulrich; Weidner, Peter; Kasic, Alexander

    2005-09-01

    The use of infrared spectroscopy for production semiconductor process monitoring has evolved recently from primarily unpatterned, i.e. blanket test wafer measurements in a limited historical application space of blanket epitaxial, BPSG, and FSG layers to new applications involving patterned product wafer measurements, and new measurement capabilities. Over the last several years, the semiconductor industry has adopted a new set of materials associated with copper/low-k interconnects, and new structures incorporating exotic materials including silicon germanium, SOI substrates and high aspect ratio trenches. The new device architectures and more chemically sophisticated materials have raised new process control and metrology challenges that are not addressed by current measurement technology. To address the challenges we have developed a new infrared metrology tool designed for emerging semiconductor production processes, in a package compatible with modern production and R&D environments. The tool incorporates recent advances in reflectance instrumentation including highly accurate signal processing, optimized reflectometry optics, and model-based calibration and analysis algorithms. To meet the production requirements of the modern automated fab, the measurement hardware has been integrated with a fully automated 300 mm platform incorporating front opening unified pod (FOUP) interfaces, automated pattern recognition and high throughput ultra clean robotics. The tool employs a suite of automated dispersion-model analysis algorithms capable of extracting a variety of layer properties from measured spectra. The new tool provides excellent measurement precision, tool matching, and a platform for deploying many new production and development applications. In this paper we will explore the use of model based infrared analysis as a tool for characterizing novel bottle capacitor structures employed in high density dynamic random access memory (DRAM) chips. We will explore

  1. Graphene integrated circuits: new prospects towards receiver realisation.

    PubMed

    Saeed, Mohamed; Hamed, Ahmed; Wang, Zhenxing; Shaygan, Mehrdad; Neumaier, Daniel; Negra, Renato

    2017-12-21

    This work demonstrates a design approach which enables the fabrication of fully integrated radio frequency (RF) and millimetre-wave frequency direct-conversion graphene receivers by adapting the frontend architecture to exploit the state-of-the-art performance of the recently reported wafer-scale CVD metal-insulator-graphene (MIG) diodes. As a proof-of-concept, we built a fully integrated microwave receiver in the frequency range 2.1-2.7 GHz employing the strong nonlinearity and the high responsivity of MIG diodes to successfully receive and demodulate complex, digitally modulated communication signals at 2.45 GHz. In addition, the fabricated receiver uses zero-biased MIG diodes and consumes zero dc power. With the flexibility to be fabricated on different substrates, the prototype receiver frontend is fabricated on a low-cost, glass substrate utilising a custom-developed MMIC process backend which enables the high performance of passive components. The measured performance of the prototype makes it suitable for Internet-of-Things (IoT) and Radio Frequency Identification (RFID) systems for medical and communication applications.

  2. Cross-scale phenological data integration to benefit resource management and monitoring

    USGS Publications Warehouse

    Richardson, Andrew D.; Weltzin, Jake F.; Morisette, Jeffrey T.

    2017-01-01

    Climate change is presenting new challenges for natural resource managers charged with maintaining sustainable ecosystems and landscapes. Phenology, a branch of science dealing with seasonal natural phenomena (bird migration or plant flowering in response to weather changes, for example), bridges the gap between the biosphere and the climate system. Phenological processes operate across scales that span orders of magnitude—from leaf to globe and from days to seasons—making phenology ideally suited to multiscale, multiplatform data integration and delivery of information at spatial and temporal scales suitable to inform resource management decisions.A workshop report: Workshop held June 2016 to investigate opportunities and challenges facing multi-scale, multi-platform integration of phenological data to support natural resource management decision-making.

  3. Improved delivery of the anticancer agent citral using BSA nanoparticles and polymeric wafers.

    PubMed

    White, Benjamin; Evison, Anna; Dombi, Eszter; Townley, Helen E

    2017-01-01

    Rhabdomyosarcoma (RMS) is the most common soft tissue sarcoma in children, with a 5-year survival rate of between 30 and 65%. Standard treatment involves surgery, radiation treatment, and chemotherapy. However, there is a high recurrence rate, particularly from locoregional spread. We investigated the use of the natural compound citral (3,7-dimethyl-2,6-octadienal), which can be found in a number of plants, but is particularly abundant in lemon grass ( Cymbopogon citratus ) oil, for activity against immortalized RMS cells. Significant cancer cell death was seen at concentrations above 150 μM citral, and mitochondrial morphological changes were seen after incubation with 10 μM citral. However, since citral is a highly volatile molecule, we prepared albumin particles by a desolvation method to encapsulate citral, as a means of stabilization. We then further incorporated the loaded nanoparticles into a biodegradable polyanhydride wafer to generate a slow release system. The wafers were shown to degrade by 50% over the course of 25 days and to release the active compound. We therefore propose the use of the citral-nanoparticle-polymer wafers for implantation into the tumor bed after surgical removal of a sarcoma as a means to control locoregional spread due to any remaining cancerous cells.

  4. Improved delivery of the anticancer agent citral using BSA nanoparticles and polymeric wafers

    PubMed Central

    White, Benjamin; Evison, Anna; Dombi, Eszter; Townley, Helen E

    2017-01-01

    Rhabdomyosarcoma (RMS) is the most common soft tissue sarcoma in children, with a 5-year survival rate of between 30 and 65%. Standard treatment involves surgery, radiation treatment, and chemotherapy. However, there is a high recurrence rate, particularly from locoregional spread. We investigated the use of the natural compound citral (3,7-dimethyl-2,6-octadienal), which can be found in a number of plants, but is particularly abundant in lemon grass (Cymbopogon citratus) oil, for activity against immortalized RMS cells. Significant cancer cell death was seen at concentrations above 150 μM citral, and mitochondrial morphological changes were seen after incubation with 10 μM citral. However, since citral is a highly volatile molecule, we prepared albumin particles by a desolvation method to encapsulate citral, as a means of stabilization. We then further incorporated the loaded nanoparticles into a biodegradable polyanhydride wafer to generate a slow release system. The wafers were shown to degrade by 50% over the course of 25 days and to release the active compound. We therefore propose the use of the citral-nanoparticle-polymer wafers for implantation into the tumor bed after surgical removal of a sarcoma as a means to control locoregional spread due to any remaining cancerous cells. PMID:29263655

  5. Fabrication of SOI structures with buried cavities using Si wafer direct bonding and electrochemical etch-stop

    NASA Astrophysics Data System (ADS)

    Chung, Gwiy-Sang

    2003-10-01

    This paper describes the fabrication of SOI structures with buried cavities using SDB and electrochemical etch-stop. These methods are suitable for thick membrane fabrication with accurate thickness, uniformity, and flatness. After a feed-through hole for supplied voltage and buried cavities was formed on a handle Si wafer with p-type, the handle wafer was bonded to an active Si wafer consisting of a p-type substrate with an n-type epitaxial layer corresponding to membrane thickness. The bonded pair was then thinned until electrochemical etch-stop occurred at the pn junction during electrochemical etchback. By using the SDB SOI structure with buried cavities, active membranes, which have a free standing structure with a dimension of 900×900 μm2, were fabricated. It is confirmed that the fabrication process of the SDB SOI structure with buried cavities is a powerful and versatile technology for new MEMS applications.

  6. Fluorescent 'two-faced' polymer wafers with embedded pyrene-functionalised gelator nanofibres.

    PubMed

    Moffat, Jamie R; Smith, David K

    2011-11-21

    Pyrene-functionalised gelators self-assemble into nano-fibrillar organogels in DMSO/styrene/divinylbenzene mixtures, which when polymerised yield polymer wafers with two distinct faces, only one of which is fluorescent and has embedded gelator nanofibres. This journal is © The Royal Society of Chemistry 2011

  7. A thermal microprobe fabricated with wafer-stage processing

    NASA Astrophysics Data System (ADS)

    Zhang, Yongxia; Zhang, Yanwei; Blaser, Juliana; Sriram, T. S.; Enver, Ahsan; Marcus, R. B.

    1998-05-01

    A thermal microprobe has been designed and built for high resolution temperature sensing. The thermal sensor is a thin-film thermocouple junction at the tip of an atomic force microprobe (AFM) silicon probe needle. Only wafer-stage processing steps are used for the fabrication. For high resolution temperature sensing it is essential that the junction be confined to a short distance at the AFM tip. This confinement is achieved by a controlled photoresist coating process. Experiment prototypes have been made with an Au/Pd junction confined to within 0.5 μm of the tip, with the two metals separated elsewhere by a thin insulating oxide layer. Processing begins with double-polished, n-type, 4 in. diameter, 300-μm-thick silicon wafers. Atomically sharp probe tips are formed by a combination of dry and wet chemical etching, and oxidation sharpening. The metal layers are sputtering deposited and the cantilevers are released by a combination of KOH and dry etching. A resistively heated calibration device was made for temperature calibration of the thermal microprobe over the temperature range 25-110 °C. Over this range the thermal outputs of two microprobes are 4.5 and 5.6 μV/K and is linear. Thermal and topographical images are also obtained from a heated tungsten thin film fuse.

  8. Integrated optic head for sensing a two-dimensional displacement of a grating scale

    NASA Astrophysics Data System (ADS)

    Ura, Shogo; Endoh, Toshiaki; Suhara, Toshiaki; Nishihara, Hiroshi

    1996-11-01

    An integrated optic sensor head was proposed for sensing a two-dimensional displacement of a scale consisting of crossed gratings. Two interferometers, crossing each other, are constructed by the integration of two pairs of linearly focusing grating couplers (LFGC's) and two pairs of photodiodes (PD's) on a Si substrate. Four beams radiated by the LFGC's from the sensor head overlap on the grating scale, and the beams are diffracted by the grating scale and interfere on the PD's. The period of the interference signal variation is just half of the scale grating period. The device was designed and fabricated with a grating scale of 3.2- mu m period, and the sensing principle was experimentally confirmed.

  9. Process for the homoepitaxial growth of single-crystal silicon carbide films on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Powell, J. Anthony (Inventor)

    1993-01-01

    The invention is a method for growing homoepitaxial films of SiC on low tilt angle vicinal (0001) SiC wafers. The invention proposes and teaches a new theoretical model for the homoepitaxial growth of SiC films on (0001) SiC substrates. The inventive method consists of preparing the growth surface of SiC wafers slightly off-axis (from less the 0.1 to 6 deg) from the (0001) plane, subjecting the growth surface to a suitable etch, and then growing the homoepitaxial film using conventional SiC growth techniques.

  10. Single Layer Broadband Anti-Reflective Coatings for Plastic Substrates Produced by Full Wafer and Roll-to-Roll Step-and-Flash Nano-Imprint Lithography

    PubMed Central

    Burghoorn, Marieke; Roosen-Melsen, Dorrit; de Riet, Joris; Sabik, Sami; Vroon, Zeger; Yakimets, Iryna; Buskens, Pascal

    2013-01-01

    Anti-reflective coatings (ARCs) are used to lower the reflection of light on the surface of a substrate. Here, we demonstrate that the two main drawbacks of moth eye-structured ARCs—i.e., the lack of suitable coating materials and a process for large area, high volume applications—can be largely eliminated, paving the way for cost-efficient and large-scale production of durable moth eye-structured ARCs on polymer substrates. We prepared moth eye coatings on polymethylmethacrylate (PMMA) and polycarbonate using wafer-by-wafer step-and-flash nano-imprint lithography (NIL). The reduction in reflection in the visible field achieved with these coatings was 3.5% and 4.0%, respectively. The adhesion of the coating to both substrates was good. The moth eye coating on PMMA demonstrated good performance in three prototypical accelerated ageing tests. The pencil hardness of the moth eye coatings on both substrates was <4B, which is less than required for most applications and needs further optimization. Additionally, we developed a roll-to-roll UV NIL pilot scale process and produced moth eye coatings on polyethylene terephthalate (PET) at line speeds up to two meters per minute. The resulting coatings showed a good replication of the moth eye structures and, consequently, a lowering in reflection of the coated PET of 3.0%. PMID:28788301

  11. Extension of optical lithography by mask-litho integration with computational lithography

    NASA Astrophysics Data System (ADS)

    Takigawa, T.; Gronlund, K.; Wiley, J.

    2010-05-01

    Wafer lithography process windows can be enlarged by using source mask co-optimization (SMO). Recently, SMO including freeform wafer scanner illumination sources has been developed. Freeform sources are generated by a programmable illumination system using a micro-mirror array or by custom Diffractive Optical Elements (DOE). The combination of freeform sources and complex masks generated by SMO show increased wafer lithography process window and reduced MEEF. Full-chip mask optimization using source optimized by SMO can generate complex masks with small variable feature size sub-resolution assist features (SRAF). These complex masks create challenges for accurate mask pattern writing and low false-defect inspection. The accuracy of the small variable-sized mask SRAF patterns is degraded by short range mask process proximity effects. To address the accuracy needed for these complex masks, we developed a highly accurate mask process correction (MPC) capability. It is also difficult to achieve low false-defect inspections of complex masks with conventional mask defect inspection systems. A printability check system, Mask Lithography Manufacturability Check (M-LMC), is developed and integrated with 199-nm high NA inspection system, NPI. M-LMC successfully identifies printable defects from all of the masses of raw defect images collected during the inspection of a complex mask. Long range mask CD uniformity errors are compensated by scanner dose control. A mask CD uniformity error map obtained by mask metrology system is used as input data to the scanner. Using this method, wafer CD uniformity is improved. As reviewed above, mask-litho integration technology with computational lithography is becoming increasingly important.

  12. Effect of void shape in Czochralski-Si wafers on the intensity of laser-scattering

    NASA Astrophysics Data System (ADS)

    Takahashi, J.; Kawakami, K.; Nakai, K.

    2001-06-01

    The shape effect of anisotropic-shaped microvoid defects in Czochralski-grown silicon wafers on the intensity of laser scattering has been investigated. The size and shape of the defects were examined by means of transmission electron microscopy. Octahedral voids in conventional (nitrogen-undoped) wafers showed an almost isotropic scattering property under the incident condition of a p-polarization beam. On the other hand, parallelepiped-plate-shaped voids in nitrogen-doped wafers showed an anisotropic scattering property on both p- and s-polarized components of scattered light, depending strongly on the incident laser direction. The measured results were explained not by scattering calculation using Born approximation but by calculation based on Rayleigh scattering. It was found that the s component is explained by an inclination of a dipole moment induced on a defect from the scattering plane. Furthermore, using numerical electromagnetic analysis it was shown that the asymmetric behavior of the s component on the parallelepiped-plate voids is ascribed to the parallelepiped shape effect. These results suggest that correction of the scattering intensity is necessary to evaluate the size and volume of anisotropic-shaped defects from the scattered intensity.

  13. Brewster's angle silicon wafer terahertz linear polarizer.

    PubMed

    Wojdyla, Antoine; Gallot, Guilhem

    2011-07-18

    We present a new cost-effective terahertz linear polarizer made from a stack of silicon wafers at Brewster's angle, andevaluate its performances. We show that this polarizer is wide-band, has a high extinction ratio (> 6 × 10(3)) and very small insertion losses (< 1%). We provide measurements of the temporal waveforms after linearly polarizing the THz beam and show that there is no distortion of the pulse. We compare its performances with a commercial wire-grid polarizer, and show that the Brewster's angle polarizer can conveniently be used to control the power of a terahertz beam.

  14. Room-temperature wafer bonding of LiNbO3 and SiO2 using a modified surface activated bonding method

    NASA Astrophysics Data System (ADS)

    Takigawa, Ryo; Higurashi, Eiji; Asano, Tanemasa

    2018-06-01

    In this paper, we report room-temperature bonding of LiNbO3 (LN) and SiO2/Si for the realization of a LN on insulator (LNOI)/Si hybrid wafer. We investigate the applicability of a modified surface activated bonding (SAB) method for the direct bonding of LN and a thermally grown SiO2 layer. The modified SAB method using ion beam bombardment demonstrates the room-temperature wafer bonding of LN and SiO2. The bonded wafer was successfully cut into 0.5 × 0.5 mm2 dies without interfacial debonding owing to the applied stress during dicing. In addition, the surface energy of the bonded wafer was estimated to be approximately 1.8 J/m2 using the crack opening method. These results indicate that a strong bond strength can be achieved, which may be sufficient for device applications.

  15. Creating a single twin boundary between two CdTe (111) wafers with controlled rotation angle by wafer bonding

    NASA Astrophysics Data System (ADS)

    Sun, Ce; Lu, Ning; Wang, Jinguo; Lee, Jihyung; Peng, Xin; Klie, Robert F.; Kim, Moon J.

    2013-12-01

    The single twin boundary with crystallographic orientation relationship (1¯1¯1¯)//(111) [01¯1]//[011¯] was created by wafer bonding. Electron diffraction patterns and high-resolution transmission electron microscopy images demonstrated the well control of the rotation angle between the bonded pair. At the twin boundary, one unit of wurtzite structure was found between two zinc-blende matrices. High-angle annular dark-field scanning transmission electron microscopy images showed Cd- and Te-terminated for the two bonded portions, respectively. The I-V curve across the twin boundary showed increasingly nonlinear behavior, indicating a potential barrier at the bonded twin boundary.

  16. Evaluation of Kirkwood-Buff integrals via finite size scaling: a large scale molecular dynamics study

    NASA Astrophysics Data System (ADS)

    Dednam, W.; Botha, A. E.

    2015-01-01

    Solvation of bio-molecules in water is severely affected by the presence of co-solvent within the hydration shell of the solute structure. Furthermore, since solute molecules can range from small molecules, such as methane, to very large protein structures, it is imperative to understand the detailed structure-function relationship on the microscopic level. For example, it is useful know the conformational transitions that occur in protein structures. Although such an understanding can be obtained through large-scale molecular dynamic simulations, it is often the case that such simulations would require excessively large simulation times. In this context, Kirkwood-Buff theory, which connects the microscopic pair-wise molecular distributions to global thermodynamic properties, together with the recently developed technique, called finite size scaling, may provide a better method to reduce system sizes, and hence also the computational times. In this paper, we present molecular dynamics trial simulations of biologically relevant low-concentration solvents, solvated by aqueous co-solvent solutions. In particular we compare two different methods of calculating the relevant Kirkwood-Buff integrals. The first (traditional) method computes running integrals over the radial distribution functions, which must be obtained from large system-size NVT or NpT simulations. The second, newer method, employs finite size scaling to obtain the Kirkwood-Buff integrals directly by counting the particle number fluctuations in small, open sub-volumes embedded within a larger reservoir that can be well approximated by a much smaller simulation cell. In agreement with previous studies, which made a similar comparison for aqueous co-solvent solutions, without the additional solvent, we conclude that the finite size scaling method is also applicable to the present case, since it can produce computationally more efficient results which are equivalent to the more costly radial distribution

  17. A novel setup for wafer curvature measurement at very high heating rates.

    PubMed

    Islam, T; Zechner, J; Bernardoni, M; Nelhiebel, M; Pippan, R

    2017-02-01

    The curvature evolution of a thin film layer stack containing a top Al layer is measured during temperature cycles with very high heating rates. The temperature cycles are generated by means of programmable electrical power pulses applied to miniaturized polysilicon heater systems embedded inside a semiconductor chip and the curvature is measured by a fast wafer curvature measurement setup. Fast temperature cycles with heating duration of 100 ms are created to heat the specimen up to 270 °C providing an average heating rate of 2500 K/s. As a second approach, curvature measurement utilizing laser scanning Doppler vibrometry is also demonstrated which verifies the results obtained from the fast wafer curvature measurement setup. Film stresses calculated from the measured curvature values compare well to literature results, indicating that the new method can be used to measure curvature during fast temperature cycling.

  18. Full wafer size investigation of N+ and P+ co-implanted layers in 4H-SiC

    NASA Astrophysics Data System (ADS)

    Blanqué, S.; Lyonnet, J.; Pérez, R.; Terziyska, P.; Contreras, S.; Godignon, P.; Mestres, N.; Pascual, J.; Camassel, J.

    2005-03-01

    We report a full wafer size investigation of the homogeneity of electrical properties in the case of co-implanted nitrogen and phosphorus ions in 4H-SiC semi-insulating wafers. To match standard industrial requirements, implantation was done at room temperature. To achieve a detailed electrical knowledge, we worked on a 35 mm wafer on which 77 different reticules have been processed. Every reticule includes one Hall cross, one Van der Pauw test structure and different TLM patterns. Hall measurements have been made on all 77 different reticules, using an Accent HL5500 Hall System® from BioRad fitted with an home-made support to collect data from room temperature down to about 150 K. At room temperature, we find that the sheet carrier concentration is only 1/4 of the total implanted dose while the average mobility is 80.6 cm2/Vs. The standard deviation is, typically, 1.5 cm2/Vs.

  19. Wafer Scale Fabrication of Dense and High Aspect Ratio Sub-50 nm Nanopillars from Phase Separation of Cross-Linkable Polysiloxane/Polystyrene Blend.

    PubMed

    Li, Yang; Hao, Yuli; Huang, Chunyu; Chen, Xingyao; Chen, Xinyu; Cui, Yushuang; Yuan, Changsheng; Qiu, Kai; Ge, Haixiong; Chen, Yanfeng

    2017-04-19

    We demonstrated a simple and effective approach to fabricate dense and high aspect ratio sub-50 nm pillars based on phase separation of a polymer blend composed of a cross-linkable polysiloxane and polystyrene (PS). In order to obtain the phase-separated domains with nanoscale size, a liquid prepolymer of cross-linkable polysiloxane was employed as one moiety for increasing the miscibility of the polymer blend. After phase separation via spin-coating, the dispersed domains of liquid polysiloxane with sub-50 nm size could be solidified by UV exposure. The solidified polysiloxane domains took the role of etching mask for formation of high aspect ratio nanopillars by O 2 reactive ion etching (RIE). The aspect ratio of the nanopillars could be further amplified by introduction of a polymer transfer layer underneath the polymer blend film. The effects of spin speeds, the weight ratio of the polysiloxane/PS blend, and the concentration of polysiloxane/PS blend in toluene on the characters of the nanopillars were investigated. The gold-coated nanopillar arrays exhibited a high Raman scattering enhancement factor in the range of 10 8 -10 9 with high uniformity across over the wafer scale sample. A superhydrophobic surface could be realized by coating a self-assembled monolayers (SAM) of fluoroalkyltrichlorosilane on the nanopillar arrays. Sub-50 nm silicon nanowires (SiNWs) with high aspect ratio of about 1000 were achieved by using the nanopillars as etching mask through a metal-assisted chemical etching process. They showed an ultralow reflectance of approximately 0.1% for wavelengths ranging from 200 to 800 nm.

  20. "Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

    NASA Astrophysics Data System (ADS)

    Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

    2013-04-01

    During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.