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Sample records for wafer scale liga

  1. The influence of wafer elasticity on acoustic waves during LIGA development.

    SciTech Connect

    Ting, Aili

    2003-12-01

    During acoustically stimulated LIGA development, a wafer receives sound waves from both sides at a wide variety of incidence angles that vary in time depending on the orientation of the wafer relative to the multiple transducers that are typically actuated in a periodic sequence. It is important to understand the influence of these variables on the transmission of energy through the wafer as well as the induced motion of the wafer itself because these processes impact the induced acoustic streaming of the fluid within features, the mechanism presently thought responsible for enhanced development of LIGA features. In the present work, the impact of wafer elasticity on LIGA development is investigated. Transmission waves, wafer bending waves, and the related concepts such as critical bending frequency, mechanical impedance, coincidence, and resonance, are discussed. Supercritical-frequency incident waves induce supersonic bending waves in the wafer. Incident wave energy is channeled into three components, transmitted, reflected and energy deposited to the wafer, depending on the wafer material, thickness and wave incidence angle. Results show at normal incidence for a 1-mm PMMA wafer, about 47% of the wave energy is deposited in the wafer. The wafer gains almost half of the incident energy, a result that agrees well with the Bankert et a1 measurements. In LIGA development, transmitted waves may sometimes produce strong acoustic motion of the developer on the wafer backside, especially for the so-called coincidence case in which almost all incident wave energy transfers to the backside. Wafer bending waves cause wafer oscillation at high frequency, promoting the development process, but features shaking may weaken their attachments to the substrate. Resonance is not likely for the entire wafer, but may occur in short and wide wafer feature columns, which are least likely to break away from the substrate, perhaps resulting in good agitation of the fluid in adjacent

  2. Gallium Arsenide wafer scale integration

    NASA Astrophysics Data System (ADS)

    McDonald, J. F.; Taylor, G.; Steinvorth, R.; Donlan, B.; Bergendahl, A. S.

    1985-08-01

    Gallium Arsenide (GaAs) digital MESFET technology has recently begun to appear in the semiconductor marketplace. The initial commercial offerings are at the small to medium scale integration levels. The high speed of these parts would seem to be very attractive for designers of high performance signal processing equipment. Persistent yield problems, however, have prevented the appearance of large scale integrated circuits. As a result, intrapackage and interpackage signal propagation problems such as coupling, parasitics and delay are likely to negate much of the benefits of the fast MESFET logic devices for large systems constructed with such small scale building blocks. An early packaging concept, Wafer Scale Integration (WSI), which could possibly be used to address some of these limitations is reexamined.

  3. Design automation for wafer scale integration

    SciTech Connect

    Donlan, B.J.

    1986-01-01

    Wafer scale integration (WSI) is a technique for implementing large digital systems on a single wafer. This thesis describes a system of design automation tools developed to aid in the implementation of wafer scale integrated systems. An overview of wafer scale integration is given with fabrication details and yield considerations discussed. The Wafer architectural Design Language (WDL) used to describe and specify a system architecture to the development system is introduced along with a compiler that translates the high level WDL description into net lists and other internal data bases. Interactive placement tools used to map the system architecture onto the functional die sites on a wafer are described. A very fast line probe router was developed to perform the custom wafer level routing need to personalize each wafer. Router data structures, algorithms, techniques, and results are discussed in detail. Sample wafer scale architectures and the result of their WSI implementations are shown. Also presented is the Wafer Transmission Module (WTM) a packaging technology related to wafer scale integration.

  4. Wafer-scale graphene integrated circuit.

    PubMed

    Lin, Yu-Ming; Valdes-Garcia, Alberto; Han, Shu-Jen; Farmer, Damon B; Meric, Inanc; Sun, Yanning; Wu, Yanqing; Dimitrakopoulos, Christos; Grill, Alfred; Avouris, Phaedon; Jenkins, Keith A

    2011-06-10

    A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

  5. Hybrid silicon wafer-scale packaging technology

    SciTech Connect

    Johnson, R.W.

    1987-01-01

    Wafer-scale integration (WSI) approaches the packaging problem by attempting to fabricate the system monolithically utilizing semiconductor techniques. However, WSI has been plagued by yield problems and the need for redundancy. This study demonstrates the feasibility of a novel hybrid technique that uses pretested integrated circuits mounted into holes etched in a master wafer. The chips are interconnected with planar, thin-film metallization. This approach achieves near WSI density, while allowing the use of separately fabricated and tested devices. Test wafers with three monolithic chips and one chip mounted in a hole were fabricated as proof of concept. The key processes developed include fabrication of metallized and patterned wafers with etched holes, mounting of die in etched holes with planar topside topology, and deposition and patterning of interlevel dielectric and metal links. Selection of suitable materials for die attach and for use as an interlevel dielectric was critical. Wafers were thermally cycled to evaluate the compatibility of the materials and the process. No cracks or chip movement were observed after 50 cycles from -25 to +85/sup 0/C.

  6. Silicon hybrid wafer scale integration interconnect evaluation

    NASA Astrophysics Data System (ADS)

    Lyke, James C.

    1989-12-01

    The electrical characteristics of interconnections that have been proposed for use in silicon hybrid wafer scale integration (WSI) approaches were investigated. The study was based on a set of 5 inch test wafers, containing various interconnection structures previously designed at AFIT. Two test wafers used a special polyimide dielectric, while a third was composed of a benzocyclobutene (BCB). The investigated structures represented 10 cm length aluminum, coupled, stripline-like transmission lines. The metrics used included continuity measurements, ac measurement of the characteristic impedance and coupling levels, and pulsed-signal response measurements. Continuity results indicated transmission and leakage failures in all wafers, although the failure mechanisms were sometimes wafer-specific. The characteristic impedance measurement technique was flawed, but revealed interesting information concerning the driving-point impedances of the structures. Most coupled structures manifested coupling responses which were consistent in shape with theoretical estimates, but higher in magnitude by 10 to 20 dB. All structures revealed coupling levels lower than -25 dB. Despite correlation difficulties, the results implied that transmission line behavior is manifested in WSIC interconnections.

  7. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  8. On the feasibility of through-wafer optical interconnects for hybrid wafer-scale-integrated architectures

    NASA Astrophysics Data System (ADS)

    Hornak, L. A.; Tewksbury, S. K.

    1987-07-01

    A method, compatible with VLSI processing, is described which makes it possible to fabricate vertical through-wafer optical interconnects for hybrid multiwafer wafer-scale-integrated (WSI) architectures. Using optical devices operating at wavelengths beyond the Si absorption cutoff, a low-loss through-the-wafer propagation between WSI circuit planes can be achieved over the distances of about 1 mm with the interstitial Si wafers as part of the interconnect 'free-space' transmission medium. VLSI-process-compatible SiO2 Fresnel phase-reversal zone plate arrays were fabricated. Initial results show that a 400-percent improvement in optical power coupling through the wafer was obtained.

  9. Future trends in wafer scale integration

    SciTech Connect

    Carlson, R.O.; Neugebauer, C.A.

    1986-12-01

    The dramatic increase in the functional density of VLSI has been achieved without greatly increasing the chip size. In wafer scale integration, the area of an entire wafer is made available to increase the functional density still further. However, the requirement for fault tolerance, additional levels of metallization, excess power dissipation, process conservatism to achieve finite yield, and nonoptimum nature of the AI/SiO/sub 2/ transmission line for cross-wafer communication have made WSI noncompetitive with state-of-the-art VLSI and dense multichip hybrid packaging approaches, at least so far. On the other hand, the potential benefits of WSI are great. Chief among them is the greatly increased expected reliability, which is partly due to an all-monolithic system and partly because of the hope that fault tolerance, which is an absolute requirement for WSI fabrication, can be extended to failure tolerance, and thus the ability to reconfigure during systems operation, and perhaps even transparent to it. Pipeline- or bus-oriented logic structures were found to be the most promising for WSI implementation.

  10. Infrared spectroscopy of wafer-scale graphene.

    PubMed

    Yan, Hugen; Xia, Fengnian; Zhu, Wenjuan; Freitag, Marcus; Dimitrakopoulos, Christos; Bol, Ageeth A; Tulevski, George; Avouris, Phaedon

    2011-12-27

    We report spectroscopy results from the mid- to far-infrared on wafer-scale graphene, grown either epitaxially on silicon carbide or by chemical vapor deposition. The free carrier absorption (Drude peak) is simultaneously obtained with the universal optical conductivity (due to interband transitions) and the wavelength at which Pauli blocking occurs due to band filling. From these, the graphene layer number, doping level, sheet resistivity, carrier mobility, and scattering rate can be inferred. The mid-IR absorption of epitaxial two-layer graphene shows a less pronounced peak at 0.37 ± 0.02 eV compared to that in exfoliated bilayer graphene. In heavily chemically doped single-layer graphene, a record high transmission reduction due to free carriers approaching 40% at 250 μm (40 cm(-1)) is measured in this atomically thin material, supporting the great potential of graphene in far-infrared and terahertz optoelectronics.

  11. The parylene-aluminum multilayer interconnection system for wafer scale integration and wafer scale hybrid packaging

    NASA Astrophysics Data System (ADS)

    Majid, N.; Dabral, S.; McDonald, J. F.

    1989-03-01

    Polyimides have been considered as interlayer dielectrics for wafer scale integration (WSI) and wafer scale hybrid packaging (WSHP). However, high temperature curing steps for polyimide lead to large stresses in polyimide films. This is due to differing thermal expansion coefficients of the metal conductor, insulator and substrate materials causing yield and reliability problems. Polyimides also require the use of solvents, and tend to outgas during subsequent processing. They tend to absorb moisture with resulting degradation of dielectric constants. Also, the spin on method used to apply and planarize polyimide layers exhibits nonuniformity of thickness on large wafers. In this paper we examine parylene (Poly-p-xylylene) and some of its derivatives as possible interlayer dielectrics due to some of their attractive features. Parylene has a low dielectric constant. It can be vapor deposited at low temperatures and in vacuum. It is also highly resistant to corrosion and is a clear, transparent material with possible use for optical interconnections. This paper studies the reactive ion etching properties for polyimides and parylenes in an oxygen containing plasma under identical conditions. The etching rates of the parylenes and polyimides have been compared. The surface properties of these polymers are examined. Further, the film growth properties of aluminum deposited on the etched surfaces using the ionized cluster beam are investigated.

  12. Parallel Assembly of LIGA Components

    SciTech Connect

    Christenson, T.R.; Feddema, J.T.

    1999-03-04

    In this paper, a prototype robotic workcell for the parallel assembly of LIGA components is described. A Cartesian robot is used to press 386 and 485 micron diameter pins into a LIGA substrate and then place a 3-inch diameter wafer with LIGA gears onto the pins. Upward and downward looking microscopes are used to locate holes in the LIGA substrate, pins to be pressed in the holes, and gears to be placed on the pins. This vision system can locate parts within 3 microns, while the Cartesian manipulator can place the parts within 0.4 microns.

  13. Wafer-scale synthesis and transfer of graphene films.

    PubMed

    Lee, Youngbin; Bae, Sukang; Jang, Houk; Jang, Sukjae; Zhu, Shou-En; Sim, Sung Hyun; Song, Young Il; Hong, Byung Hee; Ahn, Jong-Hyun

    2010-02-10

    We developed means to produce wafer scale, high-quality graphene films as large as 3 in. wafer size on Ni and Cu films under ambient pressure and transfer them onto arbitrary substrates through instantaneous etching of metal layers. We also demonstrated the applications of the large-area graphene films for the batch fabrication of field-effect transistor (FET) arrays and stretchable strain gauges showing extraordinary performances. Transistors showed the hole and electron mobilities of the device of 1100 +/- 70 and 550 +/- 50 cm(2)/(V s) at drain bias of -0.75 V, respectively. The piezo-resistance gauge factor of strain sensor was approximately 6.1. These methods represent a significant step toward the realization of graphene devices in wafer scale as well as application in optoelectronics, flexible and stretchable electronics.

  14. IGBT scaling principle toward CMOS compatible wafer processes

    NASA Astrophysics Data System (ADS)

    Tanaka, Masahiro; Omura, Ichiro

    2013-02-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in the CMOS factory is difficult. In this paper, we show the scaling principle toward shallower structure and better performance. The principle is theoretically explained by our previously proposed "Structure Oriented" analytical model. The principle represents a possibility of technology direction and roadmap for future IGBT for improving the device performance consistent with lower cost and high volume productivity with CMOS compatible large diameter wafer technologies.

  15. Radiation-Hardened Wafer Scale Integration

    DTIC Science & Technology

    1989-10-25

    tim technology. A system built with conventional ICs and packaging would be very much larger. The required radiation dose rate and single - event upset ...assuming a 10:1 scaling at the analog to digital converters . (See footnote in Section 2.5.1.) This scale factor is used, for example, in ground-based...transistors which resulted in 5 different circuits . Static CMOS circuitry was used for radiation resistance. All 5 circuits were designed and built

  16. Overlay distortions in wafer-scale integration lithography

    NASA Astrophysics Data System (ADS)

    Flack, Warren W.

    1993-08-01

    Wafer scale integration (WSI) lithography is the technique used to fabricate ultra large scale integration (ULSI) integrated circuits significantly greater in size than current products. Applications for WSI lithography include large solid state detector arrays, large area liquid crystal displays, high speed mainframe supercomputers, and large random access memories. The lithography technology required to manufacture these devices is particularly challenging, requiring stringent control of both submicron critical dimensions and accurate alignment of level to level device patterns over large chip areas.

  17. Wafer-scale aluminum plasmonics for fluorescence based biodetection

    NASA Astrophysics Data System (ADS)

    Farhang, Arash; George, Matthew C.; Williamson, Brent; Black, Mike; Wangensteen, Ted; Fraser, James; Petrova, Rumyana; Prestgard, Kent

    2015-08-01

    Moxtek has leveraged existing capabilities in wafer-scale patterning of sub-wavelength wire grid polarizers into the fabrication of 1D and 2D periodic aluminum plasmonic structures. This work will discuss progress in 200 mm diameter wafer-scale fabrication, with detailed emphasis within the realm of microarray based fluorescence detection. Aluminum nanohole arrays in a hexagonal lattice are first numerically investigated. The nanohole array geometry and periodicity are specifically tuned to coincide both with the excitation of the fluorophore Cy3, and to provide a high field enhancement within the nanoholes where labeled biomolecules are captured. This is accomplished through numerical modelling, nanofabrication, SEM imaging, and optical characterization. A 200mm diameter wafer, patterned with the optically optimized nanohole array, is cut into standard 1x3 inch microscope slide pieces and then subsequently printed with various antigens at 9 different concentrations. A sandwich bioassay is then carried out, using the corresponding conjugate antibodies in order to demonstrate specificity. The nanohole array exhibit a 3-4 times total fluorescence enhancement of Cy3, when compared to a leading commercial microarray glass slide.

  18. Wafer-scale plasmonic and photonic crystal sensors

    NASA Astrophysics Data System (ADS)

    George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

    2015-08-01

    200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

  19. Liga developer apparatus system

    DOEpatents

    Boehme, Dale R.; Bankert, Michelle A.; Christenson, Todd R.

    2003-01-01

    A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

  20. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture

  1. Video-rate fuzzy Golay processor for wafer scale integration

    SciTech Connect

    Steinvorth, R.H.

    1987-01-01

    The fuzzy Golay transformation is a novel approach for gray-level image processing. Fuzzy-set theory is used to modify the binary image processing techniques developed by M. J. Golay to permit direct gray-level image processing without thresholding. The comparison between gray-level pixels is accomplished with the Pixel Closeness Value (PCV) while comparison between gray-level neighborhoods uses the Neighborhood Closeness Value (NCV). Feature extraction is done by comparing the gray-level image neighborhood to a subset of the fourteen Golay neighborhoods using the NCV function. The Fuzzy Golay Processor (FGP) is an architecture designed to implement the fuzzy Golay transformation. The design of the FGP has been optimized to permit a successful implementation in Wafer Scale Integration (WSI). A system containing four FGPs is capable of performing thirty fuzzy Golay transformations per second on a 256 by 256 eight-bit pixel image. Such a system could fit on a four-inch wafer with enough redundant dies to allow a 30% die yield. The required dies are four Input-Output Modules (IOM) and 56 Neighborhood Evaluation Modules (NEM).

  2. Wafer-scale boundary value integrated circuit architecture

    SciTech Connect

    Delgado-Frias, J.G.

    1986-01-01

    Wafer scale integration (WSI) technology offers the potential for improving speed and reliability of a large integrated circuit system. An architecture is presented for a boundary value integrated circuit engine which lends itself to implementation in WSI. The philosophy underpinning this architecture includes local communication, cell regularity, and fault tolerance. The research described here proposes, investigates, and simulates this computer architecture and its flaw avoidance schemes for a WSI implementation. Boundary value differential equation computations are utilized in a number of scientific and engineering applications. A boundary value machine is ideally suited for solutions of finite difference and finite element problems with specified boundary values. The architecture is a 2-D array of computational cells. Each basic cell has four bit serial processing elements (PEs) and a local memory. Most communications is limited to transfer between adjacent PEs to reduce complexity, avoid long delays, and localize the effects of silicon flaws. Memory access time is kept short by restricting memory service to PEs in the same cell. I/O operation is performed by means of a row multiple single line I/O bus, which allows fast, reliable and independent data transference. WSI yield losses are due to gross defects and random defects. Gross defects which affect large portions of the wafer are usually fatal for any WSI implementation. Overcoming random defects which cover either a small area or points is achieved by defect avoidance schemes that are developed for this architecture. Those schemes are provided at array, cell, and communication level. Capabilities and limitations of the proposed WSI architecture can be observed through the simulations. Speed degradation of the array and the PE due to silicon defects is observed by means of simulation. Also, module and bus utilization are computed and presented.

  3. Wafer-Scale Microwire Transistor Array Fabricated via Evaporative Assembly.

    PubMed

    Park, Jae Hoon; Sun, Qijun; Choi, Yongsuk; Lee, Seungwoo; Lee, Dong Yun; Kim, Yong Hoon; Cho, Jeong Ho

    2016-06-22

    One-dimensional (1D) nano/microwires have attracted significant attention as promising building blocks for various electronic and optical device applications. The integration of these elements into functional device networks with controlled alignment and density presents a significant challenge for practical device applications. Here, we demonstrated the fabrication of wafer-scale microwire field-effect transistor (FET) arrays based on well-aligned inorganic semiconductor microwires (indium-gallium-zinc-oxide (IGZO)) and organic polymeric insulator microwires fabricated via a simple and large-area evaporative assembly technique. This microwire fabrication method offers a facile approach to precisely manipulating the channel dimensions of the FETs. The resulting solution-processed monolithic IGZO microwire FETs exhibited a maximum electron mobility of 1.02 cm(2) V(-1) s(-1) and an on/off current ratio of 1 × 10(6). The appropriate choice of the polymeric microwires used to define the channel lengths enabled fine control over the threshold voltages of the devices, which were employed to fabricate high-performance depletion-load inverters. Low-voltage-operated microwire FETs were successfully fabricated on a plastic substrate using a high-capacitance ion gel gate dielectric. The microwire fabrication technique involving evaporative assembly provided a facile, effective, and reliable method for preparing flexible large-area electronics.

  4. Wafer-scale arrays of epitaxial ferroelectric nanodiscs and nanorings

    NASA Astrophysics Data System (ADS)

    Han, Hee; Ji, Ran; Park, Yong Jun; Lee, Sung Kyun; LeRhun, Gwenael; Alexe, Marin; Nielsch, Kornelius; Hesse, Dietrich; Gösele, Ulrich; Baik, Sunggi

    2009-01-01

    Wafer-scale arrays of well-ordered Pb(Zr0.2Ti0.8)O3 nanodiscs and nanorings were fabricated on the entire area (10 mm × 10 mm) of the SrRuO3 bottom electrode on an SrTiO3 single-crystal substrate using the laser interference lithography (LIL) process combined with pulsed laser deposition. The shape and size of the nanostructures were controlled by the amount of PZT deposited through the patterned holes and the temperature of the post-crystallization steps. X-ray diffraction and transmission electron microscopy confirmed that (001)-oriented PZT nanostructures were grown epitaxially on the SrRuO3(001) bottom electrode layer covering the (001)-oriented single-crystal substrate. The domain structures of PZT nano-islands were characterized by reciprocal space mapping using synchrotron x-ray radiation. Ferroelectric properties of each PZT nanostructure were characterized by scanning force microscopy in the piezoresponse mode.

  5. Designing defect spins for wafer-scale quantum technologies

    SciTech Connect

    Koehl, William F.; Seo, Hosung; Galli, Giulia; Awschalom, David D.

    2015-11-27

    The past decade has seen remarkable progress in the development of the nitrogen-vacancy (NV) defect center in diamond, which is one of the leading candidates for quantum information technologies. The success of the NV center as a solid-state qubit has stimulated an active search for similar defect spins in other technologically important and mature semiconductors, such as silicon carbide. If successfully combined with the advanced microfabrication techniques available to such materials, coherent quantum control of defect spins could potentially lead to semiconductor-based, wafer-scale quantum technologies that make use of exotic quantum mechanical phenomena like entanglement. In this article, we describe the robust spin property of the NV center and the current status of NV center research for quantum information technologies. We then outline first-principles computational modeling techniques based on density functional theory to efficiently search for potential spin defects in nondiamond hosts suitable for quantum information applications. The combination of computational modeling and experimentation has proven invaluable in this area, and we describe the successful interplay between theory and experiment achieved with the divacancy spin qubit in silicon carbide.

  6. Silicon hybrid Wafer Scale Integration (WSI) used to fabricate a Hilbert transform integrated circuit module

    NASA Astrophysics Data System (ADS)

    Gaughan, Daniel J.

    1990-12-01

    This research was performed in order to develop a superior processing schedule for fabricating wafer-scale integration (WSI) circuit modules. This technology allows the design of circuitry that spans the entire surface of a silicon substrate wafer. The circuit element employed in this research was the Hilbert transform, a digital phase-shifting circuit. The transform was incorporated into a three integrated circuit (IC) die package that consisted of a mechanically supportive silicon wafer, three IC die, and a planarizing silicon wafer. The die were epoxied into this wafer using a Teflon block as a flat, and the combination was epoxied onto the substrate wafer, forming the IC module. The original design goals of this research were to keep the IC die and wafer planar and to electrically characterize of the module's interconnections. The first goal was met; the resultant process uses a low temperature (50 C) cure to achieve die-to-wafer planarity of within 5 microns. The second was not met due to the inability to pattern the chosen photosensitive dielectric material. Recommendations for further research included the need to use a stable non-stick surface as a epoxy cure fixture and the need to investigate the photopatternable dielectric material.

  7. 100-GHz Transistors from Wafer-Scale Epitaxial Graphene

    NASA Astrophysics Data System (ADS)

    Lin, Y.-M.; Dimitrakopoulos, C.; Jenkins, K. A.; Farmer, D. B.; Chiu, H.-Y.; Grill, A.; Avouris, Ph.

    2010-02-01

    The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon transistors of the same gate length.

  8. Bio/chemical microsystem designed for wafer scale testing

    NASA Astrophysics Data System (ADS)

    Jorgensen, Anders M.; Mogensen, Klaus B.; Rong, Weimin; Telleman, Pieter; Kutter, Joerg P.

    2001-04-01

    We have designed a bio/chemical microsystem for online monitoring of glucose concentrations during fermentation. The system contains several passive microfluidic components including an enzyme reactor, a flow lamination part and a detector. Detection is based on the reaction of hydrogen peroxide, that is produced from glucose in an enzyme reactor, with luminol. This chemiluminescent reaction generates light that is detected by an integrated back-side contacted photodiode array. Various tests during fabrication are outlined with the emphasis on microwave detected photo conductance decay. The presented microsystem has both fluidic and electrical connection points accessible from the backside. This allows simultaneous testing of both fluidic and electrical parts before dicing the wafer.

  9. Silicon-hybrid wafer-scale integration achieved with multilevel aluminum interconnects

    NASA Astrophysics Data System (ADS)

    Takahashi, Grant L.; Kolesar, Edward S.

    A silicon-hybrid wafer-scale integration (WSI) technique has been developed to interconnect complementary metal-oxide semiconductor (CMOS) circuits. Electrical performance tests and processing diagnostics reveal that the interconnect design is very promising. The wafer-scale integrated circuit was fabricated by mounting two CMOS integrated circuit dies into etched wells and then planarizing the surface of the silicon wafer substrate. Next the wafer's surface was coated with a photosensitive polyimide and patterned with vias to accommodate the interconnecting conductors. The CMOS dies were two-bit shift registers and were electrically interconnected with aluminum conductors using conventional silicon processing techniques. A diagnostic evaluation was accomplished to determine the electrical continuity of the conductors and via contacts. When compared to a complementary wire-bonded interconnect scheme, the silicon WSI technology was found to be the superior performer at 1-MHz operating frequencies. Discontinuous interconnects were evaluated, and the failures were identified to occur at the severe topographical steps encountered on the substrate wafer's surface.

  10. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  11. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-07

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  12. SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

    NASA Astrophysics Data System (ADS)

    Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

    2016-10-01

    Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and

  13. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates

    NASA Astrophysics Data System (ADS)

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-01

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes.

  14. Wafer-scale integration of sacrificial nanofluidic chips for detecting and manipulating single DNA molecules

    PubMed Central

    Wang, Chao; Nam, Sung-Wook; Cotte, John M.; Jahnes, Christopher V.; Colgan, Evan G.; Bruce, Robert L.; Brink, Markus; Lofaro, Michael F.; Patel, Jyotica V.; Gignac, Lynne M.; Joseph, Eric A.; Rao, Satyavolu Papa; Stolovitzky, Gustavo; Polonsky, Stanislav; Lin, Qinghuang

    2017-01-01

    Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching. Using single-molecule fluorescence imaging, we demonstrate these sacrificial nanofluidic chips can function to controllably and completely stretch lambda DNA in a two-dimensional nanofluidic network comprising channels and pillars. The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels, reliable fluidic sealing and low thermal budget make our strategy a potentially universal approach to integrating functional planar nanofluidic systems with logic circuits for lab-on-a-chip applications. PMID:28112157

  15. Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

    NASA Astrophysics Data System (ADS)

    Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

    2017-02-01

    A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (~1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

  16. Wafer-scale integration of sacrificial nanofluidic chips for detecting and manipulating single DNA molecules

    NASA Astrophysics Data System (ADS)

    Wang, Chao; Nam, Sung-Wook; Cotte, John M.; Jahnes, Christopher V.; Colgan, Evan G.; Bruce, Robert L.; Brink, Markus; Lofaro, Michael F.; Patel, Jyotica V.; Gignac, Lynne M.; Joseph, Eric A.; Rao, Satyavolu Papa; Stolovitzky, Gustavo; Polonsky, Stanislav; Lin, Qinghuang

    2017-01-01

    Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching. Using single-molecule fluorescence imaging, we demonstrate these sacrificial nanofluidic chips can function to controllably and completely stretch lambda DNA in a two-dimensional nanofluidic network comprising channels and pillars. The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels, reliable fluidic sealing and low thermal budget make our strategy a potentially universal approach to integrating functional planar nanofluidic systems with logic circuits for lab-on-a-chip applications.

  17. Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

    PubMed Central

    Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kavehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

    2017-01-01

    A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes. PMID:28211538

  18. Wafer-scale growth of VO2 thin films using a combinatorial approach

    PubMed Central

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

    2015-01-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that ‘electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

  19. Wafer-scale integration of sacrificial nanofluidic chips for detecting and manipulating single DNA molecules.

    PubMed

    Wang, Chao; Nam, Sung-Wook; Cotte, John M; Jahnes, Christopher V; Colgan, Evan G; Bruce, Robert L; Brink, Markus; Lofaro, Michael F; Patel, Jyotica V; Gignac, Lynne M; Joseph, Eric A; Rao, Satyavolu Papa; Stolovitzky, Gustavo; Polonsky, Stanislav; Lin, Qinghuang

    2017-01-23

    Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching. Using single-molecule fluorescence imaging, we demonstrate these sacrificial nanofluidic chips can function to controllably and completely stretch lambda DNA in a two-dimensional nanofluidic network comprising channels and pillars. The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels, reliable fluidic sealing and low thermal budget make our strategy a potentially universal approach to integrating functional planar nanofluidic systems with logic circuits for lab-on-a-chip applications.

  20. Fabrication of wafer-scale nanopatterned sapphire substrate through phase separation lithography

    NASA Astrophysics Data System (ADS)

    Guo, Xu; Ni, Mengyang; Zhuang, Zhe; Dai, Jiangping; Wu, Feixiang; Cui, Yushuang; Yuan, Changsheng; Ge, Haixiong; Chen, Yanfeng

    2016-04-01

    A phase separation lithography (PSL) based on polymer blend provides an extremely simple, low-cost, and high-throughput way to fabricate wafer-scale disordered nanopatterns. This method was introduced to fabricate nanopatterned sapphire substrates (NPSSs) for GaN-based light-emitting diodes (LEDs). The PSL process only involved in spin-coating of polystyrene (PS)/polyethylene glycol (PEG) polymer blend on sapphire substrate and followed by a development with deionized water to remove PEG moiety. The PS nanoporous network was facilely obtained, and the structural parameters could be effectively tuned by controlling the PS/PEG weight ratio of the spin-coating solution. 2-in. wafer-scale NPSSs were conveniently achieved through the PS nanoporous network in combination with traditional nanofabrication methods, such as O2 reactive ion etching (RIE), e-beam evaporation deposition, liftoff, and chlorine-based RIE. In order to investigate the performance of such NPSSs, typical blue LEDs with emission wavelengths of ~450 nm were grown on the NPSS and a flat sapphire substrate (FSS) by metal-organic chemical vapor deposition, respectively. The integral photoluminescence (PL) intensity of the NPSS LED was enhanced by 32.3 % compared to that of the FSS-LED. The low relative standard deviation of 4.7 % for PL mappings of NPSS LED indicated the high uniformity of PL data across the whole 2-in. wafer. Extremely simple, low cost, and high throughput of the process and the ability to fabricate at the wafer scale make PSL a potential method for production of nanopatterned sapphire substrates.

  1. Silicon hybrid wafer scale integration interconnect performance evaluation at RF frequencies

    NASA Astrophysics Data System (ADS)

    Lyke, James C., Jr.; Kolesar, Edward S., Jr.

    The RF electrical characteristics of hybrid wafer scale integration (WSI) interconnections on silicon-polyimide-aluminum and silicon-benzocyclobutene-aluminum substrates have been evaluated. The silicon wafer substrates were five in in diameter, and each contained an identical set of 200 photolithographically patterned dielectric and aluminum interconnect test structures. The aluminum conductors were 2.5-microns thick, and half of the test structure conductors were 10-microns wide, while the remainder were 25-microns wide. Measurements between 5 kHz and 220 MHz confirmed the expected transmission line behavior manifested by the longer interconnections. The coupling levels in the 400 line/cm density structures are low, but nevertheless significant, especially when digital logic applications requiring low-noise margins are anticipated. More important were the attenuation effects manifested by the longer aluminum interconnections when they were combined with low-impedence matched terminations.

  2. Sacrificial layer for the fabrication of electroformed cantilevered LIGA microparts

    NASA Astrophysics Data System (ADS)

    Morales, Alfredo M.; Aigeldinger, Georg; Bankert, Michelle A.; Domeier, Linda A.; Hachman, John T.; Hauck, Cheryl; Keifer, Patrick N.; Krafcik, Karen L.; McLean, Dorrance E.; Yang, Peter C.

    2003-01-01

    The use of silver filled PMMA as a sacrificial layer for the fabrication of multilevel LIGA microparts is presented. In this technique, a bottom level of standard electroformed LIGA parts is first produced on a metallized substrate such as a silicon wafer. A methyl methacrylate formulation mixed with silver particles is then cast and polymerized around the bottom level of metal parts to produce a conducting sacrificial layer. A second level of PMMA x-ray resist is adhered to the bottom level of metal parts and conducting PMMA and patterned to form another level of electroformed features. This presentation will discuss some the requirements for the successful fabrication of multilevel, cantilevered LIGA microparts. It will be shown that by using a silver filled PMMA, a sacrificial layer can be quickly applied around LIGA components; cantilevered microparts can be electroformed; and the final parts can be quickly released by dissolving the sacrificial layer in acetone.

  3. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    PubMed

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

  4. A Method to Pattern Silver Nanowires Directly on Wafer-Scale PDMS Substrate and Its Applications.

    PubMed

    Chou, Namsun; Kim, Youngseok; Kim, Sohee

    2016-03-09

    This study describes a fabrication method of microsized AgNW patterns based on poly dimethylsiloxane (PDMS) substrate using a poly(p-xylylene) (parylene) stencil technique. Various patterns of AgNW conductive sheets were created on the wafer scale area in the forms of straight and serpentine lines, texts, and symbols, which dimensions ranged from a few tens of micrometers to hundreds of micrometers. We demonstrated the electrical performance of straight line and serpentine line patterned AgNW electrodes when subjected to mechanical strains. The gauge factor and stretchability ranged from 0.5 to 55.2 at 2% uniaxial strain and from 4.7 to 55.7%, respectively, depending on the shapes and structures of the AgNW electrodes. Using the developed AgNW patterning technique, we fabricated strain sensors to detect small body signals epidermally such as hand motion, eye blink and heart rate. Also, tactile sensors were fabricated and exhibited the sensitivity of 3.91 MPa(-1) in the pressure range lower than 50 kPa, and 0.28 MPa(-1) in the pressure range greater than 50 kPa up to 1.3 MPa. From these results, we concluded that the proposed technique enables the fabrication of reliable AgNW patterns on wafer-scale PDMS substrate and the potential applications for various flexible electronic devices.

  5. Wafer scale integration of reduced graphene oxide by novel laser processing at room temperature in air

    NASA Astrophysics Data System (ADS)

    Bhaumik, Anagh; Narayan, Jagdish

    2016-09-01

    Physical properties of reduced graphene oxide (rGO) strongly depend on the ratio of sp2 to sp3 hybridized carbon atoms, the presence of different functional groups, and the characteristics of the substrates. This research for the very first time illustrates successful wafer scale integration of 2D rGO with Cu/TiN/Si, employing pulsed laser deposition followed by laser annealing of carbon-doped copper layers using nanosecond excimer lasers. The XRD, SEM, and Raman spectroscopy measurements indicate the presence of large area rGO onto Si having Raman active vibrational modes: D, G, and 2D. A high resolution SEM depicts the morphology and formation of rGO from zone-refined carbon formed after nanosecond laser annealing. Temperature-dependent resistance data of rGO thin films follow the Efros-Shklovskii variable range hopping (VRH) model in the low-temperature region and Arrhenius conduction in the high-temperature regime. The photoluminescence spectra also reveal a less intense and broader blue fluorescence spectra, indicating the presence of miniature sized sp2 domains in the near vicinity of π* electronic states which favor the VRH transport phenomena. This wafer scale integration of rGO with Si employing a laser annealing technique will be useful for multifunctional integrated electronic devices and will open a new frontier for further extensive research in these functionalized 2D materials.

  6. Face-to-face transfer of wafer-scale graphene films

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying

  7. Comprehensive investigation of sequential plasma activated Si/Si bonded interfaces for nano-integration on the wafer scale.

    PubMed

    Kibria, M G; Zhang, F; Lee, T H; Kim, M J; Howlader, M M R

    2010-04-02

    The sequentially plasma activated bonding of silicon wafers has been investigated to facilitate the development of chemical free, room temperature and spontaneous bonding required for nanostructure integration on the wafer scale. The contact angle of the surface and the electrical and nanostructural behavior of the interface have been studied. The contact angle measurements show that the sequentially plasma (reactive ion etching plasma followed by microwave radicals) treated surfaces offer highly reactive and hydrophilic surfaces. These highly reactive surfaces allow spontaneous integration at the nanometer scale without any chemicals, external pressure or heating. Electrical characteristics show that the current transportation across the nanobonded interface is dependent on the plasma parameters. High resolution transmission electron microscopy results confirm nanometer scale bonding which is needed for the integration of nanostructures. The findings can be applied in spontaneous integration of nanostructures such as nanowires/nanotubes/quantum dots on the wafer scale.

  8. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

    SciTech Connect

    Berman, Diana; Deshmukh, Sanket; Narayanan, Badri; Sankaranarayanan, Subramanian K.R.S.; Yan, Zhong; Balandin, Alexander A.; Zinovev, Alexander; Rosenmann, Daniel; Sumant, Anirudha V.

    2016-07-04

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here in this article, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the process can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. Additionally, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.

  9. Resolution enhancement using plasmonic metamask for wafer-scale photolithography in the far field

    NASA Astrophysics Data System (ADS)

    Baek, Seunghwa; Kang, Gumin; Kang, Min; Lee, Chang-Won; Kim, Kyoungsik

    2016-07-01

    Resolution enhancement in far-field photolithography is demonstrated using a plasmonic metamask in the proximity regime, in which Fresnel diffraction is dominant. The transverse magnetic component of the diffracted wave from the photomask, which reduces the pattern visibility and lowers the resolution, was successfully controlled by coupling with the anti-symmetric mode of the excited surface plasmon. We obtained a consistently finely-patterned photoresist surface at a distance of up to 15 μm from the mask surface for 3-μm-pitch slits because of conserved field visibility when propagating from the near-field to the proximity regime. We confirmed that sharp edge patterning is indeed possible when using a wafer-scale photomask in the proximity photolithography regime. Our plasmonic metamask method produces cost savings for ultra-large-scale high-density display fabrication by maintaining longer photomask lifetimes and by allowing sufficient tolerance for the distance between the photomask and the photoresist.

  10. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

    PubMed Central

    Berman, Diana; Deshmukh, Sanket A.; Narayanan, Badri; Sankaranarayanan, Subramanian K. R. S.; Yan, Zhong; Balandin, Alexander A.; Zinovev, Alexander; Rosenmann, Daniel; Sumant, Anirudha V.

    2016-01-01

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the process can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. In addition, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics. PMID:27373740

  11. Wafer-scale growth of MoS2 thin films by atomic layer deposition.

    PubMed

    Pyeon, Jung Joon; Kim, Soo Hyun; Jeong, Doo Seok; Baek, Seung-Hyub; Kang, Chong-Yun; Kim, Jin-Sang; Kim, Seong Keun

    2016-05-19

    The wafer-scale synthesis of MoS2 layers with precise thickness controllability and excellent uniformity is essential for their application in the nanoelectronics industry. Here, we demonstrate the atomic layer deposition (ALD) of MoS2 films with Mo(CO)6 and H2S as the Mo and S precursors, respectively. A self-limiting growth behavior is observed in the narrow ALD window of 155-175 °C. Long H2S feeding times are necessary to reduce the impurity contents in the films. The as-grown MoS2 films are amorphous due to the low growth temperature. Post-annealing at high temperatures under a H2S atmosphere efficiently improves the film properties including the crystallinity and chemical composition. An extremely uniform film growth is achieved even on a 4 inch SiO2/Si wafer. These results demonstrate that the current ALD process is well suited for the synthesis of MoS2 layers for application in industry.

  12. HED-TIE: A Wafer Scale Approach for Fabricating Hybrid Electronic Devices with Trench Isolated Electrodes.

    PubMed

    Banerjee, Sreetama; Bülz, Daniel; Solonenko, Dmytro; Reuter, Danny; Deibel, Carsten; Hiller, Karla; Zahn, Dietrich; Salvan, Georgeta

    2017-03-15

    Organic-inorganic hybrid electronic devices (HEDs) offer opportunities for functionalities that are not easily obtainable with either organic or inorganic materials individually. In the strive for down-scaling the channel length in planar geometry HEDs the records were achieved with electron beam lithography or nanoimprint lithography. Their application on the wafer level is, however, cost intensive and time consuming. Here, we propose the trench isolated electrodes (TIE) technology as a fast, cost effective, wafer level approach for fabrication of planar HEDs with electrode gaps in the range of 100 nm. The TIE technology is inspired from the process flow which has been successfully implemented in the fabrication of microelectromechanical systems (MEMS) and is based on standard photolithography and a series of isotropic and anisotropic etching steps and trench refilling with silicon oxide. We demonstrate that the formation of the organic channel can be realized by deposition from solution as well as by thermal evaporation of organic molecules. To underline one key feature of planar HED-TIEs, namely full accessibility of the active area of the devices by external stimuli such as light, TIPS-pentacene/Au HED-TIEs were successfully tested for possible application as hybrid photodetectors in the visible spectral range.

  13. Terahertz wafer-scale mobility mapping of graphene on insulating substrates without a gate.

    PubMed

    Buron, Jonas D; Mackenzie, David M A; Petersen, Dirch H; Pesquera, Amaia; Centeno, Alba; Bøggild, Peter; Zurutuza, Amaia; Jepsen, Peter U

    2015-11-30

    We demonstrate wafer-scale, non-contact mapping of essential carrier transport parameters, carrier mobility (µdrift), carrier density (Ns), DC sheet conductance (σdc), and carrier scattering time (τsc) in CVD graphene, using spatially resolved terahertz time-domain conductance spectroscopy. σdc and τsc are directly extracted from Drude model fits to terahertz conductance spectra obtained in each pixel of 10 × 10 cm2 maps with a 400 µm step size. σdc- and τsc-maps are translated into µdrift and Ns maps through Boltzmann transport theory for graphene charge carriers and these parameters are directly compared to van der Pauw device measurements on the same wafer. The technique is compatible with all substrate materials that exhibit a reasonably low absorption coefficient for terahertz radiation. This includes many materials used for transferring CVD graphene in production facilities as well as in envisioned products, such as polymer films, glass substrates, cloth, or paper substrates.

  14. Wafer-scale epitaxial graphene on SiC for sensing applications

    NASA Astrophysics Data System (ADS)

    Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

    2015-12-01

    The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

  15. Wafer scale imprint uniformity evaluated by LSPR spectroscopy: a high volume characterization method for nanometer scale structures.

    PubMed

    Jeppesen, Claus; Lindstedt, Daniel Nilsson; Vig, Asger Laurberg; Kristensen, Anders; Mortensen, N Asger

    2012-09-28

    We exploit the localized surface-plasmon resonance (LSPR) of terahertz gold gammadion structures for wafer scale critical dimension metrology of nanostructures. The proposed characterization method, LSPR spectroscopy, is based on optical transmission measurements and is benchmarked against numerical simulations of imprinted structures characterized by atomic force microscopy. There is a fair agreement between the two methods and the simulations enable the translation of optical spectra to critical dimensions of the physical structures, a concept known from scatterometry. The results demonstrate the potential of LSPR spectroscopy as an alternative characterization method to scanning electron microscopy, atomic force microscopy and scatterometry.

  16. Wafer-scale fabrication of silicon nanowire arrays with controllable dimensions

    NASA Astrophysics Data System (ADS)

    Wang, Wei; Li, Dan; Tian, Miao; Lee, Yung-Cheng; Yang, Ronggui

    2012-09-01

    A novel and facile method was successfully developed to fabricate wafer-scale Si nanowire arrays with well-controlled sizes through the in-situ porous anodic alumina (PAA) template-assisted wet-etching process. The diameter and filling ratio (inter-wire spacing) of the as-prepared Si nanowires are determined by the size and density of pores in the in-situ PAA templates, which can be tailored independently by adjusting the anodization voltages and the immersion time of PAA templates in phosphoric acid. The length of Si nanowires can be more than one hundred micrometers long, which is controlled by adjusting the wet-etching time. Moreover, this method is compatible with complex Si surface topology for creating desirable 3-dimensional hybrid micro/nano-structures. Such Si nanowire arrays exhibit ultralow reflectance and interesting wettability that are of great importance to photovoltaics and thermal management applications.

  17. Microfluidic devices fabricated using fast wafer-scale LED-lithography patterning.

    PubMed

    Challa, Pavan K; Kartanas, Tadas; Charmet, Jérôme; Knowles, Tuomas P J

    2017-01-01

    Current lithography approaches underpinning the fabrication of microfluidic devices rely on UV exposure of photoresists to define microstructures in these materials. Conventionally, this objective is achieved with gas discharge mercury lamps, which are capable of producing high intensity UV radiation. However, these sources are costly, have a comparatively short lifetime, necessitate regular calibration, and require significant time to warm up prior to exposure taking place. To address these limitations we exploit advances in solid state sources in the UV range and describe a fast and robust wafer-scale laboratory exposure system relying entirely on UV-Light emitting diode (UV-LED) illumination. As an illustration of the potential of this system for fast and low-cost microfluidic device production, we demonstrate the microfabrication of a 3D spray-drying microfluidic device and a 3D double junction microdroplet maker device.

  18. Wafer-scale design of lightweight and transparent electronics that wraps around hairs.

    PubMed

    Salvatore, Giovanni A; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

    2014-01-01

    Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

  19. Wafer-scale, three-dimensional helical porous thin films deposited at a glancing angle

    NASA Astrophysics Data System (ADS)

    Huang, Zhifeng; Bai, Fan

    2014-07-01

    Minimization of helices opens a door to impose novel functions derived from the dimensional shrinkage of optical, mechanical and electronic devices. Glancing angle deposition (GLAD) enables one to deposit three-dimensional helical porous thin films (HPTFs) composed of separated spiral micro/nano-columns. GLAD integrates a series of advantageous features, including one-step deposition, wafer-scale production with mono-handedness of spirals, flexible engineering of spiral materials and dimensions, and the adaption to various kinds of substrates. Herein, we briefly review the fabrication of HPTFs by GLAD, specific growth mechanisms, physical properties in structures, mechanics and chiral optics, and the emerging applications in green energy. A prospective outlook is presented to illuminate some promising developments in enantioselection, bio-dynamic analyses, wirelessly-controlled drug delivery and mass production.

  20. Wafer-scale synthesis of multi-layer graphene by high-temperature carbon ion implantation

    NASA Astrophysics Data System (ADS)

    Kim, Janghyuk; Lee, Geonyeop; Kim, Jihyun

    2015-07-01

    We report on the synthesis of wafer-scale (4 in. in diameter) high-quality multi-layer graphene using high-temperature carbon ion implantation on thin Ni films on a substrate of SiO2/Si. Carbon ions were bombarded at 20 keV and a dose of 1 × 1015 cm-2 onto the surface of the Ni/SiO2/Si substrate at a temperature of 500 °C. This was followed by high-temperature activation annealing (600-900 °C) to form a sp2-bonded honeycomb structure. The effects of post-implantation activation annealing conditions were systematically investigated by micro-Raman spectroscopy and transmission electron microscopy. Carbon ion implantation at elevated temperatures allowed a lower activation annealing temperature for fabricating large-area graphene. Our results indicate that carbon-ion implantation provides a facile and direct route for integrating graphene with Si microelectronics.

  1. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicron devices and integrated circuits using aligned nanotubes

    NASA Astrophysics Data System (ADS)

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Zhou, Chongwu

    2009-03-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration / assembly challenge for future beyond-silicon nanoelectronics. We report our recent advance on full wafer-scale processing of massively aligned carbon nanotube arrays for high performance submicron channel transistors and integrated nanotube circuits, including the following essential components. 1) The massively highly aligned nanotubes were successfully grown on 4 inch quartz and sapphire wafers via meticulous temperature control, and then transferred onto Si/SiO2 wafers using our facile transfer printing method. 2) Wafer-scale device fabrication was performed on 4 inch Si/SiO2 wafer to yield submicron channel transistors and circuits with high on-current density ˜ 20 μA/μm and good on/off ratio. 3) Chemical doping methods were successfully demonstrated to get CMOS inverters with a gain ˜5. 4) Defect-tolerant circuit design for NAND and NOR was proposed and demonstrated to guarantee the correct operation of logic circuit, regardless of the presence of mis-aligned or mis-positioned nanotubes.

  2. Assembly of LIGA using Electric Fields

    SciTech Connect

    FEDDEMA, JOHN T.; WARNE, LARRY K.; JOHNSON, WILLIAM A.; OGDEN, ALLISON J.; ARMOUR, DAVID L.

    2002-04-01

    The goal of this project was to develop a device that uses electric fields to grasp and possibly levitate LIGA parts. This non-contact form of grasping would solve many of the problems associated with grasping parts that are only a few microns in dimensions. Scaling laws show that for parts this size, electrostatic and electromagnetic forces are dominant over gravitational forces. This is why micro-parts often stick to mechanical tweezers. If these forces can be controlled under feedback control, the parts could be levitated, possibly even rotated in air. In this project, we designed, fabricated, and tested several grippers that use electrostatic and electromagnetic fields to grasp and release metal LIGA parts. The eventual use of this tool will be to assemble metal and non-metal LIGA parts into small electromechanical systems.

  3. High speed wafer scale bulge testing for the determination of thin film mechanical properties

    PubMed Central

    Orthner, M. P.; Rieth, L. W.; Solzbacher, F.

    2010-01-01

    A wafer scale bulge testing system has been constructed to study the mechanical properties of thin films and microstructures. The custom built test stage was coupled with a pressure regulation system and optical profilometer which gives high accuracy three-dimensional topographic images collected on the time scale of seconds. Membrane deflection measurements can be made on the wafer scale (50–150 mm) with up to nanometer-scale vertical resolution. Gauge pressures up to 689 kPa (100 psi) are controlled using an electronic regulator with and accuracy of approximately 0.344 kPa (0.05 psi). Initial testing was performed on square diaphragms 350, 550, and 1200 μm in width comprised of 720±10 nm thick low pressure chemical vapor deposited silicon nitride with ∼20 nm of e-beam evaporated aluminum. These initial experiments were focused on measuring the system limitations and used to determine what range of deflections and pressures can be accurately measured and controlled. Gauge pressures from 0 to ∼8.3 kPa (1.2 psi) were initially applied to the bottom side of the diaphragms and their deflection was subsequently measured. The overall pressure resolution of the system is good (∼350 Pa) but small fluctuations existed at pressures below 5 kPa leading to a larger standard deviation between deflection measurements. Analytical calculations and computed finite element analysis deflections closely matched those empirically measured. Using an analytical solution that relates pressure deflection data for the square diaphragms the Young’s modulus was estimated for the films assuming a Poisson’s ratio of v=0.25. Calculations to determine Young’s modulus for the smaller diaphragms proved difficult because the pressure deflection relationship remained in the linear regime over the tested pressure range. Hence, the calculations result in large error when used to estimate the Young’s modulus for the smaller membranes. The deflection measurements of three 1200×1200

  4. Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale

    PubMed Central

    2013-01-01

    We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production. PMID:24289275

  5. Wafer-scale fabrication and growth dynamics of suspended graphene nanoribbon arrays

    PubMed Central

    Suzuki, Hiroo; Kaneko, Toshiro; Shibuta, Yasushi; Ohno, Munekazu; Maekawa, Yuki; Kato, Toshiaki

    2016-01-01

    Adding a mechanical degree of freedom to the electrical and optical properties of atomically thin materials can provide an excellent platform to investigate various optoelectrical physics and devices with mechanical motion interaction. The large scale fabrication of such atomically thin materials with suspended structures remains a challenge. Here we demonstrate the wafer-scale bottom–up synthesis of suspended graphene nanoribbon arrays (over 1,000,000 graphene nanoribbons in 2 × 2 cm2 substrate) with a very high yield (over 98%). Polarized Raman measurements reveal graphene nanoribbons in the array can have relatively uniform-edge structures with near zigzag orientation dominant. A promising growth model of suspended graphene nanoribbons is also established through a comprehensive study that combined experiments, molecular dynamics simulations and theoretical calculations with a phase-diagram analysis. We believe that our results can contribute to pushing the study of graphene nanoribbons into a new stage related to the optoelectrical physics and industrial applications. PMID:27250877

  6. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

    DOE PAGES

    Berman, Diana; Deshmukh, Sanket; Narayanan, Badri; ...

    2016-07-04

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here in this article, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the processmore » can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. Additionally, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.« less

  7. Resolution enhancement using plasmonic metamask for wafer-scale photolithography in the far field

    PubMed Central

    Baek, Seunghwa; Kang, Gumin; Kang, Min; Lee, Chang-Won; Kim, Kyoungsik

    2016-01-01

    Resolution enhancement in far-field photolithography is demonstrated using a plasmonic metamask in the proximity regime, in which Fresnel diffraction is dominant. The transverse magnetic component of the diffracted wave from the photomask, which reduces the pattern visibility and lowers the resolution, was successfully controlled by coupling with the anti-symmetric mode of the excited surface plasmon. We obtained a consistently finely-patterned photoresist surface at a distance of up to 15 μm from the mask surface for 3-μm-pitch slits because of conserved field visibility when propagating from the near-field to the proximity regime. We confirmed that sharp edge patterning is indeed possible when using a wafer-scale photomask in the proximity photolithography regime. Our plasmonic metamask method produces cost savings for ultra-large-scale high-density display fabrication by maintaining longer photomask lifetimes and by allowing sufficient tolerance for the distance between the photomask and the photoresist. PMID:27457127

  8. Wafer-scale high-resolution patterning of reduced graphene oxide films for detection of low concentration biomarkers in plasma

    PubMed Central

    Kim, Jinsik; Chae, Myung-Sic; Lee, Sung Min; Jeong, Dahye; Lee, Byung Chul; Lee, Jeong Hoon; Kim, YoungSoo; Chang, Suk Tai; Hwang, Kyo Seon

    2016-01-01

    Given that reduced graphene oxide (rGO)-based biosensors allow disposable and repeatable biomarker detection at the point of care, we developed a wafer-scale rGO patterning method with mass productivity, uniformity, and high resolution by conventional micro-electro-mechanical systems (MEMS) techniques. Various rGO patterns were demonstrated with dimensions ranging from 5 μm up to several hundred μm. Manufacture of these patterns was accomplished through the optimization of dry etching conditions. The axis-homogeneity and uniformity were also measured to verify the uniform patternability in 4-inch wafer with dry etching. Over 66.2% of uniform rGO patterns, which have deviation of resistance within range of ±10%, formed the entire wafer. We selected amyloid beta (Aβ) peptides in the plasma of APP/PS1 transgenic mice as a study model and measured the peptide level by resistance changes of highly uniform rGO biosensor arrays. Aβ is a pathological hallmark of Alzheimer’s disease and its plasma concentration is in the pg mL−1 range. The sensor detected the Aβ peptides with ultra-high sensitivity; the LOD was at levels as low as 100 fg mL−1. Our results provide biological evidences that this wafer-scale high-resolution patterning method can be used in rGO-based electrical diagnostic devices for detection of low-level protein biomarkers in biofluids. PMID:27506288

  9. Wafer-scale high-resolution patterning of reduced graphene oxide films for detection of low concentration biomarkers in plasma

    NASA Astrophysics Data System (ADS)

    Kim, Jinsik; Chae, Myung-Sic; Lee, Sung Min; Jeong, Dahye; Lee, Byung Chul; Lee, Jeong Hoon; Kim, Youngsoo; Chang, Suk Tai; Hwang, Kyo Seon

    2016-08-01

    Given that reduced graphene oxide (rGO)-based biosensors allow disposable and repeatable biomarker detection at the point of care, we developed a wafer-scale rGO patterning method with mass productivity, uniformity, and high resolution by conventional micro-electro-mechanical systems (MEMS) techniques. Various rGO patterns were demonstrated with dimensions ranging from 5 μm up to several hundred μm. Manufacture of these patterns was accomplished through the optimization of dry etching conditions. The axis-homogeneity and uniformity were also measured to verify the uniform patternability in 4-inch wafer with dry etching. Over 66.2% of uniform rGO patterns, which have deviation of resistance within range of ±10%, formed the entire wafer. We selected amyloid beta (Aβ) peptides in the plasma of APP/PS1 transgenic mice as a study model and measured the peptide level by resistance changes of highly uniform rGO biosensor arrays. Aβ is a pathological hallmark of Alzheimer’s disease and its plasma concentration is in the pg mL‑1 range. The sensor detected the Aβ peptides with ultra-high sensitivity; the LOD was at levels as low as 100 fg mL‑1. Our results provide biological evidences that this wafer-scale high-resolution patterning method can be used in rGO-based electrical diagnostic devices for detection of low-level protein biomarkers in biofluids.

  10. Wafer-scale synthesis of multi-layer graphene by high-temperature carbon ion implantation

    SciTech Connect

    Kim, Janghyuk; Lee, Geonyeop; Kim, Jihyun

    2015-07-20

    We report on the synthesis of wafer-scale (4 in. in diameter) high-quality multi-layer graphene using high-temperature carbon ion implantation on thin Ni films on a substrate of SiO{sub 2}/Si. Carbon ions were bombarded at 20 keV and a dose of 1 × 10{sup 15 }cm{sup −2} onto the surface of the Ni/SiO{sub 2}/Si substrate at a temperature of 500 °C. This was followed by high-temperature activation annealing (600–900 °C) to form a sp{sup 2}-bonded honeycomb structure. The effects of post-implantation activation annealing conditions were systematically investigated by micro-Raman spectroscopy and transmission electron microscopy. Carbon ion implantation at elevated temperatures allowed a lower activation annealing temperature for fabricating large-area graphene. Our results indicate that carbon-ion implantation provides a facile and direct route for integrating graphene with Si microelectronics.

  11. Atomic layer lithography of wafer-scale nanogap arrays for extreme confinement of electromagnetic waves

    NASA Astrophysics Data System (ADS)

    Chen, Xiaoshu; Park, Hyeong-Ryeol; Pelton, Matthew; Piao, Xianji; Lindquist, Nathan C.; Im, Hyungsoon; Kim, Yun Jung; Ahn, Jae Sung; Ahn, Kwang Jun; Park, Namkyoo; Kim, Dai-Sik; Oh, Sang-Hyun

    2013-09-01

    Squeezing light through nanometre-wide gaps in metals can lead to extreme field enhancements, nonlocal electromagnetic effects and light-induced electron tunnelling. This intriguing regime, however, has not been readily accessible to experimentalists because of the lack of reliable technology to fabricate uniform nanogaps with atomic-scale resolution and high throughput. Here we introduce a new patterning technology based on atomic layer deposition and simple adhesive-tape-based planarization. Using this method, we create vertically oriented gaps in opaque metal films along the entire contour of a millimetre-sized pattern, with gap widths as narrow as 9.9 Å, and pack 150,000 such devices on a 4-inch wafer. Electromagnetic waves pass exclusively through the nanogaps, enabling background-free transmission measurements. We observe resonant transmission of near-infrared waves through 1.1-nm-wide gaps (λ/1,295) and measure an effective refractive index of 17.8. We also observe resonant transmission of millimetre waves through 1.1-nm-wide gaps (λ/4,000,000) and infer an unprecedented field enhancement factor of 25,000.

  12. Wafer-scale self-organized InP nanopillars with controlled orientation for photovoltaic devices.

    PubMed

    Sanatinia, Reza; Berrier, Audrey; Dhaka, Veer; Perros, Alexander P; Huhtio, Teppo; Lipsanen, Harri; Anand, Srinivasan

    2015-10-16

    A unique wafer-scale self-organization process for generation of InP nanopillars is demonstrated, which is based on maskless ion-beam etching (IBE) of InP developed to obtain the nanopillars, where the height, shape, and orientation of the nanopillars can be varied by controlling the processing parameters. The fabricated InP nanopillars exhibit broadband suppression of the reflectance, 'black InP,' a property useful for solar cells. The realization of a conformal p-n junction for carrier collection, in the fabricated solar cells, is achieved by a metalorganic vapor phase epitaxy (MOVPE) overgrowth step on the fabricated pillars. The conformal overgrowth retains the broadband anti-reflection property of the InP nanopillars, indicating the feasibility of this technology for solar cells. Surface passivation of the formed InP nanopillars using sulfur-oleylamine solution resulted in improved solar-cell characteristics. An open-circuit voltage of 0.71 V and an increase of 0.13 V compared to the unpassivated device were achieved.

  13. A wafer-scale graphene and ferroelectric multilayer for flexible and fast-switched modulation applications.

    PubMed

    Zhu, Minmin; Wu, Jing; Du, Zehui; Tay, Roland Yingjie; Li, Hongling; Özyilmaz, Barbarous; Teo, Edwin Hang Tong

    2015-09-21

    Here we report a wafer-scale graphene/P(VDF-TrFE)/graphene multilayer for light-weight, flexible and fast-switched broadband modulation applications. The P(VDF-TrFE) film not only significantly reduces the sheet resistance of graphene throughout heavy doping of ∼0.8 × 10(13) cm(-2) by nonvolatile ferroelectric dipoles, but also acts as an efficient electro-optic (EO) layer. Such multilayered structural integration with remarkable ferroelectric polarization, high transparency (>90%), low sheet resistance (∼302 Ω□(-1)), and excellent mechanic flexibility shows the potential of a flexible modulation application over a broad range of wavelengths. Moreover, the derived device also exhibits strong field-induced EO modulation even under bending and one large Pockels coefficient (∼54.3 pm V(-1)) is obtained. Finally, the graphene and ferroelectric hybrid demonstrates a fast switching time (∼2 μs) and works well below low sheet resistance level over a long time. This work gives insights into the potential of graphene and ferroelectric hybrid structures, enabling future exploration on next-generation high-performance, flexible transparent electronics and photonics.

  14. Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy.

    PubMed

    Wang, Dongxing; Zhu, Wenqi; Best, Michael D; Camden, Jon P; Crozier, Kenneth B

    2013-10-04

    The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures ("metasurfaces") can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent.

  15. Wafer-scale design of lightweight and transparent electronics that wraps around hairs

    NASA Astrophysics Data System (ADS)

    Salvatore, Giovanni A.; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

    2014-01-01

    Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

  16. Wafer-scale highly-transparent and superhydrophilic sapphires for high-performance optics.

    PubMed

    Leem, Jung Woo; Yu, Jae Su

    2012-11-19

    We reported the wafer-scale highly-transparent and superhydrophilic sapphires with antireflective subwavelength structures (SWSs) which were fabricated by dry etching using thermally dewetted gold (Au) nanomasks. Their optical transmittance properties were experimentally and theoretically investigated. The density, size, and period of the thermally dewetted Au nanopatterns can be controlled by the Au film thickness. For the sapphire with both-side SWSs at 5 nm of Au film, the average total transmittance (T(avg)) of ~96.5% at 350-800 nm was obtained, indicating a higher value than those of the flat sapphire (T(avg)~85.6%) and the sapphire with one-side SWSs (T(avg)~91%), and the less angle-dependent transmittance property was observed. The calculated transmittance results also showed a similar tendency to the measured data. The SWSs enhanced significantly the surface hydrophilicity of sapphires, exhibiting a water contact angle (θ(c)) of < 5° for Au film of 5 nm compared to θ(c)~37° of the flat sapphire.

  17. Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

    PubMed

    Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

    2012-07-17

    Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

  18. Electronic and optoelectronic devices based on chirality-enriched wafer-scale single-wall carbon nanotube thin films

    NASA Astrophysics Data System (ADS)

    Gao, Weilu; He, Xiaowei; Xie, Lijuan; Zhang, Qi; Haroz, Erik; Doorn, Stephen K.; Kono, Junichiro

    2015-03-01

    The unique and rich material properties of single-wall carbon nanotubes (SWCNTs) make them attractive for nano-electronic and optoelectronic applications. Slight changes in tube diameter and wrapping angle, defined by the chirality indices (n, m), can dramatically modify the bandstructure, which can be utilized for designing devices with tailored properties. However, it remains to be a challenge to fabricate macroscopic, single-chirality devices. Here, we introduce a simple way of producing chirality-enriched wafer-scale SWCNT films by combining recently developed solution-based polymer-modified sorting method and vacuum filtration. The produced thin films can be easily transferred onto any substrate to have a CMOS compatible wafer. We fabricated a transistor of (6,5)-enriched SWCNTs with an on/off ratio >103. Large-scale photothermoelectric-effect-based and photovoltaic-effect-based photodetectors made of (6,6)- and (6,5)-enriched films, respectively, will also be discussed.

  19. Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer

    PubMed Central

    Yu, Yang; Fong, Patrick W. K.; Wang, Shifeng; Surya, Charles

    2016-01-01

    High quality wafer-scale free-standing WS2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS2, which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm2 at −1 V which shows superior performances compared to the directly grown WS2/GaN heterojunctions. PMID:27897210

  20. Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer

    NASA Astrophysics Data System (ADS)

    Yu, Yang; Fong, Patrick W. K.; Wang, Shifeng; Surya, Charles

    2016-11-01

    High quality wafer-scale free-standing WS2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS2, which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm2 at ‑1 V which shows superior performances compared to the directly grown WS2/GaN heterojunctions.

  1. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  2. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    NASA Astrophysics Data System (ADS)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  3. Influence of thickness on crystallinity in wafer-scale GaTe nanolayers grown by molecular beam epitaxy

    NASA Astrophysics Data System (ADS)

    Bae, Che Jin; McMahon, Jonathan; Detz, Hermann; Strasser, Gottfried; Park, Junsung; Einarsson, Erik; Eason, D. B.

    2017-03-01

    We grew wafer-scale, uniform nanolayers of gallium telluride (GaTe) on gallium arsenide (GaAs) substrates using molecular beam epitaxy. These films initially formed in a hexagonal close-packed structure (h-GaTe), but monoclinic (m-GaTe) crystalline elements began to form as the film thicknesses increased to more than approximately 90 nm. We confirmed the coexistence of these two crystalline forms using x-ray diffraction and Raman spectroscopy, and we attribute the thickness-dependent structural change to internal stress induced by lattice mismatch with the substrate and to natural lattice relaxation at the growth conditions.

  4. Review on mechanism of directly fabricating wafer-scale graphene on dielectric substrates by chemical vapor deposition.

    PubMed

    Ning, Jing; Wang, Dong; Chai, Yang; Feng, Xin; Mu, Meishan; Guo, Lixin; Zhang, Jincheng; Hao, Yue

    2017-04-07

    To date, although the chemical vapor deposition with a catalytic transition metal is a potential way to achieve low cost, high quality and uniform wafer-scale graphene. But the annoying underneath catalytic metals removing and transferring process can also bring large amounts of uncertain facts for the performance deterioration of graphene,such as the pollution of surface polymeric residues, unmentioned doping and structural damages. Thus, to develop a technique of directly fabricating graphene on dielectric substrates is quite meaningful. In this review, we will present specific methods of catalyst- or transfer-free techniques for graphene growth and discuss the diversity of growth mechanisms.

  5. Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales

    NASA Astrophysics Data System (ADS)

    Bai, Jingwei; Wang, Deqiang; Nam, Sung-Wook; Peng, Hongbo; Bruce, Robert; Gignac, Lynn; Brink, Markus; Kratschmer, Ernst; Rossnagel, Stephen; Waggoner, Phil; Reuter, Kathleen; Wang, Chao; Astier, Yann; Balagurusamy, Venkat; Luan, Binquan; Kwark, Young; Joseph, Eric; Guillorn, Mike; Polonsky, Stanislav; Royyuru, Ajay; Papa Rao, S.; Stolovitzky, Gustavo

    2014-07-01

    We introduce a method to fabricate solid-state nanopores with sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer using CMOS compatible semiconductor processes. Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated to have high uniformity (+/-0.5 nm) across the wafer. Arrays of nanopores were fabricated with an average size of 18 +/- 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling. Shorts between the membrane-embedded metals were occasionally created after pore formation, but the RIE based pores had a much better yield (99%) of unshorted electrodes compared to TEM drilled pores (<10%). A double-stranded DNA of length 1 kbp was translocated through the multi-layer structure RIE-based nanopore demonstrating that the pores were open. The ionic current through the pore can be modulated with a gain of 3 using embedded electrodes functioning as a gate in 0.1 mM KCl aqueous solution. This fabrication approach can potentially pave the way to manufacturable nanopore arrays with the ability to electrically control the movement of single or double-stranded DNA inside the pore with embedded electrodes.We introduce a method to fabricate solid-state nanopores with sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer using CMOS compatible semiconductor processes. Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated to have high uniformity (+/-0.5 nm) across the wafer. Arrays of nanopores were fabricated with an average size of 18 +/- 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling. Shorts between the membrane-embedded metals were occasionally created after pore formation, but the RIE based pores had a much better yield (99%) of unshorted electrodes compared to TEM drilled pores (<10%). A double-stranded DNA of length 1 kbp was translocated through the multi-layer structure RIE-based nanopore

  6. Large-scale fabrication of wafer-size colloidal crystals, macroporous polymers and nanocomposites by spin-coating.

    PubMed

    Jiang, Peng; McFarland, Michael J

    2004-10-27

    This paper reports a simple spin-coating technique for rapidly fabricating three types of technologically important materials--colloidal crystal, macroporous polymer, and polymeric nanocomposite, each with high crystalline qualities and wafer-scale sizes. Dispersion of monodisperse silica colloids in triacrylate monomers is spin-coated onto a variety of substrates. Shear-induced ordering and subsequent polymerization lead to the formation of three-dimensionally (3D) ordered colloidal crystals trapped inside a polymer matrix. The thickness of as-synthesized colloidal crystal-polymer nanocomposite is highly uniform and can be controlled simply by changing the spin speed and time. Selective removal of the polymer matrix and silica spheres lead to the formation of large-area colloidal crystals and macroporous polymers, respectively. The wafer-scale process is compatible with standard semiconductor microfabrication, as multiple micrometer-sized patterns can be created simultaneously for potential device applications. Normal-incidence transmission spectra in the visible and near-infrared regions show distinct peaks due to Bragg diffraction from 3D ordered structures. The spin-coating process opens a new route to the fundamental studies of shear-induced crystallization, melting and relaxation.

  7. Wafer scale fabrication of porous three-dimensional plasmonic metamaterials for the visible region: chiral and beyond

    NASA Astrophysics Data System (ADS)

    Singh, Johnson Haobijam; Nair, Greshma; Ghosh, Arijit; Ghosh, Ambarish

    2013-07-01

    We report on a wafer scale fabrication method of a three-dimensional plasmonic metamaterial with strong chiroptical response in the visible region of the electromagnetic spectrum. The system was comprised of metallic nanoparticles arranged in a helical fashion, with high degree of flexibility over the choice of the underlying material, as well as their geometrical parameters. This resulted in exquisite control over the chiroptical properties, most importantly the spectral signature of the circular dichroism. In spite of the large variability in the arrangement, as well as the size and shape of the constituent nanoparticles, the average chiro-optical response of the material remained uniform across the wafer, thus confirming the suitability of this system as a large area chiral metamaterial. By simply heating the substrate for a few minutes, the geometrical properties of the nanoparticles could be altered, thus providing an additional handle towards tailoring the spectral response of this novel material.We report on a wafer scale fabrication method of a three-dimensional plasmonic metamaterial with strong chiroptical response in the visible region of the electromagnetic spectrum. The system was comprised of metallic nanoparticles arranged in a helical fashion, with high degree of flexibility over the choice of the underlying material, as well as their geometrical parameters. This resulted in exquisite control over the chiroptical properties, most importantly the spectral signature of the circular dichroism. In spite of the large variability in the arrangement, as well as the size and shape of the constituent nanoparticles, the average chiro-optical response of the material remained uniform across the wafer, thus confirming the suitability of this system as a large area chiral metamaterial. By simply heating the substrate for a few minutes, the geometrical properties of the nanoparticles could be altered, thus providing an additional handle towards tailoring the

  8. Fabrication method for chip-scale-vacuum-packages based on a chip-to-wafer-process

    NASA Astrophysics Data System (ADS)

    Bauer, J.; Weiler, D.; Ruß, M.; Heß, J.; Yang, P.; Voß, J.; Arnold, N.,; Vogt, H.

    2010-10-01

    This paper introduces a simple vacuum packaging method which is based on a Chip-to-Wafer process. The MEMS-device is provided with an electroplated solder frame. A Si-lid with the same solder frame is mounted on each die of the wafer using a flip chip process. The same materials for lid and substrate are used in order to reduce the mechanical stress due to the same thermal coefficients of expansion. The resulting cavity between die and lid can be evacuated and hermetically sealed with an eutectic soldering process. The feasibility of the method is demonstrated with an infrared focal plane array (IR-FPA). In this case, the Si-lid acts as an optical window and contains an anti reflective layer for the 8-14 μm wavelength area on both sides. The long-term vacuum stability is supported by a getter film inside the package. This method simplifies the sawing process and has the additional cost benefit that it is possible to package only known good dies.

  9. Fabrication of sub-20 nm nanopore arrays in membranes with embedded metal electrodes at wafer scales.

    PubMed

    Bai, Jingwei; Wang, Deqiang; Nam, Sung-Wook; Peng, Hongbo; Bruce, Robert; Gignac, Lynn; Brink, Markus; Kratschmer, Ernst; Rossnagel, Stephen; Waggoner, Phil; Reuter, Kathleen; Wang, Chao; Astier, Yann; Balagurusamy, Venkat; Luan, Binquan; Kwark, Young; Joseph, Eric; Guillorn, Mike; Polonsky, Stanislav; Royyuru, Ajay; Papa Rao, S; Stolovitzky, Gustavo

    2014-08-07

    We introduce a method to fabricate solid-state nanopores with sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer using CMOS compatible semiconductor processes. Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated to have high uniformity (± 0.5 nm) across the wafer. Arrays of nanopores were fabricated with an average size of 18 ± 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling. Shorts between the membrane-embedded metals were occasionally created after pore formation, but the RIE based pores had a much better yield (99%) of unshorted electrodes compared to TEM drilled pores (<10%). A double-stranded DNA of length 1 kbp was translocated through the multi-layer structure RIE-based nanopore demonstrating that the pores were open. The ionic current through the pore can be modulated with a gain of 3 using embedded electrodes functioning as a gate in 0.1 mM KCl aqueous solution. This fabrication approach can potentially pave the way to manufacturable nanopore arrays with the ability to electrically control the movement of single or double-stranded DNA inside the pore with embedded electrodes.

  10. Stationary Optical Concentrator Designs and Wafer Scale Monolithic Integration of Semiconductor Devices for Next Generation Photovoltaic Panels

    NASA Astrophysics Data System (ADS)

    Kim, Jung Min

    A major barrier in utilizing solar energy for large scale deployment is the cost of the photovoltaic (PV) systems. Several approaches have been used for the cost reduction such as by modifying PV system designs in addition to enhancing the efficiency of solar cells. Due to the high cost of materials, minimizing the use of solar cells such as in concentrator type systems is highly attractive for reducing the cost of the PV modules by focusing the incident light onto the PV cell. However concentrator PV systems (CPV) require constant tracking of the sun and hence are complex in design and expensive to operate, except in limited situations such as large scale PV power plants. It is desirable to design new concentrator type systems that do not require continuous tracking of the sun. These systems could ultimately reduce the PV system cost to a minimum while maximizing the power conversion efficiency. In this thesis we propose a simple design for a stationary concentrator photovoltaic (SCPV) system that could significantly reduce the cost of generating electricity using PV devices. Using optical ray tracing simulations, we have been able to design SCPV systems that could reduce the PV module cost by 2--10 times without compromising on the power conversion efficiency of the system. Another alternative approach for sustainable high efficiency PV system design is to develop low cost PV cells for terrestrial applications. To meet the demands of low cost and large scale production, larger and thinner (or flexible) substrates are required. We demonstrated the feasibility of fabricating monolithic interconnected PV devices at the wafer scale (2 inch wafers). In this study, GaSb PV cells grown on semi-insulating GaAs were used as the model material. Crucial device fabrication steps such as a selective etching process have been developed that is necessary for isolating individual devices on the wafer and interconnecting them with sub-micron scale accuracy. Selective etching of

  11. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

    PubMed Central

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-01-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80–100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes. PMID:28145513

  12. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

    NASA Astrophysics Data System (ADS)

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-02-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80–100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

  13. Highly Transparent Wafer-Scale Synthesis of Crystalline WS2 Nanoparticle Thin Film for Photodetector and Humidity-Sensing Applications.

    PubMed

    Pawbake, Amit S; Waykar, Ravindra G; Late, Dattatray J; Jadkar, Sandesh R

    2016-02-10

    In the present investigation, we report a one-step synthesis method of wafer-scale highly crystalline tungsten disulfide (WS2) nanoparticle thin film by using a modified hot wire chemical vapor deposition (HW-CVD) technique. The average size of WS2 nanoparticle is found to be 25-40 nm over an entire 4 in. wafer of quartz substrate. The low-angle XRD data of WS2 nanoparticle shows the highly crystalline nature of sample along with orientation (002) direction. Furthermore, Raman spectroscopy shows two prominent phonon vibration modes of E(1)2g and A1g at ∼356 and ∼420 cm(-1), respectively, indicating high purity of material. The TEM analysis shows good crystalline quality of sample. The synthesized WS2 nanoparticle thin film based device shows good response to humidity and good photosensitivity along with good long-term stability of the device. It was found that the resistance of the films decreases with increasing relative humidity (RH). The maximum humidity sensitivity of 469% along with response time of ∼12 s and recovery time of ∼13 s were observed for the WS2 thin film humidity sensor device. In the case of photodetection, the response time of ∼51 s and recovery time of ∼88 s were observed with sensitivity ∼137% under white light illumination. Our results open up several avenues to grow other transition metal dichalcogenide nanoparticle thin film for large-area nanoelectronics as well as industrial applications.

  14. Inspection strategy for LIGA microstructures using a programmable optical microscope.

    SciTech Connect

    Kurfess, Thomas R; Aigeldinger, Georg; Ceremuga, Joseph T.

    2004-07-01

    The LIGA process has the ability to fabricate very precise, high aspect ratio mesoscale structures with microscale features [l]. The process consists of multiple steps before a final part is produced. Materials native to the LIGA process include metals and photoresists. These structures are routinely measured for quality control and process improvement. However, metrology of LIGA structures is challenging because of their high aspect ratio and edge topography. For the scale of LIGA structures, a programmable optical microscope is well suited for lateral (XU) critical dimension measurements. Using grayscale gradient image processing with sub-pixel interpolation, edges are detected and measurements are performed. As with any measurement, understanding measurement uncertainty is necessary so that appropriate conclusions are drawn from the data. Therefore, the abilities of the inspection tool and the obstacles presented by the structures under inspection should be well understood so that precision may be quantified. This report presents an inspection method for LIGA microstructures including a comprehensive assessment of the uncertainty for each inspection scenario.

  15. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

    NASA Astrophysics Data System (ADS)

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-02-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

  16. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

    PubMed Central

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-01-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

  17. Wafer-scale fabrication of patterned carbon nanofiber nanoelectrode arrays: a route for development of multiplexed, ultrasensitive disposable biosensors.

    PubMed

    Arumugam, Prabhu U; Chen, Hua; Siddiqui, Shabnam; Weinrich, Jarret A P; Jejelowo, Ayodeji; Li, Jun; Meyyappan, M

    2009-05-15

    One of the major limitations in the development of ultrasensitive electrochemical biosensors based on one-dimensional nanostructures is the difficulty involved with reliably fabricating nanoelectrode arrays (NEAs). In this work, we describe a simple, robust and scalable wafer-scale fabrication method to produce multiplexed biosensors. Each sensor chip consists of nine individually addressable arrays that uses electron beam patterned vertically aligned carbon nanofibers (VACNFs) as the sensing element. To ensure nanoelectrode behavior with higher sensitivity, VACNFs were precisely grown on 100 nm Ni dots with 1 microm spacing on each micro pad. Pretreatments by the combination of soaking in 1.0 M HNO(3) and electrochemical etching in 1.0M NaOH dramatically improved the electrode performance, indicated by the decrease of redox peak separation in cyclic voltammogram (DeltaE(p)) to approximately 100 mV and an approximately 200% increase in steady-state currents. The electrochemical detection of the hybridization of DNA targets from E. coli O157:H7 onto oligonucleotide probes were successfully demonstrated. The 9 arrays within the chip were divided into three groups with triplicate sensors for positive control, negative control and specific hybridization. The proposed method has the potential to be scaled up to NxN arrays with N up to 10, which is ideal for detecting a myriad of organisms. In addition, such sensors can be used as a generic platform for many electroanalysis applications.

  18. Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics.

    PubMed

    Heo, Jinseong; Byun, Kyung-Eun; Lee, Jaeho; Chung, Hyun-Jong; Jeon, Sanghun; Park, Seongjun; Hwang, Sungwoo

    2013-01-01

    Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.

  19. Wafer-scale Fabrication of Non-Polar Mesoporous GaN Distributed Bragg Reflectors via Electrochemical Porosification

    PubMed Central

    Zhu, Tongtong; Liu, Yingjun; Ding, Tao; Fu, Wai Yuen; Jarman, John; Ren, Christopher Xiang; Kumar, R. Vasant; Oliver, Rachel A.

    2017-01-01

    Distributed Bragg reflectors (DBRs) are essential components for the development of optoelectronic devices. For many device applications, it is highly desirable to achieve not only high reflectivity and low absorption, but also good conductivity to allow effective electrical injection of charges. Here, we demonstrate the wafer-scale fabrication of highly reflective and conductive non-polar gallium nitride (GaN) DBRs, consisting of perfectly lattice-matched non-polar (11–20) GaN and mesoporous GaN layers that are obtained by a facile one-step electrochemical etching method without any extra processing steps. The GaN/mesoporous GaN DBRs exhibit high peak reflectivities (>96%) across the entire visible spectrum and wide spectral stop-band widths (full-width at half-maximum >80 nm), while preserving the material quality and showing good electrical conductivity. Such mesoporous GaN DBRs thus provide a promising and scalable platform for high performance GaN-based optoelectronic, photonic, and quantum photonic devices. PMID:28345612

  20. Highly uniform wafer-scale synthesis of α-MoO3 by plasma enhanced chemical vapor deposition.

    PubMed

    Kim, Hyeong-U; Son, Juhyun; Kulkarni, Atul; Ahn, Chisung; Kim, Ki Seok; Shin, Dongjoo; Yeom, Geun Yong; Kim, Taesung

    2017-04-28

    Molybdenum oxide (MoO3) has gained immense attention because of its high electron mobility, wide band gap, and excellent optical and catalytic properties. However, the synthesis of uniform and large-area MoO3 is challenging. Here, we report the synthesis of wafer-scale α-MoO3 by plasma oxidation of Mo deposited on Si/SiO2. Mo was oxidized by O2 plasma in a plasma enhanced chemical vapor deposition (PECVD) system at 150 °C. It was found that the synthesized α-MoO3 had a highly uniform crystalline structure. For the as-synthesized α-MoO3 sensor, we observed a current change when the relative humidity was increased from 11% to 95%. The sensor was exposed to different humidity levels with fast recovery time of about 8 s. Hence this feasibility study shows that MoO3 synthesized at low temperature can be utilized for gas sensing applications by adopting flexible device technology.

  1. Wafer scale fabrication of carbon nanotube thin film transistors with high yield

    NASA Astrophysics Data System (ADS)

    Tian, Boyuan; Liang, Xuelei; Yan, Qiuping; Zhang, Han; Xia, Jiye; Dong, Guodong; Peng, Lianmao; Xie, Sishen

    2016-07-01

    Carbon nanotube thin film transistors (CNT-TFTs) are promising candidates for future high performance and low cost macro-electronics. However, most of the reported CNT-TFTs are fabricated in small quantities on a relatively small size substrate. The yield of large scale fabrication and the performance uniformity of devices on large size substrates should be improved before the CNT-TFTs reach real products. In this paper, 25 200 devices, with various geometries (channel width and channel length), were fabricated on 4-in. size ridged and flexible substrates. Almost 100% device yield were obtained on a rigid substrate with high out-put current (>8 μA/μm), high on/off current ratio (>105), and high mobility (>30 cm2/V.s). More importantly, uniform performance in 4-in. area was achieved, and the fabrication process can be scaled up. The results give us more confidence for the real application of the CNT-TFT technology in the near future.

  2. Design and fabrication of a LIGA milliengine

    SciTech Connect

    Garcia, E.J.; Christenson, T.R.; Polosky, M.A.; Jojola, A.A.

    1997-04-01

    This paper reports on the design and fabrication of a new milliscale magnetic actuator that is ideally suited for LIGA processing. LIGA processing permits the fabrication of millisized machine elements that cannot be fabricated by conventional miniature machining techniques because of their small feature sizes. The Milliengine is a magnetically driven device that utilizes a unique design to extend the 2-dimensional fabrication capability of LIGA to create 3-dimensional machinery.

  3. Wafer-scale monodomain films of spontaneously aligned single-walled carbon nanotubes.

    PubMed

    He, Xiaowei; Gao, Weilu; Xie, Lijuan; Li, Bo; Zhang, Qi; Lei, Sidong; Robinson, John M; Hároz, Erik H; Doorn, Stephen K; Wang, Weipeng; Vajtai, Robert; Ajayan, Pulickel M; Adams, W Wade; Hauge, Robert H; Kono, Junichiro

    2016-07-01

    The one-dimensional character of electrons, phonons and excitons in individual single-walled carbon nanotubes leads to extremely anisotropic electronic, thermal and optical properties. However, despite significant efforts to develop ways to produce large-scale architectures of aligned nanotubes, macroscopic manifestations of such properties remain limited. Here, we show that large (>cm(2)) monodomain films of aligned single-walled carbon nanotubes can be prepared using slow vacuum filtration. The produced films are globally aligned within ±1.5° (a nematic order parameter of ∼1) and are highly packed, containing 1 × 10(6) nanotubes in a cross-sectional area of 1 μm(2). The method works for nanotubes synthesized by various methods, and film thickness is controllable from a few nanometres to ∼100 nm. We use the approach to create ideal polarizers in the terahertz frequency range and, by combining the method with recently developed sorting techniques, highly aligned and chirality-enriched nanotube thin-film devices. Semiconductor-enriched devices exhibit polarized light emission and polarization-dependent photocurrent, as well as anisotropic conductivities and transistor action with high on/off ratios.

  4. Wafer-scale monodomain films of spontaneously aligned single-walled carbon nanotubes

    NASA Astrophysics Data System (ADS)

    He, Xiaowei; Gao, Weilu; Xie, Lijuan; Li, Bo; Zhang, Qi; Lei, Sidong; Robinson, John M.; Hároz, Erik H.; Doorn, Stephen K.; Wang, Weipeng; Vajtai, Robert; Ajayan, Pulickel M.; Adams, W. Wade; Hauge, Robert H.; Kono, Junichiro

    2016-07-01

    The one-dimensional character of electrons, phonons and excitons in individual single-walled carbon nanotubes leads to extremely anisotropic electronic, thermal and optical properties. However, despite significant efforts to develop ways to produce large-scale architectures of aligned nanotubes, macroscopic manifestations of such properties remain limited. Here, we show that large (>cm2) monodomain films of aligned single-walled carbon nanotubes can be prepared using slow vacuum filtration. The produced films are globally aligned within ±1.5° (a nematic order parameter of ∼1) and are highly packed, containing 1 × 106 nanotubes in a cross-sectional area of 1 μm2. The method works for nanotubes synthesized by various methods, and film thickness is controllable from a few nanometres to ∼100 nm. We use the approach to create ideal polarizers in the terahertz frequency range and, by combining the method with recently developed sorting techniques, highly aligned and chirality-enriched nanotube thin-film devices. Semiconductor-enriched devices exhibit polarized light emission and polarization-dependent photocurrent, as well as anisotropic conductivities and transistor action with high on/off ratios.

  5. Highly stable 2D material (2DM) field-effect transistors (FETs) with wafer-scale multidyad encapsulation.

    PubMed

    Kim, Choong-Ki; Jeong, Eun Gyo; Kim, Eungtaek; Song, Jeong-Gyu; Kim, Youngjun; Woo, Whang Je; Lee, Myung Keun; Bae, Hagyoul; Jeon, Seong-Bae; Kim, Hyungjun; Choi, Kyung Cheol; Choi, Yang-Kyu

    2017-02-03

    Field-effect transistors (FETs) composed of 2D materials (2DMs) such as transition-metal dichalcogenide (TMD) materials show unstable electrical characteristics in ambient air due to the high sensitivity of 2DMs to water adsorbates. In this work, in order to demonstrate the long-term retention of electrical characteristics of a TMD FET, a multidyad encapsulation method was applied to a MoS2 FET and thereby its durability was warranted for one month. It was well known that the multidyad encapsulation method was effective to mitigate high sensitivity to ambient air in light-emitting diodes (LEDs) composed of organic materials. However, there was no attempt to check the feasibility of such a multidyad encapsulation method for 2DM FETs. It is timely to investigate the water vapor transmission ratio (WVTR) required for long-term stability of 2DM FETs. The 2DM FETs were fabricated with MoS2 flakes by both an exfoliation method, that is desirable to attain high quality film, and a chemical vapor deposition (CVD) method, that is applicable to fabrication for a large-sized substrate. In order to eliminate other unwanted variables, the MoS2 FETs composed of exfoliated flakes were primarily investigated to assure the effectiveness of the encapsulation method. The encapsulation method uses multiple dyads comprised of a polymer layer by spin coating and an Al2O3 layer deposited by atomic layer deposition (ALD). The proposed method shows wafer-scale uniformity, high transparency, and protective barrier properties against adsorbates (WVTR of 8 × 10(-6) g m(-2) day(-1)) over one month.

  6. Highly stable 2D material (2DM) field-effect transistors (FETs) with wafer-scale multidyad encapsulation

    NASA Astrophysics Data System (ADS)

    Kim, Choong-Ki; Gyo Jeong, Eun; Kim, Eungtaek; Song, Jeong-Gyu; Kim, Youngjun; Woo, Whang Je; Lee, Myung Keun; Bae, Hagyoul; Jeon, Seong-Bae; Kim, Hyungjun; Choi, Kyung Cheol; Choi, Yang-Kyu

    2017-02-01

    Field-effect transistors (FETs) composed of 2D materials (2DMs) such as transition-metal dichalcogenide (TMD) materials show unstable electrical characteristics in ambient air due to the high sensitivity of 2DMs to water adsorbates. In this work, in order to demonstrate the long-term retention of electrical characteristics of a TMD FET, a multidyad encapsulation method was applied to a MoS2 FET and thereby its durability was warranted for one month. It was well known that the multidyad encapsulation method was effective to mitigate high sensitivity to ambient air in light-emitting diodes (LEDs) composed of organic materials. However, there was no attempt to check the feasibility of such a multidyad encapsulation method for 2DM FETs. It is timely to investigate the water vapor transmission ratio (WVTR) required for long-term stability of 2DM FETs. The 2DM FETs were fabricated with MoS2 flakes by both an exfoliation method, that is desirable to attain high quality film, and a chemical vapor deposition (CVD) method, that is applicable to fabrication for a large-sized substrate. In order to eliminate other unwanted variables, the MoS2 FETs composed of exfoliated flakes were primarily investigated to assure the effectiveness of the encapsulation method. The encapsulation method uses multiple dyads comprised of a polymer layer by spin coating and an Al2O3 layer deposited by atomic layer deposition (ALD). The proposed method shows wafer-scale uniformity, high transparency, and protective barrier properties against adsorbates (WVTR of 8 × 10-6 g m-2 day-1) over one month.

  7. Fabrication of miniaturized electrostatic deflectors using LIGA

    SciTech Connect

    Jackson, K.H.; Khan-Malek, C.; Muray, L.P.

    1997-04-01

    Miniaturized electron beam columns ({open_quotes}microcolumns{close_quotes}) have been demonstrated to be suitable candidates for scanning electron microscopy (SEM), e-beam lithography and other high resolution, low voltage applications. In the present technology, microcolumns consist of {open_quotes}selectively scaled{close_quotes} micro-sized lenses and apertures, fabricated from silicon membranes with e-beam lithography, reactive ion beam etching and other semiconductor thin-film techniques. These miniaturized electron-optical elements provide significant advantages over conventional optics in performance and ease of fabrication. Since lens aberrations scale roughly with size, it is possible to fabricate simple microcolumns with extremely high brightness sources and electrostatic objective lenses, with resolution and beam current comparable to conventional e-beam columns. Moreover since microcolumns typically operate at low voltages (1 KeV), the proximity effects encountered in e-beam lithography become negligible. For high throughput applications, batch fabrication methods may be used to build large parallel arrays of microcolumns. To date, the best reported performance with a 1 keV cold field emission cathode, is 30 nm resolution at a working distance of 2mm in a 3.5mm column. Fabrication of the microcolumn deflector and stigmator, however, have remained beyond the capabilities of conventional machining operations and semiconductor processing technology. This work examines the LIGA process as a superior alternative to fabrication of the deflectors, especially in terms of degree of miniaturization, dimensional control, placement accuracy, run-out, facet smoothness and choice of suitable materials. LIGA is a combination of deep X-ray lithography, electroplating, and injection molding processes which allow the fabrication of microstructures.

  8. Wafer Scale Union.

    DTIC Science & Technology

    1992-05-31

    1992 Optically Generated 60 GHz Millimeter Waves Using AlGaAs/InGaAs HEMT’s Integrated with Both Quasi- Optical Antenna Circuits and MMIC’s D. V...quasi- optical antenna circuits and MMIC’s," IEEE Photon. Technol. Lett., vol. 4, no. 1, pp. 102-105, 1992. 7) D.C. Scott, D.V. Plant, and H.R

  9. Wafer Scale Distributed Radio

    DTIC Science & Technology

    2009-07-01

    plane was chosen to be 400 µm. Fig. 4.2 shows designed circular monopole antenna with diameter of 700 µm. 47 45 Folded Slot Antenna In terms of array , a...49 Figure 4.6: 3×3 array folded slot antenna . 4.3.1 Circular monopole antenna A circular monopole antenna was designed based on a 0.13 µm BiCMOS...45 4.2.3 Antenna Unit Element Design . . . . . . . . . . . . . . . . . . . . . . . 47 4.2.4 Antenna Array

  10. Miniature Inchworm Actuators Fabricated by Use of LIGA

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok

    2003-01-01

    Miniature inchworm actuators that would have relatively simple designs have been proposed for applications in which there are requirements for displacements of the order of microns or tens of microns and for the ability to hold their positions when electric power is not applied. The proposed actuators would be members of the class of microelectromechanical systems (MEMS), but would be designed and fabricated following an approach that is somewhat unusual for MEMS. Like other MEMS actuators, the proposed inchworm actuators could utilize thermoplastic, bimetallic, shape-memory-alloy, or piezoelectric actuation principles. The figure depicts a piezoelectric inchworm actuator according to the proposal. As in other inchworm actuators, linear motion of an extensible member would be achieved by lengthening and shortening the extensible member in synchronism with alternately clamping and releasing one and then the other end of the member. In this case, the moving member would be the middle one; the member would be piezoelectric and would be shortened by applying a voltage to it. The two outer members would also be piezoelectric; the release of the clamps on the upper or lower end would be achieved by applying a voltage to the electrodes on the upper or lower ends, respectively, of these members. Usually, MEMS actuators cannot be fabricated directly on the side walls of silicon wafers, yet the geometry of this actuator necessitates such fabrication. The solution, according to the proposal, would be to use the microfabrication technique known by the German acronym LIGA - "lithographie, galvanoformung, abformung," which means lithography, electroforming, molding. LIGA involves x-ray lithography of a polymer film followed by selective removal of material to form a three-dimensional pattern from which a mold is made. Among the advantages of LIGA for this purpose are that it is applicable to a broad range of materials, can be used to implement a variety of designs, including

  11. Imaging ATUM ultrathin section libraries with WaferMapper: a multi-scale approach to EM reconstruction of neural circuits

    PubMed Central

    Hayworth, Kenneth J.; Morgan, Josh L.; Schalek, Richard; Berger, Daniel R.; Hildebrand, David G. C.; Lichtman, Jeff W.

    2014-01-01

    The automated tape-collecting ultramicrotome (ATUM) makes it possible to collect large numbers of ultrathin sections quickly—the equivalent of a petabyte of high resolution images each day. However, even high throughput image acquisition strategies generate images far more slowly (at present ~1 terabyte per day). We therefore developed WaferMapper, a software package that takes a multi-resolution approach to mapping and imaging select regions within a library of ultrathin sections. This automated method selects and directs imaging of corresponding regions within each section of an ultrathin section library (UTSL) that may contain many thousands of sections. Using WaferMapper, it is possible to map thousands of tissue sections at low resolution and target multiple points of interest for high resolution imaging based on anatomical landmarks. The program can also be used to expand previously imaged regions, acquire data under different imaging conditions, or re-image after additional tissue treatments. PMID:25018701

  12. Laser wafering for silicon solar.

    SciTech Connect

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  13. Optimization and scale-down of wafer-based resist strip and rinse processes for photomask production

    NASA Astrophysics Data System (ADS)

    Aggus, Brant L.; Weaver, Gene

    2002-03-01

    Retrofitting of wafer processing equipment is a common scenario in the photomask industry, as most available tools are built to accommodate the high throughput and substrate size of wafers. The acid process tanks in use at most mask shops are built to suit a single rack of 25 8 inch wafers, each coated with roughly two microns of photoresist. Conversely, a typical photomask shop sends one to two masks at a time through the resist strip line, each coated with 4500 angstroms of resist. The amount of unused volume of active chemical within an 8 inch X 8.5 inch X 10 inch acid tank when it is dumped is enough to warrant a hardware change. Experimentation has shown that it is possible to decrease Piranha usage by 43 percent by optimizing tank size for photomasks. The same logic applies to quick dump rinsers (QDRs). Additionally, water is wasted with 'spray down' processes, whereby masks are sprayed via perforated bars or nozzles. Because a < 0.5 μm viscous sublayer can not be practically achieved through spraying the mask, better cleaning performance is obtained with a bottom-filled weiring process. This is demonstrated through experimental results and theoretical mass transfer models.

  14. Versatile Wafer-Scale Technique for the Formation of Ultrasmooth and Thickness-Controlled Graphene Oxide Films Based on Very Large Flakes.

    PubMed

    Azevedo, Joël; Campidelli, Stéphane; He, Delong; Cornut, Renaud; Bertucchi, Michael; Sorgues, Sébastien; Benattar, Jean-Jacques; Colbeau-Justin, Christophe; Derycke, Vincent

    2015-09-30

    We present a new strategy to form thickness-adjusted and ultrasmooth films of very large and unwrinkled graphene oxide (GO) flakes through the transfer of both hemispherical and vertical water films stabilized by surfactants. With its versatility in terms of substrate type (including flexible organic substrates) and in terms of flake density (from isolated flakes to continuous and multilayer films), this wafer-scale assembly technique is adapted to a broad range of experiments involving GO and rGO (reduced graphene oxide). We illustrate its use through the evaluation of transparent rGO electrodes.

  15. Large-area, wafer-scale epitaxial growth of germanium on silicon and integration of high-performance transistors

    NASA Astrophysics Data System (ADS)

    Ghosh, Swapnadip

    Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the ˜105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress

  16. Automated Product Test Wafer Procedure

    NASA Astrophysics Data System (ADS)

    Brown, Andrew; Minvielle, Anna; Salugsugan, Anita

    1987-04-01

    An automated test wafer procedure has been developed using the KLA 2020 wafer inspector to measure registration and critical dimensions on production wafers. The procedure reduces operator interactions to loading the wafer and entering information for wafer identification. The analysis of the registration data is performed on a PC using the methods established by Perloff to determine both intrafield and grid errors. These results are then used to correct the stepper. CD data is also analyzed by the program and corrections to the exposure time are calculated. It was found that the KLA 2020 is as much as 10 times faster and 4 times more precise in obtaining registration data then an operator reading optical verniers on a microscope. Due to the high precision of the reading, the analysis does not need a large number of readings to obtain precise and accurate stepper corrections. Further, significant improvements can be obtained by adding registration targets to measure the intrafield errors. Using the KLA 2020 and computer analysis we have demonstrated an ability to reduce the errors for a manually aligned run to a one sigma distribution of 0.09 um for x and y translation, 0.4 PPM for scaling and orthogonality, and 2.3 PPM for rotation from the first test wafer for a GCA 6100. Nearly all of this variation is due to operator misalignment or the inability of the stepper to correct the errors. The corrections with this technique measuring the same wafer are precise to + 0.01 um in translation and + 0.5 PPM for rotation, scaling, and orthogonality. It has also been shown that a simple linear equation can be used to correct exposure time, even when a process is not tightly controlled.

  17. Wafer-scale Thermodynamically Stable GaN Nanorods via Two-Step Self-Limiting Epitaxy for Optoelectronic Applications

    NASA Astrophysics Data System (ADS)

    Kum, Hyun; Seong, Han-Kyu; Lim, Wantae; Chun, Daemyung; Kim, Young-Il; Park, Youngsoo; Yoo, Geonwook

    2017-01-01

    We present a method of epitaxially growing thermodynamically stable gallium nitride (GaN) nanorods via metal-organic chemical vapor deposition (MOCVD) by invoking a two-step self-limited growth (TSSLG) mechanism. This allows for growth of nanorods with excellent geometrical uniformity with no visible extended defects over a 100 mm sapphire (Al2O3) wafer. An ex-situ study of the growth morphology as a function of growth time for the two self-limiting steps elucidate the growth dynamics, which show that formation of an Ehrlich-Schwoebel barrier and preferential growth in the c-plane direction governs the growth process. This process allows monolithic formation of dimensionally uniform nanowires on templates with varying filling matrix patterns for a variety of novel electronic and optoelectronic applications. A color tunable phosphor-free white light LED with a coaxial architecture is fabricated as a demonstration of the applicability of these nanorods grown by TSSLG.

  18. Wafer-scale production of highly uniform two-dimensional MoS2 by metal-organic chemical vapor deposition.

    PubMed

    Kim, TaeWan; Mun, Jihun; Park, Hyeji; Joung, DaeHwa; Diware, Mangesh; Won, Chegal; Park, Jonghoo; Jeong, Soo-Hwan; Kang, Sang-Woo

    2017-05-05

    Semiconducting two-dimensional (2D) materials, particularly extremely thin molybdenum disulfide (MoS2) films, are attracting considerable attention from academia and industry owing to their distinctive optical and electrical properties. Here, we present the direct growth of a MoS2 monolayer with unprecedented spatial and structural uniformity across an entire 8 inch SiO2/Si wafer. The influences of growth pressure, ambient gases (Ar, H2), and S/Mo molar flow ratio on the MoS2 layered growth were explored by considering the domain size, nucleation sites, morphology, and impurity incorporation. Monolayer MoS2-based field effect transistors achieve an electron mobility of 0.47 cm(2) V(-1) s(-1) and on/off current ratio of 5.4 × 10(4). This work demonstrates the potential for reliable wafer-scale production of 2D MoS2 for practical applications in next-generation electronic and optical devices.

  19. Wafer-scale epitaxial lift-off of optoelectronic grade GaN from a GaN substrate using a sacrificial ZnO interlayer

    NASA Astrophysics Data System (ADS)

    Rajan, Akhil; Rogers, David J.; Ton-That, Cuong; Zhu, Liangchen; Phillips, Matthew R.; Sundaram, Suresh; Gautier, Simon; Moudakir, Tarik; El-Gmili, Youssef; Ougazzaden, Abdallah; Sandana, Vinod E.; Teherani, Ferechteh H.; Bove, Philippe; Prior, Kevin A.; Djebbour, Zakaria; McClintock, Ryan; Razeghi, Manijeh

    2016-08-01

    Full 2 inch GaN epilayers were lifted off GaN and c-sapphire substrates by preferential chemical dissolution of sacrificial ZnO underlayers. Modification of the standard epitaxial lift-off (ELO) process by supporting the wax host with a glass substrate proved key in enabling full wafer scale-up. Scanning electron microscopy and x-ray diffraction confirmed that intact epitaxial GaN had been transferred to the glass host. Depth-resolved cathodoluminescence (CL) analysis of the bottom surface of the lifted-off GaN layer revealed strong near-band-edge (3.33 eV) emission indicating a superior optical quality for the GaN which was lifted off the GaN substrate. This modified ELO approach demonstrates that previous theories proposing that wax host curling was necessary to keep the ELO etch channel open do not apply to the GaN/ZnO system. The unprecedented full wafer transfer of epitaxial GaN to an alternative support by ELO offers the perspective of accelerating industrial adoption of the expensive GaN substrate through cost-reducing recycling.

  20. Microfabrication: LIGA-X and applications

    NASA Astrophysics Data System (ADS)

    Kupka, R. K.; Bouamrane, F.; Cremers, C.; Megtert, S.

    2000-09-01

    X-ray LIGA (Lithography, Electrogrowth, Moulding) is one of today's key technologies in microfabrication and upcoming modern (meso)-(nano) fabrication, already used and anticipated for micromechanics (micromotors, microsensors, spinnerets, etc.), micro-optics, micro-hydrodynamics (fluidic devices), microbiology, in medicine, in biology, and in chemistry for microchemical reactors. It compares to micro-electromechanical systems (MEMS) technology, offering a larger, non-silicon choice of materials and better inherent precision. X-ray LIGA relies on synchrotron radiation to obtain necessary X-ray fluxes and uses X-ray proximity printing. Inherent advantages are its extreme precision, depth of field and very low intrinsic surface roughness. However, the quality of fabricated structures often depends on secondary effects during exposure and effects like resist adhesion. UV-LIGA, relying on thick UV resists is an alternative for projects requiring less precision. Modulating the spectral properties of synchrotron radiation, different regimes of X-ray lithography lead to (a) the mass-fabrication of classical nanostructures, (b) the fabrication of high aspect ratio nanostructures (HARNST), (c) the fabrication of high aspect ratio microstructures (HARMST), and (d) the fabrication of high aspect ratio centimeter structures (HARCST). Reviewing very recent activities around X-ray LIGA, we show the versatility of the method, obviously finding its region of application there, where it is best and other competing microtechnologies are less advantageous. An example of surface-based X-ray and particle lenses (orthogonal reflection optics (ORO)) made by X-ray LIGA is given.

  1. Wafer-scale Thermodynamically Stable GaN Nanorods via Two-Step Self-Limiting Epitaxy for Optoelectronic Applications

    PubMed Central

    Kum, Hyun; Seong, Han-Kyu; Lim, Wantae; Chun, Daemyung; Kim, Young-il; Park, Youngsoo; Yoo, Geonwook

    2017-01-01

    We present a method of epitaxially growing thermodynamically stable gallium nitride (GaN) nanorods via metal-organic chemical vapor deposition (MOCVD) by invoking a two-step self-limited growth (TSSLG) mechanism. This allows for growth of nanorods with excellent geometrical uniformity with no visible extended defects over a 100 mm sapphire (Al2O3) wafer. An ex-situ study of the growth morphology as a function of growth time for the two self-limiting steps elucidate the growth dynamics, which show that formation of an Ehrlich-Schwoebel barrier and preferential growth in the c-plane direction governs the growth process. This process allows monolithic formation of dimensionally uniform nanowires on templates with varying filling matrix patterns for a variety of novel electronic and optoelectronic applications. A color tunable phosphor-free white light LED with a coaxial architecture is fabricated as a demonstration of the applicability of these nanorods grown by TSSLG. PMID:28098259

  2. Wafer-scale broadband antireflective silicon fabricated by metal-assisted chemical etching using spin-coating Ag ink.

    PubMed

    Yeo, Chan Il; Song, Young Min; Jang, Sung Jun; Lee, Yong Tak

    2011-09-12

    We report broadband antireflective disordered subwavelength structures (d-SWSs), which were fabricated on 4-inch silicon wafers by spin-coating Ag ink and metal-assisted chemical etching. The antireflection properties of the d-SWSs depend on its dimensions and heights, which were changed by the sintering temperature of the spin-coated Ag ink and etching time. The fabricated d-SWSs drastically reduced surface reflection over a wide range of wavelengths and incident angles, providing good surface uniformity. The d-SWSs with the most appropriate geometry for practical solar cell applications exhibit only 1.23% solar-weighted reflectance in the wavelength range of 300-1100 nm and average reflectance <5% up to an incident angle of 55° in the wavelength range of 300-2500 nm. This simple and low-cost nanofabrication method for antireflection could be of great importance in optical device applications because it allows mass production without any lithography processes or sophisticated equipment.

  3. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  4. Optical measurement of LIGA milliengine performance

    SciTech Connect

    Dickey, F.M.; Holswade, S.C.; Christenson, T.R.; Garcia, E.J.; Polosky, M.A.

    1997-12-31

    Understanding the parameters that affect the performance of milliscale and microscale actuators is essential to the development of optimized designs and fabrication processes, as well as the qualification of devices for commercial applications. This paper discusses the development of optical techniques for motion measurements of LIGA fabricated milliengines. LIGA processing permits the fabrication of precision millimeter-sized machine elements that cannot be fabricated by conventional miniature machining techniques because of their small feature sizes. In addition, tolerances of 1 part in 10{sup 3} to 10{sup 4} may be maintained in millimeter sized components with this processing technique. Optical techniques offer a convenient means for measuring long term statistical performance data and transient responses needed to optimize designs and manufacturing techniques. Optical techniques can also be used to provide feedback signals needed for control and sensing of the state of the machine. Optical probe concepts and experimental data obtained using a milliengine developed at Sandia National Laboratories are presented.

  5. Experimental evaluation of incorporating digital and analog integrated circuit die on a common substrate utilizing silicon-hybrid wafer-scale integration technology

    NASA Astrophysics Data System (ADS)

    Reamy, Philip C.

    1992-03-01

    The objective of this research effort was to investigate the implementation of analog circuits in a wafer scale integration system. A test circuit composed of analog and digital subsystems was designed and tested through simulation. IC die containing this test circuit were utilized in the WSI system fabrication. Preliminary investigations were conducted to evaluate the potential improvements to the IC die mounting procedure, a key step in fabricating functional WSI systems. These investigations demonstrated a procedure which produced repeatable results in achieving acceptable planarization of IC die and host substrate surfaces. These investigations also demonstrated the successful application of a barrier coating material to prevent adhesion between the IC die adhesive and the reference flat during the IC die mounting procedure. An evaluation of candidate polyimides to be used as the interlevel dielectric in the WSI systems was also performed. Test samples for each of the WSI configurations were fabricated and tested for electrical continuity. Additional electrical characterization measurements were conducted on two of the test samples.

  6. X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

    NASA Astrophysics Data System (ADS)

    Cha, Bo Kyung; Jeon, Seongchae; Seo, Chang-Woo

    2016-09-01

    This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 μm 1-poly/4-metal CMOS process. The pixel size is 100 μm×100 μm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd2O2S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

  7. LIGA microsystems aging : evaluation and mitigation.

    SciTech Connect

    Cadden, Charles H.; Yang, Nancy Y. C.; San Marchi, Christopher W.

    2003-12-01

    The deployment of LIGA structures in DP applications requires a thorough understanding of potential long term physical and chemical changes that may occur during service. While these components are generally fabricated from simple metallic systems such as copper, nickel and nickel alloys, the electroplating process used to form them creates microstructural features which differ from those found in conventional (e.g. ingot metallurgy) processing of such materials. Physical changes in non-equilibrium microstructures may occur due to long term exposure to temperatures sufficient to permit atomic and vacancy mobility. Chemical changes, particularly at the surfaces of LIGA parts, may occur in the presence of gaseous chemical species (e.g. water vapor, HE off-gassing compounds) and contact with other metallic structures. In this study, we have characterized the baseline microstructure of several nickel-based materials that are used to fabricate LIGA structures. Solute content and distribution was found to have a major effect on the electroplated microstructures. Microstructural features were correlated to measurements of hardness and tensile strength. Dormancy testing was conducted on one of the baseline compositions, nickel-sulfamate. Groups of specimens were exposed to controlled thermal cycles; subsequent examinations compared properties of 'aged' specimens to the baseline conditions. Results of our testing indicate that exposure to ambient temperatures (-54 C to 71 C) do not result in microstructural changes that might be expected to significantly effect mechanical performance. Additionally, no localized changes in surface appearance were found as a result of contact between electroplated parts.

  8. The Covidien LigaSure Maryland Jaw Device.

    PubMed

    Zaidi, Nisar; Glover, Anthony R; Sidhu, Stanley B

    2015-03-01

    Since its invention nearly 20 years ago, the Covidien LigaSure device along with its ForceTriad generator has dominated the Electrothermal Bipolar Vessel Sealing market. The LigaSure was used for surgical procedures, both open and laparoscopic. The purpose of this review is to provide evidence of the safety and utility of the LigaSure device compared to more traditional means of hemostasis and its ultrasonic competitor, particularly in laparoscopic applications. We will provide evidence related to electrothermal bipolar vessel sealing in general and look specifically at Covidien's newest product, the LigaSure Maryland Jaw Device.

  9. Microstructural Evolution of SAC305 Solder Joints in Wafer Level Chip-Scale Packaging (WLCSP) with Continuous and Interrupted Accelerated Thermal Cycling

    NASA Astrophysics Data System (ADS)

    Zhou, Quan; Zhou, Bite; Lee, Tae-Kyu; Bieler, Thomas

    2016-06-01

    Four high-strain design wafer level chip scale packages were given accelerated thermal cycling with a 10°C/min ramp rate and 10 min hold times between 0°C and 100°C to examine the effects of continuous and interrupted thermal cycling on the number of cycles to failure. The interruptions given two of the samples were the result of periodic examinations using electron backscattered pattern mapping, leading to room temperature aging of 30 days-2.5 years after increments of about 100 cycles at several stages of the cycling history. The continuous thermal cycling resulted in solder joints with a much larger degree of recrystallization, whereas the interrupted thermal cycling tests led to much less recrystallization, which was more localized near the package side, and the crack was more localized near the interface and had less branching. The failure mode for both conditions was still the same, with cracks nucleating along the high angle grain boundaries formed during recrystallization. In conditions where there were few recrystallized grains, recovery led to formation of subgrains that strengthened the solder, and the higher strength led to a larger driving force for crack growth through the solder, leading to failure after less than half of the cycles in the continuous accelerated thermal cycling condition. This work shows that there is a critical point where sufficient strain energy accumulation will trigger recrystallization, but this point depends on the rate of strain accumulation in each cycle and various recovery processes, which further depends on local crystal orientations, stress state evolution, and specific activated slip and twinning systems.

  10. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    PubMed

    Zhao, C; Konstantinidis, A C; Zheng, Y; Anaxagoras, T; Speller, R D; Kanicki, J

    2015-12-07

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm(-1) and a DQE of around 0.5 at spatial frequencies  <1 mm(-1). In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered.

  11. Wafer characteristics via reflectometry

    DOEpatents

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  12. Scriber for silicon wafers

    NASA Technical Reports Server (NTRS)

    Yamakawa, K. A.; Fortier, E. P. (Inventor)

    1981-01-01

    A device for dividing silicon wafers into rectangular chips is characterized by a base including a horizontally oriented bed with a planar support surface, a vacuum chuck adapted to capture a silicon wafer seated on the support for translation in mutually perpendicular directions. A stylus support mounted on the bed includes a shaft disposed above and extended across the bed and a truck mounted on the shaft and supported thereby for linear translation along a path extended across the bed a vertically oriented scribe has a diamond tip supported by the truck also adapted as to engage a silicon wafer captured by the chuck and positioned beneath it in order to form score lines in the surface of the wafer as linear translation is imparted to the truck. A chuck positioning means is mounted on the base and is connected to the chuck for positioning the chuck relative to the stylus.

  13. Wafer scale micromachine assembly method

    DOEpatents

    Christenson, Todd R.

    2001-01-01

    A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.

  14. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  15. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  16. Final-part metrology for LIGA springs, Build Group 1.

    SciTech Connect

    Aigeldinger, Georg; Skala, Dawn M.; Ceremuga, Joseph T.; Mills, Bernice E.

    2004-03-01

    The LIGA spring is a recently designed part for defense program applications. The Sandia California LIGA team has produced an initial group build of these nickel alloy parts. These are distinctive in having a macroscopic lateral size of about 1 cm, while requiring microscopic dimensional precision on the order of a few micrometers. LIGA technology capabilities at Sandia are able to manufacture such precise structures. While certain aspects of the LIGA process and its production capabilities have been dimensionally characterized in the past, [1-6] the present work is exclusive in defining a set of methods and techniques to inspect and measure final LIGA nickel alloy parts in large prototype quantities. One hundred percent inspection, meaning that every single LIGA part produced needs to be measured, ensures quality control and customer satisfaction in this prototype production run. After a general visual inspection of the parts and an x-ray check for voids, high precision dimensional metrology tools are employed. The acquired data is analyzed using both in house and commercially available software. Examples of measurements illustrating these new metrology capabilities are presented throughout the report. These examples furthermore emphasize that thorough inspection of every final part is not only essential to characterize but also improve the LIGA manufacturing process.

  17. Thinning of PLZT ceramic wafers for sensor integration

    NASA Astrophysics Data System (ADS)

    Jin, Na; Liu, Weiguo

    2010-08-01

    Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

  18. Micro-grippers for assembly of LIGA parts

    SciTech Connect

    Feddema, J.; Polosky, M.; Christenson, T.; Spletzer, B.; Simon, R.

    1997-12-31

    This paper describes ongoing testing of two microgrippers for assembly of LIGA (Lithographie Galvanoformung Abformung) parts. The goal is to place 100 micron outside diameter (OD) LIGA gears with a 50 micron inner diameter hole onto pins ranging from 35 to 49 microns. The first micro gripper is a vacuum gripper made of a 100 micron OD stainless steel tube. The second micro gripper is a set of tweezers fabricated using the LIGA process. Nickel, Permalloy, and copper materials are tested. The tweezers are actuated by a collet mechanism which is closed by a DC linear motor.

  19. Contrastive study on the mechanical performance of MEMS microsprings fabricated by LIGA and UV-LIGA technology

    NASA Astrophysics Data System (ADS)

    Li, Hua; Shi, Gengchen

    2008-03-01

    With good mechanical performance and mature fabrication technology of LIGA and UV-LIGA, Ni is chosen as the material of S style MEMS microspring. At 24°C and 25% relative humidity, five different points in LIGA Ni sample were tested with the MICRO HARDNESS TESTER, and the Young's modulus was 219GPa. From the tensile tests of UV-LIGA Ni sample the Young's modulus of UV-LIGA Ni is 180GPa. The S style microspring was fabricated by LIGA and UV-LIGA technology separately. Applying the Castigliano second theorem of energy method in macro theory, the spring constant formulas of S style microspring in three application modes were deduced, and the correctness was verified by the FEA (Finite Element Analysis) simulation. The experiments of S style microspring's deformation properties were carried out by the Tytron250 micro force test machine and a tensile measurement system separately. The experimental results agree with the theoretical analysis. Based on the above analysis, the change laws of microspring's spring coefficient in different application patters are summarized.

  20. Within-wafer CD variation induced by wafer shape

    NASA Astrophysics Data System (ADS)

    Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

    2016-03-01

    In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer

  1. Cantilevered multilevel LIGA devices and methods

    DOEpatents

    Morales, Alfredo Martin; Domeier, Linda A.

    2002-01-01

    In the formation of multilevel LIGA microstructures, a preformed sheet of photoresist material, such as polymethylmethacrylate (PMMA) is patterned by exposure through a mask to radiation, such as X-rays, and developed using a developer to remove the exposed photoresist material. A first microstructure is then formed by electroplating metal into the areas from which the photoresist has been removed. Additional levels of microstructure are added to the initial microstructure by covering the first microstructure with a conductive polymer, machining the conductive polymer layer to reveal the surface of the first microstructure, sealing the conductive polymer and surface of the first microstructure with a metal layer, and then forming the second level of structure on top of the first level structure. In such a manner, multiple layers of microstructure can be built up to allow complex cantilevered microstructures to be formed.

  2. Miniature Scroll Pumps Fabricated by LIGA

    NASA Technical Reports Server (NTRS)

    Wiberg, Dean; Shcheglov, Kirill; White, Victor; Bae, Sam

    2009-01-01

    Miniature scroll pumps have been proposed as roughing pumps (low - vacuum pumps) for miniature scientific instruments (e.g., portable mass spectrometers and gas analyzers) that depend on vacuum. The larger scroll pumps used as roughing pumps in some older vacuum systems are fabricated by conventional machining. Typically, such an older scroll pump includes (1) an electric motor with an eccentric shaft to generate orbital motion of a scroll and (2) conventional bearings to restrict the orbital motion to a circle. The proposed miniature scroll pumps would differ from the prior, larger ones in both design and fabrication. A miniature scroll pump would include two scrolls: one mounted on a stationary baseplate and one on a flexure stage (see figure). An electromagnetic actuator in the form of two pairs of voice coils in a push-pull configuration would make the flexure stage move in the desired circular orbit. The capacitance between the scrolls would be monitored to provide position (gap) feedback to a control system that would adjust the drive signals applied to the voice coils to maintain the circular orbit as needed for precise sealing of the scrolls. To minimize power consumption and maximize precision of control, the flexure stage would be driven at the frequency of its mechanical resonance. The miniaturization of these pumps would entail both operational and manufacturing tolerances of <1 m. Such tight tolerances cannot be achieved easily by conventional machining of high-aspect-ratio structures like those of scroll-pump components. In addition, the vibrations of conventional motors and ball bearings exceed these tight tolerances by an order of magnitude. Therefore, the proposed pumps would be fabricated by the microfabrication method known by the German acronym LIGA ( lithographie, galvanoformung, abformung, which means lithography, electroforming, molding) because LIGA has been shown to be capable of providing the required tolerances at large aspect ratios.

  3. Etching Of Semiconductor Wafer Edges

    DOEpatents

    Kardauskas, Michael J.; Piwczyk, Bernhard P.

    2003-12-09

    A novel method of etching a plurality of semiconductor wafers is provided which comprises assembling said plurality of wafers in a stack, and subjecting said stack of wafers to dry etching using a relatively high density plasma which is produced at atmospheric pressure. The plasma is focused magnetically and said stack is rotated so as to expose successive edge portions of said wafers to said plasma.

  4. Metallic nanowires by full wafer stencil lithography.

    PubMed

    Vazquez-Mena, O; Villanueva, G; Savu, V; Sidler, K; van den Boogaart, M A F; Brugger, J

    2008-11-01

    Aluminum and gold nanowires were fabricated using 100 mm stencil wafers containing nanoslits fabricated with a focused ion beam. The stencils were aligned and the nanowires deposited on a substrate with predefined electrical pads. The morphology and resistivity of the wires were studied. Nanowires down to 70 nm wide and 5 mum long have been achieved showing a resistivity of 10 microOmegacm for Al and 5 microOmegacm for Au and maximum current density of approximately 10(8) A/cm(2). This proves the capability of stencil lithography for the fabrication of metallic nanowires on a full wafer scale.

  5. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  6. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the

  7. AFOSR Wafer Bonding

    DTIC Science & Technology

    2009-07-31

    cleanliness (foreign particles) and surface morphology (roughness). Two silicon wafers, when properly cleaned, can easily bond at room temperature because of...4 Figure IV data for nSi-nGaN bond. Structure is similar to that shown in Figure Difficulties and Knowledge Added Surface Morphology and...Particles One of the most important features of materials in determining whether they will bond is the quality of the bonding surfaces , in both

  8. Wafer-scale crack-free AlGaN on GaN through two-step selective-area growth for optically pumped stimulated emission

    NASA Astrophysics Data System (ADS)

    Ko, Young-Ho; Bae, Sung-Bum; Kim, Sung-Bock; Kim, Dong Churl; Leem, Young Ahn; Cho, Yong-Hoon; Nam, Eun-Soo

    2016-07-01

    Crack-free AlGaN template has been successfully grown over entire 2-in. wafer by using 2-step selective-area growth (SAG). The GaN truncated structure was obtained by vertical growth mode with low growth temperature. AlGaN of second step was grown under lateral growth mode. Low pressure enhanced the relative ratio of lateral to vertical growth rate as well as absolute overall growth rate. High V/III ratio was favorable for lateral growth mode. Crack-free planar AlGaN was obtained under low pressure of 30 Torr and high V/III ratio of 4400. The AlGaN was crack-free over entire 2-in. wafer and had quite uniform Al-mole fraction. The dislocation density of the AlGaN with 20% Al-composition was as low as ~7.6×108 /cm2, measured by cathodoluminescence. GaN/AlGaN multi-quantum well (MQW) with cladding and waveguide layers were grown on the crack-free AlGaN template with low dislocation density. It was confirmed that the MQW on the AlGaN template emitted the stimulated emission at 355.5 nm through optical pumping experiment. The AlGaN obtained by 2-step SAG would provide high crystal quality for highly-efficient optoelectronic devices as well as the ultraviolet laser diode.

  9. Modeling of secondary radiation damage in LIGA PMMA resist exposure

    NASA Astrophysics Data System (ADS)

    Ting, Aili

    2003-01-01

    Secondary radiation during LIGA PMMA resist exposure adversely affects feature definition, sidewall taper and overall sidewall offset. Additionally, it can degrade the resist adjacent to the substrate, leading to the loss of free-standing features through undercutting during resist development or through mechanical failure of the degraded material. The source of this radiation includes photoelectrons, Auger electrons, fluorescence photons, etc. Sandia"s Integrated Tiger Series (ITS), a coupled electron/photon Monte Carlo transport code, was used to compute dose profiles within 1 to 2 microns of the absorber edge and near the interface of the resist with a metallized substrate. The difficulty of sub-micron resolution requirement was overcome by solving a few local problems having carefully designed micron-scale geometries. The results indicate a 2-μm dose transition region near the absorber edge resulting from PMMA"s photoelectrons. This region leads to sidewall offset and to tapered sidewalls following resist development. The results also show a dose boundary layer of around 1 μm near the substrate interface due to electrons emitted from the substrate metallization layer. The maximum dose at the resist bottom under the absorber can be very high and can lead to feature loss during development. This model was also used to investigate those resist doses resulting from multi-layer substrate.

  10. Prediction of etching-shape anomaly due to distortion of ion sheath around a large-scale three-dimensional structure by means of on-wafer monitoring technique and computer simulation

    NASA Astrophysics Data System (ADS)

    Kubota, Tomohiro; Ohtake, Hiroto; Araki, Ryosuke; Yanagisawa, Yuuki; Iwasaki, Takuya; Ono, Kohei; Miwa, Kazuhiro; Samukawa, Seiji

    2013-10-01

    A system for predicting distortion of a profile during plasma etching was developed. The system consists of a combination of measurement and simulation. An ‘on-wafer sheath-shape sensor’ for measuring the plasma-sheath parameters (sheath potential and thickness) on the stage of the plasma etcher was developed. The sensor has numerous small electrodes for measuring sheath potential and saturation ion-current density, from which sheath thickness can be calculated. The results of the measurement show reasonable dependence on source power, bias power and pressure. Based on self-consistent calculation of potential distribution and ion- and electron-density distributions, simulation of the sheath potential distribution around an arbitrary 3D structure and the trajectory of incident ions from the plasma to the structure was developed. To confirm the validity of the distortion prediction by comparing it with experimentally measured distortion, silicon trench etching under chlorine inductively coupled plasma (ICP) was performed using a sample with a vertical step. It was found that the etched trench was distorted when the distance from the step was several millimetres or less. The distortion angle was about 20° at maximum. Measurement was performed using the on-wafer sheath-shape sensor in the same plasma condition as the etching. The ion incident angle, calculated as a function of distance from the step, successfully reproduced the experimentally measured angle, indicating that the combination of measurement by the on-wafer sheath-shape sensor and simulation can predict distortion of an etched structure. This prediction system will be useful for designing devices with large-scale 3D structures (such as those in MEMS) and determining the optimum etching conditions to obtain the desired profiles.

  11. Effectiveness of LigaSure diathermy coagulation in liver surgery.

    PubMed

    Chiappa, Antonio; Bertani, Emilio; Biffi, Roberto; Zbar, Andrew P; Viale, Giuseppe; Pruneri, Giancarlo; Bellomi, Massimo; Venturino, Marco; Andreoni, Bruno

    2008-01-01

    The principal cause of perioperative morbidity and mortality following hepatic resection is excessive intraoperative hemorrhage. This study evaluates the operative use of the LigaSure device in sealing ductal structures during major and minor hepatic resections. Patients were analyzed between June 1994 and December 2005, comparing 89 randomly selected cases undergoing hepatic resections using the clamp-crushing technique with LigaSure electrocautery and hepatic inflow occlusion where appropriate with 70 patients undergoing various hepatic resections using the clamp-crushing technique alone with hepatic inflow occlusion where appropriate. Intraoperative blood loss and perioperative blood transfusion requirements were significantly less for patients in the LigaSure group. LigaSure-assisted hepatic resection was generally performed more quickly than the conventional clamp-crushing technique. The overall maximum postoperative AST, ALT, and bilirubin serum levels were similar in the two groups, as was the incidence of major postoperative complications. The LigaSure device in this randomized study is safe and simple to use, resulting in less perioperative blood loss and transfusion requirement during hepatic parenchymal transection.

  12. Wafer-scale controlled exfoliation of metal organic vapor phase epitaxy grown InGaN/GaN multi quantum well structures using low-tack two-dimensional layered h-BN

    NASA Astrophysics Data System (ADS)

    Ayari, Taha; Sundaram, Suresh; Li, Xin; El Gmili, Youssef; Voss, Paul L.; Salvestrini, Jean Paul; Ougazzaden, Abdallah

    2016-04-01

    Recent advances in epitaxial growth have led to the growth of III-nitride devices on 2D layered h-BN. This advance has the potential for wafer-scale transfer to arbitrary substrates, which could improve the thermal management and would allow III-N devices to be used more flexibly in a broader range of applications. We report wafer scale exfoliation of a metal organic vapor phase epitaxy grown InGaN/GaN Multi Quantum Well (MQW) structure from a 5 nm thick h-BN layer that was grown on a 2-inch sapphire substrate. The weak van der Waals bonds between h-BN atomic layers break easily, allowing the MQW structure to be mechanically lifted off from the sapphire substrate using a commercial adhesive tape. This results in the surface roughness of only 1.14 nm on the separated surface. Structural characterizations performed before and after the lift-off confirm the conservation of structural properties after lift-off. Cathodoluminescence at 454 nm was present before lift-off and 458 nm was present after. Electroluminescence near 450 nm from the lifted-off structure has also been observed. These results show that the high crystalline quality ultrathin h-BN serves as an effective sacrificial layer—it maintains performance, while also reducing the GaN buffer thickness and temperature ramps as compared to a conventional two-step growth method. These results support the use of h-BN as a low-tack sacrificial underlying layer for GaN-based device structures and demonstrate the feasibility of large area lift-off and transfer to any template, which is important for industrial scale production.

  13. Recent Developments in Microsystems Fabricated by the Liga-Technique

    NASA Technical Reports Server (NTRS)

    Schulz, J.; Bade, K.; El-Kholi, A.; Hein, H.; Mohr, J.

    1995-01-01

    As an example of microsystems fabricated by the LIGA-technique (x-ray lithography, electroplating and molding), three systems are described and characterized: a triaxial acceleration sensor system, a micro-optical switch, and a microsystem for the analysis of pollutants. The fabrication technologies are reviewed with respect to the key components of the three systems: an acceleration sensor, and electrostatic actuator, and a spectrometer made by the LIGA-technique. Aa micro-pump and micro-valve made by using micromachined tools for molding and optical fiber imaging are made possible by combining LIGA and anisotropic etching of silicon in a batch process. These examples show that the combination of technologies and components is the key to complex microsystems. The design of such microsystems will be facilitated is standardized interfaces are available.

  14. Ulnar Impaction Syndrome: Ulnar Shortening vs. Arthroscopic Wafer Procedure

    PubMed Central

    Smet, Luc De; Vandenberghe, Lore; Degreef, Ilse

    2014-01-01

    The outcome of ulnar shortenings was compared with that of arthroscopic wafer resections for ulnar impaction (or abutment) syndrome in patients with a positive ulnar variance. The outcome was measured by DASH score, visual analog scale for pain, and working incapacity. The mean DASH score in the ulnar shortening group was 26; in the wafer group it was 36. The VAS scores were respectively 4.4 and 4.6. The working incapacity was 7?months in the ulnar shortening group and 6.1 months in the wafer group. The differences between the two groups were not statistically significant. PMID:25032075

  15. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  16. A LIGA Fabricated Quadrupole Array for Mass Spectroscopy

    NASA Technical Reports Server (NTRS)

    Jackson, K.; Wiberg, D. V.; Hecht, M. H.; Orient, O. J.; Chutjian, A.; Yee, K.; Fuerstenau, S.; Brennen, R. A.; Hruby, J.; Bonivert, W.

    1997-01-01

    A linear array of nine quadrupoles was fabricated using the LIGA process. Pole heights ranging from 1 to 3 mm were fabricated using synchrotron X-ray exposures to form free standing polymethylmethacrylate (PMMA) molds into which copper, gold or nickel were electroplated.

  17. Wafer-Level Vacuum Packaging of Smart Sensors.

    PubMed

    Hilton, Allan; Temple, Dorota S

    2016-10-31

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  18. Wafer-Level Vacuum Packaging of Smart Sensors

    PubMed Central

    Hilton, Allan; Temple, Dorota S.

    2016-01-01

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology. PMID:27809249

  19. System for slicing wafers

    NASA Technical Reports Server (NTRS)

    1982-01-01

    A newly patented process for slicing silicon wafers that has distinct advantages over methods now widely used is described. The primary advantage of the new system is that it allows the efficient slicing of a number of ingots simultaneously at high speed. The cutting action is performed mechanically, most often with diamond particles that are transported to the cutting zone by a fluid vehicle or have been made an integral part of the blade by plating or impregnation. The new system uses a multiple or ganged band saw, arranged and spaced so that each side, or length, segment of a blade element, or loop, provides a cutting function. Each blade is maintained precisely in position by guides as it enters and leaves each ingot. The cutting action is performed with a conventional abrasive slurry composed of diamond grit suspended in an oil- or water-based vehicle. The distribution system draws the slurry from the supply reservoir and pumps it to the injection tubes to supply it to each side of each ingot. A flush system is provided at the outer end of the work-station zone. In order to reduce potential damage, a pneumatically driven flushing fluid is provided.

  20. Wafer handling and placement tool

    DOEpatents

    Witherspoon, Linda L.

    1988-01-05

    A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

  1. Note: Near infrared interferometric silicon wafer metrology.

    PubMed

    Choi, M S; Park, H M; Joo, K N

    2016-04-01

    In this investigation, two near infrared (NIR) interferometric techniques for silicon wafer metrology are described and verified with experimental results. Based on the transparent characteristic of NIR light to a silicon wafer, the fiber based spectrally resolved interferometry can measure the optical thickness of the wafer and stitching low coherence scanning interferometry can reconstruct entire surfaces of the wafer.

  2. Wafer dicing utilizing unique beam shapes

    NASA Astrophysics Data System (ADS)

    Lizotte, Todd; Ohar, Orest

    2007-09-01

    Laser dicing of wafers is of keen interest to the semiconductor and LED industry. Devices such as ASICs, Ultra-thin Wafer Scale Packages and LEDS are unique in that they typically are formed from various materials in a multilayered structure. Many of these layers include active device materials, passivation coatings, conductors and dielectric films all deposited on top of a bulk wafer substrate and all potentially having differing ablation thresholds. These composite multi-layered structures require high finesse laser processes to ensure yields, cut quality and low process cost. Such processes have become very complex over the years as new devices have become miniaturized, requiring smaller kerf sizes. Of critical concern is the need to minimize substrate micro-cracking or lift off of upper layers along the dicing streets which directly corresponds to bulk device strength and device operational integrity over its projected lifetime. Laser processes involving the sequential use of single or multiple diode pumped solid state (DPSS) lasers, such as UV DPSS (355nn, 266nm, 532 nm), VIS DPSS (~532 nm) and IR DPSS (1064nm, 1070nm) as well as (UV, VIS, NIR, FIR and Eye Safe Wavelengths) DPFL (Diode Pumped Fiber Lasers) lasers to penetrate various and differing material layers and substrates including Silicon Carbide (SiC), Silicon, GaAs and Sapphire. Development of beam shaping optics with the purpose of permitting two or more differing energy densities within a single focused or imaged beam spot would provide opportunities for pre-processing or pre-scribing of thinner cover layers, while following through with a higher energy density segment to cut through the bulk base substrates. This paper will describe the development of beam shaping optical elements with unique beam shapes that could benefit dicing and patterning of delicate thin film coatings. Various designs will be described, with processing examples using LED wafer materials.

  3. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    PubMed

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

  4. Wafer-Scale Precise Patterning of Organic Single-Crystal Nanowire Arrays via a Photolithography-Assisted Spin-Coating Method.

    PubMed

    Deng, Wei; Zhang, Xiujuan; Wang, Liang; Wang, Jincheng; Shang, Qixun; Zhang, Xiaohong; Huang, Liming; Jie, Jiansheng

    2015-12-02

    A photolithography-assisted spin-coating approach is developed to produce single-crystal organic nanowire (NW) arrays at designated locations with high precision and high efficiency. This strategy enables the large-scale fabrication of organic NW arrays with nearly the same accuracy, reliability, and flexibility as photolithography. The high mobilities of the organic NWs enable the control of the switch of multicolored light-emitting devices with good stability.

  5. Development of Megasonic cleaning for silicon wafers. Final report

    SciTech Connect

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  6. Variants of LIGA technology for the production of plastic microcomponents

    NASA Astrophysics Data System (ADS)

    Singleton, Laurence; Detemple, Peter; Loewe, Holger

    2003-03-01

    Moulding of plastics enables fluidic and optical features to be integrated into a single element. This is particularly an advantage for product designs that impose space and weight constraints. Therefore, the use of plastic for biomedical and non telecommunications orientated optical applications continues to grow as design engineers take advantage of the ease of fabrication and the material flexibility. LIGA presents itself as a method ideally suited for the production of moulds for the manufacture of plastic microcomponents. Although LIGA is synonymous for lithography using synchrotron radiation x-rays, many other lithography and non-lithography methods for master production have been developed in the last few years, offering cost effective solutions to template production. These include UV LIGA methods, where deep resists such as SU-8 and AZ 4562, are employed for the master production. In addition, excimer laser micromachining offers a cost effective and efficient method for master fabrication, which later forms a template for electroforming. Furthermore, the use of Advanced Silicon Etching methods to prestructure silicon templates for electroforming, allows to the production of stepped mould inserts, which are particularly useful for microfluidic applications. This paper provides an overview of the different technologies, emphasizing the strengths and application areas of the different master structuring technologies. Considerations for the electroforming of microstructured mould inserts are also presented.

  7. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R.

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  8. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  9. SVX3 Six Inch Wafer Failure Report

    SciTech Connect

    Yarema, R.

    1999-05-01

    In 1997 an order was placed with Honeywell for 265 four inch SVX3 wafers. After the initial delivery, the processing line at Honeywell was switched to 6 inch wafers. It was quickly apparent that there were serious problems on the 6 inch wafers which were not seen on the 4 inch wafers. Wafers from one of the 6 inch lots generally have a high yield and do not exhibit the center of the wafer via problem. It is not know if bad vias will recover or good vias go bad with time, temperature and radiation.

  10. Smoother Scribing of Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Danyluk, S.

    1986-01-01

    Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

  11. Assembly of LIGA Using Electric Fields

    NASA Astrophysics Data System (ADS)

    Feddema, J. T.; Warne, L. K.; Johnson, W. A.; Ogden, A. J.; Armour, D. L.

    2002-04-01

    The goal of this project was to develop a device that uses electric fields to grasp and possibly levitate LlGA parts. This non-contact form of grasping would solve many of the problems associated with grasping parts that are only a few microns in dimensions. Scaling laws show that for parts this size, electrostatic and electromagnetic forces are dominant over gravitational forces. This is why micro-parts often stick to mechanical tweezers. If these forces can be controlled under feedback control, the parts could be levitated, possibly even rotated in air. In this project, we designed, fabricated, and tested several grippers that use electrostatic and electromagnetic fields to grasp and release metal LlGA parts. The eventual use of this tool will be to assemble metal and non-metal LlGA parts into small electromechanical systems.

  12. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    DOEpatents

    Bajikar, Sateesh S.; De Carlo, Francesco; Song, Joshua J.

    2001-01-01

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  13. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    DOEpatents

    Bajikar, Sateesh S.; De Carlo, Francesco; Song, Joshua J.

    2004-01-27

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  14. NREL Core Program; Session: Wafer Silicon (Presentation)

    SciTech Connect

    Wang, Q.

    2008-04-01

    This project supports the Solar America Initiative by working on: (1) wafer Si accounts for 92% world-wide solar cell production; (2) research to fill the industry R and D pipeline for the issues in wafer Si; (3) development of industry collaborative research; (4) improvement of NREL tools and capabilities; and (5) strengthen US wafer Si research.

  15. Silicon Hybrid Wafer Scale Integration Interconnect Evaluation

    DTIC Science & Technology

    1989-12-01

    the assessment of the current state -of-the-art in electromagnetic analyses to determine its applicability to NVSI interconnections. Weak links or... states that transmission line effects are clearly exhibited when the physical length of any component of an electrical system (include interconnections...assumedl for coniduc- tois and dielectrics. Furthermore, all geometric distances arc assuimedl to bie uniform. unless otherwise stated . This assertion

  16. Wafer Scale Integration of Parallel Processors.

    DTIC Science & Technology

    1982-11-01

    epartment of Computer S( Ie(( e Matih Scienices Buildling Wes(t IdfdCote. Ind(ian~a 1 7%7 45 82 11 29 003 Uclassif ind 5ECUflITY CLASSIFICATION OF THIS...Lafayette, Indiana 47907____________ IL. CONTROLLING0 OFFICE NAME AND ADDRESS 12. REPORT DATE Office of Naval Research November, 1982 Information ...price model , CHiP computer, switch lattice, two level hierarchy, reflective switch, high parallel computers 20. ABST RAC T (Continue on reverse side

  17. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Astrophysics Data System (ADS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-02-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  18. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  19. GEM-type detectors using LIGA and etchable glass technologies

    SciTech Connect

    Ahn, S.K.; Kim, J.G.; Perez-Mendez, V.; Chang, S.; Jackson, K.H.; Kadyk, J.A.; Wenzel, W.A.; Cho, G.

    2001-11-02

    Gas electron multipliers (GEMS) have been made by a deep X-ray lithography technique (LIGA process) using synchrotron radiation on polymethylmethacrylate (PMMA) and by UV processes using a UV etchable glass. Gain, stability and rate capability for these detectors are described.The LIGA detectors described consist of PMMA sheets of various thicknesses, 125mm to 350mm, and have 150mm x 150mm square holes spaced with a pitch of 300mm. Thin copper electrodes are plated on the top and bottom surfaces using a Damascene method, followed by electroless plating of the copper onto a palladium-tin base layer. For various thicknesses of PMMA measurements have been made of absolute gain vs. voltage, time stability of gain, and rate capability. The operating gas mixture was usually Ar/CO2 (70/30) gas, but some tests were also done using P10 gas. We also made GEM-like detectors using the UV etchable glass called Foturan, patterned by exposure to UV light and subsequent etching. A few measurements using these detectors will be reported, including avalanche gain and time stability.

  20. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  1. Long-term results using LigaSure™ 5 mm instrument for treatment of Zenker's diverticulum.

    PubMed

    Andersen, Michelle Fog; Trolle, Waldemar; Anthonsen, Kristian; Nielsen, Hans Ulrik; Homøe, Preben

    2017-04-01

    The purpose of the present study was to evaluate the long-term results and patient's satisfaction of a new approach using the LigaSure™ 5 mm instrument for treatment of Zenker's diverticulum (ZD) and to compare with other long-term results using traditional treatment modalities. Between December 2011 and August 2013, a total of 23 patients with ZD underwent endoscopic surgery using the LigaSure™ technique in our department. A retrospective evaluation of the surgery was based on medical records and additionally a long-term follow-up was performed using a standardized questionnaire that was send to all patients. The questions dealt with complaints according to a visual analog scale (VAS) and were sent a minimum of one year after the surgery (mean time 22 months, range 12-32 month). The overall response rate was 91%. The mean age of the patients was 69 years (range 37-89 years). The patients reported nine for overall satisfaction on the VAS (range 0-10: 10 being very content and 0 very uncontent, 25 and 75% quartiles: 7 and 10) regarding the final outcome of their surgery, although several of the patients had continuous symptoms within the first postoperative year. Eight patients (38%) reported no symptoms at all. Our results suggest that endoscopic management of ZD with the LigaSure™ 5 mm instrument is a minimally invasive, fast and safe method with solid long-term outcome with relief of symptoms and patient satisfaction. This new operative instrument was not found inferior to traditional endoscopic techniques and is now the standard treatment method for ZD in our departments.

  2. LIGA-based microsystem manufacturing:the electrochemistry of through-mold depostion and material properties.

    SciTech Connect

    Kelly, James J. (Sandia National Laboratories, Livermore, CA); Goods, Steven Howard (Sandia National Laboratories, Livermore, CA)

    2005-06-01

    The report presented below is to appear in ''Electrochemistry at the Nanoscale'', Patrik Schmuki, Ed. Springer-Verlag, (ca. 2005). The history of the LIGA process, used for fabricating dimensional precise structures for microsystem applications, is briefly reviewed, as are the basic elements of the technology. The principal focus however, is on the unique aspects of the electrochemistry of LIGA through-mask metal deposition and the generation of the fine and uniform microstructures necessary to ensure proper functionality of LIGA components. We draw from both previously published work by external researchers in the field as well as from published and unpublished studies from within Sandia.

  3. Non-Reciprocal on Wafer Microwave Devices

    DTIC Science & Technology

    2015-05-27

    materials for on-wafer microwave devices concentrated on barium hexagonal ferrite (BaM) films grown on Si because these material is a good candidate...SECURITY CLASSIFICATION OF: We studied the growth, structural and magnetic properties of the hexagonal ferrite (BaAlxFe12-xO19) films on a surface of...Pt template/Si wafer. We determine that our hexagonal ferrite films are highly textured, with the c axis perpendicular to the Si wafer surface and

  4. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    DOEpatents

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  5. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  6. Stress Voiding During Wafer Processing

    SciTech Connect

    Yost, F.G.

    1999-03-01

    Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

  7. Low-loss LIGA-micromachined conductor-backed coplanar waveguide.

    SciTech Connect

    Forman, Michael A.

    2004-12-01

    A mesoscale low-loss LIGA-micromachined conductor-backed coplanar waveguide is presented. The 517 {micro}m lines are the tallest uniplanar LIGA-fabricated microwave transmission lines to date, as well as the first to be constructed of copper rather than nickel. The conductor-backed micromachined CPW on quartz achieves a measured attenuation of 0.064 dB/cm at 15.5 GHz.

  8. Mechanics of the pad-abrasive-wafer contact in chemical mechanical polishing

    NASA Astrophysics Data System (ADS)

    Bozkaya, Dincer

    2009-12-01

    In chemical mechanical polishing (CMP), a rigid wafer is forced on a rough, elastomeric polishing pad, while a slurry containing abrasive particles flows through the interface. The applied pressure on the wafer is carried partially by the 2-body pad-wafer contact (direct contact) and partially by the 3-body contact of pad, wafer and abrasive particles ( particle contact). The fraction of the applied pressure carried by particle contacts is an important factor affecting the material removal rate (MRR) as the majority of the material is removed by the abrasive particles trapped between the pad asperities and the wafer. In this thesis, the contact of a rough, deformable pad and a smooth, rigid wafer in the presence of rigid abrasive particles at the contact interface is investigated by using contact mechanics and finite element (FE) modeling. The interactions between the pad, the wafer and the abrasive particles are modeled at different scales of contact, starting from particle level interactions, and gradually expanding the contact scale to the multi-asperity contact of pad and wafer. The effect of surface forces consisting of van der Waals and electrical double layer forces acting between the wafer and the abrasive particles are also investigated in this work. The wear rate due to each abrasive particle is calculated based on the wafer-abrasive particle contact force, and by considering adhesive and abrasive wear mechanisms. A passivated layer on the wafer surface with a hardness and thickness determined by the chemical effects is modeled, in order to characterize the effect of chemical reactions between slurry and wafer on the MRR. The model provides accurate predictions for the MRR as a function of pad related parameters; pad elastic modulus, pad porosity and pad topography, particle related parameters; particle size and concentration, and slurry related parameters; slurry pH, thickness and hardness of the passivated surface layer of wafer. A good qualitative

  9. Preparation and Characterization of PZT Wafers

    NASA Astrophysics Data System (ADS)

    Seal, A.; Rao, B. S. S. Chandra; Kamath, S. V.; Sen, A.; Maiti, H. S.

    2008-07-01

    Piezoelectric materials have recently attracted a lot of attention for ultrasonic structural health monitoring (shm) in aerospace, defence and civilian sectors, where they can act as both actuators and sensors. Incidentally, piezoelectric materials in the form of wafers (pwas-piezoelectric wafer active sensor, approx. 5-10 mm square and 0.2-0.3 mm thickness) are inexpensive, non intrusive and non-resonant wide band devices that can be surface-mounted on existing structures, inserted between the layers of lap joints or embedded inside composite materials. The material of choice for piezoelectric wafers is lead zirconate titanate (PZT) of composition close to morphotropic phase boundary [pb(zr0.52 ti0.48)o3]. However, an excess pbo is normally added to pzt as a densification aid and also to make up for the lead loss during high temperature sintering. Hence, it is of paramount importance to know how the shift of the lead content from the morphotropic composition affects the piezoelectric and mechanical properties of the sintered wafers, keeping in view the importance of mechanical properties of wafers in shm. In the present study, we observed that with the increase in the lead content of the sintered wafers, the dielectric and piezoelectric constants decreased. However, the elastic modulus, hardness and fracture toughness of the wafers increased with increasing lead content in the composition. Hence, the lead content in the sintered wafers should be optimized to get acceptable piezoelectric and mechanical

  10. Methane production using resin-wafer electrodeionization

    DOEpatents

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  11. An aluminum resist substrate for microfabrication by LIGA.

    SciTech Connect

    Kelly, James J.; Boehme, Dale R.; Hauck, Cheryl A.; Yang, Chu-Yeu Peter; Hunter, Luke L.; Griffiths, Stewart K.; McLean, Dorrance E.; Aigeldinger, Georg; Hekmaty, Michelle A.; Hachman, John T.; Losey, Matthew W.; Skala, Dawn M.; Korellis, John S.; Friedmann, Thomas Aquinas; Yang, Nancy Y. C.; Lu, Wei-Yang

    2005-04-01

    Resist substrates used in the LIGA process must provide high initial bond strength between the substrate and resist, little degradation of the bond strength during x-ray exposure, acceptable undercut rates during development, and a surface enabling good electrodeposition of metals. Additionally, they should produce little fluorescence radiation and give small secondary doses in bright regions of the resist at the substrate interface. To develop a new substrate satisfying all these requirements, we have investigated secondary resist doses due to electrons and fluorescence, resist adhesion before exposure, loss of fine features during extended development, and the nucleation and adhesion of electrodeposits for various substrate materials. The result of these studies is a new anodized aluminum substrate and accompanying methods for resist bonding and electrodeposition. We demonstrate successful use of this substrate through all process steps and establish its capabilities via the fabrication of isolated resist features down to 6 {micro}m, feature aspect ratios up to 280 and electroformed nickel structures at heights of 190 to 1400 {micro}m. The minimum mask absorber thickness required for this new substrate ranges from 7 to 15 {micro}m depending on the resist thickness.

  12. Micro cycloid-gear system fabricated by multiexposure LIGA technique

    NASA Astrophysics Data System (ADS)

    Hirata, Toru; Chung, Song-Jo; Hein, Herbert; Akashi, Tomoyuki; Mohr, Juergen

    1999-09-01

    In this paper, a prototype of 2 mm-diameter micro-cycloid gear system fabricated by the multi-exposure LIGA technique is presented. The entire gear system consists of a casing and three vertically stacked disks and gears. Each part is composed of three different levels. The first level, 40 micrometers high, was fabricated by UV-lithography, and the second as well as the third level, 195 micrometers and 250 micrometers high respectively, were processed by aligned deep X-ray lithography (DXL). The alignment error between two DXL- processed layers was measured, and the results have turned out to be within +/- 5 micrometers range. As a result of the height control process by the mechanical surface machining, the deviation of structural height has been maintained within +/- 3 micrometers range for the UV-lithography-processed structures, and +/- 10 micrometers for the DXL-processed structures. Further the tests of gear assembly were implemented with 125 micrometers -diameter glass fiber, by using a die-bonding machine with vacuum gripper under stereo- microscope. Finally the dynamic tests of the gear system were successfully conducted with the mechanical torque input by an electrical motor. A proper rotational speed reduction was observed in the operational input range of 3 to 1500 rpm with the designed gear ratio of 18.

  13. LIGA-fabricated compact mm-wave linear accelerator cavities.

    SciTech Connect

    Song, J.J.; Bajikar, S.S.; DeCarlo, F.; Kang, Y.W.; Kustom, R.L.; Mancini, D.C.; Nassiri, A.; Lai, B.; Feinerman, A.D.; White, V.

    1998-03-23

    Millimeter-wave rf cavities for use in linear accelerators, free-electron lasers, and mm-wave undulatory are under development at Argonne National Laboratory. Typical cavity dimensions are in the 1000 mm range, and the overall length of the accelerator structure, which consists of 30-100 cavities, is about 50-100 mm. An accuracy of 0.2% in the cavity dimensions is necessary in order to achieve a high Q-factor of the cavity. To achieve this these structures are being fabricated using deep X-ray lithography, electroforming, and assembly (LIGA). The first prototype cavity structures are designed for 108 GHz and 2p/3-mode operation. Input and output couplers are integrated with the cavity structures. The cavities are fabricated on copper substrates by electroforming copper into 1-mm-thick PMMA resists patterned by deep x-ray lithography and polishing the copper down to the desired thickness. These are fabricated separately and subsequently assembled with precision spacing and alignment using microspheres, optical fibers, or microfabricated spacers/alignment pieces. Details of the fabrication process, alignment, and assembly work are presented in here.

  14. Switchable static friction of piezoelectric composite—silicon wafer contacts

    NASA Astrophysics Data System (ADS)

    van den Ende, D. A.; Fischer, H. R.; Groen, W. A.; van der Zwaag, S.

    2013-04-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and a silicon wafer counter surface rests solely on the matrix region of the piezocomposite surface. When actuated, the piezoelectric ceramic fibers protrude from the surface and the wafer rests solely on these protrusions. A threefold decrease in engineering static friction coefficient upon actuation of the piezocomposite was observed: from μ* = 1.65 to μ* = 0.50. These experimental results could be linked to the change in contact surface area and roughness using capillary adhesion theory, which relates the adhesive force to the number and size of the contacting asperities for the different surface states.

  15. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  16. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  17. Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

    NASA Technical Reports Server (NTRS)

    Jones, G. T.; Rhee, S. S.

    1979-01-01

    Several aspects of silicon wafer surface texturizing were studied. A low cost cleaning method that utilizes recycled Freon in an ultrasonic vapor degreaser to remove organic and inorganic contaminants from the surface of silicon wafers as received from silicon suppliers was investigated. The use of clean dry air and high throughout wafer batch drying techniques was shown to lower the cost of wafer drying. A two stage texturizing process was examined for suitability in large scale production. Also, an in-depth gettering study with the two stage texturizing process was performed for the enhancement of solar cell efficiency, minimization of current versus voltage curve dispersion, and improvement in process reproducibility. The 10% efficiency improvement goal was exceeded for the near term implementation of flat plate photovoltaic cost reduction.

  18. Universal segregation growth approach to wafer-size graphene from non-noble metals.

    PubMed

    Liu, Nan; Fu, Lei; Dai, Boya; Yan, Kai; Liu, Xun; Zhao, Ruiqi; Zhang, Yanfeng; Liu, Zhongfan

    2011-01-12

    Graphene has been attracting wide interests owing to its excellent electronic, thermal, and mechanical performances. Despite the availability of several production techniques, it is still a great challenge to achieve wafer-size graphene with acceptable uniformity and low cost, which would determine the future of graphene electronics. Here we report a universal segregation growth technique for batch production of high-quality wafer-scale graphene from non-noble metal films. Without any extraneous carbon sources, 4 in. graphene wafers have been obtained from Ni, Co, Cu-Ni alloy, and so forth via thermal annealing with over 82% being 1-3 layers and excellent reproducibility. We demonstrate the first example of monolayer and bilayer graphene wafers using Cu-Ni alloy by combining the distinct segregation behaviors of Cu and Ni. Together with the easy detachment from growth substrates, we believe this facile segregation technique will offer a great driving force for graphene research.

  19. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  20. Forming electrical interconnections through semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Anthony, T. R.

    1981-01-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  1. A model for reaction-assisted polymer dissolution in LIGA.

    SciTech Connect

    Larson, Richard S.

    2004-05-01

    A new chemically-oriented mathematical model for the development step of the LIGA process is presented. The key assumption is that the developer can react with the polymeric resist material in order to increase the solubility of the latter, thereby partially overcoming the need to reduce the polymer size. The ease with which this reaction takes place is assumed to be determined by the number of side chain scissions that occur during the x-ray exposure phase of the process. The dynamics of the dissolution process are simulated by solving the reaction-diffusion equations for this three-component, two-phase system, the three species being the unreacted and reacted polymers and the solvent. The mass fluxes are described by the multicomponent diffusion (Stefan-Maxwell) equations, and the chemical potentials are assumed to be given by the Flory-Huggins theory. Sample calculations are used to determine the dependence of the dissolution rate on key system parameters such as the reaction rate constant, polymer size, solid-phase diffusivity, and Flory-Huggins interaction parameters. A simple photochemistry model is used to relate the reaction rate constant and the polymer size to the absorbed x-ray dose. The resulting formula for the dissolution rate as a function of dose and temperature is ?t to an extensive experimental data base in order to evaluate a set of unknown global parameters. The results suggest that reaction-assisted dissolution is very important at low doses and low temperatures, the solubility of the unreacted polymer being too small for it to be dissolved at an appreciable rate. However, at high doses or at higher temperatures, the solubility is such that the reaction is no longer needed, and dissolution can take place via the conventional route. These results provide an explanation for the observed dependences of both the dissolution rate and its activation energy on the absorbed dose.

  2. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  3. ALD Enabled Wafer Level Polymer Packaging for MEMS

    NASA Astrophysics Data System (ADS)

    Zhang, Yadong

    Wafer level polymer packaging for MEMS is a cost-effective approach that is also compatible with microelectronic packaging technologies. However, polymer packages are not hermetic and cannot be used for MEMS devices, which usually demand vacuum or low moisture environment inside the packages. This problem can be solved by applying atomic layer deposition (ALD) of nano-scaled Al 2O3 or other inorganic materials over the polymer packages. Defects and mechanical cracks in ALD coatings are major concerns for hermetic/vacuum sealing. Several techniques have been developed to inspect such defects and cracks. Assisted by the electroplating copper technique, we have reduced the defect density by 1000 times for an ultra-thin, 2-nm ALD Al2O 3 film. Such an ultra-thin coating is essential to enhance coating's mechanical toughness. The toughness is usually determined by monitoring coating's crack initiation and growth in a bending test. A real-time, non-destructive inspection technique has been developed for in-situ characterization of an ALD film coated on a surface or buried in a multilayer structure. With the knowledge and technology established, we have successfully demonstrated a wafer-level polymer packaging process for MEMS using a Pirani gauge as the vacuum sensor. The leak rate through the polymer package has been reduced by 100 times by the ALD Al2O3 coating. More importantly, we have developed models and identified issues that are critical to ALD-enabled wafer level polymer packaging for MEMS.

  4. The Imaging Properties of a Silicon Wafer X-Ray Telescope

    NASA Technical Reports Server (NTRS)

    Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

    1994-01-01

    Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

  5. Porous solid ion exchange wafer for immobilizing biomolecules

    DOEpatents

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  6. Improvement of focus accuracy on processed wafer

    NASA Astrophysics Data System (ADS)

    Higashibata, Satomi; Komine, Nobuhiro; Fukuhara, Kazuya; Koike, Takashi; Kato, Yoshimitsu; Hashimoto, Kohji

    2013-04-01

    As feature size shrinkage in semiconductor device progress, process fluctuation, especially focus strongly affects device performance. Because focus control is an ongoing challenge in optical lithography, various studies have sought for improving focus monitoring and control. Focus errors are due to wafers, exposure tools, reticles, QCs, and so on. Few studies are performed to minimize the measurement errors of auto focus (AF) sensors of exposure tool, especially when processed wafers are exposed. With current focus measurement techniques, the phase shift grating (PSG) focus monitor 1) has been already proposed and its basic principle is that the intensity of the diffraction light of the mask pattern is made asymmetric by arranging a π/2 phase shift area on a reticle. The resist pattern exposed at the defocus position is shifted on the wafer and shifted pattern can be easily measured using an overlay inspection tool. However, it is difficult to measure shifted pattern for the pattern on the processed wafer because of interruptions caused by other patterns in the underlayer. In this paper, we therefore propose "SEM-PSG" technique, where the shift of the PSG resist mark is measured by employing critical dimension-scanning electron microscope (CD-SEM) to measure the focus error on the processed wafer. First, we evaluate the accuracy of SEM-PSG technique. Second, by applying the SEM-PSG technique and feeding the results back to the exposure, we evaluate the focus accuracy on processed wafers. By applying SEM-PSG feedback, the focus accuracy on the processed wafer was improved from 40 to 29 nm in 3σ.

  7. Integrating III-V compound semiconductors with silicon using wafer bonding

    NASA Astrophysics Data System (ADS)

    Zhou, Yucai

    2000-12-01

    From Main Street to Wall Street, everyone has felt the effects caused by the Internet revolution. The Internet has created a new economy in the New Information Age and has brought significant changes in both business and personal life. This revolution has placed strong demands for higher bandwidth and higher computing speed due to high data traffic on today's information highway. In order to alleviate this problem, growing interconnection bottlenecks in digital designs have to be solved. The most feasible and practical way is to replace the conventional electrical interconnect with an optical interconnect. Since silicon does not have the optical properties necessary to accommodate these optical interconnect requirements, III-V based devices, most of which are GaAs-based or InP-based, must be intimately interconnected with the Si circuit at chip level. This monolithic integration technology enables the development of both intrachip and interchip optical connectors to take advantage of the enormous bandwidth provided by both high-performance very-large-scale integrated (VLSI) circuits and allied fiber and free-space optical technologies. However, lattice mismatch and thermal expansion mismatches between III-V materials and Si create enormous challenges for developing a feasible technology to tackle this problem. Among all the available approaches today, wafer bonding distinguishes itself as the most promising technology for integration due to its ability to overcome the constraints of both lattice constant mismatch and thermal expansion coefficient differences and even strain due to the crystal orientation. We present our development of wafer bonding technology for integrating III-V with Si in my dissertation. First, the pick-and-place multiple-wafer bonding technology was introduced. Then we systematically studied the wafer bonding of GaAs and InP with Si. Both high temperature wafer fusion and low/room temperature (LT/RT) wafer bonding have been investigated for

  8. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

  9. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y.; James, Ralph B.

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  10. Stability of laser-propelled wafer satellites

    NASA Astrophysics Data System (ADS)

    Srinivasan, Prashant; Hughes, Gary B.; Lubin, Philip; Zhang, Qicheng; Madajian, Jonathan; Brashears, Travis; Kulkarni, Neeraj; Cohen, Alexander; Griswold, Janelle

    2016-09-01

    For interstellar missions, directed energy is envisioned to drive wafer-scale spacecraft to relativistic speeds. Spacecraft propulsion is provided by a large array of phase-locked lasers, either in Earth orbit or stationed on the ground. The directed-energy beam is focused on the spacecraft, which includes a reflective sail that propels the craft by reflecting the beam. Fluctuations and asymmetry in the beam will create rotational forces on the sail, so the sail geometry must possess an inherent, passive stabilizing effect. A hyperboloid shape is proposed, since changes in the incident beam angle due to yaw will passively counteract rotational forces. This paper explores passive stability properties of a hyperboloid reflector being bombarded by directed-energy beam. A 2D cross-section is analyzed for stability under simulated asymmetric loads. Passive stabilization is confirmed over a range of asymmetries. Realistic values of radiation pressure magnitude are drawn from the physics of light-mirror interaction. Estimates of beam asymmetry are drawn from optical modeling of a laser array far-field intensity using fixed and stochastic phase perturbations. A 3D multi-physics model is presented, using boundary conditions and forcing terms derived from beam simulations and lightmirror interaction models. The question of optimal sail geometry can be pursued, using concepts developed for the baseline hyperboloid. For example, higher curvature of the hyperboloid increases stability, but reduces effective thrust. A hyperboloid sail could be optimized by seeking the minimum curvature that is stable over the expected range of beam asymmetries.

  11. Harmonic versus LigaSure hemostasis technique in thyroid surgery: A meta-analysis.

    PubMed

    Upadhyaya, Arun; Hu, Tianpeng; Meng, Zhaowei; Li, Xue; He, Xianghui; Tian, Weijun; Jia, Qiang; Tan, Jian

    2016-08-01

    Harmonic scalpel and LigaSure vessel sealing systems have been suggested as options for saving surgical time and reducing postoperative complications. The aim of the present meta-analysis was to compare surgical time, postoperative complications and other parameters between them in for the open thyroidectomy procedure. Studies were retrieved from MEDLINE, Cochrane Library, EMBASE and ISI Web of Science until December 2015. All the randomized controlled trials (RCTs) comparing Harmonic scalpel and LigaSure during open thyroidectomy were selected. Following data extraction, statistical analyses were performed. Among the 24 studies that were evaluated for eligibility, 7 RCTs with 981 patients were included. The Harmonic scalpel significantly reduced surgical time compared with LigaSure techniques (8.79 min; 95% confidence interval, -15.91 to -1.67; P=0.02). However, no significant difference was observed for the intraoperative blood loss, postoperative blood loss, duration of hospital stay, thyroid weight and serum calcium level postoperatively in either group. The present meta-analysis indicated superiority of Harmonic Scalpel only in terms of surgical time compared with LigaSure hemostasis techniques in open thyroid surgery.

  12. Total x-ray power measurements in the Sandia LIGA program.

    SciTech Connect

    Malinowski, Michael E. (Sandia National Laboratories, Livermore, CA); Ting, Aili (Sandia National Laboratories, Livermore, CA)

    2005-08-01

    Total X-ray power measurements using aluminum block calorimetry and other techniques were made at LIGA X-ray scanner synchrotron beamlines located at both the Advanced Light Source (ALS) and the Advanced Photon Source (APS). This block calorimetry work was initially performed on the LIGA beamline 3.3.1 of the ALS to provide experimental checks of predictions of the LEX-D (LIGA Exposure- Development) code for LIGA X-ray exposures, version 7.56, the version of the code in use at the time calorimetry was done. These experiments showed that it was necessary to use bend magnet field strengths and electron storage ring energies different from the default values originally in the code in order to obtain good agreement between experiment and theory. The results indicated that agreement between LEX-D predictions and experiment could be as good as 5% only if (1) more accurate values of the ring energies, (2) local values of the magnet field at the beamline source point, and (3) the NIST database for X-ray/materials interactions were used as code inputs. These local magnetic field value and accurate ring energies, together with NIST database, are now defaults in the newest release of LEX-D, version 7.61. Three dimensional simulations of the temperature distributions in the aluminum calorimeter block for a typical ALS power measurement were made with the ABAQUS code and found to be in good agreement with the experimental temperature data. As an application of the block calorimetry technique, the X-ray power exiting the mirror in place at a LIGA scanner located at the APS beamline 10 BM was measured with a calorimeter similar to the one used at the ALS. The overall results at the APS demonstrated the utility of calorimetry in helping to characterize the total X-ray power in LIGA beamlines. In addition to the block calorimetry work at the ALS and APS, a preliminary comparison of the use of heat flux sensors, photodiodes and modified beam calorimeters as total X-ray power

  13. On-wafer high temperature characterization system

    NASA Astrophysics Data System (ADS)

    Teodorescu, L.; ǎghici, F., Dr; Rusu, I.; Brezeanu, G.

    2016-12-01

    In this work a on-wafer high temperature characterization system for wide bandgap semiconductor devices and circuits has been designed, implemented and tested. The proposed system can perform the wafer temperature adjustment in a large domain, from the room temperature up to 3000C with a resolution better than +/-0.50C. In order to obtain both low-noise measurements and low EMI, the heating element of the wafer chuck is supplied in two ways: one is from a DC linear power supply connected to the mains electricity, another one is from a second DC unit powered by batteries. An original temperature control algorithm, different from classical PID, is used to modify the power applied to the chuck.

  14. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  15. Temperature Sensitivity Conferred by ligA Alleles from Psychrophilic Bacteria upon Substitution in Mesophilic Bacteria and a Yeast Species

    PubMed Central

    Pankowski, Jarosław A.; Puckett, Stephanie M.

    2016-01-01

    We have assembled a collection of 13 psychrophilic ligA alleles that can serve as genetic elements for engineering mesophiles to a temperature-sensitive (TS) phenotype. When these ligA alleles were substituted into Francisella novicida, they conferred a TS phenotype with restrictive temperatures between 33 and 39°C. When the F. novicida ligA hybrid strains were plated above their restrictive temperatures, eight of them generated temperature-resistant variants. For two alleles, the mutations that led to temperature resistance clustered near the 5′ end of the gene, and the mutations increased the predicted strength of the ribosome binding site at least 3-fold. Four F. novicida ligA hybrid strains generated no temperature-resistant variants at a detectable level. These results suggest that multiple mutations are needed to create temperature-resistant variants of these ligA gene products. One ligA allele was isolated from a Colwellia species that has a maximal growth temperature of 12°C, and this allele supported growth of F. novicida only as a hybrid between the psychrophilic and the F. novicida ligA genes. However, the full psychrophilic gene alone supported the growth of Salmonella enterica, imparting a restrictive temperature of 27°C. We also tested two ligA alleles from two Pseudoalteromonas strains for their ability to support the viability of a Saccharomyces cerevisiae strain that lacked its essential gene, CDC9, encoding an ATP-dependent DNA ligase. In both cases, the psychrophilic bacterial alleles supported yeast viability and their expression generated TS phenotypes. This collection of ligA alleles should be useful in engineering bacteria, and possibly eukaryotic microbes, to predictable TS phenotypes. PMID:26773080

  16. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  17. Si-gold-glass hybrid wafer bond for 3D-MEMS and wafer level packaging

    NASA Astrophysics Data System (ADS)

    Reddy, Jayaprakash; Pratap, Rudra

    2017-01-01

    We report a relatively low temperature (<400 °C) hybrid wafer bonding process that results in the simultaneous anodic and eutectic bonding in different predetermined regions of the wafer. This hybrid bonding process has potential applications in CMOS-MEMS device integration and wafer level packaging. We demonstrate the process by realizing a simple MEMS cantilever beam and a complex MEMS gyroscope structure. These structures are characterized for ohmic contact and electromechanical response to verify the electrical interconnect and the mechanical strength of the structure at the bond interface.

  18. Methanol Steam Reformer on a Silicon Wafer

    SciTech Connect

    Park, H; Malen, J; Piggott, T; Morse, J; Sopchak, D; Greif, R; Grigoropoulos, C; Havstad, M; Upadhye, R

    2004-04-15

    A study of the reforming rates, heat transfer and flow through a methanol reforming catalytic microreactor fabricated on a silicon wafer are presented. Comparison of computed and measured conversion efficiencies are shown to be favorable. Concepts for insulating the reactor while maintaining small overall size and starting operation from ambient temperature are analyzed.

  19. Bubble-domain circuit wafer evaluation coil set

    NASA Technical Reports Server (NTRS)

    Chen, T. T.; Williams, J. L.

    1975-01-01

    Coil structures have been designed to permit nondestructive testing of bubble wafers. Wafers can be electrically or optically inspected and operated from quasi-static frequency to maximum device operating frequency.

  20. Noncontact sheet resistance measurement technique for wafer inspection

    NASA Astrophysics Data System (ADS)

    Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

    1995-12-01

    A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

  1. Design and simulation of non-resonant 1-DOF drive mode and anchored 2-DOF sense mode gyroscope for implementation using UV-LIGA process

    NASA Astrophysics Data System (ADS)

    Verma, Payal; Gopal, Ram; Butt, M. A.; Khonina, Svetlana N.; Skidanov, Roman V.

    2016-03-01

    This paper presents the design and simulation of a 3-DOF (degree-of-freedom) MEMS gyroscope structure with 1-DOF drive mode and anchored 2-DOF sense mode, based on UV-LIGA technology. The 3-DOF system has the drive resonance located in the flat zone between the two sense resonances. It is an inherently robust structure and offers a high sense frequency band width and high gain without much scaling down the mass on which the sensing comb fingers are attached and it is also immune to process imperfections and environmental conditions. The design is optimized to be compatible with the UV-LIGA process, having 9 μm thick nickel as structural layer. The electrostatic gap between the drive comb fingers is 4 μm and sense comb fingers gap are 4 μm/12 μm. The damping effect is considered by assuming the flexures and the proof mass suspended about 6 μm over the substrate. Accordingly, mask is designed in L-Edit software.

  2. Laser-assisted removal of particles on silicon wafers

    NASA Astrophysics Data System (ADS)

    Vereecke, G.; Röhr, E.; Heyns, M. M.

    1999-04-01

    Laser cleaning is one of the new promising dry cleaning techniques considered by semiconductor companies to replace wet cleans in the near future. A dry laser cleaning tool was tested that uses an inert gas jet to remove particles lifted off by the action of a DUV excimer laser. A model was developed to simulate the cleaning process and analyze the influence of experimental parameters on laser cleaning efficiency. The best cleaning efficiencies obtained with 1.0 μm SiO2, ˜0.3 μm Si3N4, and 0.3 μm SiO2 particles deposited on Si wafers were 84±8%, 33±4%, and 12±7%, respectively. This is in qualitative agreement with theoretical calculations showing the existence of a size threshold for the removal of nonabsorbing particles by dry laser cleaning. Among the process parameters tested to optimize the process efficiency, fluence showed the highest influence on removal efficiency, before the number of laser pulses and the laser repetition rate. The use of high fluences was limited by the damaging of the wafer surface, which was not homogeneous on a macroscopic scale. The optimum number of laser pulses per unit area depended on the type of particle. The laser repetition rate had no significant influence on cleaning efficiency and can be used to reduce process time. The influence of capillary condensation on the process was demonstrated by the higher removal efficiency of 0.3 μm SiO2 and Si3N4 particles, 88±6% and 78%, respectively, upon exposure of wafers to air saturated with moisture prior to laser processing. This was attributed to the explosive evaporation of capillary condensed water, similar to the mechanism proposed for liquid assisted laser cleaning.

  3. Effects of cleaning procedures of silica wafers on their friction characteristics.

    PubMed

    Donose, Bogdan C; Taran, Elena; Vakarelski, Ivan U; Shinto, Hiroyuki; Higashitani, Ko

    2006-07-01

    Silicon wafers with thermal silicon oxide layers were cleaned and hydrophilized by three different methods: (1) the remote chemical analysis (RCA) wet cleaning by use of ammonia and hydrogen peroxide mixture solutions, (2) water-vapor plasma cleaning, and (3) UV/ozone combined cleaning. All procedures were found to remove effectively organic contaminations on wafers and gave identical characteristics of the contact angle, the surface roughness and the normal force interactions, measured by atomic force microscopy (AFM). However, it is found that wafers cleaned by the RCA method have several times larger friction coefficients than those cleaned by the plasma and UV/ozone methods. The difference was explained by the atomic-scale topological difference induced during the RCA cleaning. This study reveals the lateral force microscopy as a very sensitive method to detect the microstructure of surfaces.

  4. Uniaxially strained silicon by wafer bonding and layer transfer

    NASA Astrophysics Data System (ADS)

    Himcinschi, C.; Radu, I.; Muster, F.; Singh, R.; Reiche, M.; Petzold, M.; Gösele, U.; Christiansen, S. H.

    2007-02-01

    Uniaxial strain on wafer-level was realised by mechanically bending and direct wafer bonding of Si wafers in the bent state followed by thinning one of the Si wafers by the smart-cut process. This approach is flexible and allows to obtain different strain values at wafer-level in both tension and compression. UV micro-Raman spectroscopy was used to determine the strain in the thin transferred Si layers. Numerical modelling by 3D finite elements of the strain provided a good description of the experimental results.

  5. A Transdermal Drug Delivery System Based on LIGA Technology and Soft Lithography

    NASA Astrophysics Data System (ADS)

    Matteucci, Marco; Perennes, Frederic; Marmiroli, Benedetta; Di Fabrizio, Enzo

    2007-01-01

    This report presents a transdermal drug delivery system based on LIGA fabricated microparts. It is a portable device combining a magnetically actuated micro gear pump with a microneedle array. The fluidic behaviour of the system is analyzed in order to predict its performance according to the dimension of the microparts and then compared to experimental data. The manufacturing process of both micropump and microneedle array are described.

  6. Diamond-like nanocomposite coatings for LIGA-fabricated nickel alloy parts.

    SciTech Connect

    Prasad, Somuri V.; Scharf, Thomas W.

    2005-03-01

    A commercial plasma enhanced chemical vapor deposition (PECVD) technique with planetary substrate rotation was used to apply a thin (200-400 nm thick) conformal diamond-like carbon (DLC) coating (known as a diamond-like nanocomposite (DLN)) on LIGA fabricated Ni-Mn alloy parts. The PECVD technique is known to overcome the drawbacks associated with the line-of-sight nature of physical vapor deposition (PVD) and substrate heating inherent with traditional chemical vapor deposition (CVD). The purpose of the present study is to characterize the coverage, adhesion, and tribological (friction and wear) behavior of DLN coatings applied to planar and sidewall surfaces of small featured LIGA Ni-Mn fabricated parts, e.g. 280 {micro}m thick sidewalls. Friction and wear tests were performed in dry nitrogen, dry air, and air with 50% RH at Hertzian contact pressures ranging from 0.3 to 0.6 GPa. The friction coefficient of bare Ni-Mn alloy was determined to be 0.9. In contrast, low friction coefficients ({approx}0.02 in dry nitrogen and {approx}0.2 in 50% RH air) and minimal amount of wear were exhibited for the DLN coated LIGA Ni-Mn alloy parts and test coupons. This behavior was due to the ability of the coating to transfer to the rubbing counterface providing low interfacial shear at the sliding contact; resultantly, coating one surface was adequate for low friction and wear. In addition, a 30 nm thick titanium bond layer was determined to be necessary for good adhesion of DLN coating to Ni-Mn alloy substrates. Raman spectroscopy and cross-sectional SEM with energy dispersive x-ray analysis revealed that the DLN coatings deposited by the PECVD with planetary substrate rotation covered both the planar and sidewall surfaces of LIGA fabricated parts, as well as narrow holes of 300 {micro}m (0.012 inch) diameter.

  7. LigaSure meets endobronchial valve in a case of lung cancer with pneumoconiosis

    PubMed Central

    Fiorelli, Alfonso; Accardo, Marina; Vicidomini, Giovanni

    2013-01-01

    Resection of lung cancer associated with pneumoconiosis may be difficult since fibrosis limits the exposure of hilum, and the use of stapler; yet, surgery may be complicated by persistent air leaks due to the underlying disease. In this setting, LigaSure was used to perform the tumor resection, and the postoperative treatment of air leaks in the same patient was treated with placement of endobronchial valves. PMID:25806247

  8. Thermal modeling of wafer-based precision glass molding process

    NASA Astrophysics Data System (ADS)

    Hu, Yang; Shen, Lianguan; Zhou, Jian; Li, Mujun

    2016-10-01

    Wafer based precision glass optics manufacturing has been an innovative approach for combining high accuracy with mass production. However, due to the small ratio of thickness and diameter of the glass wafer, deformation and residual stress would be induced for the nonuniform temperature distribution in the glass wafer after molding. Therefore, thermal modelling of the heating system in the wafer based precision glass molding (PGM) process is of great importance in optimizing the heating system and the technique of the process. The current paper deals with a transient thermal modelling of a self-developed heating system for wafer based PGM process. First, in order to investigate the effect of radiation from the surface and interior of the glass wafer, the thermal modeling is simulated with a discrete ordinates radiation model in the CFD software FLUENT. Temperature distribution of the glass wafer obtained from the simulations is then used to evaluate the performance of heating system and investigate some importance parameters in the model, such as interior and surface radiation in glass wafer, thermal contact conductance between glass wafer and molds, thickness to diameter ratio of glass wafer. Finally, structure modification in the molding chamber is raised to decrease the temperature gradient in the glass wafer and the effect is significant.

  9. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.; St. Martin, Edward; Arora, Michelle; de la Garza, Linda

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  10. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  11. Carbon dioxide capture using resin-wafer electrodeionization

    DOEpatents

    Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

    2015-09-08

    The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

  12. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  13. Wafer plane inspection with soft resist thresholding

    NASA Astrophysics Data System (ADS)

    Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

    2008-10-01

    Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

  14. Precipitating Chromium Impurities in Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Salama, A. M.

    1982-01-01

    Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

  15. Optical characterization of SiC wafers

    SciTech Connect

    Burton, J.C.; Pophristic, M.; Long, F.H.; Ferguson, I.

    1999-07-01

    Raman spectroscopy has been used to investigate wafers of both 4H-SiC and 6H-SiC. The two-phonon Raman spectra from both 4H- and 6H-SiC have been measured and found to be polytype dependent, consistent with changes in the vibrational density of states. They have observed electronic Raman scattering from nitrogen defect levels in both 4H- and 6H-SiC at room temperature. They have found that electronic Raman scattering from the nitrogen defect levels is significantly enhanced with excitation by red or near IR laser light. These results demonstrate that the laser wavelength is a key parameter in the characterization of SiC by Raman scattering. These results suggest that Raman spectroscopy can be used as a noninvasive, in situ diagnostic for SiC wafer production and substrate evaluation. They also present results on time-resolved photoluminescence spectra of n-type SiC wafers.

  16. Mask-to-wafer alignment system

    DOEpatents

    Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

    2003-11-04

    A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

  17. Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size

    NASA Astrophysics Data System (ADS)

    Kim, Hee Yeoun; Yang, Chungmo; Park, Jae Hong; Jung, Ho; Kim, Taehyun; Kim, Kyung Tae; Lim, Sung Kyu; Lee, Sang Woo; Mitchell, Jay; Hwang, Wook Joong; Lee, Kwyro

    2013-06-01

    For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.

  18. Equipment for On-Wafer Testing From 220 to 325 GHz

    NASA Technical Reports Server (NTRS)

    Samoska, Lorene; Peralta, Alejandro; Dawson, Douglas; Lee, Karen; Boll, Greg; Oleson, Chuck

    2006-01-01

    A system of electronic instrumentation, constituting the equivalent of a two-port vector network analyzer, has been developed for use in on-wafer measurement of key electrical characteristics of semiconductor devices at frequencies from 220 to 325 GHz. A prior system designed according to similar principles was reported in Equipment for On-Wafer Testing at Frequencies Up to 220 GHz (NPO-20760), NASA Tech Briefs, Vol. 25, No. 11 (November 2001), page 42. As one would expect, a major source of difficulty in progressing to the present higher-frequency-range system was the need for greater mechanical precision as wavelengths shorten into the millimeter range, approaching the scale of mechanical tolerances of prior systems. The system (see figure) includes both commercial off-the-shelf and custom equipment. As in the system of the cited prior article, the equipment includes test sets that are extended versions of commercial network analyzers that function in a lower frequency range. The extension to the higher frequency range is accomplished by use of custom frequency-extension modules that contain frequency multipliers and harmonic mixers. On-wafer measurement is made possible by waveguide wafer probes that were custom designed and built for this wavelength range, plus an on-wafer calibration substrate designed for use with these probes. In this case, the calibration substrate was specially fabricated by laser milling. The system was used to make the first on-wafer measurements of a semiconductor device in the frequency range from 220 to 320 GHz. Some of the measurement results showed that the device had gain.

  19. Compliant membranes improve resolution in full-wafer micro/nanostencil lithography.

    PubMed

    Sidler, Katrin; Villanueva, Luis G; Vazquez-Mena, Oscar; Savu, Veronica; Brugger, Juergen

    2012-02-07

    This work reports on a considerable resolution improvement of micro/nanostencil lithography when applied on full-wafer scale by using compliant membranes to reduce gap-induced pattern blurring. Silicon nitride (SiN) membranes are mechanically decoupled from a rigid silicon (Si) frame by means of four compliant, protruding cantilevers. When pressing the stencil into contact with a surface to be patterned, the membranes thus adapt to the surface independently and reduce the gap between the membrane and the substrate even over large, uneven surfaces. Finite element modeling (FEM) simulations show that compliant membranes can deflect vertically 40 μm which is a typical maximal non-planarity observed in standard Si wafers, due to polishing. Microapertures in the stencil membrane are defined by UV lithography and nanoapertures, down to 200 nm in diameter, using focused ion beam (FIB). A thin aluminium (Al) layer is deposited through both compliant and non-compliant membranes on a Si wafer, for comparison. The blurring in the case of compliant membranes is up to 95% reduced on full-wafer scale compared to standard (non-compliant) membranes.

  20. Method of bond strength evaluation for silicon direct wafer bonding

    NASA Astrophysics Data System (ADS)

    Spivak, Alexander; Avagyan, Avag; Davies, Brady R.

    2001-09-01

    A crack-opening method used for characterization of silicon direct wafer bonding (DWB) techniques was analyzed. Mathematical model describing the influence of the pattern shape on the wafer pair resistance curve, so-called the R-curve, was developed. Two-dimensional patterns were created on a mirror-polished silicon wafer surface by a combination of photolithography, deposition and etching steps. Experimental observations did show that structured wafers can be used for large bond energy measurements. We propose utilization of structured wafers for bond energy measurements. It allows R-curve shape manipulation, increases the method sensitivity, and reduces probability of wafer failure. The resulting theory can also be used for developing new experimental methods for large bond energy measurements.

  1. Brewster's angle silicon wafer terahertz linear polarizer.

    PubMed

    Wojdyla, Antoine; Gallot, Guilhem

    2011-07-18

    We present a new cost-effective terahertz linear polarizer made from a stack of silicon wafers at Brewster's angle, andevaluate its performances. We show that this polarizer is wide-band, has a high extinction ratio (> 6 × 10(3)) and very small insertion losses (< 1%). We provide measurements of the temporal waveforms after linearly polarizing the THz beam and show that there is no distortion of the pulse. We compare its performances with a commercial wire-grid polarizer, and show that the Brewster's angle polarizer can conveniently be used to control the power of a terahertz beam.

  2. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  3. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  4. Beginning-to-end wafer bonding for advanced optical systems

    NASA Astrophysics Data System (ADS)

    Farrens, Shari N.; Lindner, Paul; Dwyer, Steven; Wimplinger, Markus

    2003-11-01

    The old adage "Work Smarter, Not Harder" is certainly applicable in today's competitive marketplace for Optical MEMS. In order to survive the current economic conditions, high volume manufacturers must get optimum performance and yield from each design and manufactured component. Wafer bonding, and its numerous variants, is entering mainstream production environments by providing solutions throughout the production flow. For example, SOI (silicon on insulator) and other laminated materials such as GaAs/Si are used as cost effective alternatives to molecular epitaxy methods for Bragg mirrors, rf resonators, and hybrid device fabrication. Temporary wafer bonding is used extensively to allow fragile compound semiconductors to be attached to rigid support wafers. This allows for front side and backside processing with a reduction in wafer breakage and increases in thickness uniformity results after backgrind operations. Permanent wafer bonding is used to attach compound semiconductors to each other or silicon to completely integrate optical components and logic or MEMS components. Permanent hermetic sealing is used for waveguide formation and, when combined with vacuum sealing, higher performance is achieved for RF resonators. Finally, many of the low temperature solders and eutectic alloys are finding application in low temperature wafer-to-wafer level packaging of optical devices to ceramic packages. Through clever application of these bonding methods, throughput increases and reduction in fabrication complexity givs a clear edge in the market place. This presentation will provide guidelines and process overviews needed to adopt wafer-to-wafer bonding technologies into the high volume-manufacturing environment.

  5. Dominant factors of the laser gettering of silicon wafers

    SciTech Connect

    Bokhan, Yu. I. E-mail: yuibokhan@gmail.com; Kamenkov, V. S.; Tolochko, N. K.

    2015-02-15

    The laser gettering of silicon wafers is experimentally investigated. The typical gettering parameters are considered. The surfaces of laser-treated silicon wafers are investigated by microscopy. When studying the effect of laser radiation on silicon wafers during gettering, a group of factors determining the conditions of interaction between the laser beam and silicon-wafer surface and affecting the final result of treatment are selected. The main factors determining the gettering efficiency are revealed. Limitations on the desired value of the getter-layer capacity on surfaces with insufficiently high cleanness (for example, ground or matte) are established.

  6. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M.

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  7. Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections

    NASA Astrophysics Data System (ADS)

    Lin, Chiung-Wen; Yang, Hsueh-An; Wang, Wei Chung; Fang, Weileun

    2007-06-01

    Packaging is an emerging technology for microsystem integration. The silicon-on-insulator (SOI) wafer has been extensively employed for micromachined devices for its reliable fabrication steps and robust structures. This research reports a packaging approach for silicon-on- insulator-micro-electro-mechanical system (SOI-MEMS) devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling and electroplating. These vias provide electrical signal paths to the MEMS device, while isolating MEMS devices from the outer environment. A high-strength hermetic sealing is then achieved after anodic bonding of the through-wafer-vias-embedded SOI wafer to a Pyrex 7740 glass. Moreover, the packaged SOI-MEMS chip is compatible with surface mount technology, and provides a superior way for 3D heterogeneous integration.

  8. Multi-dimensional multi-species modeling of transient electrodeposition in LIGA microfabrication.

    SciTech Connect

    Evans, Gregory Herbert; Chen, Ken Shuang

    2004-06-01

    This report documents the efforts and accomplishments of the LIGA electrodeposition modeling project which was headed by the ASCI Materials and Physics Modeling Program. A multi-dimensional framework based on GOMA was developed for modeling time-dependent diffusion and migration of multiple charged species in a dilute electrolyte solution with reduction electro-chemical reactions on moving deposition surfaces. By combining the species mass conservation equations with the electroneutrality constraint, a Poisson equation that explicitly describes the electrolyte potential was derived. The set of coupled, nonlinear equations governing species transport, electric potential, velocity, hydrodynamic pressure, and mesh motion were solved in GOMA, using the finite-element method and a fully-coupled implicit solution scheme via Newton's method. By treating the finite-element mesh as a pseudo solid with an arbitrary Lagrangian-Eulerian formulation and by repeatedly performing re-meshing with CUBIT and re-mapping with MAPVAR, the moving deposition surfaces were tracked explicitly from start of deposition until the trenches were filled with metal, thus enabling the computation of local current densities that potentially influence the microstructure and frictional/mechanical properties of the deposit. The multi-dimensional, multi-species, transient computational framework was demonstrated in case studies of two-dimensional nickel electrodeposition in single and multiple trenches, without and with bath stirring or forced flow. Effects of buoyancy-induced convection on deposition were also investigated. To further illustrate its utility, the framework was employed to simulate deposition in microscreen-based LIGA molds. Lastly, future needs for modeling LIGA electrodeposition are discussed.

  9. Breakthrough UV LIGA Microfabrication of Sub-mm and THz Circuits

    DTIC Science & Technology

    2013-01-01

    showcased in a demonstration 220 GHz serpentine waveguide amplifier tube [5] in a companion paper [6]. II. THE TOLERANCE CHALLENGE Fig. 1 compares two...and (d) 1.5 THz. REFERENCES [1] A. M. Cook, et al., “Wideband W-band Serpentine Waveguide TWT,” these proceedings. [2] J. H. Booske, et al...filed March 15, 2012; inventor: C. D. Joye. [5] C. D. Joye, et al, “3D UV-LIGA Microfabricated Circuits for a Wideband 50W G-band Serpentine

  10. Wafer-level assembly and sealing of a MEMS nanoreactor for in situ microscopy

    NASA Astrophysics Data System (ADS)

    Mele, L.; Santagata, F.; Pandraud, G.; Morana, B.; Tichelaar, F. D.; Creemer, J. F.; Sarro, P. M.

    2010-08-01

    This paper presents a new process for the fabrication of MEMS-based nanoreactors for in situ atomic-scale imaging of nanoparticles under relevant industrial conditions. The fabrication of the device is completed fully at wafer level in an ISO 5 clean room and it is based on silicon fusion bonding and thin film encapsulation for sealed lateral electrical feedthroughs. The fabrication process considerably improves the performances of previous nanoreactors. The wafer-level assembly allows faster preparation of devices, hydrocarbon contamination is no longer observed and the control of the channel height leads to a better flow reproducibility. The channel is shown to be sufficiently hermetic to work in the vacuum of a transmission electron microscope while a pressure of 100 kPa is maintained inside the nanoreactor. The transparency is demonstrated by the atomic scale imaging of YBCO nanoparticles, with a line spacing resolution of 0.19 nm.

  11. High-throughput automatic defect review for 300mm blank wafers with atomic force microscope

    NASA Astrophysics Data System (ADS)

    Zandiatashbar, Ardavan; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

    2015-03-01

    While feature size in lithography process continuously becomes smaller, defect sizes on blank wafers become more comparable to device sizes. Defects with nm-scale characteristic size could be misclassified by automated optical inspection (AOI) and require post-processing for proper classification. Atomic force microscope (AFM) is known to provide high lateral and the highest vertical resolution by mechanical probing among all techniques. However, its low throughput and tip life in addition to the laborious efforts for finding the defects have been the major limitations of this technique. In this paper we introduce automatic defect review (ADR) AFM as a post-inspection metrology tool for defect study and classification for 300 mm blank wafers and to overcome the limitations stated above. The ADR AFM provides high throughput, high resolution, and non-destructive means for obtaining 3D information for nm-scale defect review and classification.

  12. Laser-Induced Diode Linking for Wafer-Scale Integration

    DTIC Science & Technology

    1989-03-16

    JMAX IS THE LIMIT FOR THE TOTAL NUM3ER OF STEPS C K IS THE NUMBER OF POINTS USED IN THE EXTRAPOLATION 51 Aug 3 08:33 1987 /ul/ssc/theta/teta.F...SUBROUTINE CARRIES THE INTEGRATION C EPS IS THE FRACTIONAL ACCURACY OF THE INTEGRATION C JMAX IS THE LIMIT FOR THE TOTAL NUMBER OF STEPS C K...THE FRACTIONAL-ACCURACY OF THE INTEGRATION C JMAX IS THE LIMIT FOR THE TOTAL NUMBER OF STEPS C K IS THE NUMBER OF POINTS USED IN THE

  13. Diamond MEMS: wafer scale processing, devices, and technology insertion

    NASA Astrophysics Data System (ADS)

    Carlisle, J. A.

    2009-05-01

    Diamond has long held the promise of revolutionary new devices: impervious chemical barriers, smooth and reliable microscopic machines, and tough mechanical tools. Yet it's been an outsider. Laboratories have been effectively growing diamond crystals for at least 25 years, but the jump to market viability has always been blocked by the expense of diamond production and inability to integrate with other materials. Advances in chemical vapor deposition (CVD) processes have given rise to a hierarchy of carbon films ranging from diamond-like carbon (DLC) to vapor-deposited diamond coatings, however. All have pros and cons based on structure and cost, but they all share some of diamond's heralded attributes. The best performer, in theory, is the purest form of diamond film possible, one absent of graphitic phases. Such a material would capture the extreme hardness, high Young's modulus and chemical inertness of natural diamond. Advanced Diamond Technologies Inc., Romeoville, Ill., is the first company to develop a distinct chemical process to create a marketable phase-pure diamond film. The material, called UNCD® (for ultrananocrystalline diamond), features grain sizes from 3 to 300 nm in size, and layers just 1 to 2 microns thick. With significant advantages over other thin films, UNCD is designed to be inexpensive enough for use in atomic force microscopy (AFM) probes, microelectromechanical machines (MEMS), cell phone circuitry, radio frequency devices, and even biosensors.

  14. Wafer-scale Reduced Graphene Oxide Films for Nanomechanical Devices

    DTIC Science & Technology

    2008-08-01

    easily extract the elastic properties of these rGO films, we created drum resonators by transfer- ring films onto prepatterned, 250 nm SiO2/Si substrates...Nature 1998, 392 (6672), 160–162. (4) LaHaye, M. D.; Buu, O .; Camarota, B.; Schwab, K. C. Science 2004, 304 (5667), 74–77. (5) Freeman, M.; Hiebert, W...Dubon, O . D. Nano Lett. 2007, 7 (7), 2009–2013. (24) Bak, J. H.; Kim, Y. D.; Hong, S. S.; Lee, B. Y.; Lee, S. R.; Jang, J. H.; Kim, M.; Char, K.; Hong

  15. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, Gary S.

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  16. Analysis of wafer heating in 14nm DUV layers

    NASA Astrophysics Data System (ADS)

    Subramany, Lokesh; Chung, Woong Jae; Samudrala, Pavan; Gao, Haiyong; Aung, Nyan; Gomez, Juan Manuel; Minghetti, Blandine; Lee, Shawn

    2016-03-01

    To further shrink the contact and trench dimensions, Negative Tone Development (NTD) has become the de facto process at these layers. The NTD process uses a positive tone resist and an organic solvent-based negative tone developer which leads to improved image contrast, larger process window and smaller Mask Error Enhancement Factor (MEEF)[1]. The NTD masks have high transmission values leading to lens heating and as observed here wafer heating as well. Both lens and wafer heating will contribute to overlay error, however the effects of lens heating can be mitigated by applying lens heating corrections while no such corrections exist for wafer heating yet. Although the magnitude of overlay error due to wafer heating is low relative to lens heating; ever tightening overlay requirements imply that the distortions due to wafer heating will quickly become a significant part of the overlay budget. In this work the effects, analysis and observations of wafer heating on contact and metal layers of the 14nm node are presented. On product wafers it manifests as a difference in the scan up and scan down signatures between layers. An experiment to further understand wafer heating is performed with a test reticle that is used to monitor scanner performance.

  17. Wafer hot spot identification through advanced photomask characterization techniques

    NASA Astrophysics Data System (ADS)

    Choi, Yohan; Green, Michael; McMurran, Jeff; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

    2016-10-01

    As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that the classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced characterization methods in order to optimize the mask process to meet the wafer lithographer's needs. These advanced characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled wafer performance.

  18. Strength of Si Wafers with Microcracks: A Theoretical Model; Preprint

    SciTech Connect

    Rupnowski, P.; Sopori, B.

    2008-05-01

    This paper concentrates on the modeling of the strength of photovoltaic (PV) wafers. First a multimodal Weibull distribution is presented for the strength of a silicon specimen with bulk, surface, and edge imperfections. Next, a specific case is analyzed of a PV wafer with surface damage that takes the form of subsurface microcracks.

  19. Positioning control system of three-dimensional wafer stage of lithography

    NASA Astrophysics Data System (ADS)

    Tian, Peng; Yan, Wei; Yang, Fan; Li, Fanxing; Hu, Song

    2016-10-01

    Three-dimensional wafer stage is an important component of lithography. It is required to high positioning precision and efficiency. The closed-loop positioning control system, that consists of five-phase step motor and grating scale, implements rapid and precision positioning control of the three-dimensional wafer stage. The MCU STC15W4K32S4, which is possession of six independent PWM output channels and the pulse width, period is adjustable, is used to control the three axes. The stepper motor driver and grating scale are subdivided according to the precision of lithography, and grating scale data is transmitted to the computer for display in real time via USB communication. According to the lithography material, mask parameter, incident light intensity, it's able to calculate the speed of Z axis, and then get the value of PWM period based on the mathematical formula of speed and pulse period, finally realize high precision control. Experiments show that the positioning control system of three-dimensional wafer stage can meet the requirement of lithography, the closed-loop system is high stability and precision, strong practicability.

  20. MAPPER alignment sensor evaluation on process wafers

    NASA Astrophysics Data System (ADS)

    Vergeer, N.; Lattard, L.; de Boer, G.; Couweleers, F.; Dave, D.; Pradelles, J.; Bustos, J.

    2013-03-01

    MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing. In order to reduce costs and to minimize the footprint of this tool a new alignment sensor has been developed; based on technologies used for DVD optical heads. A wafer with an alignment mark is scanned with the sensor, resulting in an intensity pattern versus position. From this pattern the mark position can be calculated. Evaluations have been made over the performance of this type of sensor using different mark designs at several lithography process steps for FEOL and BEOL manufacturing. It has been shown that sub-nanometer reproducibility (3σ std) of alignment mark readings can be achieved while being robust against various process steps.

  1. Reduction of Thermal Conductivity in Wafer-Bonded Silicon

    SciTech Connect

    ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

    2006-11-27

    Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

  2. Backside EBR process performance with various wafer properties

    NASA Astrophysics Data System (ADS)

    Goto, Tomohiro; Shigemori, Kazuhito; Vangheluwe, Rik; Erich, Daub; Sanada, Masakazu

    2009-03-01

    In immersion lithography process, film stacking architecture will be necessary to avoid top coat film peeling. To achieve suitable stacking architecture for immersion lithography process, an EBR process that delivers tightly controlled film edge position and good uniformity around the wafer circumference is needed. We demonstrated a new bevel rinse system on a SOKUDO RF3 coat-and-develop track for immersion lithography. The performance of the new bevel rinse system for various wafer properties was evaluated. It was found that the bevel rinse system has a good controllability of film edge position and good uniformity around the wafer circumference. The results indicate that the bevel rinse system has a large margin for wafer centering accuracy, back side particles, wafer shape and substrates with good film edge position controllability, uniformity and clean apex. The system has been demonstrated to provide a suitable film stacking architecture for immersion lithography mass production process.

  3. Overlay Tolerances For VLSI Using Wafer Steppers

    NASA Astrophysics Data System (ADS)

    Levinson, Harry J.; Rice, Rory

    1988-01-01

    In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his

  4. Compensating measured intra-wafer ring oscillator stage delay with intra-wafer exposure dose corrections

    NASA Astrophysics Data System (ADS)

    Verhaegen, Staf; Nackaerts, Axel; Dusa, Mircea; Carpaij, Rene; Vandenberghe, Geert; Finders, Jo

    2006-03-01

    The purpose of this paper is to use measurements on real working devices to derive more information than typically measured by the classic line-width measurement techniques. The first part of the paper will discuss the principle of the measurements with a ring oscillator, a circuit used to measure the speed of elementary logic gates. These measurements contribute to the understanding of the exact timing dependencies in circuits, which is of utmost importance for the design and simulation of these circuits. When connecting an odd number of digital inverting stages in a ring, the circuit has no stable digital state but acts as an analog oscillator with the oscillation frequency dependent on the analog propagation delay of the signals through the stages. By varying some conditions during a litho step, the delay change caused by the process condition change can be measured very accurately. The response of the ring oscillator delay to exposure dose is measured and presented in this paper together with a comparison of measured line-width values of the poly gate lines. The second part of the paper will focus on improving the intra-wafer variation of the stage delay. A number of ring oscillators are put in a design at different slit and scan locations. 200mm wafers are processed with 48 full dies present. From the intra-wafer delay fingerprint and the dose sensitivity of the delay an intra-wafer dose correction, also called a dose recipe, is calculated. This dose recipe is used on the scanner to compensate for effects that are the root cause for the delay profile; including reticle and processing such as track, etch and annealing.

  5. Rapid defect detections of bonded wafer using near infrared polariscope

    NASA Astrophysics Data System (ADS)

    Ng, Chi Seng; Asundi, Anand K.

    2011-10-01

    In modern field of microelectronics and MEMS, wafer bonding has emerged as an important processing step in wide range of manufacturing applications. During the manufacturing process, even in the modern clean room, small defects result from trapped particles and gas bubbles exist at bonded interface. Defects and trapped particles may exist on the top and bottom of the wafers, or at the interface of bonded wafer pair. These inclusions will generate high stress around debond region at the wafers bonded interface. In this paper, inspection at the bonded interface will be the interest of investigation. Since silicon wafer is opaque to visible light, defect detection at the bonded interface of silicon wafer is not possible. Due to the fact that silicon wafer is transparent to wavelength greater than 1150nm, an Near Infrared Polariscope which has showed some promises on residual stress measurement on silicon devices has been adapted and developed. This method is based on the well known photoelastic principles, where the stress variations are measured based on the changes of light propagation velocity in birefringence material. The results are compared and contrast with conventional Infrared Transmission Imaging tool (IRT) which is widely used to inspect the bonded silicon wafer. In this research, the trapped particles that are not visible via conventional infrared transmission method are identified via the generated residual stress pattern. The magnitude of the residual stress fields associated with each defect is examined qualitatively and quantitatively. The stress field generated at the wafers bonded interface will looks like a 'butterfly' pattern. Wafer pairs Pyrex-Si and Si-Si bonded interface will be examined.

  6. Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage

    PubMed Central

    Rack, Alexander; Scheel, Mario; Danilewsky, Andreas N.

    2016-01-01

    Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1–2 ms followed by jumps faster than 2–6 m s−1, leading to a macroscopically observed average velocity of 0.028–0.055 m s−1. The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound. PMID:27006774

  7. Capacitive micromachined ultrasonic transducers with through-wafer interconnects

    NASA Astrophysics Data System (ADS)

    Zhuang, Xuefeng

    Capacitive micromachined ultrasonic transducer (CMUT) is a promising candidate for making ultrasound transducer arrays for applications such as 3D medical ultrasound, non-destructive evaluation and chemical sensing. Advantages of CMUTs over traditional piezoelectric transducers include low-cost batch fabrication, wide bandwidth, and ability to fabricate arrays with broad operation frequency range and different geometric configurations on a single wafer. When incorporated with through-wafer interconnects, a CMUT array can be directly integrated with a front-end integrated circuit (IC) to achieve compact packaging and to mitigate the effects of the parasitic capacitance from the connection cables. Through-wafer via is the existing interconnect scheme for CMUT arrays, and many other types of micro-electro-mechanical system (MEMS) devices. However, to date, no successful through-wafer via fabrication technique compatible with the wafer-bonding method of making CMUT arrays has been demonstrated. The through-wafer via fabrication steps degrade the surface conditions of the wafer, reduce the radius of curvature, thus making it difficult to bond. This work focuses on new through-wafer interconnect techniques that are compatible with common MEMS fabrication techniques, including both surface-micromachining and direct wafer-to-wafer fusion bonding. In this dissertation, first, a through-wafer via interconnect technique with improved characteristics is presented. Then, two implementations of through-wafer trench isolation are demonstrated. The through-wafer trench methods differ from the through-wafer vias in that the electrical conduction is through the bulk silicon instead of the conductor in the vias. In the first implementation, a carrier wafer is used to provide mechanical support; in the second, mechanical support is provided by a silicon frame structure embedded inside the isolation trenches. Both implementations reduce fabrication complexity compared to the through-wafer

  8. A Comparison of the LigaSure and Harmonic Scalpel in Thyroid Surgery: A Single Institution Review

    PubMed Central

    Zarebczan, Barbara; Mohanty, Devi; Chen, Herbert

    2010-01-01

    Background Over the last few years many surgeons have begun to utilize the LigaSure device or Harmonic scalpel to perform thyroid surgery. Several papers have demonstrated the benefits of these devices over traditional hand-tying techniques. The purpose of this study was to examine our institution’s experience with the LigaSure device and Harmonic scalpel during thyroid surgery and to compare mean operative times and complications associated with each device. Methods A retrospective chart review was performed on all patients who underwent thyroid surgery using either the LigaSure device or Harmonic scalpel at a single institution between December 2005 and August 2009. Charts were reviewed for patient demographics, mean operative time, length of stay, and complications such as transient recurrent laryngeal nerve injury, hypocalcemia, and hematoma formation. Results Two hundred and thirty-one patients were included in the study, of whom 123 underwent total thyroidectomy and 108 underwent lobectomy. There was a significant decrease in the operative time for both thyroidectomies and lobectomies when the Harmonic scalpel was utilized. In regard to complications, there was no statistically significant difference in the number of transient and permanent recurrent laryngeal nerve injuries, percentage of patients developing hypocalcemia, or in the rate of hematoma development. Conclusion In this study, there was no difference in the rate of complications between the two devices. However, the use of the Harmonic scalpel significantly decreased operative time for both thyroidectomies and thyroid lobectomies when compared to the LigaSure device. PMID:20853030

  9. Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

    2014-01-01

    This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

  10. Preparation of Freestanding GaN Wafers by Hydride Vapor Phase Epitaxy with Void-Assisted Separation

    NASA Astrophysics Data System (ADS)

    Oshima, Yuichi; Eri, Takeshi; Shibata, Masatomo; Sunakawa, Haruo; Kobayashi, Kenji; Ichihashi, Toshinari; Usui, Akira

    2003-01-01

    We have developed a novel technique for preparing large-scale freestanding GaN wafers. Hydride vapor phase epitaxy (HVPE) growth of thick GaN layer was performed on a GaN template with a thin TiN film on the top. After the cooling process of the HVPE growth, the thick GaN layer was easily separated from the template by the assistance of many voids generated around the TiN film. As a result, a freestanding GaN wafer was obtained. The wafer obtained had a diameter of 45 mm, and a mirror-like surface. The-full-width-at-half-maximum (FWHM) of (0002) and (10\\bar{1}0) peaks in the X-ray rocking curve profile were 60 and 92 arcsec, respectively. The dislocation density was evaluated at 5× 106 cm-3 by etch pit density measurement.

  11. Wafer-level vacuum/hermetic packaging technologies for MEMS

    NASA Astrophysics Data System (ADS)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  12. Development of optical automatic positioning and wafer defect detection system

    NASA Astrophysics Data System (ADS)

    Tien, Chuen-Lin; Lai, Qun-Huang; Lin, Chern-Sheng

    2016-02-01

    The data of a wafer with defects can provide engineers with very important information and clues to improve the yield rate and quality in manufacturing. This paper presents a microscope automatic positioning and wafer detection system with human-machine interface based on image processing and fuzzy inference algorithms. In the proposed system, a XY table is used to move the position of each die on 6 inch or 8 inch wafers. Then, a high-resolution CCD and one set of two-axis optical linear encoder are used to accurately measure the position on the wafer. Finally, the developed human-machine interface is used to display the current position of an actual wafer in order to complete automatic positioning, and a wafer map database can be created. In the process of defect detection, CCD is used for image processing, and during preprocessing, it is required to filter noise, acquire the defect characteristics, define the defective template, and then take the characteristic points of the defective template as the reference input for fuzzy inference. A high-accuracy optical automatic positioning and wafer defect detection system is thus constructed. This study focused on automatic detection of spots, scratches, and bruises, and attempted to reduce the time to detect defective die and improve the accuracy of determining the defects of semiconductor devices.

  13. Techniques for the evaluation of outgassing from polymeric wafer pods

    SciTech Connect

    McIntyre, D.C.; Liang, A.; Thornberg, S.M.; Bender, S.F.; Lujan, R.D.; Blewer, R.S.; Bowers, W.D.

    1994-03-01

    In recent years there has been increasing interest in using wafer-level isolation environments or pods (microenvironments) to provide a more controllable, cleaner wafer environment during wafer processing. It has been shown that pods can be effective in reducing the amount of particulate contamination on wafers during manufacturing. However, there have also been studies that indicate that pods and wafer boxes can be the source of condensible, molecular organic contamination. This paper summarizes the work that has been performed during the past year at Sandia National Laboratories` Contamination Free Manufacturing Research Center (CFMRC) on (1) devising standard, low-temperature, high sensitivity techniques to detect outgassing of volatile organic compounds (VOCs) from polymers used to construct wafer pods and (2) development of a technique that can be used to continuously measure the condensible contamination within pods so that the pod environment can be monitored during manufacturing. Although these techniques have been developed specifically for assessing contamination threats from wafer pods, they can be used to evaluate other potential contamination sources. The high sensitivity outgassing techniques can be used to evaluate outgassing of volatiles from other clean-room materials and the real-time outgassing sensor can be used to monitor contamination condensation in non-pod environments such as ballroom-type cleanrooms and minienvironments.

  14. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    NASA Technical Reports Server (NTRS)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

    2016-01-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN(sub x)) materials and microwave structures, and the resulting performance improvements.

  15. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    NASA Astrophysics Data System (ADS)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

    2016-08-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

  16. Temperature rise of the mask-resist assembly during LIGA exposure.

    SciTech Connect

    Ting, Aili

    2004-11-01

    Deep X-ray lithography on PMMA resist is used in the LIGA process. The resist is exposed to synchrotron X-rays through a patterned mask and then is developed in a liquid developer to make high aspect ratio microstructures. The limitations in dimensional accuracies of the LIGA generated microstructure originate from many sources, including synchrotron and X-ray physics, thermal and mechanical properties of mask and resist, and from the kinetics of the developer. This work addresses the thermal analysis and temperature rise of the mask-resist assembly during exposure in air at the Advanced Light Source (ALS) synchrotron. The concern is that dimensional errors generated at the mask and the resist due to thermal expansion will lower the accuracy of the lithography. We have developed a three-dimensional finite-element model of the mask and resist assembly that includes a mask with absorber, a resist with substrate, three metal holders, and a water-cooling block. We employed the LIGA exposure-development software LEX-D to calculate volumetric heat sources generated in the assembly by X-ray absorption and the commercial software ABAQUS to calculate heat transfer including thermal conduction inside the assembly, natural and forced convection, and thermal radiation. at assembly outer and/or inner surfaces. The calculations of assembly maximum temperature. have been compared with temperature measurements conducted at ALS. In some of these experiments, additional cooling of the assembly was produced by forced nitrogen flow ('nitrogen jets') directed at the mask surface. The temperature rise in the silicon mask and the mask holder comes directly from the X-ray absorption, but nitrogen jets carry away a significant portion of heat energy from the mask surface, while natural convection carries away negligibly small amounts energy from the holder. The temperature rise in PMMA resist is mainly from heat conducted from the silicon substrate backward to the resist and from the inner

  17. Analysis of the interdigitated back contact solar cells: The n-type substrate lifetime and wafer thickness

    NASA Astrophysics Data System (ADS)

    Zhang, Wei; Chen, Chen; Jia, Rui; Sun, Yun; Xing, Zhao; Jin, Zhi; Liu, Xin-Yu; Liu, Xiao-Wen

    2015-10-01

    The n-type silicon integrated-back contact (IBC) solar cell has attracted much attention due to its high efficiency, whereas its performance is very sensitive to the wafer of low quality or the contamination during high temperature fabrication processing, which leads to low bulk lifetime τbulk. In order to clarify the influence of bulk lifetime on cell characteristics, two-dimensional (2D) TCAD simulation, combined with our experimental data, is used to simulate the cell performances, with the wafer thickness scaled down under various τbulk conditions. The modeling results show that for the IBC solar cell with high τbulk, (such as 1 ms-2 ms), its open-circuit voltage Voc almost remains unchanged, and the short-circuit current density Jsc monotonically decreases as the wafer thickness scales down. In comparison, for the solar cell with low τbulk (for instance, < 500 μs) wafer or the wafer contaminated during device processing, the Voc increases monotonically but the Jsc first increases to a maximum value and then drops off as the wafer’s thickness decreases. A model combing the light absorption and the minority carrier diffusion is used to explain this phenomenon. The research results show that for the wafer with thinner thickness and high bulk lifetime, the good light trapping technology must be developed to offset the decrease in Jsc. Project supported by the Chinese Ministry of Science and Technology Projects (Grant Nos. 2012AA050304 and Y0GZ124S01), the National Natural Science Foundation of China (Grant Nos. 11104319, 11274346, 51202285, 51402347, and 51172268), and the Fund of the Solar Energy Action Plan from the Chinese Academy of Sciences (Grant Nos. Y3ZR044001 and Y2YF014001).

  18. Wafer Stepper Characterization And Process Control Techniques

    NASA Astrophysics Data System (ADS)

    Curry, S. C.; Friedberg, C. B.

    1982-09-01

    A process control vehicle is described which allows the characterization and comparison of wafer steppers with respect to distortion, resolution, uniformity, and misregistration. A block of test structures consisting of optical resolution patterns, verniers, and electrical line width and misalignment resistors is arrayed on an 11 x 11 grid which fills the entire available field of a 10X reticle. Fach block also contains a pair of targets for the THE laser-interferometric auto-alignment system. The ability of the auto-aligner to acquire such targets to within 500 is exploited as a metrology tool whereby the measured coordinates at each site are compared to the ideal (theoretical) coordinates to generate a vector distortion map across the field. Subsequent reduction of misregistration data is accomplished via application of the six parameter model developed by Perloff and co-workers. It is shown that these diagnostic tools permit the rapid characterization of distortion anisotropy for a given stepper and can be used to optimize and monitor level-to-level regis-tration. Further applications are suggested.

  19. Fundamental limitations of LIGA x-ray lithography : sidewall offset, slope and minimum feature size.

    SciTech Connect

    Griffiths, Stewart K.

    2004-01-01

    Analytical and numerical methods are used to examine photoelectron doses and their effect on the dimensions of features produced by deep x-ray lithography. New analytical models describing electron doses are presented and used to compute dose distributions for several feature geometries. The history of development and final feature dimensions are also computed, taking into account the dose field, dissolution kinetics based on measured development rates, and the transport of PMMA fragments away from the dissolution front. We find that sidewall offsets, sidewall slope and producible feature sizes all exhibit at least practical minima and that these minima represent fundamental limitations of the LIGA process. The minimum values under optimum conditions are insensitive to the synchrotron spectrum, but depend strongly on resist thickness. This dependence on thickness is well approximated by simple analytical expressions describing the minimum offset, minimum sidewall slope, minimum producible size of positive and negative features, maximum aspect ratio and minimum radius of inside and outside corners.

  20. Wafer-bonded 2-D CMUT arrays incorporating through-wafer trench-isolated interconnects with a supporting frame.

    PubMed

    Zhuang, Xuefeng; Wygant, Ira O; Lin, Der-Song; Kupnik, Mario; Oralkan, Omer; Khuri-Yakub, Butrus T

    2009-01-01

    This paper reports on wafer-bonded, fully populated 2-D capacitive micromachined ultrasonic transducer (CMUT) arrays. To date, no successful through-wafer via fabrication technique has been demonstrated that is compatible with the wafer-bonding method of making CMUT arrays. As an alternative to through-wafer vias, trench isolation with a supporting frame is incorporated into the 2-D arrays to provide through-wafer electrical connections. The CMUT arrays are built on a silicon-on-insulator (SOI) wafer, and all electrical connections to the array elements are brought to the back side of the wafer through the highly conductive silicon substrate. Neighboring array elements are separated by trenches on both the device layer and the bulk silicon. A mesh frame structure, providing mechanical support, is embedded between silicon pillars, which electrically connect to individual elements. We successfully fabricated a 16 x 16-element 2-D CMUT array using wafer bonding with a yield of 100%. Across the array, the pulse-echo amplitude distribution is uniform (rho = 6.6% of the mean amplitude). In one design, we measured a center frequency of 7.6 MHz, a peak-to-peak output pressure of 2.9 MPa at the transducer surface, and a 3-dB fractional bandwidth of 95%. Volumetric ultrasound imaging was demonstrated by chip-to-chip bonding one of the fabricated 2-D arrays to a custom-designed integrated circuit (IC). This study shows that through-wafer trench-isolation with a supporting frame is a viable solution for providing electrical interconnects to CMUT elements and that 2-D arrays fabricated using waferbonding deliver good performance.

  1. UV-LIGA microfabrication process for sub-terahertz waveguides utilizing multiple layered SU-8 photoresist

    NASA Astrophysics Data System (ADS)

    Malekabadi, Ali; Paoloni, Claudio

    2016-09-01

    A microfabrication process based on UV LIGA (German acronym of lithography, electroplating and molding) is proposed for the fabrication of relatively high aspect ratio sub-terahertz (100-1000 GHz) metal waveguides, to be used as a slow wave structure in sub-THz vacuum electron devices. The high accuracy and tight tolerances required to properly support frequencies in the sub-THz range can be only achieved by a stable process with full parameter control. The proposed process, based on SU-8 photoresist, has been developed to satisfy high planar surface requirements for metal sub-THz waveguides. It will be demonstrated that, for a given thickness, it is more effective to stack a number of layers of SU-8 with lower thickness rather than using a single thick layer obtained at lower spin rate. The multiple layer approach provides the planarity and the surface quality required for electroforming of ground planes or assembly surfaces and for assuring low ohmic losses of waveguides. A systematic procedure is provided to calculate soft and post-bake times to produce high homogeneity SU-8 multiple layer coating as a mold for very high quality metal waveguides. A double corrugated waveguide designed for 0.3 THz operating frequency, to be used in vacuum electronic devices, was fabricated as test structure. The proposed process based on UV LIGA will enable low cost production of high accuracy sub-THz 3D waveguides. This is fundamental for producing a new generation of affordable sub-THz vacuum electron devices, to fill the technological gap that still prevents a wide diffusion of numerous applications based on THz radiation.

  2. Temperature rise of the silicon mask-PMMA resist assembly during LIGA exposure

    NASA Astrophysics Data System (ADS)

    Ting, Aili

    2005-01-01

    Deep X-ray lithography on PMMA resist is used in the LIGA process. The resist is exposed to synchrotron X-rays through a patterned mask and then is developed in a liquid developer to make high aspect ratio microstructures. This work addresses the thermal analysis and temperature rise of the mask-resist assembly during exposure at the Advanced Light Source (ALS) synchrotron. The concern is that the thermal expansion will lower the accuracy of the lithography. We have developed a three-dimensional finite-element model of the mask and resist assembly. We employed the LIGA exposure-development software LEX-D and the commercial software ABAQUS to calculate heat transfer of the assembly during exposure. The calculations of assembly maximum temperature have been compared with temperature measurements conducted at ALS. The temperature rise in the silicon mask and the mask holder comes directly from the X-ray absorption, but forced convection of nitrogen jets carry away a significant portion of heat energy from the mask surface, while natural convection plays a negligible role. The temperature rise in PMMA resist is mainly from heat conducted from the silicon substrate backward to the resist and from the mask plate through inner cavity air forward to the resist, while the X-ray absorption is only secondary. Therefore, reduction of heat flow conducted from both substrate and cavity air to the resist is essential. An improved water-cooling block is expected to carry away most heat energy along the main heat conductive path, leaving the resist at a favorable working temperature.

  3. Proceedings of the Low-Cost Solar Array Wafering Workshop

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1982-01-01

    The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

  4. Stress-warping relation in thin film coated wafers

    NASA Astrophysics Data System (ADS)

    Schicker, J.; Khan, W. A.; Arnold, T.; Hirschl, C.

    2017-02-01

    A misfit strain or stress in a thin layer on the surface of a wafer lets the composite disk warp. When the wafer is thin and large, the Stoney estimation of the film stress as function of the curvature yields large errors. We present a nonlinear analytical model that describes the relationship between warpage and film stress on an anisotropic wafer, and give evidence for its suitability for large thin wafers by a comparison to finite element results. Finally, we show the confidence limit of the Stoney estimation and the benefit by the nonlinear model. For thin coatings, it can be succesfully used even without knowledge of the film properties, which was the main advantage of the Stoney estimation.

  5. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-03-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  6. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  7. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2008-10-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  8. Stress rate and proof-testing of silicon wafers

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1985-01-01

    Fracture mechanics test methods were applied to evaluate the proof-test characteristics of single-crystal silicon wafers. The results indicate that the strength distribution of silicon wafers is truncated by proof-testing. No subcritical crack growth occurred during proof-loading, as inferred from the lack of a stress-rate effect on strength. Mechanical proof-testing appears to be an effective method for eliminating weak samples before cell processing.

  9. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  10. Strategy optimization for mask rule check in wafer fab

    NASA Astrophysics Data System (ADS)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  11. Further investigation of EUV process sensitivities for wafer track processing

    NASA Astrophysics Data System (ADS)

    Bradon, Neil; Nafus, K.; Shite, H.; Kitano, J.; Kosugi, H.; Goethals, M.; Cheng, S.; Hermans, J.; Hendrickx, E.; Baudemprez, B.; Van Den Heuvel, D.

    2010-04-01

    As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.

  12. Monitoring Dielectric Thin-Film Production on Product Wafers Using Infrared Emission Spectroscopy

    SciTech Connect

    NIEMCZYK,THOMAS M.; ZHANG,SONGBIAO; HAALAND,DAVID M.

    2000-12-18

    Monitoring of dielectric thin-film production in the microelectronics industry is generally accomplished by depositing a representative film on a monitor wafer and determining the film properties off line. One of the most important dielectric thin films in the manufacture of integrated circuits is borophosphosilicate glass (BPSG). The critical properties of BPSG thin films are the boron content, phosphorus content and film thickness. We have completed an experimental study that demonstrates that infrared emission spectroscopy coupled with multivariate analysis can be used to simultaneous y determine these properties directly from the spectra of product wafers, thus eliminating the need of producing monitor wafers. In addition, infrared emission data can be used to simultaneously determine the film temperature, which is an important film production parameter. The infrared data required to make these determinations can be collected on a time scale that is much faster than the film deposition time, hence infrared emission is an ideal candidate for an in-situ process monitor for dielectric thin-film production.

  13. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  14. Wave-front propagation of rinsing flows on rotating semiconductor wafers

    NASA Astrophysics Data System (ADS)

    Frostad, John M.; Ylitalo, Andy; Walls, Daniel J.; Mui, David S. L.; Fuller, Gerald G.

    2016-11-01

    The semiconductor manufacturing industry is migrating to a cleaning technology that involves dispersing cleaning solutions onto a rotating wafer, similar to spin-coating. Advantages include a more continuous overall fabrication process, lower particle level, no cross contamination from the back side of a wafer, and less usage of harsh chemicals for a lower environmental impact. Rapid rotation of the wafer during rinsing can be more effective, but centrifugal forces can pull spiral-like ribbons of liquid radially outward from the advancing wave-front where particles can build up, causing higher instances of device failure at these locations. A better understanding of the rinsing flow is essential for reducing yield losses while taking advantage of the benefits of rotation. In the present work, high-speed video and image processing are used to study the dynamics of the advancing wave-front from an impinging jet on a rotating substrate. The flow-rate and rotation-speed are varied for substrates coated with a thin layer of a second liquid that has a different surface tension than the jet liquid. The difference in surface tension of the two fluids gives rise to Marangoni stresses at the interface that have a significant impact on the rinsing process, despite the extremely short time-scales involved.

  15. High Throughput, Noncontact System for Screening Silicon Wafers Predisposed to Breakage During Solar Cell Production

    SciTech Connect

    Sopori, B.; Rupnowski, P.; Basnyat, P.; Mehta, V.

    2011-01-01

    We describe a non-contact, on-line system for screening wafers that are likely to break during solar cell/module fabrication. The wafers are transported on a conveyor belt under a light source, which illuminates the wafers with a specific light distribution. Each wafer undergoes a dynamic thermal stress whose magnitude mimics the highest stress the wafer will experience during cell/module fabrication. As a result of the stress, the weak wafers break, leaving only the wafers that are strong enough to survive the production processes. We will describe the mechanism of wafer breakage, introduce the wafer system, and discuss the results of the time-temperature (t-T) profile of wafers with and without microcracks.

  16. Improving on-wafer CD correlation analysis using advanced diagnostics and across-wafer light-source monitoring

    NASA Astrophysics Data System (ADS)

    Alagna, Paolo; Zurita, Omar; Rechtsteiner, Gregory; Lalovic, Ivan; Bekaert, Joost

    2014-04-01

    With the implementation of multi-patterning ArF-immersion for sub 20nm integrated circuits (IC), advances in equipment monitoring and control are needed to support on-wafer yield performance. These in-situ equipment monitoring improvements, along with advanced litho-cell corrections based on on-wafer measurements, enable meeting stringent overlay and CD control requirements for advanced lithography patterning. The importance of light-source performance on lithography pattering (CD and overlay) has been discussed in previous publications.[1-3] Recent developments of Cymer ArF light-source metrology and on-board monitoring enable end-users to detect, for each exposed wafer, changes in the near-field and far-field spatial profiles and polarization performance, [4-6] in addition to the key `optical' scalar parameters, such as bandwidth, wavelength and energy. The major advantage of this capability is that the key performance metrics are sampled at rates matched to wafer performance, e.g. every exposure field across the wafer, which is critical for direct correlation with on-wafer performance for process control and excursion detection.

  17. ILT based defect simulation of inspection images accurately predicts mask defect printability on wafer

    NASA Astrophysics Data System (ADS)

    Deep, Prakash; Paninjath, Sankaranarayanan; Pereira, Mark; Buck, Peter

    2016-05-01

    At advanced technology nodes mask complexity has been increased because of large-scale use of resolution enhancement technologies (RET) which includes Optical Proximity Correction (OPC), Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO). The number of defects detected during inspection of such mask increased drastically and differentiation of critical and non-critical defects are more challenging, complex and time consuming. Because of significant defectivity of EUVL masks and non-availability of actinic inspection, it is important and also challenging to predict the criticality of defects for printability on wafer. This is one of the significant barriers for the adoption of EUVL for semiconductor manufacturing. Techniques to decide criticality of defects from images captured using non actinic inspection images is desired till actinic inspection is not available. High resolution inspection of photomask images detects many defects which are used for process and mask qualification. Repairing all defects is not practical and probably not required, however it's imperative to know which defects are severe enough to impact wafer before repair. Additionally, wafer printability check is always desired after repairing a defect. AIMSTM review is the industry standard for this, however doing AIMSTM review for all defects is expensive and very time consuming. Fast, accurate and an economical mechanism is desired which can predict defect printability on wafer accurately and quickly from images captured using high resolution inspection machine. Predicting defect printability from such images is challenging due to the fact that the high resolution images do not correlate with actual mask contours. The challenge is increased due to use of different optical condition during inspection other than actual scanner condition, and defects found in such images do not have correlation with actual impact on wafer. Our automated defect simulation tool predicts

  18. Scales

    MedlinePlus

    Scales are a visible peeling or flaking of outer skin layers. These layers are called the stratum ... Scales may be caused by dry skin, certain inflammatory skin conditions, or infections. Eczema , ringworm , and psoriasis ...

  19. Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering

    NASA Astrophysics Data System (ADS)

    Chen, Po-Ying; Tsai, Ming-Hsing; Yeh, Wen-Kuan; Jing, Ming-Haw; Chang, Yukon

    2009-12-01

    Silicon wafer breakage has become a major concern for all semiconductor fabrication lines because it is brittle, and thus high stresses are easily induced in its manufacture. The production cost of devices significantly increases even for a breakage loss of a few percent if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant. In this investigation, we develop a brand new approach to reducing breakage by using a charge-coupled device (CCD) to capture the cross-section image of the wafer at its edge; the data measured at the edge can be used to determine overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength, and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in the wafer bulk before failure. We also describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unidentified causes. Our analysis gives the optimal front size (B1), edge widths (A1,A2), and bevel angle (θ) for the edge profiles of wafers to prevent wafer breakage. Briefly, when a suitable material and suitable process control approaches are utilized, silicon wafer breakage can be prevented. This is the first investigation providing evidence that whole-wafer strength is an important issue. We present a physical model to explain why wafer fracture has become an increasingly serious problem as the diameter of wafers has increased. The control of wafer edge geometry has been demonstrated to be an effective means of protecting wafers with large diameters against breakage. This model reveals that the breakage rate of wafers can be reduced by controlling the uniformity of the differences between the front size and the rear edge widths during the wafer manufacturing process.

  20. Assessment of patients’ quality of life after haemorrhoidectomy using the LigaSure device

    PubMed Central

    Leksowski, Krzysztof

    2015-01-01

    Introduction Haemorrhoids are small anatomical structures within the anal canal that are involved in the proper functioning of the lower gastrointestinal tract. Factors favouring the development of haemorrhoidal disease are insufficient physical activity, prolonged sitting and hence a shortage of physical activity, as well as poor diet which lacks adequate amounts of fibre. The main symptom of this disease is bleeding with bright red blood just after defecation. Haemorrhoidal disease occurs when the ligamentous apparatus comes loose and the internal haemorrhoidal plexus translocates down, whereas haemorrhoids enlarge and move out of the anal canal. Haemorrhoidal disease treatment includes conservative, instrumental and surgical therapy. Aim To assess treatment and satisfaction in particular life domains after haemorrhoidectomy. Material and methods The research was undertaken in the General, Thoracic and Vascular Surgery Clinic of the 10th Military Clinical Hospital with Polyclinic in Bydgoszcz among 50 patients treated due to haemorrhoids and operated on in the period 2007–2008. The study evaluated quality of patients’ life after haemorrhoidectomy by Ferguson's method using a LigaSure appliance. Results The study investigated whether patients perceived a difference before and after surgery. The research proved that patients can describe disease symptoms and know the risk factors for haemorrhoids. In the studied group patients are able to describe characteristic signs of haemorrhoidal disease and also indicate differences in everyday life before and after the surgery. They can also describe and classify the pain before and 1 year after the haemorrhoidectomy, which was statistically significantly lower already 3 months after the operation. Conclusions Conducted examinations showed that sick people in the precise way were able to determine manifestations and know risk factors of the prevalence of disease hemorrhoidal. Operated sick people indicated the difference

  1. Quantitative phase measurement for wafer-level optics

    NASA Astrophysics Data System (ADS)

    Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

    2015-07-01

    Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

  2. Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.

    2004-01-01

    An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

  3. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    NASA Astrophysics Data System (ADS)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  4. WaferOptics® mass volume production and reliability

    NASA Astrophysics Data System (ADS)

    Wolterink, E.; Demeyer, K.

    2010-05-01

    The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

  5. A benchmark investigation on cleaning photomasks using wafer cleaning technologies

    NASA Astrophysics Data System (ADS)

    Kindt, Louis; Burnham, Jay; Marmillion, Pat

    2004-12-01

    As new technologies are developed for smaller linewidths, the specifications for mask cleanliness become much stricter. Not only must the particle removal efficiency increase, but the largest allowable particle size decreases. Specifications for film thickness and surface roughness are becoming tighter and consequently the integrity of these films must be maintained in order to preserve the functionality of the masks. Residual contamination remaining on the surface of the mask after cleaning processes can lead to subpellicle defect growth once the mask is exposed in a stepper environment. Only during the last several years, has an increased focus been put on improving mask cleaning. Over the years, considerably more effort has been put into developing advanced wafer cleaning technologies. However, because of the small market involved with mask cleaning, wafer cleaning equipment vendors have been reluctant to invest time and effort into developing cleaning processes and adapting their toolset to accommodate masks. With the advent of 300 mm processing, wafer cleaning tools are now more easily adapted to processing masks. These wafer cleaning technologies may offer a solution to the difficulties of mask cleaning and need to be investigated to determine whether or not they warrant continued investigation. This paper focuses on benchmarking advanced wafer cleaning technologies applied to mask cleaning. Ozonated water, hydrogenated water, super critical fluids, and cryogenic cleaning have been investigated with regards to stripping resist and cleaning particles from masks. Results that include film thickness changes, surface contamination, and particle removal efficiency will be discussed.

  6. 100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices

    SciTech Connect

    OLIVER,ANDREW D.; MATZKE,CAROLYN M.

    2000-04-06

    A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

  7. Optical wafer metrology sensors for process-robust CD and overlay control in semiconductor device manufacturing

    NASA Astrophysics Data System (ADS)

    den Boef, Arie J.

    2016-06-01

    This paper presents three optical wafer metrology sensors that are used in lithography for robustly measuring the shape and position of wafers and device patterns on these wafers. The first two sensors are a level sensor and an alignment sensor that measure, respectively, a wafer height map and a wafer position before a new pattern is printed on the wafer. The third sensor is an optical scatterometer that measures critical dimension-variations and overlay after the resist has been exposed and developed. These sensors have different optical concepts but they share the same challenge that sub-nm precision is required at high throughput on a large variety of processed wafers and in the presence of unknown wafer processing variations. It is the purpose of this paper to explain these challenges in more detail and give an overview of the various solutions that have been introduced over the years to come to process-robust optical wafer metrology.

  8. Surface quality of silicon wafer improved by hydrodynamic effect polishing

    NASA Astrophysics Data System (ADS)

    Peng, Wenqiang; Guan, Chaoliang; Li, Shengyi

    2014-08-01

    Differing from the traditional pad polishing, hydrodynamic effect polishing (HEP) is non-contact polishing with the wheel floated on the workpiece. A hydrodynamic lubricated film is established between the wheel and the workpiece when the wheel rotates at a certain speed in HEP. Nanoparticles mixed with deionized water are employed as the polishing slurry, and with action of the dynamic pressure, nanoparticles with high chemisorption due to the high specific surface area can easily reacted with the surface atoms forming a linkage with workpiece surface. The surface atoms are dragged away when nanoparticles are transported to separate by the flow shear stress. The development of grand scale integration put extremely high requirements on the surface quality on the silicon wafer with surface roughness at subnanometer and extremely low surface damage. In our experiment a silicon sample was processed by HEP, and the surface topography before and after polishing was observed by the atomic force microscopy. Experiment results show that plastic pits and bumpy structures on the initial surface have been removed away clearly with the removal depth of 140nm by HEP process. The processed surface roughness has been improved from 0.737nm RMS to 0.175nm RMS(10μm×10μm) and the section profile shows peaks of the process surface are almost at the same height. However, the machining ripples on the wheel surface will duplicate on the silicon surface under the action of the hydrodynamic effect. Fluid dynamic simulation demonstrated that the coarse surface on the wheel has greatly influence on the distribution of shear stress and dynamic pressure on the workpiece surface.

  9. On-wafer magnetic resonance of magnetite nanoparticles

    NASA Astrophysics Data System (ADS)

    Little, Charles A. E.; Russek, Stephen E.; Booth, James C.; Kabos, Pavel; Usselman, Robert J.

    2015-11-01

    Magnetic resonance measurements of ferumoxytol and TEMPO were made using an on-wafer transmission line technique with a vector network analyzer, allowing for broadband measurements of small sample volumes (4 nL) and small numbers of spins (1 nmol). On-wafer resonance measurements were compared with standard single-frequency cavity-based electron paramagnetic resonance (EPR) measurements using a new power conservation approach and the results show similar line shape. On-wafer magnetic resonance measurements using integrated microfluidics and microwave technology can significantly reduce the cost and sample volumes required for EPR spectral analysis and allow for integration of EPR with existing lab-on-a-chip processing and characterization techniques for point-of-care medical diagnostic applications.

  10. Growth of silver nanowires on GaAs wafers.

    PubMed

    Sun, Yugang

    2011-05-01

    Silver (Ag) nanowires with chemically clean surfaces have been directly grown on semi-insulating gallium arsenide (GaAs) wafers through a simple solution/solid interfacial reaction (SSIR) between the GaAs wafers themselves and aqueous solutions of silver nitrate (AgNO(3)) at room temperature. The success in synthesis of Ag nanowires mainly benefits from the low concentration of surface electrons in the semi-insulating GaAs wafers that can lead to the formation of a low-density of nuclei that facilitate their anisotropic growth into nanowires. The resulting Ag nanowires exhibit rough surfaces and reasonably good electric conductivity. These characteristics are beneficial to sensing applications based on single-nanowire surface-enhanced Raman scattering (SERS) and possible surface-adsorption-induced conductivity variation.

  11. Monitoring of acoustic emission activity using thin wafer piezoelectric sensors

    NASA Astrophysics Data System (ADS)

    Trujillo, Blaine; Zagrai, Andrei; Meisner, Daniel; Momeni, Sepand

    2014-03-01

    Acoustic emission (AE) is a well-known technique for monitoring onset and propagation of material damage. The technique has demonstrated utility in assessment of metallic and composite materials in applications ranging from civil structures to aerospace vehicles. While over the course of few decades AE hardware has changed dramatically with the sensors experiencing little changes. A traditional acoustic emission sensor solution utilizes a thickness resonance of the internal piezoelectric element which, coupled with internal amplification circuit, results in relatively large sensor footprint. Thin wafer piezoelectric sensors are small and unobtrusive, but they have seen limited AE applications due to low signal-to-noise ratio and other operation difficulties. In this contribution, issues and possible solutions pertaining to the utility of thin wafer piezoelectrics as AE sensors are discussed. Results of AE monitoring of fatigue damage using thin wafer piezoelectric and conventional AE sensors are presented.

  12. Low cost wafer metrology using a NIR low coherence interferometry.

    PubMed

    Kim, Young Gwang; Seo, Yong Bum; Joo, Ki-Nam

    2013-06-03

    In this investigation, a low cost Si wafer metrology system based on low coherence interferometry using NIR light is proposed and verified. The whole system consists of two low coherence interferometric principles: low coherence scanning interferometry (LCSI) for measuring surface profiles and spectrally-resolved interferometry (SRI) to obtain the nominal optical thickness of the double-sided polished Si wafer. The combination of two techniques can reduce the measurement time and give adequate dimensional information of the Si wafer. The wavelength of the optical source is around 1 μm, for which transmission is non-zero for undoped silicon and can be also detected by a typical CCD camera. Because of the typical CCD camera, the whole system can be constructed inexpensively.

  13. Minority lifetime degradation of silicon wafers after electric zone melting

    NASA Astrophysics Data System (ADS)

    Wu, M. C.; Yang, C. F.; Lan, C. W.

    2015-06-01

    The degradation of minority lifetime of mono- and multi-crystalline silicon wafers after electric zone melting, a simple and contamination-free process, was investigated. The thermal-stress induced dislocations were responsible to the degradation; however, the grain size also played a crucial role. It was believed that the grain boundaries helped the relaxation of thermal stress, so that the degradation was reduced as the grain size decreased. In addition to lifetime mapping and etch pit density, photoluminescence mapping was also used to examine the electrically active defects after zone melting. Factors affecting lifetime degradation of silicon wafers after electric zone melting were examined. Small-grain multi-crystalline wafers showed better lifetime after zone melting. Twining area showed better lifetime. The formation of new grains relaxed the thermal stress mitigating lifetime degradation.

  14. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  15. Characterizing SOI Wafers By Use Of AOTF-PHI

    NASA Technical Reports Server (NTRS)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  16. 450mm wafer patterning with jet and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  17. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    SciTech Connect

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  18. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  19. Overview of recent direct wafer bonding advances and applications

    NASA Astrophysics Data System (ADS)

    Moriceau, H.; Rieutord, F.; Fournel, F.; Le Tiec, Y.; Di Cioccio, L.; Morales, C.; Charvet, A. M.; Deguet, C.

    2010-12-01

    Direct wafer bonding processes are being increasingly used to achieve innovative stacking structures. Many of them have already been implemented in industrial applications. This article looks at direct bonding mechanisms, processes developed recently and trends. Homogeneous and heterogeneous bonded structures have been successfully achieved with various materials. Active, insulating or conductive materials have been widely investigated. This article gives an overview of Si and SiO2 direct wafer bonding processes and mechanisms, silicon-on-insulator type bonding, diverse material stacking and the transfer of devices. Direct bonding clearly enables the emergence and development of new applications, such as for microelectronics, microtechnologies, sensors, MEMs, optical devices, biotechnologies and 3D integration.

  20. An application of selective electrochemical wafer thinning for silicon characterization

    SciTech Connect

    Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

    1990-01-01

    A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

  1. Hypervelocity impact on silicon wafers with metallic and polymeric coatings

    NASA Astrophysics Data System (ADS)

    Taylor, E. A.; Scott, H. J.; Abraham, M.; Kearsley, A. T.

    2001-10-01

    Current and near future developments in microsystem technologies (MST, also known as MEMS) are defining a new trend towards lower mass, smaller volume spacecraft, without loss of functionality. The MST spacecraft components are etched onto silicon wafers coated with different metallic or polymeric material layers (typically 1-2 microns in thickness). These silicon wafers are then integrated to provide the spacecraft structure subsystem. For the majority of spacecraft, small debris and meteoroid impacts are not often able to cause large satellite platform failures, due to the shielding provided by existing structural and thermal materials and the high percentage of 'empty volume' contained within a typical spacecraft structure. Smaller satellites incorporating MST and based on silicon wafers, whilst presenting a smaller surface area, are expected to be vulnerable to impacts as the lower subsystem mass defines a less substantial structure, providing significantly less protection against impact. This paper presents results of a BNSC-funded study aimed at identifying the vulnerability of MST technologies based on silicon wafers to space debris and meteoroid impact. Hypervelocity impact tests were carried out on silicon wafers coated with five different types of deposited material. Multiple glass spheres were fired simultaneously at velocities in the range of 6 km/s. The impact results identify the hypervelocity impact response of the silicon wafers. The impacted targets showed a brittle material damage morphology (defined by fracture) and linked to the crystalline structure of the silicon wafer. As predicted from the mechanical properties, it was found that the silicon tended to fracture along the 111 planes. Cross-sectioned craters also showed the crystalline structure of the silicon, with the onset of fracture-driven spall on the rear surface. The metal and polymeric coatings produced diverse damage morphologies, with delamination zones being up to twice the diameter

  2. Comparison and efficacy of LigaSure and rubber band ligature in closing the inflamed cecal stump in a rat model of acute appendicitis.

    PubMed

    Yeh, Chun-Chieh; Jan, Chia-Ing; Yang, Horng-Ren; Huang, Po-Han; Jeng, Long-Bin; Su, Wen-Pang; Chen, Hui-Chen

    2015-01-01

    Safety of either LigaSure or rubber band in closing inflamed appendiceal stump in acute appendicitis has been less investigated. In this study, cecal ligation followed by resecting inflamed cecum was performed to mimic appendectomy in a rat model of acute appendicitis. Rats were sacrificed immediately (Group A) and 7 days (Group B) after cecal resection, respectively. The cecal stumps were closed by silk ligature (S), 5 mm LigaSure (L), or rubber band (R). Seven days after cecal resection, the LigaSure (BL) and silk subgroups (BS) had significantly less intra-abdominal adhesion and better laparotomy wound healing than rubber band subgroup (BR). The initial bursting pressure at cecal stump was comparable among the three methods; along with tissue healing process, both BL and BS provided a higher bursting pressure than BR 7 days after appendectomy. BL subgroup had more abundant hydroxyproline deposition than BS and BR subgroup. Furthermore, serum TNF-α in BR group kept persistently increasing along with time after cecal resection. Thus, the finding that LigaSure but not rubber band is safe in sealing off the inflamed cecal stump in rat model of acute appendicitis suggests the possibility of applying LigaSure for appendectomy via single port procedure or natural orifice transluminal endoscopic surgery (NOTES).

  3. Comparison and Efficacy of LigaSure and Rubber Band Ligature in Closing the Inflamed Cecal Stump in a Rat Model of Acute Appendicitis

    PubMed Central

    Yeh, Chun-Chieh; Jan, Chia-Ing; Yang, Horng-Ren; Jeng, Long-Bin; Su, Wen-Pang

    2015-01-01

    Safety of either LigaSure or rubber band in closing inflamed appendiceal stump in acute appendicitis has been less investigated. In this study, cecal ligation followed by resecting inflamed cecum was performed to mimic appendectomy in a rat model of acute appendicitis. Rats were sacrificed immediately (Group A) and 7 days (Group B) after cecal resection, respectively. The cecal stumps were closed by silk ligature (S), 5 mm LigaSure (L), or rubber band (R). Seven days after cecal resection, the LigaSure (BL) and silk subgroups (BS) had significantly less intra-abdominal adhesion and better laparotomy wound healing than rubber band subgroup (BR). The initial bursting pressure at cecal stump was comparable among the three methods; along with tissue healing process, both BL and BS provided a higher bursting pressure than BR 7 days after appendectomy. BL subgroup had more abundant hydroxyproline deposition than BS and BR subgroup. Furthermore, serum TNF-α in BR group kept persistently increasing along with time after cecal resection. Thus, the finding that LigaSure but not rubber band is safe in sealing off the inflamed cecal stump in rat model of acute appendicitis suggests the possibility of applying LigaSure for appendectomy via single port procedure or natural orifice transluminal endoscopic surgery (NOTES). PMID:25699264

  4. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  5. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    NASA Astrophysics Data System (ADS)

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, Sanghyeon; Choi, Won Jun

    2016-02-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

  6. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    PubMed Central

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  7. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    SciTech Connect

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

  8. National solar technology roadmap: Wafer-silicon PV

    SciTech Connect

    Sopori, Bhushan

    2007-06-01

    This report applies to all bulk-silicon-based PV technologies, including those based on Czochralski, multicrystalline, float-zone wafers, and melt-grown crystals that are 100 μm or thicker, such as ribbons, sheet, or spheral silicon.

  9. An Advanced Wafer Stepper For Sub-Micron Fabrication

    NASA Astrophysics Data System (ADS)

    Mayer, Herbert E.; Loebach, Ernst W.

    1987-09-01

    An advanced wafer stepper is presented addressing the specific problems involved by sub-micron lithography such as alignment and focusing to multilayer resist films. New sub-systems were developed while maintaining principles well proven in a previous design. The system is described emphasizing the new sub-systems, and performance data are presented.

  10. Scatterometry on pelliclized masks: an option for wafer fabs

    NASA Astrophysics Data System (ADS)

    Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

    2007-03-01

    Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

  11. Method for reuse of wafers for growth of vertically-aligned wire arrays

    DOEpatents

    Spurgeon, Joshua M; Plass, Katherine E; Lewis, Nathan S; Atwater, Harry A

    2013-06-04

    Reusing a Si wafer for the formation of wire arrays by transferring the wire arrays to a polymer matrix, reusing a patterned oxide for several array growths, and finally polishing and reoxidizing the wafer surface and reapplying the patterned oxide.

  12. Bonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits

    NASA Astrophysics Data System (ADS)

    Kim, Hyun S.; Blick, Robert H.; Kim, D. M.; Eom, C. B.

    2004-09-01

    We report a method for bonding silicon-on-insulator wafers onto glass wafers. After pre-cleaning the wafers by an ozone and ultraviolet exposure, followed by mega-sonic water rinse, the SOI wafers are bonded to glass wafers in a vacuum chamber. This is performed at a temperature of 400 °C under an applied voltage of 700 V. The interface between the glass and SOI wafer is tested mechanically and inspected by electron beam microscopy. Furthermore, we demonstrate removal of the silicon bulk layer after wafer bonding. The quality of the single crystalline Si thin film on the glass wafers has been verified by four-circle x-ray diffraction and scanning electron microscopy. This process will allow us the integration of thin-film electronics in biological sensor applications.

  13. Correlation of the structural properties of a Pt seed layer with the perpendicular magnetic anisotropy features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 junctions via a 12-inch scale Si wafer process

    NASA Astrophysics Data System (ADS)

    Chae, Kyo-Suk; Lee, Du-Yeong; Shim, Tae-Hun; Hong, Jin-Pyo; Park, Jea-Gun

    2013-10-01

    We elucidated the interfacial-perpendicular magnetic anisotropy (i-PMA) features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 magnetic-tunnel-junctions as functions of the structural properties of the Pt seed layer including its thickness and ex situ annealing temperature. All of the samples were prepared in a 12-inch silicon wafer process for real industry applications. The observations of the M-H loops emphasize that a thinner Pt seed layer and a high ex situ annealing temperature enhance the surface roughness of the seed layer, providing better i-PMA characteristics. HR-TEM images of the samples were evaluated to understand the structural effects of thin and thick Pt seed layers.

  14. Advanced FTIR technology for the chemical characterization of product wafers

    NASA Astrophysics Data System (ADS)

    Rosenthal, P. A.; Bosch-Charpenay, S.; Xu, J.; Yakovlev, V.; Solomon, P. R.

    2001-01-01

    Advances in chemically sensitive diagnostic techniques are needed for the characterization of compositionally variable materials such as chemically amplified resists, low-k dielectrics and BPSG films on product wafers. In this context, Fourier Transform Infrared (FTIR) reflectance spectroscopy is emerging as a preferred technique to characterize film chemistry and composition, due to its non-destructive nature and excellent sensitivity to molecular bonds and free carriers. While FTIR has been widely used in R&D environments, its application to mainstream production metrology and process monitoring on product wafers has historically been limited. These limitations have been eliminated in a series of recent FTIR technology advances, which include the use of 1) new sampling optics, which suppress artifact backside reflections and 2) comprehensive model-based analysis. With these recent improvements, it is now possible to characterize films on standard single-side polished product wafers with much simpler training wafer sets and machine-independent calibrations. In this new approach, the chemistry of the films is tracked via the measured infrared optical constants as opposed to conventional absorbance measurements. The extracted spectral optical constants can then be reduced to a limited set of parameters for process control. This paper describes the application of this new FTIR methodology to the characterization of 1) DUV photoresists after various processing steps, 2) low-k materials of different types and after various curing conditions, and 3) doped glass BPSG films of various concentration and, for the first time, widely different thicknesses. Such measurements can be used for improved process control on actual product wafers.

  15. Performance of Ultra Hard Carbon Wear Coatings on Microgears Fabricated by Liga

    SciTech Connect

    Ager III, J.W.; Brown, I.G.; Christenson, T.R.; Dugger, M.T.; Follstaedt, D.M.; Knapp, J.A.; Monteiro, O.R.

    1998-12-18

    Stiction and friction are of concern for the reliable, long-term application of Ni-alloy micromachines. We have found that the application of a 30-70 nm hard carbon coating produces a significant reduction in the friction coefficient and wear rate of electroformed Ni substrates in reciprocating sliding contact under simulated MEMS operating conditions. To evaluate the performance of coated components, a series of 70-pm-thick microgears ranging in diameter from 0.2 to 2.2 mm were fabricated from electroformed Ni via standard LIGA processes and fixtured on posts in preparation for the coating procedure. A pulsed vacuum- arc deposition process was used to deposit a carbon coating on the gears with the plasma incident at a shallow angle to the gears' top surface. A sample bias of -2 keV was used in order to produce a coating with relatively low stress and good adhesion while maintaining high hardness. This coating process is known to be somewhat comformal to the component surfaces. The coating uniformity, particularly in the high-aspect-ratio areas between the gear teeth, was evaluated with micro-Raman spectroscopy. It is shown that the coating can be applied uniformly on the top gear surface. Between the gear teeth the coating was the same thickness as on top of the gear down to a point 50 ~m below the top surface. Below that point (i.e. between 50 and 70 Lm), the coating thickness is somewhat thinner, but is still present. These results demonstrate that it is possible to a deposit hard carbon coating on microgears to reduce friction and wear in micromachines.

  16. The Study of Deep Lithography and Moulding Process of LIGA Technique

    NASA Astrophysics Data System (ADS)

    Guo, Yuhua; Liu, Gang; Kan, Ya; Tian, Yangchao

    2007-01-01

    The knowledge of the development behavior, especially the development rate, is of primary importance for the study of deep x-ray lithography in LIGA technique. In the first part of this paper, we have measured the development rates of crosslinked PMMA foils irradiated in NSRL covering a wide dose range (bottom dose in the range:2.5-8.0 kJ/cm3). After the exposure, we use a so-called period-development method (to dip development in GG-developer for 20 minutes and clean in rinse solution for 40 minutes as a development period). For processing the experiment data, we get the KDβ model to describe our PMMA/GG-developer system. The aim of this work is to find out a stable experiment condition for deep X-ray lithography and development. The result shows that in small amount of dose (bottom dose range: 2.5-4 kJ/cm3), this model is very stable. While in large amount of dose (bottom dose range: 5-8kJ/cm3), the model becomes very sensitive and even unavailable. To verify the conclusion validity, the fixed dose range (bottom dose range: 3.5-4 kJ/cm3) is applied on PMMA microstructures. And the result shows an effective development process. In the following procedure, mold inserts can be produced by micro-electroforming and plastic replicas can be mass produced by hot embossing. To emboss high-aspect-ratio microstructures, the deformation of microstructures usually occurs due to the demolding forces between the sidewall of mold inserts and the thermoplastic (PMMA). To minimize the friction force the optimized experiment has been performed using Ni-PTFE compound material mold inserts. Typical defects like pull-up and damaged edges can be greatly reduced.

  17. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    NASA Astrophysics Data System (ADS)

    Qiusheng, Y.; Senkai, C.; Jisheng, P.

    2015-03-01

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  18. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    SciTech Connect

    Qiusheng, Y. Senkai, C. Jisheng, P.

    2015-03-30

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  19. Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

    NASA Astrophysics Data System (ADS)

    Matsuoka, Yoichi; Seki, Junichi; Nakayama, Takahiro; Nakagawa, Kazuki; Azuma, Hisanobu; Yamamoto, Kiyohito; Sato, Chiaki; Sakai, Fumio; Takabayashi, Yukio; Aghili, Ali; Mizuno, Makoto; Choi, Jin; Jones, Chris E.

    2016-10-01

    Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. On the mask side, a new replication tool, the FPA-1100 NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control, resolution and image placement accuracy. In this paper we discuss the progress made in both feature resolution and in meeting the image placement specification for replica masks.

  20. Enhanced capture rate for haze defects in production wafer inspection

    NASA Astrophysics Data System (ADS)

    Auerbach, Ditza; Shulman, Adi; Rozentsvige, Moshe

    2010-03-01

    Photomask degradation via haze defect formation is an increasing troublesome yield problem in the semiconductor fab. Wafer inspection is often utilized to detect haze defects due to the fact that it can be a bi-product of process control wafer inspection; furthermore, the detection of the haze on the wafer is effectively enhanced due to the multitude of distinct fields being scanned. In this paper, we demonstrate a novel application for enhancing the wafer inspection tool's sensitivity to haze defects even further. In particular, we present results of bright field wafer inspection using the on several photo layers suffering from haze defects. One way in which the enhanced sensitivity can be achieved in inspection tools is by using a double scan of the wafer: one regular scan with the normal recipe and another high sensitivity scan from which only the repeater defects are extracted (the non-repeater defects consist largely of noise which is difficult to filter). Our solution essentially combines the double scan into a single high sensitivity scan whose processing is carried out along two parallel routes (see Fig. 1). Along one route, potential defects follow the standard recipe thresholds to produce a defect map at the nominal sensitivity. Along the alternate route, potential defects are used to extract only field repeater defects which are identified using an optimal repeater algorithm that eliminates "false repeaters". At the end of the scan, the two defect maps are merged into one with optical scan images available for all the merged defects. It is important to note, that there is no throughput hit; in addition, the repeater sensitivity is increased relative to a double scan, due to a novel runtime algorithm implementation whose memory requirements are minimized, thus enabling to search a much larger number of potential defects for repeaters. We evaluated the new application on photo wafers which consisted of both random and haze defects. The evaluation procedure

  1. Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers for PV Cells

    SciTech Connect

    Guthrey, H.; Gorman, B.; Al-Jassim, M.

    2011-01-01

    As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay ({mu}PCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

  2. Wafer-level packaging with compression-controlled seal ring bonding

    DOEpatents

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  3. Compressive uniaxially strained silicon on insulator by prestrained wafer bonding and layer transfer

    NASA Astrophysics Data System (ADS)

    Himcinschi, C.; Reiche, M.; Scholz, R.; Christiansen, S. H.; Gösele, U.

    2007-06-01

    Wafer level compressive uniaxially strained silicon on insulator is obtained by direct wafer bonding of silicon wafers in cylindrically curved state, followed by thinning one of the wafers using the smart-cut process. The mapping of the wafer bow demonstrates the uniaxial character of the strain induced by the cylindrical bending. The interfacial properties are investigated by infrared transmission imaging, scanning acoustic microscopy, and transmission electron microscopy. UV-Raman spectroscopy is employed to determine the strain in the thin transferred layer as a function of radius of curvature of the initial bending.

  4. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    NASA Astrophysics Data System (ADS)

    Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

    2016-02-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

  5. Characterization of Boron Diffusion Phenomena According to the Specific Resistivity of N-Type Si Wafer.

    PubMed

    Lee, Woo-Jin; Choi, Chel-Jong; Park, Gye-Choon; Yang, O-Bong

    2016-02-01

    This paper is directed to characterize the boron diffusion process according to the specific resistivity of the Si wafer. N-type Si wafers were used with the specific resistivity of 0.5-3.2 omega-cm, 1.0-6.5 omega-cm and 2.0-8.0 omega-cm. The boron tribromide (BBr3) was used as boron source to create the PN junction on N-type Si wafer. The boron diffusion in N-type Si wafer was characterized by sheet resistance of wafer surface, secondary ion mass spectroscopy measurements (SIMS) and surface life time analysis. The degree of boron diffusion was depended on the variation in specific resistivity and sheet resistance of the bare N-type Si wafer. The boron diffused N-Si wafer exhibited the average junction depth of 750 nm and boron concentration of 1 x 10(19). N-type Si wafer with the different specific resistance considerably affected the boron diffusion length and life time of Si wafer. It was found that the lifetime of boron diffused wafer was proportional to the sheet resistance and resistivity. However, optimization process may necessary to achieve the high efficiency through the high sheet resistance wafer, because the metallization process control is very sensitive.

  6. Optimization of wafer-back pressure profile in chemical mechanical planarization

    NASA Astrophysics Data System (ADS)

    Yang, Tian-Shiang; Wang, Yao-Chen; Hu, Ian

    2008-11-01

    In chemical mechanical planarization (CMP), a rotating wafer is pressed facedown against a rotating pad, while a slurry is dragged into the pad--wafer interface to assist in planarizing the wafer surface. Due to stress concentration, the interfacial contact stress near the wafer edge generally is much higher than that near the wafer center, resulting in spatially nonuniform material removal rate and hence imperfect planarity of the wafer surface. Here, integrating theories of fluid film lubrication and two-dimensional contact mechanics, we calculate the interfacial contact stress and slurry pressure distributions. In particular, the possibility of using a multizone wafer-back pressure profile to improve the contact stress uniformity is examined, by studying a practical case. The numerical results indicate that using a two-zone wafer-back pressure profile with optimized zonal sizes and pressures can increase the ``usable'' wafer surface area by as much as 12%. Using an optimized three- zone wafer-back pressure profile, however, does not much further increase the usable wafer surface area.

  7. Metal adsorbent for alkaline etching aqua solutions of Si wafer

    NASA Astrophysics Data System (ADS)

    Tamada, Masao; Ueki, Yuji; Seko, Noriaki; Takeda, Toshihide; Kawano, Shin-ichi

    2012-08-01

    High performance adsorbent is expected to be synthesized for the removal of Ni and Cu ions from strong alkaline solution used in the surface etching process of Si wafer. Fibrous adsorbent was synthesized by radiation-induce emulsion graft polymerization onto polyethylene nonwoven fabric and subsequent amination. The reaction condition was optimized using 30 L reaction vessel and nonwoven fabric, 0.3 m width and 18 m long. The resulting fibrous adsorbent was evaluated by 48 wt% NaOH and KOH contaminated with Ni and Cu ions, respectively. The concentration levels of Ni and Cu ions was reduced to less than 1 μg/kg (ppb) at the flow rate of 10 h-1 in space velocity. The life of adsorbent was 30 times higher than that of the commercialized resin. This novel adsorbent was commercialized as METOLATE® since the ability of adsorption is remarkably higher than that of commercial resin used practically in Si wafer processing.

  8. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    SciTech Connect

    Montoya, Angela C.; Maji, Arup K.

    2010-02-22

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  9. Influence of the bonding front propagation on the wafer stack curvature

    SciTech Connect

    Navarro, E.; Bréchet, Y.; Barthelemy, A.; Radu, I.; Pardoen, T.; Raskin, J.-P.

    2014-08-11

    The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

  10. Scales

    ScienceCinema

    Murray Gibson

    2016-07-12

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain — a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  11. Scales

    SciTech Connect

    Murray Gibson

    2007-04-27

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain — a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  12. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    NASA Astrophysics Data System (ADS)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  13. Reticle and wafer CD variation for different dummy pattern

    NASA Astrophysics Data System (ADS)

    Ning, GuoXiang; Buergel, Christian; Ackmann, Paul; Staples, Marc; Thamm, Thomas; Lim, Chin Teong; Leschok, Andre; Roling, Stefan; Zhou, Anthony; Gn, Fang Hong; Richter, Frank

    2012-11-01

    Dummy pattern fill is added to a layout of a reticle for the purpose of raising the pattern-density of specific regions. The pattern-density has also an influence on different process-steps which were performed when manufacturing a reticle (e.g. proximity effect of electron beam exposure process, developer, and etch-processes). Although the reticle processes are set up to compensate the influence of the pattern density, dummy pattern can have an influence onto the reticle CD. When the isolated features become "nested" by insertion of dummy pattern, the reticle CD variation is even larger because nested features exacerbate the proximity effect of an electron beam. Another reason is that the etch ratio as well as the develop dynamics during the reticle manufacturing process are slightly dependent on the local pattern-density of pattern. With different dummy pattern around the main feature, the final reticle CD will be changed. Wafer CD of main feature is also dependant on the surrounding patterns which will induce different boundary conditions for wafer exposure. We have investigated three manufacturing sites for a 28nm first-metal layer reticle. Two of them were manufactured with a comparable process using the same advanced reticle binary blank material. For the third site a different reticle blank material with a relatively thin absorber layer thickness was used which was made with a comparable reticle process. The optical proximity correction (OPC) test patterns were designed with two different dummy patterns. The CD differences of the three reticles will be demonstrated for different dummy pattern and will be discussed individually. All three reticles have been exposed and the respective wafer critical dimension through pitch (CDTP) and linearity performance is demonstrated. Also the line-end performance for two dimensional (2D) structures is shown for the three sites of the reticle. The wafer CD difference for CDTP, linearity, and 2D structures are also

  14. Towards reduced impact of EUV mask defectivity on wafer

    NASA Astrophysics Data System (ADS)

    Jonckheere, R.; Van den Heuvel, D.; Pacco, A.; Pollentier, I.; Baudemprez, B.; Jehoul, C.; Hermans, J.; Hendrickx, E.

    2014-07-01

    The defectivity challenges of extreme ultraviolet (EUV) masks, that need to be addressed before production readiness of EUV lithography is assured from the mask perspective, are twofold. First, the EUV-specific defect type relating to the multi-layer (ML) mirror, the so-called ML-defects, require to become more detectable than they are printable. This not only requires proven capability of blank inspection, but also the existence of satisfactory printability mitigation strategies (comprising avoidance, pattern shift methodology, compensation repair). Both these assets need to become available within the mask supply chain, as there is little that can still be done about such residual defects at the wafer fab. In a production phase, finding unexpected printing ML-defects is unacceptable. It is shown how the specific way-of-working in use at imec, starting from the printed wafer, contributes to related learning and identification of remaining gaps, in getting this issue fully dealt with. The second challenge relates to particle contamination during use of the reticle at the wafer fab. Avoiding overlaycritical particles on the backside of NXE3100 reticles is facilitated by the established way-of-working. Minimizing the occurrence of particles "hopping" between reticles via the electrostatic clamp of the scanner (so-called clamp-traveling particles) is a major driver for appropriate mask cleaning. The latter may not have negative impact by frequent use, in view of the highly vulnerable EUV mask stack, and especially for the present "black-border" solution in which the ML is etched away at the image border on the reticle. A lot of effort is spent into monitoring of NXE3100 reticles for particle adders on the pattern side. This is realized by comparing past and present mask defect maps obtained by inspection of printed wafers with subsequent repeater analysis.

  15. Production of Optical Quality Free Standing Diamond Wafer

    DTIC Science & Technology

    2008-05-19

    Title : Production of Optical Quality Free Standing Diamond Wafer Prime Contractor : Onyx Optics, Inc. 6551 Sierra Lane Dublin, Ca 94568...www.onyxoptics.com Program Manager : Helmuth Meissner Onyx Optics, Inc. 6551 Sierra Lane Dublin, CA 94568 Email: hmeissner@onyxoptics.com Ph: 925...PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) Onyx Optics, Inc. 6551 Sierra Lane Dublin, Ca 94568 8. PERFORMING ORGANIZATION REPORT NUMBER 9. SPONSORING

  16. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, C.M.; Hui, W.C.

    1996-11-19

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

  17. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, Conrad M.; Hui, Wing C.

    1996-01-01

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

  18. Novel analytical methods for the characterization of oral wafers.

    PubMed

    Garsuch, Verena; Breitkreutz, Jörg

    2009-09-01

    This study aims at compensating the lack of adequate methods for the characterization of the novel dosage forms buccal wafers by applying recent advanced analytical techniques. Fast-dissolving oral wafers need special methods for assessing their properties in drug development and quality control. For morphologic investigations, scanning electron microscopy (SEM) and near-infrared chemical imaging (NIR-CI) were used. Differences in the distribution of the active pharmaceutical ingredient within wafers can be depicted by NIR-CI. Film thickness was determined by micrometer screw and coating thickness gauge revealing no significant differences between the obtained values. To distinguish between the mechanical properties of different polymers, tensile test was performed. Suitable methods to predict disintegration behaviour are thermomechanical analysis and contact angle measurement. The determination of drug release was carried out by three different methods. Fibre-optic sensor systems allow an online measurement of the drug release profiles and the thorough analysis even within the first seconds of disintegration and drug dissolution.

  19. Physical mechanisms of copper-copper wafer bonding

    SciTech Connect

    Rebhan, B.; Hingerl, K.

    2015-10-07

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing.

  20. Wettability investigating on the wet etching textured multicrystalline silicon wafer

    NASA Astrophysics Data System (ADS)

    Liu, Xiangju; Niu, Yuchao; Zhai, Tongguang; Ma, Yuying; Zhen, Yongtai; Ma, Xiaoyu; Gao, Ying

    2016-02-01

    In order to investigate the wettability properties of multicrystalline silicon (mc-Si), the different surface structures were fabricated on the as-cut p-type multi-wire slurry sawn mc-Si wafers, such as as-cut, polished and etched in various acid solutions. The contact angles and the XRD spectra of these samples were measured. It was noted that both the surface structures and the use of surfactant, such as Tween 80, made a stronger effect on wettability of the Si wafer. Due to the lipophilic groups of Tween 80 combined with the Si atoms while the hydrophilic groups of it were outward, a lipophilic surface of Si changed into a hydrophilic one and the rougher the surface, the stronger the hydrophily. Thus, it is feasible to add an appropriate surfactant into the etching solution during black-Si wafer fabrication for solar cells. In addition, different crystal plains of Si had different dangling bond density, so that their surface energies were different. A surface with higher surface energy could attract more water atoms and its wettability was better. However, the effect of crystal plain on the surface wettability was much weaker than surface morphology.

  1. Characterization and mitigation of overlay error on silicon wafers with nonuniform stress

    NASA Astrophysics Data System (ADS)

    Brunner, T.; Menon, V.; Wong, C.; Felix, N.; Pike, M.; Gluschenkov, O.; Belyansky, M.; Vukkadala, P.; Veeraraghavan, S.; Klein, S.; Hoo, C. H.; Sinha, J.

    2014-03-01

    Process-induced overlay errors are a growing problem in meeting the ever-tightening overlay requirements for integrated circuit production. While uniform process-induced stress is easily corrected, non-uniform stress across the wafer is much more problematic, often resulting in non-correctable overlay errors. Measurements of the wafer geometry of free, unchucked wafers give a powerful method for characterization of such non-uniform stress. We will describe a Patterned Wafer Geometry (PWG) tool, which uses optical methods to measure the geometry of in-process wafers. PWG data can be related to In-Plane Distortion (IPD) of the wafer through the PIR (Predicted IPD Residual) metric. This paper will explore the relationship between the PIR data and measured overlay data on Engineered Stress Monitor (ESM) wafers containing various designed stress variations. The process used to fabricate ESM wafers is quite versatile and can mimic many different stress variation signatures. For this study, ESM wafers were built with strong across-wafer stress variation and another ESM wafer set was built with strong intrafield stress variation. IPD was extensively characterized in two different ways: using standard overlay error metrology and using PWG metrology. Strong correlation is observed between these two independent sets of data, indicating that the PIR metric is able to clearly see wafer distortions. We have taken another step forward by using PIR data from the PWG tool to correct process-induced overlay error by feedforward to the exposure tool, a novel method that we call PWG-FF. We conclude that appropriate wafer geometry measurements of in-process wafers have strong potential to characterize and reduce process-induced overlay errors.

  2. Bulk Laser Material Modification: Towards a Kerfless Laser Wafering Process

    NASA Astrophysics Data System (ADS)

    LeBeau, James

    Due to the ever increasing relevance of finer machining control as well as necessary reduction in material waste by large area semiconductor device manufacturers, a novel bulk laser machining method was investigated. Because the cost of silicon and sapphire substrates are limiting to the reduction in cost of devices in both the light emitting diode (LED) and solar industries, and the present substrate wafering process results in >50% waste, the need for an improved ingot wafering technique exists. The focus of this work is the design and understanding of a novel semiconductor wafering technique that utilizes the nonlinear absorption properties of band-gapped materials to achieve bulk (subsurface) morphological changes in matter using highly focused laser light. A method and tool was designed and developed to form controlled damage regions in the bulk of a crystalline sapphire wafer leaving the surfaces unaltered. The controllability of the subsurface damage geometry was investigated, and the effect of numerical aperture of the focusing optic, energy per pulse, wavelength, and number of pulses was characterized for a nanosecond pulse length variable wavelength Nd:YAG OPO laser. A novel model was developed to describe the geometry of laser induced morphological changes in the bulk of semiconducting materials for nanosecond pulse lengths. The beam propagation aspect of the model was based on ray-optics, and the full Keldysh multiphoton photoionization theory in conjuncture with Thornber's and Drude's models for impact ionization were used to describe high fluence laser light absorption and carrier generation ultimately resulting in permanent material modification though strong electron-plasma absorption and plasma melting. Although the electron-plasma description of laser damage formation is usually reserved for extremely short laser pulses (<20 ps), this work shows that it can be adapted for longer pulses of up to tens of nanoseconds. In addition to a model

  3. The optimization of FA/O barrier slurry with respect to removal rate selectivity on patterned Cu wafers

    NASA Astrophysics Data System (ADS)

    Yi, Hu; Yan, Li; Yuling, Liu; Yangang, He

    2016-02-01

    Because the polishing of different materials is required in barrier chemical mechanical planarization (CMP) processes, the development of a kind of barrier slurry with improved removal rate selectivity for Cu/barrier/TEOS would reduce erosion and dishing defects on patterned Cu wafers. In this study, we developed a new benzotriazole-free barrier slurry named FA/O barrier slurry, containing 20 mL/L of the chelating agent FA/O, 5 mL/L surfactant, and a 1:5 concentration of abrasive particles. By controlling the polishing slurry ingredients, the removal rate of different materials could be controlled. For process integration considerations, the effect of the FA/O barrier slurry on the dielectric layer of the patterned Cu wafer was investigated. After CMP processing by the FA/O barrier slurry, the characteristics of the dielectric material were tested. The results showed that the dielectric characteristics met demands for industrial production. The current leakage was of pA scale. The resistance and capacitance were 2.4 kω and 2.3 pF, respectively. The dishing and erosion defects were both below 30 nm in size. CMP-processed wafers using this barrier slurry could meet industrial production demands. Project supported by the Special Project Items No. 2 in National Long-Term Technology Development Plan (No. 2009ZX02308), the Natural Science Foundation of Hebei Province (No. F2012202094), and the Doctoral Program Foundation of Xinjiang Normal University Plan (No. XJNUBS1226).

  4. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    SciTech Connect

    Daix, N. Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup −2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  5. Performances of accumulation-mode n- and p-MOSFETs on Si(110) wafers

    NASA Astrophysics Data System (ADS)

    Gaubert, Philippe; Teramoto, Akinobu; Sugawa, Shigetoshi

    2017-04-01

    In this study, we investigate the electrical and noise performances of accumulation-mode n- and p-MOSFETs on Si(110) wafers and compare them with conventional MOSFETs fabricated either on Si(100) or Si(110) wafers. With regard to electrical performances, accumulation-mode p-type MOSFETs are in every aspect superior. However, its n-type counterpart does not provide the best performances even though they are still superior to conventional transistors when fabricated on the same type of wafer. Conventional inversion-mode n-MOSFETs on Si(100) wafers still display the best performances. The simultaneous improvement and reduction in drivability respectively in the p- and n-type transistors make the accumulation-mode MOSFETs fabricated on Si(110) wafers extremely well suited for complementary technologies owing to their great balance in terms of drivability. With regard to noise evaluation, accumulation-mode MOSFETs on Si(110) wafers exhibit the highest noise level even though they compare relatively well with the inversion transistors on Si(110) wafers, especially for p-type ones. The lowest noise level is obtained for conventional inversion-mode MOSFETs on Si(100) wafers, and the type of wafer upon which transistors are fabricated is the reason. Indeed, the fabrication of high-quality Si/SiO2 interfaces is better achieved for silicon wafers with a (100) crystallographic orientation, leading to few interface defects and consequently less noise.

  6. Two-dimensional X-ray waveguides: fabrication by wafer-bonding process and characterization

    NASA Astrophysics Data System (ADS)

    Kohlstedt, A.; Kalbfleisch, S.; Salditt, T.; Reiche, M.; Gösele, U.; Lima, E.; Willmott, P.

    2008-04-01

    The fabrication of two-dimensionally confining X-ray waveguides enables the generation of nanoscopic X-ray beams. First applications of such waveguides for lens-less holographic imaging have already been demonstrated, but were limited by the fabrication methods and the design. To overcome these limitations, we present here the fabrication process for a second generation of X-ray waveguide with air or vacuum as guiding channel, based on e-beam lithography, ion etching and subsequent wafer bonding. This is a first step towards waveguides fulfilling requirements of high transmission and high confinement, since the process can be scaled down to smaller channel dimensions from the present structures. We address the structuring method used and present results of first X-ray characterization at synchrotron beamlines, under two entirely different beam settings, corresponding to the coupling of a coherent beam and an incoherent beam.

  7. [As the twig is bent, so is the tree inclined: children and the Liga Brasileira de Higiene Mental's eugenic programs].

    PubMed

    Reis, J R

    2000-01-01

    Created in the early 1920s, at a moment when the country's psychiatric field was embracing the preventive outlook, the Liga Brasileira de Higiene Mental included within its members the elite of Brazilian psychiatry, along with a number of physicians and intellectuals. The article discusses the institution's proposals for intervention among children. The league ended up incorporating into its theoretical arsenal the basic themes of mental hygiene and eugenics as part of its general goal of collaborating in Brazil's process of "racial sanitation". With this objective in mind, and viewing the child as a "pre-citizen" who is a "fundamental part within the man of the future", league members included the children's issue in their projects and saw an imperative need for mental health care from early ages on.

  8. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  9. Characterization of wafer charging mechanisms and oxide survival prediction methodology

    SciTech Connect

    Lukaszek, W.; Dixon, W.; Vella, M.; Messick, C.; Reno, S.; Shideler, J.

    1994-04-01

    Unipolar, EEPROM-based peak potential sensors and current sensors have been used to characterize the I-V relationship of charging transients which devices normally experience during the course of ion implantation. The results indicate that the charging sources may appear to behave like current-sources or voltage-sources, depending on the impedance of the load. This behavior may be understood in terms of plasma concepts. The ability to empirically characterize the I-V characteristics of charging sources using the CHARM-2 monitor wafers opens the way for prediction of failure rates of oxides subjected to specific processes, if the oxide Q{sub bd} distributions are known.

  10. Selected applications of photothermal and photoluminescence heterodyne techniques for process control in silicon wafer manufacturing

    NASA Astrophysics Data System (ADS)

    Ehlert, Andreas; Kerstan, Michael; Lundt, Holger; Huber, Anton; Helmreich, Dieter; Geiler, Hans-Dieter; Karge, Harald; Wagner, Matthias

    1997-02-01

    Two noncontact laser-based heterodyne techniques, photothermal heterodyne (PTH) and photoluminescence heterodyne (PLH), are introduced and applied to processing and quality control in silicon wafer manufacturing. The crystallographic characteristics of process-induced defects in silicon wafers are suitable for the application of PTH and PLH techniques, which are demonstrated on selected examples from different steps of silicon wafer production. Both PLH and PTH techniques meet the demand for nondestructive and on-line-suitable measurement in the semiconductor industry.

  11. Optical characterization of double-side-textured silicon wafer based on photonic nanostructures for thin-wafer crystalline silicon solar cells

    NASA Astrophysics Data System (ADS)

    Tayagaki, Takeshi; Furuta, Daichi; Aonuma, Osamu; Takahashi, Isao; Hoshi, Yusuke; Kurokawa, Yasuyoshi; Usami, Noritaka

    2017-04-01

    Crystalline silicon (c-Si) wafers have found extensive use in photovoltaic applications. In this regard, to enable advanced light manipulation in thin-wafer c-Si solar cells, we demonstrate the fabrication of double-side-textured Si wafers composed of a front-surface photonic nanotexture fabricated with quantum dot arrays and a rear-surface microtexture. The addition of the rear-surface microtexture to a Si wafer with the front-surface photonic nanotexture increases the wafer’s optical absorption in the near-infrared region, thus enabling enhanced light trapping. Excitation spectroscopy reveals that the photoluminescence intensity in the Si wafer with the double-sided texture is higher than that in the Si wafer without the rear-surface microtexture, thus indicating an increase in true optical absorption in the Si wafer with the double-sided texture. Our results indicate that the double-sided textures, i.e., the front-surface photonic nanotexture and rear-surface microtexture, can effectively reduce the surface reflection loss and provide enhanced light trapping, respectively.

  12. Fabrication of micro-nano composite textured surface for slurry sawn mc-Si wafers cell

    NASA Astrophysics Data System (ADS)

    Niu, Y. C.; liu, Z.; Ren, X. K.; Liu, X. J.; Liu, H. T.; Jiang, Y. S.

    2017-01-01

    In order to enhance the PV efficiency of the cell made from slurry sawn (SS) mc-Si wafers, using a Ag-assisted electroless etching (AgNO3+HF+H2O2) combined with an auxiliary etching (HF+HNO3) the RENA textured SS mc-Si wafers (called as RENA wafers) were further textured (nano pores were formed on the original micro pits) to change into micro-nano composite textured wafers (called as MN-RENA wafers). The solar cells made from the MN-RENA wafers had a better PV efficiency than that of RENA wafers. This is mainly attributed to the higher light-trapping of the micro-nano composite texture. The nano size texture enhanced the light-trap of wafer surface and, at the same time, the micro size texture maintained the light-trap uniformity of different gains of RENA wafer. However, there still exist a potential for optimization, such as, the SiNx passviation coating should be improved to be deposited more uniformly in order to passivate the bottom of pits better and to reduce the reflectance of the obtuse tips of pits.

  13. Improved quality control of silicon wafers using novel off-line air pocket image analysis

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Sanna, M. Cristina

    2014-08-01

    Air pockets (APK) occur randomly in Czochralski (Cz) grown silicon (Si) crystals and may become included in wafers after slicing and polishing. Previously the only APK of interest were those that intersected the front surface of the wafer and therefore directly impacted device yield. However mobile and other electronics have placed new demands on wafers to be internally APK-free for reasons of thermal management and packaging yield. We present a novel, recently patented, APK image processing technique and demonstrate the use of that technique, off-line, to improve quality control during wafer manufacturing.

  14. Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

    NASA Astrophysics Data System (ADS)

    Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

    2015-07-01

    Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

  15. How accurate are rapid prototyped (RP) final orthognathic surgical wafers? A pilot study.

    PubMed

    Shqaidef, Abedalrahman; Ayoub, Ashraf F; Khambay, Balvinder S

    2014-09-01

    Computer packages have been introduced to simulate the movements of the jaw in three dimensions to facilitate planning of treatment. After final 3-dimensional virtual planning, a rapid prototype wafer can be manufactured and used in theatre. Our aim was to assess the accuracy of rapid prototyping of virtual wafers derived from laser scanned dental models using CAD/CAM software. Upper and lower plaster models from 10 orthognathic patients, the articulated models, and the conventional wafers were scanned. The virtual wafers were made from CAD/CAM software, and printed on a stereolithographic printer. We also scanned the articulated models with rapid prototype wafers in place. The validity of the final rapid prototype wafer was measured by the accuracy with which upper and lower models related to one another. The absolute mean error of the rapid prototype wafer when aligned with the dental models was 0.94 (0.09) mm. The absolute distance of the 2 models articulated by conventional and rapid prototype wafers ranged from 0.04 - 1.73mm. The rapid prototype wafers were able to orientate the upper and lower dental models with an absolute mean error of 0.94 (0.09) mm, but it ranged from 0.04-1.73mm.

  16. Growth of Catalyst-Free Epitaxial InAs Nanowires on Si Wafers Using Metallic Masks.

    PubMed

    Soo, M Teng; Zheng, Kun; Gao, Qiang; Tan, H Hoe; Jagadish, Chennupati; Zou, Jin

    2016-07-13

    Development of heteroepitaxy growth of catalyst-free vertical III-V nanowires on Si wafers is highly desirable for future nanoscale Si-based electronic and optoelectronic devices. In this study, a proof-of-concept approach is developed for catalyst-free heteroepitaxy growth of InAs nanowires on Si wafers. Before the growth of InAs nanowires, a Si-compatible metallic film with a thickness of several tens of nanometers was predeposited on a Si wafer and then annealed to form nanosize openings so as to obtain a metallic mask. These nano-openings exposed the surface of the Si wafer, which allowed subsequent nucleation and growth of epitaxial InAs nanowires directly on the surface of the Si wafer. The small size of the nano-openings limits the lateral growth of the nanostructures but promotes their axial growth. Through this approach, catalyst-free InAs nanowires were grown on both Si (111) and (001) wafers successfully at different growth temperatures. In particular, ultralong defect-free InAs nanowires with the wurtzite structure were grown the Si (111) wafers at 550 °C using the Ni mask. This study offers a simple, cost-effective, and scalable method to grow catalyst-free III-V nanowires on Si wafers. The simplicity of the approach opens a new avenue for the growth and integration of catalyst-free high-quality heteroepitaxial III-V nanowires on Si wafers.

  17. Temperature switching waves in a silicon wafer on lamp-based heating

    NASA Astrophysics Data System (ADS)

    Ovcharov, Vladimir V.; Kurenya, Alexey L.; Rudakov, Valery I.; Prigara, Valeriya P.

    2016-12-01

    The dynamic properties of a silicon wafer thermally heated up under a bistable regime in a lamp-based reactor are simulated with regard to an optical non-gomogeneity as a nucleus of a high-temperature phase. The optical non-gomogeneity is represented by a doped layer region on the surface of the wafer imposed by radiation. It is shown that under these conditions temperature switching waves are formed in the wafer. Experimental verification of propagating the switching waves of temperature is obtained at the silicon wafer transition derived from the lower-temperature state to its upper-temperature state and the velocity of the waves is evaluated.

  18. Measuring the thickness profiles of wafers to subnanometer resolution using Fabry-Perot interferometry

    SciTech Connect

    Farrant, David I.; Arkwright, John W.; Fairman, Philip S.; Netterfield, Roger P

    2007-05-20

    The resolution of an angle-scanning technique for measuring transparent optical wafers is analyzed, and it is shown both theoretically and experimentally that subnanometer resolution can be readily achieved. Data are acquired simultaneously over the whole area of the wafer, producing two-dimensional thickness variation maps in as little as 10 s.Repeatabilities of 0.07 nm have been demonstrated, and wafers of up to100 mm diameter have been measured, with1 mm or better spatial resolution. A technique for compensating wafer and system aberrations is incorporated and analyzed.

  19. Dual-Side Wafer Processing and Resonant Tunneling Transistor Applications

    SciTech Connect

    Moon, J.S.; Simmons, J.A.; Wendt, J.R.; Hietala, V.M.; Reno, J.L.; Baca, W.E.; Blount, M.A.

    1999-07-20

    We describe dual-side wafer processing and its application to resonant tunneling transistors in a planar configuration. The fabrication technique utilizes a novel flip-chip, wafer thinning process called epoxy-bond and stop-etch (EBASE) process, where the substrate material is removed by selective wet etching and stopped at an etch-stop layer. This EBASE method results in a semiconductor epitaxial layer that is typically less than a micron thick and has a mirror-finish, allowing backside gates to be placed in close proximity to frontside gates. Utilizing this technique, a resonant tunneling transistor--the double electron layer tunneling transistor (DELTT)--can be fabricated in a fully planar configuration, where the tunneling between two selectively-contacted 2DEGs in GaAs or InGaAs quantum wells is modulated by surface Schottky gate. Low temperature electrical characterization yields source-drain I-V curves with a gate-tunable negative differential resistance.

  20. UV/Ozone Cleaning For Organics Removal On Silicon Wafers

    NASA Astrophysics Data System (ADS)

    Zafonte, Leo; Chiu, Rafael

    1984-06-01

    The feasibility for using a combination of ultraviolet light and ozone - UV/Ozone Cleaning - for organics removal and photoresist residue cleaning from silicon semiconductor wafers was investigated. The process generates a highly oxidative atmosphere that is specific for removing trace organic residues. Product of the reactions are carbon dioxide and water. In most cases, stable inorganic materials such as oxide coatings remain unaffected. UV/Ozone exposure of silicon causes formation of a thin layer of silicon oxide that tends to retard further oxidation of the silicon. Based on the expected photochemistry o," this process, specific enhancements to accelerate the cleaning rates were tested. The enhancements involved the use of both gas phase and liquio phase additives, and comparative rates of removal were determined. The technique was tested on several photoresists, potential organic residues, and common solvent systems. The photoresists studies were primarily positive resists and were tested at several levels of ion implantation. The results of the testing suggests that the highest potential applications of UV/Ozone Cleaning in the processing of semiconductor wafers include: a) Removal of solvent residues and process contaminants. b) A pre-process step to insure cleanliness by removal of residual organic or airborne organic contaminants. c) As a post-process step to insure cleanliness or to remove trace organics.

  1. Deposition and removal of sodium contamination on silicon wafers

    NASA Astrophysics Data System (ADS)

    Constant, I.; Tardif, F.; Derrien, J.

    2000-01-01

    In this paper investigations are performed in order to understand the source of sodium contamination in clean-room environments and to find different cleaning processes able to limit or suppress sodium deposition. In a clean-room environment, the human being has been identified as one of the major sources of sodium. The airborne sodium contamination is essentially transmitted in particle form. In order to limit sodium deposition from the air, the wafers awaiting subsequent processing need to be stored in a protective box or placed far from the human environment and should not be left for much more than 1 week in a class 1 clean room. Also, wet chemistries could cause sodium contamination on wafers particularly during the deionized water rinse. In order to limit the possible contamination, the sodium deposition mechanisms have been studied: they show the typical characteristics of Langmuir adsorption. Temperature and ionic concentration are both parameters which influence the deposition. In water, sodium deposition can be avoided by introducing acid or alkaline solutions or increasing the temperature: it can be drastically reduced by adding traces of HCl (0.01%). Finally, other cleaning chemistries such as SC1 (NH4 OH-H2 O2 -H2 O) in 0.25:1:5 proportion, SC2 (HCl-H2 O2 -H2 O) in 1:1:5 proportion, 0.1% HF and SPM (H2 SO4 -H2 O2 ) in 3:1 proportion reduce the contamination as well.

  2. Thin-film resistance thermometers on silicon wafers

    NASA Astrophysics Data System (ADS)

    Kreider, Kenneth G; Ripple, Dean C; Kimes, William A

    2009-04-01

    We have fabricated Pt thin-film resistors directly sputtered on silicon substrates to evaluate their use as resistance thermal detectors (RTDs). This technique was chosen to achieve more accurate temperature measurements of large silicon wafers during semiconductor processing. High-purity (0.999 968 mass fraction) platinum was sputter deposited on silicon test coupons using titanium and zirconium bond coats. These test coupons were annealed, and four-point resistance specimens were prepared for thermal evaluation. Their response was compared with calibrated platinum-palladium thermocouples in a tube furnace. We evaluated the effects of furnace atmosphere, thin-film thickness, bond coats, annealing temperature and peak thermal excursion of the Pt thin films. Secondary ion mass spectrometry (SIMS) was performed to evaluate the effect of impurities on the thermal resistance coefficient, α. We present typical resistance versus temperature curves, hysteresis plots versus temperature and an analysis of the causes of uncertainties in the measurement of seven test coupons. We conclude that sputtered thin-film platinum resistors on silicon wafers can yield temperature measurements with uncertainties of less than 1 °C, k = 1 up to 600 °C. This is comparable to or better than commercially available techniques.

  3. Process Performance of Optima XEx Single Wafer High Energy Implanter

    SciTech Connect

    Kim, J. H.; Yoon, Jongyoon; Kondratenko, S.; David, J.; Rubin, L. M.; Jang, I. S.; Cha, J. C.; Joo, Y. H.; Lee, A. B.; Jin, S. W.

    2011-01-07

    To meet the process requirements for well formation in future CMOS memory production, high energy implanters require more robust angle, dose, and energy control while maintaining high productivity. The Optima XEx high energy implanter meets these requirements by integrating a traditional LINAC beamline with a robust single wafer handling system. To achieve beam angle control, Optima XEx can control both the horizontal and vertical beam angles to within 0.1 degrees using advanced beam angle measurement and correction. Accurate energy calibration and energy trim functions accelerate process matching by eliminating energy calibration errors. The large volume process chamber and UDC (upstream dose control) using faraday cups outside of the process chamber precisely control implant dose regardless of any chamber pressure increase due to PR (photoresist) outgassing. An optimized RF LINAC accelerator improves reliability and enables singly charged phosphorus and boron energies up to 1200 keV and 1500 keV respectively with higher beam currents. A new single wafer endstation combined with increased beam performance leads to overall increased productivity. We report on the advanced performance of Optima XEx observed during tool installation and volume production at an advanced memory fab.

  4. A thermal microprobe fabricated with wafer-stage processing

    NASA Astrophysics Data System (ADS)

    Zhang, Yongxia; Zhang, Yanwei; Blaser, Juliana; Sriram, T. S.; Enver, Ahsan; Marcus, R. B.

    1998-05-01

    A thermal microprobe has been designed and built for high resolution temperature sensing. The thermal sensor is a thin-film thermocouple junction at the tip of an atomic force microprobe (AFM) silicon probe needle. Only wafer-stage processing steps are used for the fabrication. For high resolution temperature sensing it is essential that the junction be confined to a short distance at the AFM tip. This confinement is achieved by a controlled photoresist coating process. Experiment prototypes have been made with an Au/Pd junction confined to within 0.5 μm of the tip, with the two metals separated elsewhere by a thin insulating oxide layer. Processing begins with double-polished, n-type, 4 in. diameter, 300-μm-thick silicon wafers. Atomically sharp probe tips are formed by a combination of dry and wet chemical etching, and oxidation sharpening. The metal layers are sputtering deposited and the cantilevers are released by a combination of KOH and dry etching. A resistively heated calibration device was made for temperature calibration of the thermal microprobe over the temperature range 25-110 °C. Over this range the thermal outputs of two microprobes are 4.5 and 5.6 μV/K and is linear. Thermal and topographical images are also obtained from a heated tungsten thin film fuse.

  5. Residual stress in silicon wafer using IR polariscope

    NASA Astrophysics Data System (ADS)

    Lu, Zhijia; Wang, Pin; Asundi, Anand

    2008-09-01

    The infrared phase shift polariscope (IR-PSP) is a full-field optical technique for stress analysis in Silicon wafers. Phase shift polariscope is preferred to a conventional polariscope, as it can provide quantitative information of the normal stress difference and the shear stress in the specimen. The method is based on the principles of photoelasticity, in which stresses induces temporary birefringence in materials which can be quantitatively analyzed using a phase shift polariscope. Compared to other stress analysis techniques such as x-ray diffraction or laser scanning, infrared photoelastic stress analysis provides full-field information with high resolution and in near real time. As the semiconductor fabrication is advancing, larger wafers, thinner films and more compact packages are being manufactured. This results in a growing demand of process control. Residual stress exist in silicon during semiconductor fabrication and these stresses may make cell processing difficult or even cause the failure of the silicon. Reducing these stresses would improve manufacturability and reliability. Therefore stress analysis is essential to trace the root cause of the stresses. The polariscope images are processed using MATLAB and four-step phase shifting method to provide quantitative as well as qualitative information regarding the residual stress of the sample. The system is calibrated using four-point bend specimen and then the residual stress distribution in a MEMS sample is shown.

  6. Steel bridge fatigue crack detection with piezoelectric wafer active sensors

    NASA Astrophysics Data System (ADS)

    Yu, Lingyu; Giurgiutiu, Victor; Ziehl, Paul; Ozevin, Didem; Pollock, Patrick

    2010-04-01

    Piezoelectric wafer active sensors (PWAS) are well known for its dual capabilities in structural health monitoring, acting as either actuators or sensors. Due to the variety of deterioration sources and locations of bridge defects, there is currently no single method that can detect and address the potential sources globally. In our research, our use of the PWAS based sensing has the novelty of implementing both passive (as acoustic emission) and active (as ultrasonic transducers) sensing with a single PWAS network. The combined schematic is using acoustic emission to detect the presence of fatigue cracks in steel bridges in their early stage since methods such as ultrasonics are unable to quantify the initial condition of crack growth since most of the fatigue life for these details is consumed while the fatigue crack is too small to be detected. Hence, combing acoustic emission with ultrasonic active sensing will strengthen the damage detection process. The integration of passive acoustic emission detection with active sensing will be a technological leap forward from the current practice of periodic and subjective visual inspection, and bridge management based primarily on history of past performance. In this study, extensive laboratory investigation is performed supported by theoretical modeling analysis. A demonstration system will be presented to show how piezoelectric wafer active sensor is used for acoustic emission. Specimens representing complex structures are tested. The results will also be compared with traditional acoustic emission transducers to identify the application barriers.

  7. Molded, wafer level optics for long wave infra-red applications

    NASA Astrophysics Data System (ADS)

    Franks, John

    2016-05-01

    For many years, the Thermal Imaging market has been driven by the high volume consumer market. The first signs of this came with the launch of night vision systems for cars, first by Cadillac and Honda and then, more successfully by BMW, Daimler and Audi. For the first time, simple thermal imaging systems were being manufactured at the rate of more than 10,000 units a year. This step change in volumes enabled a step change in system costs, with thermal imaging moving into the consumer's price range. Today we see that the consumer awareness and the consumer market continues to increase with the launch of a number of consumer focused smart phone add-ons. This has brought a further step change in system costs, with the possibility to turn your mobile phone into a thermal imager for under $250. As the detector technology has matured, the pixel pitches have dropped from 50μm in 2002 to 12 μm or even 10μm in today's detectors. This dramatic shrinkage in size has had an equally dramatic effect on the optics required to produce the image on the detector. A moderate field of view that would have required a focal length of 40mm in 2002 now requires a focal length of 8mm. For wide field of view applications and small detector formats, focal lengths in the range 1mm to 5mm are becoming common. For lenses, the quantity manufactured, quality and costs will require a new approach to high volume Infra-Red (IR) manufacturing to meet customer expectations. This, taken with the SwaP-C requirements and the emerging requirement for very small lenses driven by the new detectors, suggests that wafer scale optics are part of the solution. Umicore can now present initial results from an intensive research and development program to mold and coat wafer level optics, using its chalcogenide glass, GASIR®.

  8. 75 FR 76952 - Grant of Authority for Subzone Status; Lam Research Corporation (Wafer Fabrication Equipment...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-12-10

    ... Fabrication Equipment) Fremont, Newark, and Livermore, CA Pursuant to its authority under the Foreign-Trade... authority to establish a special-purpose subzone at the wafer fabrication equipment manufacturing and... authority for subzone status for activity related to the manufacturing and distribution of wafer...

  9. Non-Destructive Damping Measurement for Wafer-Level Packaged Microelectromechanical System (MEMS) Acceleration Switches

    DTIC Science & Technology

    2014-09-01

    Non-destructive Damping Measurement for Wafer-level Packaged Microelectromechanical System (MEMS) Acceleration Switches by Ryan Knight and...Microelectromechanical System (MEMS) Acceleration Switches Ryan Knight and Evan Cheng Sensors and Electron Devices Directorate, ARL...Damping Measurement for Wafer-level Packaged Microelectromechanical System (MEMS) Acceleration Switches 5a. CONTRACT NUMBER 5b. GRANT NUMBER

  10. A meta-analysis comparing the outcomes of LigaSure Small Jaw versus clamp-and-tie technique or Harmonic Focus Scalpel in thyroidectomy

    PubMed Central

    Zhang, Lei; Li, Namei; Yang, Xuemei; Chen, Jie

    2017-01-01

    Abstract Background: LigaSure (LS) Small Jaw is a surgical hemostasis equipment that is newly introduced in thyroid surgery. The objective of this study is to assess the short-term efficacy and safety outcomes of LS Small Jaw compared with clamp-and-tie technique or Harmonic Focus Scalpel in thyroidectomy. Methods: A literature search was performed in the PubMed and Embase databases (until June 12, 2016) that reported the comparisons between LS Small Jaw and other techniques in thyroidectomy. Quality assessments were performed according to The Cochrane Collaboration's risk of bias tool and a modification of the Newcastle-Ottawa Scale in randomized controlled trials (RCTs) and non-RCTs, respectively. All statistical analyses were conducted using RevMan 5.3. Results: Finally, 7 studies with 813 patients were included into the meta-analysis, and all included studies were comparable with moderate-to-high quality. There was significant reduced operative time in LS Small Jaw, compared with clamp-and-tie (mean difference [MD] = −17.49, 95% confidence interval [CI]: −22.20 to 12.77, P < 0.00001) or Harmonic Focus Scalpel (MD = −2.29, 95% CI: −3.19 to 1.39, P < 0.00001). Besides, other perioperative outcomes including intraoperative blood loss and postoperative blood loss favored LS Small Jaw compared with clamp-and-tie. In terms of complications, less-temporary hypocalcemia rate was observed in LS Small Jaw compared with clamp-and-tie (odds ratio [OR] = 0.49, 95% CI: 0.27–0.90, P = 0.02), although no significant difference was detected compared with Harmonic Focus Scalpel (OR = 0.47, 95% CI: 0.14–1.56, P = 0.22). Other complications such as length of hospital stay, permanent hypocalcemia, temporary or permanent recurrent laryngeal nerve palsy, and hematomas were not significant. Conclusion: In conclusion, LS Small Jaw is more favorable than clamp-and-tie technique or Harmonic Focus Scalpel in thyroidectomy. PMID:28296728

  11. Visible luminescence from silicon wafers subjected to stain etches

    NASA Technical Reports Server (NTRS)

    Fathauer, R. W.; George, T.; Ksendzov, A.; Vasquez, R. P.

    1992-01-01

    Etching of Si in a variety of solutions is known to cause staining. These stain layers consist of porous material similar to that produced by anodic etching of Si in HF solutions. In this work, photoluminescence peaked in the red from stain-etched Si wafers of different dopant types, concentrations, and orientations produced in solutions of HF:HNO3:H2O was observed. Luminescence is also observed in stain films produced in solutions of NaNO2 in HF, but not in stain films produced in solutions of CrO3 in HF. The luminescence spectra are similar to those reported recently for porous Si films produced by anodic etching in HF solutions. However, stain films are much easier to produce, requiring no special equipment.

  12. Nanotribology of nanooxide materials in ionic liquids on silicon wafers

    NASA Astrophysics Data System (ADS)

    Hamidunsani, Ahmad Termizi; Radiman, Shahidan; Hassan, Masjuki Haji; Rahman, Irman Abdul

    2015-09-01

    Nanotribological properties have a significant impact on daily life. Ionic liquids (ILs) are becoming new favourable lubricants currently in researches. Addition of nanooxide materials in lubricants provide improvements to new technology. In this study, we determine nanotribological properties of BMIM+BF4- IL addition of different amount of ZnO nanomaterial on single crystals silicon wafer (Si110). The viscosity changes of IL samples against temperature increase were determined by rheological method. Nanotribological properties were determined by changes in friction coefficient and wear rate on silicon substrate surfaces using a reciprocating friction and wear monitor in 1 hour duration time. Aluminium cylinders acted as pins used to rub Si (110) substrate sample surfaces. Thus, on range between 0 mg to 3.5 mg of ZnO nanooxide material dispersed in 10ml BMIM+BF4- showed a good friction coefficient, wear and surface roughness reduction.

  13. Precise Fabrication of Silicon Wafers Using Gas Cluster Ion Beams

    SciTech Connect

    Isogai, Hiromichi; Toyoda, Eiji; Izunome, Koji; Kashima, Kazuhiko; Mashita, Takafumi; Toyoda, Noriaki; Yamada, Isao

    2009-03-10

    Precise surface processing of a silicon wafer was studied by using a gas cluster ion beam (GCIB). The damage caused to the silicon surface was strongly dependent on irradiation parameters. The extent of damage varied with the species of source gas and the acceleration voltage (Va) of cluster ions. It also varied with the cluster size and residual gas pressure. The influence of electron acceleration voltage (Ve) used for ionization of a neutral cluster was also investigated. The irradiation damage, such as an amorphous silicon (a-Si) layer, a mixed layer of a-Si and c-Si (transition layer), and surface roughness, was increased with Ve. It is suggested that the increase in the amount of energy per atom was induced by high Ve, because of variation of the cluster size and/or cluster charge. An undamaged smooth surface can be produced by Ar-GCIB irradiation at low Ve and Va.

  14. Chemical strategies for die/wafer submicron alignment and bonding.

    SciTech Connect

    Martin, James Ellis; Baca, Alicia I.; Chu, Dahwey; Rohwer, Lauren Elizabeth Shea

    2010-09-01

    This late-start LDRD explores chemical strategies that will enable sub-micron alignment accuracy of dies and wafers by exploiting the interfacial energies of chemical ligands. We have micropatterned commensurate features, such as 2-d arrays of micron-sized gold lines on the die to be bonded. Each gold line is functionalized with alkanethiol ligands before the die are brought into contact. The ligand interfacial energy is minimized when the lines on the die are brought into registration, due to favorable interactions between the complementary ligand tails. After registration is achieved, standard bonding techniques are used to create precision permanent bonds. We have computed the alignment forces and torque between two surfaces patterned with arrays of lines or square pads to illustrate how best to maximize the tendency to align. We also discuss complex, aperiodic patterns such as rectilinear pad assemblies, concentric circles, and spirals that point the way towards extremely precise alignment.

  15. High performance LWIR microbolometer with Si/SiGe quantum well thermistor and wafer level packaging

    NASA Astrophysics Data System (ADS)

    Roer, Audun; Lapadatu, Adriana; Bring, Martin; Wolla, Erik; Hohler, Erling; Kittilsland, Gjermund

    2011-11-01

    An uncooled microbolometer with peak responsivity in the long wave infrared region of the electromagnetic radiation is developed at Sensonor Technologies. It is a 384 x 288 focal plane array with a pixel pitch of 25μm, based on monocrystalline Si/SiGe quantum wells as IR sensitive material. The high sensitivity (TCR) and low 1/f noise are the main performance characteristics of the product. The frame rate is maximum 60Hz and the output interface is digital (LVDS). The quantum well thermistor material is transferred to the read-out integrated circuit (ROIC) by direct wafer bonding. The ROIC wafer containing the released pixels is bonded in vacuum with a silicon cap wafer, providing hermetic encapsulation at low cost. The resulting wafer stack is mounted in a standard ceramic package. In this paper the architecture of the pixels and the ROIC, the wafer packaging and the electro-optical measurement results are presented.

  16. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbrecher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-01-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  17. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbracher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-07-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  18. Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

    SciTech Connect

    Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

    2006-03-13

    An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection.

  19. The terminal portion of leptospiral immunoglobulin-like protein LigA confers protective immunity against lethal infection in the hamster model of leptospirosis

    PubMed Central

    Silva, Éverton F.; Medeiros, Marco A.; McBride, Alan J. A.; Matsunaga, Jim; Esteves, Gabriela S.; Ramos, João G. R.; Santos, Cleiton S.; Croda, Júlio; Homma, Akira; Dellagostin, Odir A.; Haake, David A.; Reis, Mitermayer G.; Ko, Albert I.

    2007-01-01

    Subunit vaccines are a potential intervention strategy against leptospirosis, which is a major public health problem in developing countries and a veterinary disease in livestock and companion animals worldwide. Leptospiral immunoglobulin-like (Lig) proteins are a family of surface-exposed determinants that have Ig-like repeat domains found in virulence factors such as intimin and invasin. We expressed fragments of the repeat domain regions of LigA and LigB from Leptospira interrogans serovar Copenhageni. Immunization of Golden Syrian hamsters with Lig fragments in Freund’s adjuvant induced robust antibody responses against recombinant protein and native protein, as detected by ELISA and immunoblot, respectively. A single fragment, LigANI, which corresponds to the six carboxy-terminal Ig-like repeat domains of the LigA molecule, conferred immunoprotection against mortality (67-100%, P <0.05) in hamsters which received a lethal inoculum of L. interrogans serovar Copenhageni. However, immunization with this fragment did not confer sterilizing immunity. These findings indicate that the carboxy-terminal portion of LigA is an immunoprotective domain and may serve as a vaccine candidate for human and veterinary leptospirosis. PMID:17629368

  20. Photostimulated near-infrared persistent luminescence as a new optical read-out from Cr3+-doped LiGa5O8

    PubMed Central

    Liu, Feng; Yan, Wuzhao; Chuang, Yen-Jun; Zhen, Zipeng; Xie, Jin; Pan, Zhengwei

    2013-01-01

    In conventional photostimulable storage phosphors, the optical information written by x-ray or ultraviolet irradiation is usually read out as a visible photostimulated luminescence (PSL) signal under the stimulation of a low-energy light with appropriate wavelength. Unlike the transient PSL, here we report a new optical read-out form, photostimulated persistent luminescence (PSPL) in the near-infrared (NIR), from a Cr3+-doped LiGa5O8 NIR persistent phosphor exhibiting a super-long NIR persistent luminescence of more than 1,000 h. An intense PSPL signal peaking at 716 nm can be repeatedly obtained in a period of more than 1,000 h when an ultraviolet-light (250–360 nm) pre-irradiated LiGa5O8:Cr3+ phosphor is repeatedly stimulated with a visible light or a NIR light. The LiGa5O8:Cr3+ phosphor has promising applications in optical information storage, night-vision surveillance, and in vivo bio-imaging. PMID:23532003

  1. A universal process development methodology for complete removal of residues from 300mm wafer edge bevel

    NASA Astrophysics Data System (ADS)

    Randall, Mai; Linnane, Michael; Longstaff, Chris; Ueda, Kenichi; Winter, Tom

    2006-03-01

    Many yield limiting, etch blocking defects are attributed to "flake" type contamination from the lithography process. The wafer edge bevel is a prime location for generation of this type of defect. Wafer bevel quality is not readily observed with top down or even most off axis inspection equipment. Not all chemistries are removed with one "universal" cleaning process. IC manufacturers must maximize usable silicon area as well. These requirements have made traditional chemical treatments to clean the wafer edge inadequate for many chemistry types used in 193nm processing. IBM has evaluated a method to create a robust wafer bevel and backside cleaning process. An August Technology AXi TM Series advanced macro inspection tool with E20 TM edge inspection module has been used to check wafer bevel cleanliness. Process impact on the removal of post apply residues has been investigated. The new process used backside solvent rinse nozzles only and cleaned the wafer bevel completely. The use of the topside edge solvent clean nozzles was eliminated. Thickness, wet film defect measurements (wet FM), and pattern wafer defect monitors showed no difference between the new backside rinse edge bead removal process and the process of record. Solvent topside edge bead removal of both bottom anti-reflective coatings and resist materials showed better cut width control and uniformity. We conclude that the topside solvent edge bead removal nozzle can be removed from the process. Backside solvent rinse nozzles can clean the backside of the wafer, the wafer bevel, and can wrap to the front edge of the wafer to provide a uniform edge bead removal cut width that is not sensitive to coater module tolerances. Recommendations are made for changes to the typical preventive maintenance procedures.

  2. Infrared differential interference contrast microscopy for overlay metrology on 3D-interconnect bonded wafers

    NASA Astrophysics Data System (ADS)

    Ku, Yi-sha; Shyu, Deh-Ming; Lin, Yeou-Sung; Cho, Chia-Hung

    2013-04-01

    Overlay metrology for stacked layers will be playing a key role in bringing 3D IC devices into manufacturing. However, such bonded wafer pairs present a metrology challenge for optical microscopy tools by the opaque nature of silicon. Using infrared microscopy, silicon wafers become transparent to the near-infrared (NIR) wavelengths of the electromagnetic spectrum, enabling metrology at the interface of bonded wafer pairs. Wafers can be bonded face to face (F2F) or face to back (F2B) which the stacking direction is dictated by how the stacks are carried in the process and functionality required. For example, Memory stacks tend to use F2B stacking enables a better managed design. Current commercial tools use single image technique for F2F bonding overlay measurement because depth of focus is sufficient to include both surfaces; and use multiple image techniques for F2B overlay measurement application for the depth of focus is no longer sufficient to include both stacked wafer surfaces. There is a need to specify the Z coordinate or stacking wafer number through the silicon when visiting measurement wafer sites. Two shown images are of the same (X, Y) but separate Z location acquired at focus position of each wafer surface containing overlay marks. Usually the top surface image is bright and clear; however, the bottom surface image is somewhat darker and noisier as an adhesive layer is used in between to bond the silicon wafers. Thus the top and bottom surface images are further processed to achieve similar brightness and noise level before merged for overlay measurement. This paper presents a special overlay measurement technique, using the infrared differential interference contrast (DIC) microscopy technique to measure the F2B wafer bonding overlay by a single shot image. A pair of thinned wafers at 50 and 150 μm thickness is bonded on top of a carrier wafer to evaluate the bonding overlay. It works on the principle of interferometry to gain information about the

  3. Mask and wafer evaluation of Sigma7500 pattern generator applied to 65nm logic metal and via layers

    NASA Astrophysics Data System (ADS)

    Liu, Frank; Shi, Irene; Liu, Qingwei; Zhu, Likeit; Zhao, Shirley; Guo, Eric

    2009-04-01

    As pattern density and OPC complexity grow, photomask write times on electron beam tools increase in proportion. Reducing the write time would decrease mask-making costs, but the performance of any alternative mask writer must meet all of the technical requirements on both mask and wafer. In addition, it is desirable to use existing OPC models in order to avoid the costs of developing and maintaining separate OPC models for each writer. The Sigma7500 deep-UV pattern generator provides the highest resolution available from a laser-based tool, and it has the advantage of maintaining about a 3 hour write time even as the feature count increases. In this study, the Sigma7500 and a variable shaped e-beam (VSB) tool are compared on 65nm metal1 and via1 layers. In the first phase, the Sigma pattern positioning was matched to a SMIC reference grid and a registration value of 10 nm (3s) was achieved with scales removed. In the second phase, M1 and V1 masks were printed with both laser and e-beam writers using the same pattern data and compared on CD uniformity, linearity and proximity. The Sigma7500 met all of the photomask requirements for these layers. The masks were then printed on wafers and the wafer data was evaluated. The results were comparable to those for the e-beam masks and were within the requirements, indicating that the Sigma7500 can handle these layers without the need to revise the e-beam mask OPC models.

  4. 78 FR 61389 - Sanyo Solar of Oregon, LLC, Wafer Slicing and Quality Control Operations, Including On-Site...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-10-03

    ... Employment and Training Administration Sanyo Solar of Oregon, LLC, Wafer Slicing and Quality Control... to workers of Sanyo Solar of Oregon, LLC, Wafer Slicing and Quality Control Operations, Salem, Oregon... Salem, Oregon location of Sanyo Solar of Oregon, LLC, Wafer Slicing and Quality Control Operations....

  5. Contact doping of silicon wafers and nanostructures with phosphine oxide monolayers.

    PubMed

    Hazut, Ori; Agarwala, Arunava; Amit, Iddo; Subramani, Thangavel; Zaidiner, Seva; Rosenwaks, Yossi; Yerushalmi, Roie

    2012-11-27

    Contact doping method for the controlled surface doping of silicon wafers and nanometer scale structures is presented. The method, monolayer contact doping (MLCD), utilizes the formation of a dopant-containing monolayer on a donor substrate that is brought to contact and annealed with the interface or structure intended for doping. A unique feature of the MLCD method is that the monolayer used for doping is formed on a separate substrate (termed donor substrate), which is distinct from the interface intended for doping (termed acceptor substrate). The doping process is controlled by anneal conditions, details of the interface, and molecular precursor used for the formation of the dopant-containing monolayer. The MLCD process does not involve formation and removal of SiO(2) capping layer, allowing utilization of surface chemistry details for tuning and simplifying the doping process. Surface contact doping of intrinsic Si wafers (i-Si) and intrinsic silicon nanowires (i-SiNWs) is demonstrated and characterized. Nanowire devices were formed using the i-SiNW channel and contact doped using the MLCD process, yielding highly doped SiNWs. Kelvin probe force microscopy (KPFM) was used to measure the longitudinal dopant distribution of the SiNWs and demonstrated highly uniform distribution in comparison with in situ doped wires. The MLCD process was studied for i-Si substrates with native oxide and H-terminated surface for three types of phosphorus-containing molecules. Sheet resistance measurements reveal the dependency of the doping process on the details of the surface chemistry used and relation to the different chemical environments of the P═O group. Characterization of the thermal decomposition of several monolayer types formed on SiO(2) nanoparticles (NPs) using TGA and XPS provides insight regarding the role of phosphorus surface chemistry at the SiO(2) interface in the overall MLCD process. The new MLCD process presented here for controlled surface doping

  6. An Integrated Microfabricated Chip with Double Functions as an Ion Source and Air Pump Based on LIGA Technology

    PubMed Central

    Li, Hua; Jiang, Linxiu; Guo, Chaoqun; Zhu, Jianmin; Jiang, Yongrong; Chen, Zhencheng

    2017-01-01

    The injection and ionization of volatile organic compounds (VOA) by an integrated chip is experimentally analyzed in this paper. The integrated chip consists of a needle-to-cylinder electrode mounting on the Polymethyl Methacrylate (PMMA) substrate. The needle-to-cylinder electrode is designed and fabricated by Lithographie, Galvanoformung and Abformung (LIGA) technology. In this paper, the needle is connected to a negative power supply of −5 kV and used as the cathode; the cylinder electrodes are composed of two arrays of cylinders and serve as the anode. The ionic wind is produced based on corona and glow discharges of needle-to-cylinder electrodes. The experimental setup is designed to observe the properties of the needle-to-cylinder discharge and prove its functions as an ion source and air pump. In summary, the main results are as follows: (1) the ionic wind velocity produced by the chip is about 0.79 m/s at an applied voltage of −3300 V; (2) acetic acid and ammonia water can be injected through the chip, which is proved by pH test paper; and (3) the current measured by a Faraday cup is about 10 pA for acetic acid and ammonia with an applied voltage of −3185 V. The integrated chip is promising for portable analytical instruments, such as ion mobility spectrometry (IMS), field asymmetric ion mobility spectrometry (FAIMS), and mass spectrometry (MS). PMID:28054980

  7. An Integrated Microfabricated Chip with Double Functions as an Ion Source and Air Pump Based on LIGA Technology.

    PubMed

    Li, Hua; Jiang, Linxiu; Guo, Chaoqun; Zhu, Jianmin; Jiang, Yongrong; Chen, Zhencheng

    2017-01-04

    The injection and ionization of volatile organic compounds (VOA) by an integrated chip is experimentally analyzed in this paper. The integrated chip consists of a needle-to-cylinder electrode mounting on the Polymethyl Methacrylate (PMMA) substrate. The needle-to-cylinder electrode is designed and fabricated by Lithographie, Galvanoformung and Abformung (LIGA) technology. In this paper, the needle is connected to a negative power supply of -5 kV and used as the cathode; the cylinder electrodes are composed of two arrays of cylinders and serve as the anode. The ionic wind is produced based on corona and glow discharges of needle-to-cylinder electrodes. The experimental setup is designed to observe the properties of the needle-to-cylinder discharge and prove its functions as an ion source and air pump. In summary, the main results are as follows: (1) the ionic wind velocity produced by the chip is about 0.79 m/s at an applied voltage of -3300 V; (2) acetic acid and ammonia water can be injected through the chip, which is proved by pH test paper; and (3) the current measured by a Faraday cup is about 10 pA for acetic acid and ammonia with an applied voltage of -3185 V. The integrated chip is promising for portable analytical instruments, such as ion mobility spectrometry (IMS), field asymmetric ion mobility spectrometry (FAIMS), and mass spectrometry (MS).

  8. Development of a gate metal etch process for gallium arsenide wafers

    NASA Astrophysics Data System (ADS)

    Bammi, Rahul; Cale, Timothy S.; Grivna, Gordon

    1994-12-01

    The reactive ion etching of TiWN, which is used as a gate metal on gallium-arsenide device wafers, was studied in a parallel-plate, single-wafer plasma reactor operating at a frequency of 13.56 MHz. We discuss our experimental program designed to develop a highly uniform TiWN etch process with low linewidth loss for 100 mm GaAs wafers, using a sulfur hexafluoride, trifluoromethane, helium chemistry. The effects of different gas compositions, plasma power, inter-electrode gap, chamber pressure, and electrode temperature on the TiWN etch rate, linewidth loss, and etch uniformity were determined. The effects of adding oxygen and/or nitrogen to the above mixture were also studied. In preliminary experiments on Si wafers, standard design of experiments methods were used to narrow the ranges of parameters for further experiments to develop an optimum process for Si wafers. The results of these experiments guided us to the optimum process for GaAs wafers. The optimum conditions, for both Si and GaAs wafers, are presented.

  9. Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010

    SciTech Connect

    Lorenz, A.

    2011-06-01

    1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

  10. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss

    PubMed Central

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-01-01

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping. PMID:24820403

  11. Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

    NASA Technical Reports Server (NTRS)

    Okojie, Robert S. (Inventor)

    2002-01-01

    A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

  12. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

    PubMed

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-05-13

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

  13. Validation of thermodesorption method for analysis of semi-volatile organic compounds adsorbed on wafer surface.

    PubMed

    Hayeck, Nathalie; Gligorovski, Sasho; Poulet, Irène; Wortham, Henri

    2014-05-01

    To prevent the degradation of the device characteristics it is important to detect the organic contaminants adsorbed on the wafers. In this respect, a reliable qualitative and quantitative analytical method for analysis of semi-volatile organic compounds which can adsorb on wafer surfaces is of paramount importance. Here, we present a new analytical method based on Wafer Outgassing System (WOS) coupled to Automated Thermal Desorber-Gas chromatography-Mass spectrometry (ATD-GC-MS) to identify and quantify volatile and semi-volatile organic compounds from 6", 8" and 12" wafers. WOS technique allows the desorption of organic compounds from one side of the wafers. This method was tested on three important airborne contaminants in cleanroom i.e. tris-(2-chloroethyl) phosphate (TCEP), tris-(2-chloroisopropyl) phosphate (TCPP) and diethyl phthalate (DEP). In addition, we validated this method for the analysis and quantification of DEP, TCEP and TCPP and we estimated the backside organic contamination which may contribute to the front side of the contaminated wafers. We are demonstrating that WOS/ATD-GC-MS is a suitable and highly efficient technique for desorption and quantitative analysis of organophosphorous compounds and phthalate ester which could be found on the wafer surface.

  14. Nondestructive characterization of dislocations and micropipes in high-resistivity 6H-SiC wafers by deep-level photoluminescence mapping

    NASA Astrophysics Data System (ADS)

    Tajima, M.; Higashi, E.; Hayashi, T.; Kinoshita, H.; Shiomi, H.

    2005-02-01

    We demonstrated the effectiveness of deep-level photoluminescence (PL) mapping for nondestructive detection of dislocations and micropipes in high-resistivity 6H-SiC wafers. PL spectra of the wafers at room temperature were dominated by a broad band with a peak at 1.3eV, which was traceable to the Si vacancy-related V1, V2, and V3 lines at 4.2K. The intensity-mapping pattern agreed closely with the etch-pit pattern both on a wafer scale and on a microscopic scale. Large dark spots with one or two bright cores, small dark spots, and dark lines corresponded to micropipes, threading screw dislocations, and edge dislocations forming small angle grain boundaries, respectively. The intensity reduction around dislocations and micropipes was attributed to a decrease of the radiative centers for the 1.3eV band, which occurred as a result either of the interaction between vacancies and dislocations or of the gettering effect of vacancy-related defects.

  15. Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers Used for PV Cells: Preprint

    SciTech Connect

    Guthrey, H.; Gorman, B.; Al-Jassim, M.

    2011-07-01

    As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay (uPCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

  16. Wafer chamber having a gas curtain for extreme-UV lithography

    DOEpatents

    Kanouff, Michael P.; Ray-Chaudhuri, Avijit K.

    2001-01-01

    An EUVL device includes a wafer chamber that is separated from the upstream optics by a barrier having an aperture that is permeable to the inert gas. Maintaining an inert gas curtain in the proximity of a wafer positioned in a chamber of an extreme ultraviolet lithography device can effectively prevent contaminants from reaching the optics in an extreme ultraviolet photolithography device even though solid window filters are not employed between the source of reflected radiation, e.g., the camera, and the wafer. The inert gas removes the contaminants by entrainment.

  17. Non-Contact Wafer Fabrication Process Using Gas Cluster Ion Beams

    SciTech Connect

    Toyoda, Noriaki; Yamada, Iaso; Isogai, Hiromichi

    2008-11-03

    Gas cluster ion beam (GCIB) was used for precise wafer fabrication process. GCIB realizes a quite low-energy ion beam and shows very precise and good repeatability. To obtain thickness uniformity of Si over the whole wafer, small beam diameter ({approx}4 mm) of GCIB was used. Thickness variations on the wafer can be reduced by location specific irradiation of collimated GCIB. By controlling the scan speed of GCIB irradiation based on the removal thickness at each irradiation position, thickness and height uniformity of Si can be improved to several tens of nm. In addition, etching enhancement by using Ar/SF{sub 6} mixed cluster was studied.

  18. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sang Min; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Vukkadala, Pradeep; Awasthi, Amartya; Kim, J. H.; Veeraraghavan, Sathish; Choi, DongSub; Huang, Kevin; Dighe, Prasanna; Lee, Cheouljung; Byeon, Jungho; Dey, Soham; Sinha, Jaydeep

    2015-03-01

    Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes - which is directly related to

  19. Low temperature solder process to join a copper tube to a silicon wafer

    NASA Astrophysics Data System (ADS)

    Versteeg, Christo; Scarpim de Souza, Marcio

    2014-06-01

    With the application for wafer level packages, which could be Complementary Metal-Oxide-Semiconductor (CMOS) based, and which requires a reduced atmosphere, a copper tube connection to a vacuum pump and the package is proposed. The method evaluated uses laser assisted brazing of a solder, to join the copper tube to a silicon wafer. The method was applied to a silicon wafer coated with a metallic interface to bond to the solder. The hermeticity of the joint was tested with a helium leak rate tester and the bonding energy thermal extent was verified with a thin layer of indium that melted wherever the substrate temperature rose above its melting temperature.

  20. The removal of deformed submicron particles from silicon wafers by spin rinse and megasonics

    NASA Astrophysics Data System (ADS)

    Zhang, Fan; Busnaina, Ahmed A.; Fury, Michael A.; Wang, Shi-Qing

    2000-02-01

    In order to successfully clean particulate contamination from wafer surfaces, it is necessary to understand the adhesion and deformation between the particles and the substrate in contact. The adhesion and removal mechanisms of deformed submicron particles have not been addressed in many previous studies. Submicron polystyrene latex particles (0.1-0.5 µm) were deposited on silicon wafers and removed by spin rinse and megasonic cleanings. Particle rolling is identified as the major removal mechanism for the deformed submicron particles from silicon wafers. Megasonics provides larger streaming velocity because of the extremely thin boundary layer resulting in a larger removal force that is capable of achieving complete removal of contamination particles.

  1. SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

    NASA Astrophysics Data System (ADS)

    Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

    2010-05-01

    Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

  2. Reflectance reduction of InP wafers after high-temperature annealing.

    PubMed

    Semyonov, Oleg G; Subashiev, Arsen V; Shabalov, Alexander; Lifshitz, Nadia; Chen, Zhichao; Hosoda, Takashi; Luryi, Serge

    2012-08-01

    Broadband reduction of light reflection from the surface of InP wafers after high-temperature annealing in air has been observed. In the transparency region of the material, the reflection drop is accompanied by increasing transmission of light through the wafer. The spectral position of a deep minimum of the reflection coefficient can be tuned, by varying the temperature and the time of annealing, in a wide spectral range from ultraviolet to infrared. The effect is due to formation of thermal oxide layers on the surfaces of the wafer with optical parameters favorable for antireflection.

  3. Development of a fixed abrasive slicing technique (FAST) for reducing the cost of photovoltaic wafers

    SciTech Connect

    Schmid, F. )

    1991-12-01

    This report examines a wafer slicing technique developed by Crystal Systems, Inc. that reduces the cost of photovoltaic wafers. This fixed, abrasive slicing technique (FAST) uses a multiwire bladepack and a diamond-plated wirepack; water is the coolant. FAST is in the prototype production stage and reduces expendable material costs while retaining the advantages of a multiwire slurry technique. The cost analysis revealed that costs can be decreased by making more cuts per bladepack and slicing more wafers per linear inch. Researchers studied the degradation of bladepacks and increased wirepack life. 21 refs.

  4. Adhesive disbond detection using piezoelectric wafer active sensors

    NASA Astrophysics Data System (ADS)

    Roth, William; Giurgiutiu, Victor

    2015-04-01

    The aerospace industry continues to increase the use of adhesives for structural bonding due to the increased joint efficiency (reduced weight), even distribution of the load path and decreases in stress concentrations. However, the limited techniques for verifying the strength of adhesive bonds has reduced its use on primary structures and requires an intensive inspection schedule. This paper discusses a potential structural health monitoring (SHM) technique for the detection of disbonds through the in situ inspection of adhesive joints. This is achieved through the use of piezoelectric wafer active sensors (PWAS), thin unobtrusive sensors which are permanently bonded to the aircraft structure. The detection method discussed in this study is electromechanical impedance spectroscopy (EMIS), a local vibration method. This method detects disbonds from the change in the mechanical impedance of the structure surrounding the disbond. This paper will discuss how predictive modeling can provide valuable insight into the inspection method, and provide better results than empirical methods alone. The inspection scheme was evaluated using the finite element method, and the results were verified experimentally using a large aluminum test article, and included both pristine and disbond coupons.

  5. Wafer level optoelectronic device packaging using MEMS (Invited Paper)

    NASA Astrophysics Data System (ADS)

    Nallani, Arunkumar; Chen, Ting; Lee, J.-B.; Hayes, Donald; Wallace, David

    2005-07-01

    The emergence of vertical cavity surface emitting laser (VCSEL) and photo diode (PD) arrays has given scope for the development of many applications such as high speed data communication. Further increase in performance can be obtained by the inclusion of micro-mirrors and microlens in the optical path between these components. However, the lack of efficient assembly and alignment techniques has become bottlenecks for new products. In this paper, we present development of optical sub-assembly and metallic MEMS structures that enable in the massively parallel assembly and alignment of these components to form a single miniature package. VCSEL wafer was processed to have polymer pedestal and polymeric lens on top of it. Such optical sub assembly greatly increases coupling efficiency between the VCSEL and optical fibers. Multiple numbers of suspended MEMS serpentine springs made out of electroplated nickel have been fabricated on ceramic substrates. These springs serve for clamping and alignment of multiple numbers of optoelectronic components. They are designed to be self-aligning with alignment accuracies of less than 3 micron after final assembly. Electrical connection between the bond pads of VCSEL's and PD's to the electrical leads on the substrate has been demonstrated by molten solder inkjet printing into precisely designed MEMS mold structures. This novel massively parallel assembly process is substrate independent and relatively simple process. This technique will provide reliable assembly of optoelectronic components and miniature optical systems in low cost mass production manner.

  6. Disbond detection with piezoelectric wafer active sensors in RC structures strengthened with FRP composite overlays

    NASA Astrophysics Data System (ADS)

    Giurgiutiu, Victor; Harries, Kent; Petrou, Michael; Bost, Joel; Quattlebaum, Josh B.

    2003-12-01

    The capability of embedded piezoelectric wafer active sensors (PWAS) to perform in-situ nondestructive evaluation (NDE) for structural health monitoring (SHM) of reinforced concrete (RC) structures strengthened with fiber reinforced polymer (FRP) composite overlays is explored. First, the disbond detection method were developed on coupon specimens consisting of concrete blocks covered with an FRP composite layer. It was found that the presence of a disbond crack drastically changes the electromechanical (E/M) impedance spectrum measured at the PWAS terminals. The spectral changes depend on the distance between the PWAS and the crack tip. Second, large scale experiments were conducted on a RC beam strengthened with carbon fiber reinforced polymer (CFRP) composite overlay. The beam was subject to an accelerated fatigue load regime in a three-point bending configuration up to a total of 807,415 cycles. During these fatigue tests, the CFRP overlay experienced disbonding beginning at about 500,000 cycles. The PWAS were able to detect the disbonding before it could be reliably seen by visual inspection. Good correlation between the PWAS readings and the position and extent of disbond damage was observed. These preliminary results demonstrate the potential of PWAS technology for SHM of RC structures strengthened with FRP composite overlays.

  7. Defect Characterization of 4H-SiC Wafers for Power Electronic Device Applications.

    NASA Astrophysics Data System (ADS)

    Cicero, G.; Ferrero, S.; Cocuzza, M.; Giorgis, F.; Mandracci, P.; Ricciardi, C.; Scaltrito, L.; Pirri, C. F.; Richieri, G.; Sgorlon, C.

    2002-03-01

    Silicon carbide is a wide band gap semiconductor, interesting for its physical properties such as high breakdown field, high saturated drift velocity and high thermal conductivity, which has been intensively studied in the last years. Although the high potentiality of this material, the SiC technology shows at the moment some limitations and requires further study in order to obtain electronic devices with the same quality standards of the Si technology. Indeed, the reliability of SiC-based devices is strictly correlated to the defects present in the crystalline structure. We have focused our investigation on 4H-SiC wafers and on 4H epitaxial layers in order to determine in both the situations the different type of defects. A preliminary investigation has been performed by optical microscopy and Scanning Electron Microscopy with the aim to evidence the defect morphology on large scale. A deeper insight on the defects typology has been obtained by Atomic Force Microscopy, Profilometer technique, Micro-Raman and Micro-Photoluminescence spectroscopies. Different types of defects such as micropipes, comets, super dislocations, etch pits and so on, have been characterized finding particular physical finger-prints. This investigation is aimed at correlating the defects and the electrical properties of SiC for power electronic device applications.

  8. Low Loss, Finite Width Ground Plane, Thin Film Microstrip Lines on Si Wafers

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Margomenos, Alexandros; Katehi, Linda P. B.

    1999-01-01

    Si RFICs on standard, 2 Omega-cm. Si wafers require novel transmission lines to reduce the loss caused by the resistive substrate. One such transmission line is commonly called Thin Film Microstrip (TFMS), which is created by depositing a metallic ground plane, thin insulating layers, and the microstrip lines on the Si wafer. Thus, the electric fields are isolated from the Si wafer. In this paper, it is shown through experimental results that the ground plane of TFMS may be finite width and comparable to the strip width in size while still achieving low loss on 2 Omega-cm Si. Measured effective permittivity shows that the field interaction with the Si wafer is small.

  9. Influence of thermal load on 450 mm Si-wafer IPD during lithographic patterning

    NASA Astrophysics Data System (ADS)

    Peschel, Thomas; Kalkowski, Gerhard; Eberhardt, Ramona

    2012-03-01

    We report on Finite Element Modeling (FEM) of the influence of heat load due to the lithographic exposure on the inplane distortion (IPD) of 450 mm Si-wafers and hence on the effect of the heat load on the achievable image placement accuracy. Based on a scenario of electron beam writing at an exposure power of 20 mW, the thermo-mechanical behavior of the chuck and the attached Si wafer is modeled and used to derive corresponding IPD values. To account for the pin structured chuck surface, an effective layer model is derived. Different materials for the wafer chuck are compared with respect to their influence on wafer IPD and thermal characteristics of the exposure process. Guidelines for the selection of the chuck material und suggestions for its cooling and corrective strategies on e-beam steering during exposure are derived.

  10. Analysis of organic contaminants from silicon wafer and disk surfaces by thermal desorption-GC-MS

    NASA Astrophysics Data System (ADS)

    Camenzind, Mark J.; Ahmed, Latif; Kumar, Anurag

    1999-03-01

    Organic contaminants can affect semiconductor wafer processing including gate oxide integrity, polysilicon growth, deep ultraviolet photoresist line-width, and cleaning & etching steps. Organophosphates are known to counter dope silicon wafers. Organic contaminants in disk drives can cause failures due to stiction or buildup on the heads. Therefore, it is important to identify organic contaminants adsorbed on wafer or disk surfaces and find their sources so they can be either completely eliminated or at least controlled. Dynamic headspace TD-GC-MS (Thermal Desorption-Gas Chromatography-Mass Spectrometry) methods are very sensitive and can be used to identify organic contaminants on disks and wafers, in air, or outgassing from running drives or their individual components.

  11. A study of defects on EUV mask using blank inspection, patterned mask inspection, and wafer inspection

    SciTech Connect

    Huh, S.; Ren, L.; Chan, D.; Wurm, S.; Goldberg, K. A.; Mochi, I.; Nakajima, T.; Kishimoto, M.; Ahn, B.; Kang, I.; Park, J.-O.; Cho, K.; Han, S.-I.; Laursen, T.

    2010-03-12

    The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing. yet link data is available for understanding native defects on real masks. In this paper, a full-field EUV mask is fabricated to investigate the printability of various defects on the mask. The printability of defects and identification of their source from mask fabrication to handling were studied using wafer inspection. The printable blank defect density excluding particles and patterns is 0.63 cm{sup 2}. Mask inspection is shown to have better sensitivity than wafer inspection. The sensitivity of wafer inspection must be improved using through-focus analysis and a different wafer stack.

  12. Effects of wafer noise on the detection of 20-nm defects using optical volumetric inspection

    NASA Astrophysics Data System (ADS)

    Barnes, Bryan M.; Goasmat, Francois; Sohn, Martin Y.; Zhou, Hui; Vladár, András E.; Silver, Richard M.

    2015-01-01

    Patterning imperfections in semiconductor device fabrication may either be noncritical [e.g., line edge roughness (LER)] or critical, such as defects that impact manufacturing yield. As the sizes of the pitches and linewidths decrease in lithography, detection of the optical scattering from killer defects may be obscured by the scattering from other variations, called wafer noise. Understanding and separating these optical signals are critical to reduce false positives and overlooked defects. The effects of wafer noise on defect detection are assessed using volumetric processing on both measurements and simulations with the SEMATECH 9-nm gate intentional defect array. Increases in LER in simulation lead to decreases in signal-to-noise ratios due to wafer noise. Measurement procedures illustrate the potential uses in manufacturing while illustrating challenges to be overcome for full implementation. Highly geometry-dependent, the ratio of wafer noise to defect signal should continue to be evaluated for new process architectures and production nodes.

  13. On-wafer vector network analyzer measurements in the 220-325 Ghz frequency band

    NASA Technical Reports Server (NTRS)

    Fung, King Man Andy; Dawson, D.; Samoska, L.; Lee, K.; Oleson, C.; Boll, G.

    2006-01-01

    We report on a full two-port on-wafer vector network analyzer test set for the 220-325 GHz (WR3) frequency band. The test set utilizes Oleson Microwave Labs frequency extenders with the Agilent 8510C network analyzer. Two port on-wafer measurements are made with GGB Industries coplanar waveguide (CPW) probes. With this test set we have measured the WR3 band S-parameters of amplifiers on-wafer, and the characteristics of the CPW wafer probes. Results for a three stage InP HEMT amplifier show 10 dB gain at 235 GHz [1], and that of a single stage amplifier, 2.9 dB gain at 231 GHz. The approximate upper limit of loss per CPW probe range from 3.0 to 4.8 dB across the WR3 frequency band.

  14. Multi-wire slurry wafering demonstrations. [slicing silicon ingots for solar arrays

    NASA Technical Reports Server (NTRS)

    Chen, C. P.

    1978-01-01

    Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

  15. High-temperature healing of interfacial voids in GaAs wafer bonding

    NASA Astrophysics Data System (ADS)

    Wu, YewChung Sermon; Liu, Po Chun; Feigelson, R. S.; Route, R. K.

    2002-02-01

    Artificial voids were introduced at bonding interfaces to study how processing parameters affected the healing mechanism of interfacial voids in GaAs wafer bonding. These voids were created by placing unpatterned wafers in contact with topographically patterned wafers. During the bonding process, crystallites formed within these voids and corresponded to bonded regions within the voids. Their formation depended strongly on the height of the surface irregularities at the wafer interfaces. When the void depth (h) was ⩾200 nm, most of the crystallites were diamond shaped. The edges of the diamond features were elongated in the <100> direction. On the other hand, when the void depth was small (h⩽70 nm), dendrites grew quickly in the <110> direction.

  16. Nanoetching process on silicon solar cell wafers during mass production for surface texture improvement.

    PubMed

    Ahn, Chisung; Kulkarni, Atul; Ha, Soohyun; Cho, Yujin; Kim, Jeongin; Park, Heejin; Kim, Taesung

    2014-12-01

    Major challenge in nanotechnology is to improve the solar cells efficiency. This can be achieved by controlling the silicon solar cell wafer surface structure. Herein, we report a KOH wet etching process along with an ultrasonic cleaning process to improve the surface texture of silicon solar cell wafers. We evaluated the KOH temperature, concentration, and ultra-sonication time. It was observed that the surface texture of the silicon solar wafer changed from a pyramid shape to a rectangular shape under edge cutting as the concentration of the KOH solution was increased. We controlled the etching time to avoid pattern damage and any further increase of the reflectance. The present study will be helpful for the mass processing of silicon solar cell wafers with improved reflectance.

  17. Robust wafer identification recognition based on asterisk-shape filter and high-low score comparison method.

    PubMed

    Hsu, Wei-Chih; Yu, Tsan-Ying; Chen, Kuan-Liang

    2009-12-10

    Wafer identifications (wafer ID) can be used to identify wafers from each other so that wafer processing can be traced easily. Wafer ID recognition is one of the problems of optical character recognition. The process to recognize wafer IDs is similar to that used in recognizing car license-plate characters. However, due to some unique characteristics, such as the irregular space between two characters and the unsuccessive strokes of wafer ID, it will not get a good result to recognize wafer ID by directly utilizing the approaches used in car license-plate character recognition. Wafer ID scratches are engraved by a laser scribe almost along the following four fixed directions: horizontal, vertical, plus 45 degrees , and minus 45 degrees orientations. The closer to the center line of a wafer ID scratch, the higher the gray level will be. These and other characteristics increase the difficulty to recognize the wafer ID. In this paper a wafer ID recognition scheme based on an asterisk-shape filter and a high-low score comparison method is proposed to cope with the serious influence of uneven luminance and make recognition more efficiently. Our proposed approach consists of some processing stages. Especially in the final recognition stage, a template-matching method combined with stroke analysis is used as a recognizing scheme. This is because wafer IDs are composed of Semiconductor Equipment and Materials International (SEMI) standard Arabic numbers and English alphabets, and thus the template ID images are easy to obtain. Furthermore, compared with the approach that requires prior training, such as a support vector machine, which often needs a large amount of training image samples, no prior training is required for our approach. The testing results show that our proposed scheme can efficiently and correctly segment out and recognize the wafer ID with high performance.

  18. Improved algorithm for automated alignment of wafers via optimized features location

    NASA Astrophysics Data System (ADS)

    Parshin, Michael; Zalevsky, Zeev

    2009-10-01

    We present a new fuzzy logic-based approach for automatic optimized features location. The technique is used for improved automatic alignment and classification of silicon wafers and chips that are used in the electronics industry. The proposed automatic image processing approach was realized and experimentally demonstrated in real industrial application with typical wafers. The automatic features location and grading supported the industrial requirements and could replace human expert-based inspection that currently is performed manually.

  19. A front-end wafer-level microsystem packaging technique with micro-cap array

    NASA Astrophysics Data System (ADS)

    Chiang, Yuh-Min

    2002-09-01

    The back-end packaging process is the remaining challenge for the micromachining industry to commercialize microsystem technology (MST) devices at low cost. This dissertation presents a novel wafer level protection technique as a final step of the front-end fabrication process for MSTs. It facilitates improved manufacturing throughput and automation in package assembly, wafer level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized micro-cap array, which consists of an assortment of small caps micro-molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments during packaging. The micro-cap array is first constructed by a micromachining process with micro-molding technique, then sealed to the device wafer at wafer level. Epoxy-based wafer-level micro cap array has been successfully fabricated and showed good compatibility with conventional back-end packaging processes. An adhesive transfer technique was demonstrated to seal the micro cap array with a MEMS device wafer. No damage or gross leak was observed while wafer dicing or later during a gross leak test. Applications of the micro cap array are demonstrated on MEMS, microactuators fabricated using CRONOS MUMPS process. Depending on the application needs, the micro-molded cap can be designed and modified to facilitate additional component functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. Successful fabrication of a micro cap array comprised with microlenses can provide active functions as well as passive protection. An optical tweezer array could be one possibility for applications of a micro cap with microlenses. The micro cap itself could serve as micro well for DNA or bacteria amplification as well.

  20. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.

    2011-07-12

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  1. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.

    2008-11-18

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  2. Kinetic mechanism and fidelity of nick sealing by Escherichia coli NAD+-dependent DNA ligase (LigA)

    PubMed Central

    Chauleau, Mathieu; Shuman, Stewart

    2016-01-01

    Escherichia coli DNA ligase (EcoLigA) repairs 3′-OH/5′-PO4 nicks in duplex DNA via reaction of LigA with NAD+ to form a covalent LigA-(lysyl-Nζ)–AMP intermediate (step 1); transfer of AMP to the nick 5′-PO4 to form an AppDNA intermediate (step 2); and attack of the nick 3′-OH on AppDNA to form a 3′-5′ phosphodiester (step 3). A distinctive feature of EcoLigA is its stimulation by ammonium ion. Here we used rapid mix-quench methods to analyze the kinetic mechanism of single-turnover nick sealing by EcoLigA–AMP. For substrates with correctly base-paired 3′-OH/5′-PO4 nicks, kstep2 was fast (6.8–27 s−1) and similar to kstep3 (8.3–42 s−1). Absent ammonium, kstep2 and kstep3 were 48-fold and 16-fold slower, respectively. EcoLigA was exquisitely sensitive to 3′-OH base mispairs and 3′ N:abasic lesions, which elicited 1000- to >20000-fold decrements in kstep2. The exception was the non-canonical 3′ A:oxoG configuration, which EcoLigA accepted as correctly paired for rapid sealing. These results underscore: (i) how EcoLigA requires proper positioning of the nick 3′ nucleoside for catalysis of 5′ adenylylation; and (ii) EcoLigA's potential to embed mutations during the repair of oxidative damage. EcoLigA was relatively tolerant of 5′-phosphate base mispairs and 5′ N:abasic lesions. PMID:26857547

  3. Quantitative analysis of trace bulk oxygen in silicon wafers using an inert gas fusion method.

    PubMed

    Uchihara, Hiroshi; Ikeda, Masahiko; Nakahara, Taketoshi

    2003-11-01

    This paper describes a method for removing oxide film from the surface of silicon wafers using an inert gas fusion impulse furnace and precise determination of bulk oxygen within the wafer. A silicon wafer was cut to about 0.35 g (6 x 13 x 2 mm) and dropped into a graphite crucible. The sample was then heated for 40 s at 1300 degrees C. The wafer's oxide film was reduced by carbon and removed as carbon monoxide. The treated silicon sample was taken out of the graphite crucible and maintained again with the holder of the oxygen analyzer. The graphite crucible was then heated to 2100 degrees C. The treated silicon sample was dropped into the heated graphite crucible and the trace bulk oxygen in the wafer was measured using the inert gas fusion infrared absorption method. The relative standard deviations of the oxygen in silicon wafer samples with the removed surface oxide film were determined to be 0.8% for 9.8 x 10(17) atoms/cm3, and 2.7% for 13.0 x 10(17) atoms/cm3.

  4. A wafer mapping technique for residual stress in surface micromachined films

    NASA Astrophysics Data System (ADS)

    Schiavone, G.; Murray, J.; Smith, S.; Desmulliez, M. P. Y.; Mount, A. R.; Walton, A. J.

    2016-09-01

    The design of MEMS devices employing movable structures is crucially dependant on the mechanical behaviour of the deposited materials. It is therefore important to be able to fully characterize the micromachined films and predict with confidence the mechanical properties of patterned structures. This paper presents a characterization technique that enables the residual stress in MEMS films to be mapped at the wafer level by using microstructures released by surface micromachining. These dedicated MEMS test structures and the associated measurement techniques are used to extract localized information on the strain and Young’s modulus of the film under investigation. The residual stress is then determined by numerically coupling this data with a finite element analysis of the structure. This paper illustrates the measurement routine and demonstrates it with a case study using electrochemically deposited alloys of nickel and iron, particularly prone to develop high levels of residual stress. The results show that the technique enables wafer mapping of film non-uniformities and identifies wafer-to-wafer differences. A comparison between the results obtained from the mapping technique and conventional wafer bow measurements highlights the benefits of using a procedure tailored to films that are non-uniform, patterned and surface-micromachined, as opposed to simple standard stress extraction methods. The presented technique reveals detailed information that is generally unexplored when using conventional stress extraction methods such as wafer bow measurements.

  5. Reduction of batwing effect in white light interferometry for measurement of patterned sapphire substrates (PSS) wafer

    NASA Astrophysics Data System (ADS)

    Tapilouw, Abraham Mario; Chang, Yi-Wei; Yu, Long-Yo; Wang, Hau-Wei

    2016-08-01

    Patterned sapphire substrates (PSS) wafers are used in LED manufacturing to enhance the luminous conversion of LED chips. The most critical characteristics in PSS wafers are height, width, pitch and shape of the pattern. The common way to measure these characteristics is by using surface electron microscope (SEM). White light interferometry is capable to measure dimension with nanometer accuracy and it is suitable for measuring the characteristics of PSS wafers. One of the difficulties in measuring PSS wafers is the aspect ratio and density of the features. The high aspect ratio combined with dense pattern spacing diffracts incoming lights and reduces the accuracy of the white light interferometry measurement. In this paper, a method to improve the capability of white light interferometry for measuring PSS wafers by choosing the appropriate wavelength and microscope objective with high numerical aperture. The technique is proven to be effective for reducing the batwing effect in edges of the feature and improves measurement accuracy for PSS wafers with circular features of 1.95 um in height and diameters, and 700 nm spacing between the features. Repeatability of the measurement is up to 5 nm for height measurement and 20 nm for pitch measurement.

  6. Detection of Metal Contamination on Silicon Wafer Backside and Edge by New TXRF Methods

    NASA Astrophysics Data System (ADS)

    Kohno, Hiroshi; Yamagami, Motoyuki; Formica, Joseph; Shen, Liyong

    2009-09-01

    In conventional 200 mm wafer processing, backside defects are not considered to be of much concern because they are obscured by wafer backside topography. However, in current 300 mm wafer processing where both sides of a wafer are polished, backside defects require more consideration. In the beginning, backside defect inspection examined particle contamination because particle contamination adversely influences the depth of field in lithography. Recently, metal contamination is of concern because backside metal contamination causes cross-contamination in a process line, and backside metals easily transfer to the front surface. As the industry strives to yield more devices from the area around the wafer edge, edge exclusion requirements have also become more important. The current International Technology Roadmap for Semiconductors [1] requires a 2 mm edge exclusion. Therefore, metal contamination must be controlled to less than 2 mm from the edge because metal contamination easily diffuses in silicon wafers. To meet these current semiconductor processing requirements, newly developed zero edge exclusion TXRF (ZEE-TXRF) and backside measurement TXRF (BAC-TXRF) are effective metrology methods.

  7. A randomized clinical trial comparing the efficacy of bite wafer and low level laser therapy in reducing pain following initial arch wire placement

    PubMed Central

    Bayani, Shahin; Rostami, Shima; Saeedipouya, Iman

    2016-01-01

    Background and aims: This study aimed to evaluate the efficacy of ibuprofen, bite wafer and low power red and infrared lasers in orthodontic pain management. Subjects and methods: One hundred subjects were randomly assigned to 5 groups of 20 each. The patients in each group received one of the following treatments after the placement of fixed orthodontic appliances: 1. placebo medication, 2. ibuprofen, 3. bite wafer, 4. irradiation from a low level red laser (LLRL; 660 nm, 200 mW, 1 J/point, 6 points), 5. irradiation from a low level infrared laser (LLIL; 810 nm, 200 mW, 1 J/point, 6 points). A Visual Analogue Scale (VAS) was used to record pain intensity while chewing, biting, fitting front teeth, and fitting back teeth at 2 hours, 6 hours, bedtime, 24 hours, 2 days, 3 days and 7 days following arch wire placement. Results: Significant between-group differences were found in pain at chewing, biting, fitting front teeth and fitting back teeth at all time points (p<0.001). Generally, VAS scores in the LLIL, ibuprofen and bite wafer groups were close to each other and significantly lower than those in the LLRL and control groups (p<0.05), which showed comparable pain level at most intervals. The infrared laser group (LLIL) showed significantly lower pain than all other groups at some points over the experiment (p<0.05). Conclusions: A single irradiation from a low level infrared laser proved to be the best strategy for orthodontic pain control. Alternatively, chewing on a bite wafer could be recommended. These methods should be considered as suitable alternatives for ibuprofen in orthodontic patients. PMID:27721564

  8. A randomized clinical trial comparing the efficacy of bite wafer and low level laser therapy in reducing pain following initial arch wire placement.

    PubMed

    Bayani, Shahin; Rostami, Shima; Ahrari, Farzaneh; Saeedipouya, Iman

    2016-06-29

    Background and aims: This study aimed to evaluate the efficacy of ibuprofen, bite wafer and low power red and infrared lasers in orthodontic pain management. Subjects and methods: One hundred subjects were randomly assigned to 5 groups of 20 each. The patients in each group received one of the following treatments after the placement of fixed orthodontic appliances: 1. placebo medication, 2. ibuprofen, 3. bite wafer, 4. irradiation from a low level red laser (LLRL; 660 nm, 200 mW, 1 J/point, 6 points), 5. irradiation from a low level infrared laser (LLIL; 810 nm, 200 mW, 1 J/point, 6 points). A Visual Analogue Scale (VAS) was used to record pain intensity while chewing, biting, fitting front teeth, and fitting back teeth at 2 hours, 6 hours, bedtime, 24 hours, 2 days, 3 days and 7 days following arch wire placement. Results: Significant between-group differences were found in pain at chewing, biting, fitting front teeth and fitting back teeth at all time points (p<0.001). Generally, VAS scores in the LLIL, ibuprofen and bite wafer groups were close to each other and significantly lower than those in the LLRL and control groups (p<0.05), which showed comparable pain level at most intervals. The infrared laser group (LLIL) showed significantly lower pain than all other groups at some points over the experiment (p<0.05). Conclusions: A single irradiation from a low level infrared laser proved to be the best strategy for orthodontic pain control. Alternatively, chewing on a bite wafer could be recommended. These methods should be considered as suitable alternatives for ibuprofen in orthodontic patients.

  9. P/N InP solar cells on Ge wafers

    NASA Technical Reports Server (NTRS)

    Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

    1994-01-01

    Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented

  10. Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule

    SciTech Connect

    Emanuel Sachs Tonio Buonassisi

    2013-01-16

    The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the

  11. Autophobic dewetting of a poly(methyl methacrylate) thin film on a silicon wafer treated in good solvent vapor.

    PubMed

    Xue, Longjian; Han, Yanchun

    2009-05-05

    The wettability of thin poly(methyl methacrylate) (PMMA) films on a silicon wafer with a native oxide layer exposed to solvent vapors is dependent on the solvent properties. In the nonsolvent vapor, the film spread on the substrate with some protrusions generated on the film surface. In the good solvent vapor, dewetting happened. A new interface formed between the anchored PMMA chains and the swollen upper part of the film. Entropy effects caused the upper movable chains to dewet on the anchored chains. The rim instability depended on the surface tension of solvent (i.e., the finger was generated in acetone vapor (gamma(acetone) = 24 mN/m), not in dioxane vapor (gamma(dioxane) = 33 mN/m)). The spacing (lambda) that grew as an exponential function of film thickness h scaled as approximately h(1.31), whereas the mean size (D) of the resulting droplets grew linearly with h.

  12. Electron mobility-lifetime and resistivity mapping of GaAs:Cr wafers

    NASA Astrophysics Data System (ADS)

    Chsherbakov, I.; Kolesnikova, I.; Lozinskaya, A.; Mihaylov, T.; Novikov, V.; Shemeryankina, A.; Tolbanov, O.; Tyazhev, A.; Zarubin, A.

    2017-02-01

    Previous works onchromium compensated gallium arsenide (GaAs:Cr) have shown high efficiency, good spatial and energy resolution, which is obviously connected with the high quality of material itself. The purpose of this research was to aggravate the diffusion process by increasing the annealing temperature and to observe whether there will be any degradation of material characteristics. The investigation of three 3-inch GaAs:Cr wafers with different annealing temperature of chromium was carried out. Resistivity and mobility-lifetime measurements were made using pad sensors made of these wafers. The I-V curves were built to estimate the resistivity across the wafer. Furthermore charge collection efficiency (CCE) measurements were carried out in order to estimate the μeτ e product of GaAs:Cr. The resistivity mapping has showed a variation of resistivity across the wafer in the range from 1.25 × 109 to 5.5 × 108 Ohm cm. Although the third wafer showed quite good uniformity, the resistance didn't reached values higher than 3.5 × 108 Ohm cm. In spite of harsh diffusion conditions all the materials showed quite good CCE (about 90%) and μ eτe more than 5 × 10‑5 cm2/V. Also a strong dependency between the resistivity and mobility-lifetime product was found only for one wafer. So the uniformity of μeτ e product across the wafer can be stated independently of resistivity. More detailed information and discussion of experimental results is presented in the article.

  13. In-line TEM sample preparation and wafer return strategy for rapid yield learning

    NASA Astrophysics Data System (ADS)

    Bicaïs-Lépinay, N.; André, F.; Brevers, S.; Guyader, P.; Trouiller, C.; Kwakman, L. F. Tz.; Pokrant, S.; Verkleij, D.; Schampers, R.; Ithier, L.; Sicurani, E.; Wyon, C.

    2006-03-01

    Full wafer dual beam FIB-SEM systems have received a lot of industrial interest in the last years and by now are operational in several 200mm and 300mm fabs. These tools offer a 3D-physical characterization capability of defects and device structures and as such allow for more rapid yield learning and increased process control. Moreover, if SEM resolution is insufficient to reveal defect origin or the necessary process details, it is now also possible to prepare TEM samples using a controlled, easy to learn in-situ process and to efficiently continue the characterization with a high resolution TEM inspection. Thanks to latest hardware developments and the high degree of automation of this TEM sample preparation process, wafers no longer need to be broken and remain essentially free from contamination. Hence, the TEM lamella process can be considered as non-destructive and wafers may continue the fabrication process flow. In this paper we examine the SEM and TEM application capabilities offered by in-line dual beam systems. To qualify the wafer return strategy, the particle contamination generated by the system hardware as well as the process-induced contamination have been investigated. The particle levels measured are fully acceptable to adopt the wafer return strategy. Ga-contamination does exist but is sufficiently low and localized so that the wafer return strategy can be applied safely in the back-end of line process. Yield analysis has confirmed that there is no measurable impact on device yield. Although yet to be proven for the frond-end of line processes, the wafer return strategy has been demonstrated as a valuable one already in the backend of line processes. The as developed non-destructive 3-D SEM-TEM characterization capability does offer value added data that allow to determine the root cause of critical process defects in almost real-time and this for both standard (SEM) and more advanced (TEM) technologies.

  14. Wafer-level fabrication of arrays of glass lens doublets

    NASA Astrophysics Data System (ADS)

    Passilly, Nicolas; Perrin, Stéphane; Albero, Jorge; Krauter, Johann; Gaiffe, Olivier; Gauthier-Manuel, Ludovic; Froehly, Luc; Lullin, Justine; Bargiel, Sylwester; Osten, Wolfgang; Gorecki, Christophe

    2016-04-01

    Systems for imaging require to employ high quality optical components in order to dispose of optical aberrations and thus reach sufficient resolution. However, well-known methods to get rid of optical aberrations, such as aspherical profiles or diffractive corrections are not easy to apply to micro-optics. In particular, some of these methods rely on polymers which cannot be associated when such lenses are to be used in integrated devices requiring high temperature process for their further assembly and separation. Among the different approaches, the most common is the lens splitting that consists in dividing the focusing power between two or more optical components. In here, we propose to take advantage of a wafer-level technique, devoted to the generation of glass lenses, which involves thermal reflow in silicon cavities to generate lens doublets. After the convex lens sides are generated, grinding and polishing of both stack sides allow, on the first hand, to form the planar lens backside and, on the other hand, to open the silicon cavity. Nevertheless, silicon frames are then kept and thinned down to form well-controlled and auto-aligned spacers between the lenses. Subsequent accurate vertical assembly of the glass lens arrays is performed by anodic bonding. The latter ensures a high level of alignment both laterally and axially since no additional material is required. Thanks to polishing, the generated lens doublets are then as thin as several hundreds of microns and compatible with micro-opto-electro-systems (MOEMS) technologies since they are only made of glass and silicon. The generated optical module is then robust and provide improved optical performances. Indeed, theoretically, two stacked lenses with similar features and spherical profiles can be almost diffraction limited whereas a single lens characterized by the same numerical aperture than the doublet presents five times higher wavefront error. To demonstrate such assumption, we fabricated glass

  15. Growth of oriented diamond on nickel wafers and thin films

    NASA Astrophysics Data System (ADS)

    Liu, Wei

    2000-10-01

    Growth of highly oriented diamond thin films on nickel was achieved by a multi-step process involving seeding, high temperature carbon dissolution, and growth. This process is very sensitive to the substrate temperature and requires accurate timing of both the nucleation and growth steps. It was observed that the surface morphology changed dramatically during the nucleation process and that in-situ monitoring of the surface morphology could provide valuable feedback for process control. An optical monitoring system developed under this study has significantly improved both the reproducibility and overall quality of the oriented diamond films grown on Ni substrates. However, since a significant fraction of carbon diffused into the bulk, as confirmed by Auger carbon depth profiling, the highest nucleation density on the bulk Ni substrate was 107 cm-2. To prevent carbon diffusion away from the surface and to maintain a supersaturated surface region, epitaxial nickel and iridium thin films were deposited by electron-beam evaporation on MgO which acted as a carbon diffusion barrier. A multi-layer structure with 100 A iridium and 1 mum nickel grown epitaxially on an MgO (100) wafer by electron-beam evaporation was used as a substrate. The 100 A thick Ir interlayer was used to overcome the delamination of Ni from the MgO substrate during processing. Oriented diamond was successfully deposited on these substrates and yielded nucleation densities of 3 x 108 cm-2, that resulted in faster coalescence of diamond particles. Coalesced diamond thin films on Ni/Ir/MgO substrates were grown in about six hours of growth, as compared to about 25 hours for the bulk Ni substrates. However, a much narrower process widow on Ni thin films made reproducible growth of oriented diamond more challenging. Cross-sectional high-resolution transmission electron microscopy (XHRTEM) was used to investigate the interfacial microstructure formed during hot filament chemical vapor deposition (HFCVD

  16. Behavior of piezoelectric wafer active sensor in various media

    NASA Astrophysics Data System (ADS)

    Kamas, Tuncay

    The dissertation addresses structural health monitoring (SHM) techniques using ultrasonic waves generated by piezoelectric wafer active sensors (PWAS) with an emphasis on the development of theoretical models of standing harmonic waves and guided waves. The focal objective of the research is to extend the theoretical study of electro-mechanical coupled PWAS as a resonator/transducer that interacts with standing and traveling waves in various media through electro-mechanical impedance spectroscopy (EMIS) method and guided wave propagation. The analytical models are developed and the coupled field finite element analysis (CF-FEA) models are simulated and verified with experiments. The dissertation is divided into two parts with respect to the developments in EMIS methods and GWP methods. In the first part, analytical and finite element models have been developed for the simulation of PWAS-EMIS in in-plane (longitudinal) and out-of-plane (thickness) mode. Temperature effects on free PWAS-EMIS are also discussed with respect to the in-plane mode. Piezoelectric material degradation on certain electrical and mechanical properties as the temperature increases is simulated by our analytical model for in-plane circular PWAS-EMIS that agrees well with the sets of experiments. Then the thickness mode PWAS-EMIS model was further developed for a PWAS resonator bonded on a plate-like structure. The latter analytical model was to determine the resonance frequencies for the normal mode expansion method through the global matrix method by considering PWAS-substrate and proof mass-PWAS-substrate models. The proof mass concept was adapted to shift the systems resonance frequencies in thickness mode. PWAS in contact with liquid medium on one of its surface has been analytically modeled and simulated the electro-mechanical response of PWAS with various liquids with different material properties such as the density and the viscosity. The second part discusses the guided wave propagation

  17. Radiation, temperature, and vacuum effects on piezoelectric wafer active sensors

    NASA Astrophysics Data System (ADS)

    Giurgiutiu, Victor; Postolache, Cristian; Tudose, Mihai

    2016-03-01

    The effect of radiation, temperature, and vacuum (RTV) on piezoelectric wafer active sensors (PWASs) is discussed. This study is relevant for extending structural health monitoring (SHM) methods to space vehicle applications that are likely to be subjected to harsh environmental conditions such as extreme temperatures (hot and cold), cosmic radiation, and interplanetary vacuums. This study contains both theoretical and experimental investigations with the use of electromechanical impedance spectroscopy (EMIS). In the theoretical part, analytical models of circular PWAS resonators were used to derive analytical expressions for the temperature sensitivities of EMIS resonance and antiresonance behavior. Closed-form expressions for frequency and peak values at resonance and antiresonance were derived as functions of the coefficients of thermal expansion, {α }1, {α }2, {α }3; the Poisson ratio, ν and its sensitivity, \\partial ν /\\partial T; the relative compliance gradient (\\partial {s}11E/\\partial T)/{s}11E; and the Bessel function root, z and its sensitivity, \\partial z/\\partial T. In the experimental part, tests were conducted to subject the PWAS transducers to RTV conditions. In one set of experiments, several RTV exposure, cycles were applied with EMIS signatures recorded at the beginning and after each of the repeated cycles. In another set of experiments, PWAS transducers were subjected to various temperatures and the EMIS signatures were recorded at each temperature after stabilization. The processing of measured EMIS data from the first set of experiments revealed that the resonance and antiresonance frequencies changed by less than 1% due to RTV exposure, whereas the resonance and antiresonance amplitudes changed by around 15%. After processing an individual set of EMIS data from the second set of experiments, it was determined that the relative temperature sensitivity of the antiresonance frequency ({f}{{AR}}/{f}{{AR}}) is approximately 63.1× {10

  18. Rinsing of wafers after wet processing: Simulation and experiments

    NASA Astrophysics Data System (ADS)

    Chiang, Chieh-Chun

    In semiconductor manufacturing, a large amount (50 billion gallons for US semiconductor fabrication plants in 2006) of ultrapure water (UPW) is used to rinse wafers after wet chemical processing to remove ionic contaminants on surfaces. Of great concern are the contaminants left in narrow (tens of nm), high-aspect-ratio (5:1 to 20:1) features (trenches, vias, and contact holes). The International Technology Roadmap for Semiconductors (ITRS) stipulates that ionic contaminant levels be reduced to below ˜ 10 10 atoms/cm2. Understanding the bottlenecks in the rinsing process would enable conservation of rinse water usage. A comprehensive process model has been developed on the COMSOL platform to predict the dynamics of rinsing of narrow structures on patterned SiO 2 substrates initially cleaned with NH4OH. The model considers the effect of various mass-transport mechanisms, including convection and diffusion/dispersion, which occur simultaneously with various surface phenomena, such as adsorption and desorption of impurities. The influences of charged species in the bulk and on the surface, and their induced electric field that affect both transport and surface interactions, have been addressed. Modeling results show that the efficacy of rinsing is strongly influenced by the rate of desorption of adsorbed contaminants, mass transfer of contaminants from the mouth of the feature to the bulk liquid, and the trench aspect ratio. Detection of the end point of rinsing is another way to conserve water used for rinsing after wet processing. The applicability of electrochemical impedance spectroscopy (EIS) to monitor rinsing of Si processed in HF with and without copper contaminant was explored. In the first study, the effect of the nature of surface state (flat band, depletion, or accumulation) of silicon on rinsing rate was investigated. The experimental results show that the state of silicon could affect rinsing kinetics through modulation of ion adsorption. In the second

  19. Structural Damage Detection with Piezoelectric Wafer Active Sensors

    NASA Astrophysics Data System (ADS)

    Giurgiutiu, Victor

    2011-07-01

    Piezoelectric wafer active sensors (PWAS) are lightweight and inexpensive enablers for a large class of damage detection and structural health monitoring (SHM) applications. This paper starts with a brief review of PWAS physical principles and basic modelling and continues by considering the various ways in which PWAS can be used for damage detection: (a) embedded guided-wave ultrasonics, i.e., pitch-catch, pulse-echo, phased arrays, thickness mode; (b) high-frequency modal sensing, i.e., the electro-mechanical (E/M) impedance method; (c) passive detection, i.e., acoustic emission and impact detection. An example of crack-like damage detection and localization with PWAS phased arrays on a small metallic plate is given. The modelling of PWAS detection of disbond damage in adhesive joints is achieved with the analytical transfer matrix method (TMM). The analytical methods offer the advantage of fast computation which enables parameter studies and carpet plots. A parametric study of the effect of crack size and PWAS location on disbond detection is presented. The power and energy transduction between PWAS and structure is studied analytically with a wave propagation method. Special attention is given to the mechatronics modeling of the complete transduction cycle from electrical excitation into ultrasonic acoustic waves by the piezoelectric effect, the transfer through the structure, and finally reverse piezoelectric transduction to generate the received electric signal. It is found that the combination of PWAS size and wave frequency/wavelength play an important role in identifying transduction maxima and minima that could be exploited to achieve an optimum power-efficient design. The multi-physics finite element method (MP-FEM), which permits fine discretization of damaged regions and complicated structural geometries, is used to study the generation of guided waves in a plate from an electrically excited transmitter PWAS and the capture of these waves as electric

  20. Dissolution of Oxygen Precipitate Nuclei in n-Type CZ-Si Wafers to Improve Their Material Quality: Experimental Results

    SciTech Connect

    Sopori, Bhushan; Basnyat, Prakash; Devayajanam, Srinivas; Tan, Teh; Upadhyaya, Ajay; Tate, Keith; Rohatgi, Ajeet; Xu, Han

    2017-01-01

    We present experimental results which show that oxygen-related precipitate nuclei (OPN) present in p-doped, n-type, Czochralski wafers can be dissolved using a flash-annealing process, yielding very high quality wafers for high-efficiency solar cells. Flash annealing consists of heating a wafer in an optical furnace to temperature between 1150 and 1250 degrees C for a short time. This process produces a large increase in the minority carrier lifetime (MCLT) and homogenizes each wafer. We have tested wafers from different axial locations of two ingots. All wafers reach nearly the same high value of MCLT. The OPN dissolution is confirmed by oxygen analysis using Fourier transform infrared spectra and injection-level dependence of MCLT.

  1. Spatial characterization of a 2 in GaN wafer by Raman spectroscopy and capacitance voltage measurements

    NASA Astrophysics Data System (ADS)

    Huang, Y.; Chen, X. D.; Fung, S.; Beling, C. D.; Ling, C. C.

    2004-10-01

    Micro-Raman spectroscopy and capacitance-voltage (C-V) measurements have been used to investigate 2 in GaN epitaxial wafers grown by hydride vapour phase epitaxy on sapphire substrates. The position and line shape of the A1 longitudinal optical (LO) phonon mode were used to determine the carrier concentration at different locations across the wafer. The line-shape fitting of the Raman A1 (LO) coupled modes taken from horizontal lateral-different positions on the wafer yielded a rudimentary spatial map of the carrier concentration. These data compare well with a carrier density map of the wafer obtained by C-V measurements, confirming the non-uniform distribution of carrier concentration in the GaN epitaxial film and that Raman spectroscopy of the LO phonon-plasmon mode can be used as a reliable and production friendly wafer quality test for GaN wafer manufacturing processes.

  2. Long persistent near infrared luminescence nanoprobes LiGa5O8:Cr3+-PEG-OCH3 for in vivo imaging

    NASA Astrophysics Data System (ADS)

    Fu, Xiaoyan; Liu, Chunlin; Shi, Junpeng; Man, Huizi; Xu, Jia; Zhang, Hongwu

    2014-09-01

    The Cr3+-doped LiGa5O8 nanoparticles (LGNPs) with long-persistent near-infrared phosphorescence were obtained through a sol-gel approach followed by heat treatment at 800 °C in air. The obtained results reveal that the nanoparticles with an average diameter of 100 nm are well defined and have pure structure of LiGa5O8. After illumination for 3 min using a 254 nm UV lamp, the LGNPs exhibit strong near-infrared peak at ca. 720 nm belonging to tissue transparency window which can last for more than 1 h. Via surface modified with PEG-5000-OCH3, the LGNPs-PEG-OCH3 exhibit excellent biocompatibility and low toxicity. Under in vitro pre-excitation using a 254 nm UV lamp for 3 min, the in vivo distribution of the LGNPs-PEG-OCH3 in the abdomen can be detected in real time for more than 1 h. All the results indicate that the LGNPs-PEG-OCH3 can be used as potential nanoprobes to realize in vivo, real time and long time imaging with high sensitivity.

  3. Wafer-scale fabrication of high-density nanoslit arrays for surface-enhanced Raman spectroscopy

    NASA Astrophysics Data System (ADS)

    Jin, Mingliang; Zhu, Yunfei; van den Berg, Albert; Zhang, Zhang; Zhou, Guofu; Shui, Lingling

    2016-12-01

    Surfaces with a periodic nanostructure and controllable feature size are sought after for optical applications, and the fabrication of such surfaces in large areas with high reproducibility, good stability and low deviation is very important. We present a strategy to fabricate large-area nanoslit arrays with controllable pitches and gaps. Au nanoslit arrays with gaps down to around 10 nm and a high gap density of 2.0 × 104 cm-1 have been fabricated, which can greatly enhance the near-field electromagnetic field to achieve localized surface plasmon resonance (LSPR). An averaged surface-enhanced Raman scattering analytical enhancement factor of 8.0 × 107 has been achieved on the substrate using a 633 nm laser source and the ‘coupling effect’ of LSPR of the nanoslits.

  4. Wafer-scale patterning of lead telluride nanowires: structure, characterization, and electrical properties.

    PubMed

    Yang, Yongan; Taggart, David K; Brown, Matthew A; Xiang, Chengxiang; Kung, Sheng-Chin; Yang, Fan; Hemminger, John C; Penner, Reginald M

    2009-12-22

    Nanowires of lead telluride (PbTe) were patterned on glass surfaces using lithographically patterned nanowire electrodeposition (LPNE). LPNE involved the fabrication by photolithography of a contoured nickel nanoband that is recessed by approximately 300 nm into a horizontal photoresist trench. Cubic PbTe was then electrodeposited from a basic aqueous solution containing Pb(2+) and TeO(3)(2-) at the nickel nanoband using a cyclic deposition/stripping potential program in which lead-rich PbTe was first deposited in a negative-going potential scan and excess lead was then anodically stripped from the nascent nanowire by scanning in the positive direction to produce near stoichiometric PbTe. Repeating this scanning procedure permitted PbTe nanowires 60-400 nm in width to be obtained. The wire height was controlled over the range of 20-100 nm based upon the nickel film thickness. Nanowires with lengths exceeding 1 cm were prepared in this study. We report the characterization of these nanowires using X-ray diffraction, transmission electron microscopy and electron diffraction, scanning electron microscopy, and X-ray photoelectron spectroscopy (XPS). The surface chemical composition of PbTe nanowires was monitored by XPS as a function of time during the exposure of these nanowires to laboratory air. One to two monolayers of a mixed Pb and Te oxide are formed during a 24 h exposure. The electrical conductivity of PbTe nanowires was strongly affected by air oxidation, declining from an initial value of 2.0(+/-1.5) x 10 (4) S/m by 61% (for nanowires with a 20 nm thickness), 55% (for 40 nm), and 12% (for 60 nm).

  5. Long Spin Relaxation Times in Wafer Scale Epitaxial Graphene on SiC(0001)

    NASA Astrophysics Data System (ADS)

    Maassen, Thomas; van den Berg, J. Jasper; Ijbema, Natasja; Fromm, Felix; Seyller, Thomas; Yakimova, Rositza; van Wees, Bart J.

    2012-03-01

    We developed an easy, upscalable process to prepare lateral spin-valve devices on epitaxially grown monolayer graphene on SiC(0001) and perform nonlocal spin transport measurements. We observe the longest spin relaxation times tau_S in monolayer graphene, while the spin diffusion coefficient D_S is strongly reduced compared to typical results on exfoliated graphene. The increase of tau_S is probably related to the changed substrate, while the cause for the small value of D_S remains an open question.

  6. Parallel fabrication of wafer-scale plasmonic metamaterials for nano-optics

    NASA Astrophysics Data System (ADS)

    Eslami, S.; Gibbs, J. G.; Mark, A. G.; Lee, T. C.; Jeong, H.-H.; Kim, I.; Fischer, P.

    2015-03-01

    We describe how physical vapor deposition coupled with micelle-nanolithography-seeded substrates permits the growth of metamaterials with 3D structural and material control at the nanoscale. Novel plasmonic hybrid structures with tuned optical response from the UV to the near IR are demonstrated.

  7. An architecture for a wafer-scale-implemented MIMD parallel computer

    SciTech Connect

    Wang, Chiajiu.

    1988-01-01

    In this dissertation, a general-purpose parallel computer architecture is proposed and studied. The proposed architecture, called the modified mesh-connected parallel computer (MMCPC) is obtained by enhancing a mesh-connected parallel computer with row buses and column buses. The MMCPC is a multiple instruction multiple data parallel machine. Because of the regular structure and distributed control mechanisms, the MMCPC is suitable for VLSI or WSI implementation. The bus structure of the MMCPC lends itself to configurability and fault tolerance. The MMCPC can be logically configured as a number of different parallel computer topologies. The MMCPC can tolerate as many faulty PE's, located randomly, as there are available spares, resulting in 100% redundancy utilization. The performance of the MMCPC was analyzed by applying a generalized stochastic Petri net graph to the MMCPC. The GSPN performance modeling results show a need for a new processing element (PE). A new PE architecture, able to handle data processing and message passing concurrently, is proposed and the silicon overhead is estimated in comparison with transputer-like PE's. Based upon the proposed PE, optimum sizes of the MMCPC for different program structures are derived. Two routing algorithms for the MMCPC were proposed and studied. Routing analysis was carried out through simulation. The simulation results show that the dynamic routing algorithm out performs the deterministic routing algorithm.

  8. Heteroepitaxial growth of wafer scale highly oriented graphene using inductively coupled plasma chemical vapor deposition

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Xu, Hai; Li, Linjun; Yang, Yang; Fu, Qiang; Bao, Xinhe; Loh, Kian Ping

    2016-06-01

    The chemical vapor deposition (CVD) of graphene on Cu has attracted much attention because of its industrial scalability. Herein, we report inductively coupled plasma-assisted CVD of epitaxially grown graphene on (111)-textured Cu film alloyed with a small amount of Ni, where large area high quality graphene film can be grown in less than 5 min at 800 °C, thus affording industrial scalability. The epitaxially grown graphene films on (111)-textured Cu contain grains which are predominantly aligned with the Cu lattice and about 10% of 30°-rotated grains (anti-grains). Such graphene films are exclusively monolayer and possess good electrical conductivity, high carrier mobility, and room temperature quantum Hall effect. Magnetoresistance measurements reveal that the reduction of the grain sizes from 150 nm to 50 nm produce increasing Anderson localization and the appearance of a transport gap. Owing to the presence of grain boundaries in these anti-grains, epitaxially grown graphene films possess n-type characteristics and exhibit ultra-high sensitivity to adsorbates.

  9. Thin Film Transistors Using Wafer-Scale Low-Temperature MOCVD WSe2

    NASA Astrophysics Data System (ADS)

    Gong, Yiyang; Zhang, Xiaotian; Redwing, Joan M.; Jackson, Thomas N.

    2016-12-01

    We report on thin film transistors using continuous WSe2 thin films synthesized by metal organic chemical vapor deposition at 400°C. O2 plasma etching is used to provide precise thickness modification of the WSe2 thin film with an etch rate ˜0.25 nm/min. Device performance is found to vary with the thickness of the WSe2 films. P-channel thin film transistors with plasma-thinned 3 nm WSe2 channels have mobility ˜0.01 cm2/Vs and current on-off ratio greater than 104. Our results suggest that plasma etching may provide an approach for post-growth modification of the electrical properties of two-dimensional transition metal dichalcogenide thin films.

  10. Wafer-scale growth of large arrays of perovskite microplate crystals for functional electronics and optoelectronics

    PubMed Central

    Wang, Gongming; Li, Dehui; Cheng, Hung-Chieh; Li, Yongjia; Chen, Chih-Yen; Yin, Anxiang; Zhao, Zipeng; Lin, Zhaoyang; Wu, Hao; He, Qiyuan; Ding, Mengning; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

    2015-01-01

    Methylammonium lead iodide perovskite has attracted intensive interest for its diverse optoelectronic applications. However, most studies to date have been limited to bulk thin films that are difficult to implement for integrated device arrays because of their incompatibility with typical lithography processes. We report the first patterned growth of regular arrays of perovskite microplate crystals for functional electronics and optoelectronics. We show that large arrays of lead iodide microplates can be grown from an aqueous solution through a seeded growth process and can be further intercalated with methylammonium iodide to produce perovskite crystals. Structural and optical characterizations demonstrate that the resulting materials display excellent crystalline quality and optical properties. We further show that perovskite crystals can be selectively grown on prepatterned electrode arrays to create independently addressable photodetector arrays and functional field effect transistors. The ability to grow perovskite microplates and to precisely place them at specific locations offers a new material platform for the fundamental investigation of the electronic and optical properties of perovskite materials and opens a pathway for integrated electronic and optoelectronic systems. PMID:26601297

  11. Ultraviolet-LIGA-based fabrication and characterization of a nonresonant drive-mode vibratory gyro/accelerometer

    NASA Astrophysics Data System (ADS)

    Verma, Payal; Zaman Khan, Khamar; Khonina, Svetlana Nikolaevna; Kazanskiy, Nikolay Lvovich; Gopal, Ram

    2016-07-01

    A dual-purpose nonresonant 2-degrees of freedom (DOF) drive-mode and 1-DOF sense-mode vibratory gyro/accelerometer fabricated using the economical ultraviolet-lithographie-galvanoformung-abformung (UV-LIGA) fabrication process using SU-8 photoresist is reported. The dual-purpose device presented is capable of detecting acceleration at the lower-frequency band and angular rate at the operating frequency band thereby functioning as both accelerometer and gyroscope. This is achieved by designing the structure such that the frequency response of the drive oscillator has two drive resonances with a flat zone between them, while the sense oscillator has one resonance, which is deliberately placed in the flat region between the two drive resonances. For angular rate detection, the device is operated in the flat zone at the sense resonance frequency at which the device is less susceptible to frequency variations due to both environmental variation and fabrication imperfections and hence is said to be operating in robust mode. The steady-state response and discrimination for angular rate and acceleration sensing have been devised using analytical modeling. The fabrication process is optimized to realize a gyro/accelerometer that has a 9-μm-thick nickel structural layer and 4-μm capacitive gaps. The overall miniature device size is 2.0 mm×1.9 mm. The experimental frequency response of the fabricated devices shows drive-mode resonances at 2.85 and 4.96 kHz and sense resonance at 3.85 kHz compared to the respective design values of drive-mode resonance frequencies 2.97 and 4.81 kHz and sense resonance frequency of 4 kHz. To demonstrate the dual-purpose capability of the device, acceleration characterization has been carried out and presented. The fabricated sensor is packaged in a ceramic package and interfaced with a MS3110 differential capacitive read out IC to characterize the acceleration response of the sensor, using an out-of-plane shaker. The bandwidth for

  12. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

    1992-01-01

    A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  13. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Powell, J. Anthony (Inventor)

    1991-01-01

    This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  14. High-density-plasma (HDP)-CVD oxide to thermal oxide wafer bonding for strained silicon layer transfer applications

    NASA Astrophysics Data System (ADS)

    Singh, R.; Radu, I.; Reiche, M.; Himcinschi, C.; Kuck, B.; Tillack, B.; Gösele, U.; Christiansen, S. H.

    2007-01-01

    Direct wafer bonding between high-density-plasma chemical vapour deposited (HDP-CVD) oxide and thermal oxide (TO) has been investigated. HDP-CVD oxides, about 230 nm in thickness, were deposited on Si(0 0 1) control wafers and the wafers of interest that contain a thin strained silicon (sSi) layer on a so-called virtual substrate that is composed of relaxed SiGe (˜4 μm thick) on Si(0 0 1) wafers. The surfaces of the as-deposited HDP-CVD oxides on the Si control wafers were smooth with a root-mean-square (RMS) roughness of <1 nm, which is sufficiently smooth for direct wafer bonding. The surfaces of the sSi/SiGe/Si(0 0 1) substrates show an RMS roughness of >2 nm. After HDP-CVD oxide deposition on the sSi/SiGe/Si substrates, the RMS roughness of the oxide surfaces was also found to be the same, i.e., >2 nm. To use these wafers for direct bonding the RMS roughness had to be reduced below 1 nm, which was carried out using a chemo-mechanical polishing (CMP) step. After bonding the HDP-CVD oxides to thermally oxidized handle wafers, the bonded interfaces were mostly bubble- and void-free for the silicon control and the sSi/SiGe/Si(0 0 1) wafers. The bonded wafer pairs were then annealed at higher temperatures up to 800 °C and the bonded interfaces were still found to be almost bubble- and void-free. Thus, HDP-CVD oxide is quite suitable for direct wafer bonding and layer transfer of ultrathin sSi layers on oxidized Si wafers for the fabrication of novel sSOI substrates.

  15. Correlation between reticle- and wafer-CD difference of multiple 28nm reticle-sites

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Richter, Frank; Thamm, Thomas; Ackmann, Paul; Staples, Marc; Weisbuch, Francois; Kurth, Karin; Schenker, Joerg; Leschok, Andre; GN, Fang Hong

    2012-11-01

    Reticle critical dimension uniformity (CDU) is an important criterion for the qualification of mask layer processes. Normally, the smaller the three sigma value of reticle CDU is, the better is the reticle CDU performance. For qualification of mask processes, the mask layers to be qualified should have a comparable reticle CDU compared to the process of record (POR) mask layers. Because the reticle critical dimension (CD) measurement is based on algorithms like "middle side lobe measurement", evaluation of the reticle CD-values can not reflect aspects like the sidewall angle of the reticle and variation in corner rounding which may be critical for 45nm technology nodes (and below). All involved tools and processes contribute to the wafer intra-field CDU (scanner, track, reticle, metrology). Normally, the reticle contribution to the wafer CDU should be as small as possible. In order to reduce the process contributions to the wafer intra-field CDU during the mask qualification process, the same toolset (exposure tool, metrology tool) should be applied as for the POR. Out of the results of these investigations the correlation between wafer measurement to target (MTT) and reticle MTT can be obtained in order to accurately qualify the CDU performance of the mask processes. We will demonstrate the correlation between reticle MTT and wafer MTT by use of multiple mask processes and alternative mask blank materials. We will investigate the results of four process-layers looking at advanced binary maskblank material from two different suppliers (moreover the results of a 2X-via layer as an example for a phase-shift maskblank is discussed). Objective of this article is to demonstrate the distribution between reticle MTT and wafer MTT as a qualification criterion for mask processes. The correlation between wafer CD-difference and reticle CD-difference of these mask processes are demonstrated by having performed investigations of dense features of different 28nmtechnology

  16. Wafer bonding technology for new generation vacuum MEMS: challenges and promises

    NASA Astrophysics Data System (ADS)

    Dragoi, V.; Pabo, E.

    2015-05-01

    Various MEMS devices are incorporated into consumer electronic devices. A particular category of MEMS require vacuum packaging by wafer bonding with the need to encapsulate vacuum levels of 10-2 mbar or higher with long time stability. The vacuum requirement is limiting the choice of the wafer bonding process and raises significant challenges to the existing investigation methods (metrology) used for results qualification. From the broad range of wafer bonding processes only few are compatible with vacuum applications: fusion bonding, anodic bonding, glass frit bonding and metal-based bonding. The outgassing from the enclosed surfaces after bonding will affect the vacuum level in the cavity: in some cases, a getter material is used inside the device cavity to compensate for this outgassing. Additionally the selected bonding process must be compatible with the devices on the wafers being bonded. This work reviews the principles of vacuum encapsulation using wafer bonding. Examples showing the suitability of each process for specific applications types will be presented. A significant challenge in vacuum MEMS fabrication is the lack of analytical methods needed for process characterization or reliability testing. A short overview of the most used methods and their limitations will be presented. Specific needs to be addressed will be introduced with examples.

  17. Front-end wafer-level microsystem packaging technique with microcap array

    NASA Astrophysics Data System (ADS)

    Chiang, Yuh-Min; Bachman, Mark; Li, Guann-pyng

    2002-07-01

    Packaging represents a significant and expensive obstacle in commercializing microsystem technology (MST) devices such as micro-electro-mechanical systems (MEMS), micro-optical-electro-mechanical-systems (MOEMS), microsensors, microactuators and other micromachined devices. This paper describes a novel wafer level protection method for MST devices which facilitates improved manufacturing throughput and automation in package assembly, wafer level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized micro-cap array. This array consists of an assortment of small caps molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments associated with packaging. It may also include modifications which enhance its adhesion to the MST wafer or increase the MST device function. Depending on the application, the micro-molded cap can be designed and modified to facilitate additional functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. The fabrication method, materials selection, and the compatibility of the micro cap device to conventional packaging process are discussed in this paper. The results of wafer-level micro cap packaging demonstrations are also presented.

  18. Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

    PubMed

    Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

    2011-04-21

    A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

  19. Engineering Controlled Spalling in (100)-Oriented GaAs for Wafer Reuse

    SciTech Connect

    Sweet, Cassi A.; McNeely, Joshua E.; Gorman, Brian; Young, David L.; Ptak, Aaron J.; Packard, Corinne E.

    2015-06-14

    Controlled spalling offers a way to cleave thin, single-crystal films or devices from wafers, particularly if the fracture planes in the material are oriented parallel to the wafer surface. Unfortunately, misalignment between the favored fracture planes and the wafer surface preferred for photovoltaic growth in (100)-oriented GaAs produces a highly faceted surface when subject to controlled spalling. This highly faceted cleavage surface is problematic in several ways: (1) it can result in large variations of spall depth due to unstable crack propagation; (2) it may introduce defects into the device zone or underlying substrate; and (3) it consumes many microns of material outside of the device zone. We present the ways in which we have engineered controlled spalling for (100)-oriented GaAs to minimize these effects. We expand the operational window for controlled spalling to avoid spontaneous spalling, find no evidence of dislocation activity in the spalled film or the parent wafer, and reduce facet height and facet height irregularity. Resolving these issues provides a viable path forward for reducing III-V device cost through the controlled spalling of (100)-oriented GaAs devices and subsequent wafer reuse when these processes are combined with a high-throughput growth method such as Hydride Vapor Phase Epitaxy.

  20. Mask and wafer cost of ownership (COO) from 65 to 22 nm half-pitch nodes

    NASA Astrophysics Data System (ADS)

    Hughes, Greg; Litt, Lloyd C.; Wüest, Andrea; Palaiyanur, Shyam

    2008-05-01

    Anticipating the cost of ownership (COO) of different lithography approaches into the future is an act of faith. It requires that one believe that all of the lithographic problems with next generation lithography (NGL) approaches will be sufficiently resolved to support the production of manufacturing wafers. This paper assumes that all of the necessary technologies will be available in the future and that the cost of the components can be extrapolated from historic cost trends. Mask and wafer costs of a single critical lithography layer for the 65, 45, 32 and 22 nm half-pitch (HP) nodes will be compared for immersion, double process (DP), double expose (DE), extreme ultraviolet (EUV), and imprint technologies. The mask COO analysis assumes that the basic yield of an optical mask is constant from node to node and that the infrastructure that allows this performance will be in place when the technologies are needed. The primary differences in mask costs among lithography approaches are driven by the patterning write time and materials. The wafer COO is driven by the mask cost (for the low wafer-per-mask use case), the lithography tool cost, and the effective wafers per hour (wph) for the lithography approach being considered.

  1. Microwave ECR plasma electron flood for low pressure wafer charge neutralization

    SciTech Connect

    Vanderberg, Bo; Nakatsugawa, Tomoya; Divergilio, William

    2012-11-06

    Modern ion implanters typically use dc arc discharge Plasma Electron Floods (PEFs) to neutralize wafer charge. The arc discharge requires using at least some refractory metal hardware, e.g. a thermionically emitting filament, which can be undesirable in applications where no metallic contamination is critical. rf discharge PEFs have been proposed to mitigate contamination risks but the gas flows required can result in high process chamber pressures. Axcelis has developed a microwave electron cyclotron resonance (ECR) PEF to provide refractory metals contamination-free wafer neutralization with low gas flow requirement. Our PEF uses a custom, reentrant cusp magnet field providing ECR and superior electron confinement. Stable PEF operation with extraction slits sized for 300 mm wafers can be attained at Xe gas flows lower than 0.2 sccm. Electron extraction currents can be as high as 20 mA at absorbed microwave powers < 70 W. On Axcelis' new medium current implanter, plasma generation has proven robust against pressure transients caused by, for example, photoresist outgassing by high power ion beams. Charge monitor and floating potential measurements along the wafer surface corroborate adequate wafer charge neutralization for low energy, high current ion beams.

  2. Silymarin released from sterile wafers restores glucose impaired endothelial cell migration.

    PubMed

    Gadad, Pramod C; Matthews, Kerr H; Knott, Rachel M

    2013-11-30

    Reduced oxygen tension combined with high glucose concentration leads to chronic wounds in diabetic patients. Delayed wound healing is due in part to impaired angiogenesis as a result of reduced endothelial cell migration. Topical applications, in the form of sterile lyophilised wafers hold promise for the treatment of chronic diabetic wounds. In this study wafers containing silymarin were prepared using xanthan gum and sterilised with 25 and 40 kGy gamma radiation. The rheological properties of xanthan gels, before and after lyophilisation, were measured and it was concluded that an increased dose of gamma rays (40 kGy) increased the viscosity coefficient and yield stress of silymarin wafers. HPLC analysis indicated that 89-90% of silymarin was retained in the wafers after irradiation. Dermal microvascular cell migration studies in the presence of high glucose and reduced oxygen tension levels, using novel radial migration and wound healing assays developed 'in house', were also undertaken. Silymarin, when formulated as a lyophilised wafer, successfully retained its ability to overcome the high glucose induced reduction in endothelial cell migration.

  3. Surface Formation of Single Silicon Wafer Polished with Nano-sized Al2O3 Powders

    NASA Astrophysics Data System (ADS)

    Sun, Yu-li; Zuo, Dun-wen; Zhu, Yong-wei; Wang, Min

    2007-12-01

    Ice polishing single silicon wafers with nano-sized Al2O3 abrasives can be known as ice fixed abrasives chemical mechanical polishing (IFA-CMP). TAn abrasive slurry was made of nano-sized Al2O3 particles dispersed in de-ionized water with a surfactant and the slurry was frozen to form an ice polishing pad. Then polishing tests of blanket silicon wafers with the above ice polishing pad were carried out. The morphologies and surface roughness of the polished silicon wafers were observed and examined on an atomic force microscope. The subsurface damage was assessed by means of cross-section transmission electron microscopy. The surface chemical constituents of the polished silicon wafers were characterized using X-ray photoelectron spectroscopy in order to gain insight into the chemical mechanisms in the process. Scratch resistance of the single silicon wafer was measured by nanoscratching using a nanoindenter to explore the mechanical removal mechanism. The results show that a super smooth surface with an average roughness of 0.367 nm is obtained within 1000 nm × 1000 nm and there is a perfect silicon diamond structure without any microcracks in the subsurface. The removal of material is dominated by the coactions of ductile regime machining and chemical corrosion. In the end, a model of material removal of IFA-CMP is built.

  4. Gaussian diffusion sphere model to predict deposition velocity onto wafers in laminar parallel airflow considering thermophoresis

    NASA Astrophysics Data System (ADS)

    Woo, Sang-Hee; Yook, Se-Jin; Han, Seog Young

    2012-11-01

    The Gaussian Diffusion Sphere Model (GDSM) was developed and improved to predict the particle deposition velocity onto a flat plate exposed to parallel airflow by considering thermophoresis in addition to the Brownian diffusion and the gravitational settling of particles. The plate surface temperature was varied and considered to be either hotter or colder than the temperature of the parallel airflow. The GDSM was able to estimate the particle deposition velocity under the influence of thermophoresis not only correctly but also very quickly, compared to the numerical approach to calculate the deposition velocity by simulating thermo-flow and particle transport. As the next step, the particle deposition velocities onto both face-up and face-down surfaces of the 450 mm wafer exposed to the parallel airflow were predicted with the GDSM by varying the wafer temperature. It was anticipated that the schemes of heating the wafer and placing the critical surface inverted during the horizontal transport of the wafer could greatly reduce the particulate contamination of the wafer critical surface.

  5. Influence of electrode geometry on the high-field characteristics of photoconductive silicon wafers

    SciTech Connect

    Madangarli, V.P.; Gradinaru, G.; Korony, G.; Sudarshan, T.S.; Loubriel, G.M.; Zutavern, F.J.; Patterson, P.E.

    1994-07-01

    A series of experiment were conducted to study the influence of electrode geometry on the prebreakdown (and breakdown) characteristics of high resistivity ({rho} > 30 k{Omega}-cm), p-type Si wafers under quasi-uniform and non-uniform electric field configurations. In the quasi-uniform field configuration, the 1mm thick Si wafer was mounted between the slots of two plane parallel stainless steel disc electrodes (parallel), while the non-uniform field was obtained by mounting the wafer between two pillar-type electrodes with a hemispherical tip (pillar). The main objective of the above investigation was to verify if the uniform field configuration under a parallel system has a positive influence by reducing the field enhancement at the contact region, as opposed to the definite field enhancement present in the case of the non-uniform pillar system. Also, it was proposed to study the effect of the contact profile on the field distribution over the wafer surface and hence its influence on the high-field performance of the Si wafers.

  6. Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

    NASA Astrophysics Data System (ADS)

    Pa, Pai-Shan

    2010-01-01

    A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

  7. Automated defect review of the wafer bevel with a defect review scanning electron microscope

    NASA Astrophysics Data System (ADS)

    McGarvey, Steve; Kanezawa, Masakazu

    2009-03-01

    One of the few remaining bastions of non-regulated Integrated Circuit defectivity is the wafer bevel. Recent internal Integrated Circuit Manufacturing studies have suggested that the edge bevel may be responsible for as much as a two to three percent yield loss during a defect excursion on the manufacturing line and a one to two percent yield loss during ongoing wafer manufacturing. A new generation of defect inspection equipment has been introduced to the Research and Development, Integrated Circuit, MEM's and Si wafer manufacturing markets that has imparted the ability for the end equipment user to detect defects located on the bevel of the wafer. The inherent weakness of the current batch of wafer bevel inspection equipment is the lack of automatic discrete defect classification data into multiple, significant classification bins and the lack of discrete elemental analysis data. Root cause analysis is based on minimal discrete defect analysis as a surrogate for a statistically valid sampling of defects from the bevel. This paper provides a study of the methods employed with a Hitachi RS-5500EQEQ Defect Review Scanning Electron Microscope (DRSEM) to automatically capture high resolution/high magnification images and collect elemental analysis on a statistically valid sample of the discrete defects that were located by a bevel inspection system.

  8. Measurement and mapping of materials parameters for gallium arsenide wafers by infrared transmission topography

    SciTech Connect

    Mier, M.G.; Look, D.C.; Walters, D.C.

    1996-12-01

    Polished wafers of semiinsulating (SI) undoped GaAs or of doped conducting GaAs are important for manufacture of monolithic microwave integrated circuits or of junction light emitters. For SI wafers, the EL2 defect causes the SI state, and variation in EL2 density can cause on-wafer variations in device isolation and other device properties. With conducting materials, crystalline dislocations cause dark-line defects and other recombination centers that limit carrier lifetime in fabricated lasers. High free carrier concentration leads to low series resistance ohmic contacts and is very desirable in semiconductor lasers. In the process of evaluating these materials, we have found that infrared transmission measurements can provide dense data on device-pertinent materials parameters for correlation to device parameters. Our custom color maps of these materials parameters keyed to color histograms of the measurement data can provide informative presentations of very large data sets for comparison to device measurements. For example, we discuss nondestructive neutral and total EL2 density measurements in SI GaAs and nondestructive dislocation density and free carrier concentration measurements in GaAs: Si, both by infrared topography. When test devices can be fabricated at known positions on the materials evaluation wafer (or on a nearby wafer from the same boule), sensitive comparison of materials evaluation data to measured device performance can be achieved. We show that topographic color maps allow meaningful comparisons of the materials measurements to device measurements at different spacings.

  9. Reliability study of wafer bonding for micro-electro-mechanical systems

    NASA Astrophysics Data System (ADS)

    Almasri, Mahmoud; Altemus, Bruce; Gracias, Alison; Clow, Larry; Tokranova, Natalya; Castracane, James; Xu, Bai

    2003-12-01

    Wafer bonding has attracted significant attention in applications that require integration of Micro-Electro-Mechanical Systems (MEMS) with Integrated Circuits (IC). The integration of monolithic MEMS and electronic devices is difficult because of issues such as material compatibility, process compliance and thermal budget. It is important to establish a wafer bonding process which provides long-term protection for the MEMS devices yet does not affect their performance. The attentions for such integration are at the die level and wafer level. Recently, the trend is toward wafer-level integration as a cost effective solution to combine sensing, logic, actuation and communications on a single platform. This paper describes the development of low temperature bonding techniques for post-CMOS MEMS integration in system-on-chip (SOC) applications. The bonding methods discussed in this paper involve Benzocyclobutene polymer (BCB) as glue layer to joint two 200 mm wafers together. The bonding temperature is lower than 400°C. Four-point bending and stud-pull methods were used to investigate the mechanical properties of the bonding interfaces. These methods can provide critical information such as adhesion energy and bonding strength of the bonded interfaces. Initial test results at room temperature showed that the BCB bond stayed intact up to an average stress of 50 MPa. It was observed that the BCB bond strength decreased with increasing temperatures and the energy release rate decreased with decreasing BCB thickness.

  10. Reliability study of wafer bonding for micro-electro-mechanical systems

    NASA Astrophysics Data System (ADS)

    Almasri, Mahmoud; Altemus, Bruce; Gracias, Alison; Clow, Larry; Tokranova, Natalya; Castracane, James; Xu, Bai

    2004-01-01

    Wafer bonding has attracted significant attention in applications that require integration of Micro-Electro-Mechanical Systems (MEMS) with Integrated Circuits (IC). The integration of monolithic MEMS and electronic devices is difficult because of issues such as material compatibility, process compliance and thermal budget. It is important to establish a wafer bonding process which provides long-term protection for the MEMS devices yet does not affect their performance. The attentions for such integration are at the die level and wafer level. Recently, the trend is toward wafer-level integration as a cost effective solution to combine sensing, logic, actuation and communications on a single platform. This paper describes the development of low temperature bonding techniques for post-CMOS MEMS integration in system-on-chip (SOC) applications. The bonding methods discussed in this paper involve Benzocyclobutene polymer (BCB) as glue layer to joint two 200 mm wafers together. The bonding temperature is lower than 400°C. Four-point bending and stud-pull methods were used to investigate the mechanical properties of the bonding interfaces. These methods can provide critical information such as adhesion energy and bonding strength of the bonded interfaces. Initial test results at room temperature showed that the BCB bond stayed intact up to an average stress of 50 MPa. It was observed that the BCB bond strength decreased with increasing temperatures and the energy release rate decreased with decreasing BCB thickness.

  11. Gated Silicon Drift Detector Fabricated from a Low-Cost Silicon Wafer

    PubMed Central

    Matsuura, Hideharu; Sakurai, Shungo; Oda, Yuya; Fukushima, Shinya; Ishikawa, Shohei; Takeshita, Akinobu; Hidaka, Atsuki

    2015-01-01

    Inexpensive high-resolution silicon (Si) X-ray detectors are required for on-site surveys of traces of hazardous elements in food and soil by measuring the energies and counts of X-ray fluorescence photons radially emitted from these elements. Gated silicon drift detectors (GSDDs) are much cheaper to fabricate than commercial silicon drift detectors (SDDs). However, previous GSDDs were fabricated from 10-kΩ·cm Si wafers, which are more expensive than 2-kΩ·cm Si wafers used in commercial SDDs. To fabricate cheaper portable X-ray fluorescence instruments, we investigate GSDDs formed from 2-kΩ·cm Si wafers. The thicknesses of commercial SDDs are up to 0.5 mm, which can detect photons with energies up to 27 keV, whereas we describe GSDDs that can detect photons with energies of up to 35 keV. We simulate the electric potential distributions in GSDDs with Si thicknesses of 0.5 and 1 mm at a single high reverse bias. GSDDs with one gate pattern using any resistivity Si wafer can work well for changing the reverse bias that is inversely proportional to the resistivity of the Si wafer. PMID:26007742

  12. A pad roughness model for the analysis of lubrication in the chemical mechanical polishing of a silicon wafer

    NASA Astrophysics Data System (ADS)

    Guo, Dongming; Liu, Jingyuan; Kang, Renke; Jin, Zhuji

    2007-07-01

    The slurry flow beneath the wafer in chemical mechanical polishing (CMP), involving the chemical reaction and the lubrication, is critical to the planarity and surface quality of a large-sized silicon wafer. In order to analyse the effects of pad roughness and some important operating parameters on the slurry flow with the suspended abrasives between the wafer and the pad, a complicated three-dimensional model based on the micropolar fluid theory, Brinkman equations and Darcy's law is developed. The effects of pad roughness and vital parameters on the slurry flow between the pad and the wafer are well discussed.

  13. Small footprint wafer-level vacuum packaging using compressible gold sealing rings

    NASA Astrophysics Data System (ADS)

    Antelius, Mikael; Stemme, Göran; Niklaus, Frank

    2011-08-01

    A novel low-temperature wafer-level vacuum packaging process is presented. The process uses plastically deformed gold rings as sealing structures in combination with flux-free soldering to provide the bond force for a sealing wafer. This process enables the separation of the sealing and the bonding functions both spatially on the wafer and temporally in different process steps, which results in reduced areas for the sealing rings and prevents outgassing from the solder process in the cavity. This enables space savings and yields improvements. We show the experimental result of the hermetic sealing. The leak rate into the packages is determined, by measuring the package lid deformation over 10 months, to be lower than 3.5 × 10-13 mbar l s-1, which is suitable for most MEMS packages. The pressure inside the produced packages is measured to be lower than 10 mbar.

  14. Initiation time of near-infrared laser-induced slip on the surface of silicon wafers

    SciTech Connect

    Choi, Sungho; Jhang, Kyung-Young

    2014-06-23

    We have determined the initiation time of laser-induced slip on a silicon wafer surface subjected to a near-infrared continuous-wave laser by numerical simulations and experiments. First, numerical analysis was performed based on the heat transfer and thermoelasticity model to calculate the resolved shear stress and the temperature-dependent yield stress. Slip initiation time was predicted by finding the time at which the resolved shear stress reached the yield stress. Experimentally, the slip initiation time was measured by using a laser scattering technique that collects scattered light from the silicon wafer surface and detects strong scattering when the surface slip is initiated. The surface morphology of the silicon wafer surface after laser irradiation was also observed using an optical microscope to confirm the occurrence of slip. The measured slip initiation times agreed well with the numerical predictions.

  15. First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

    NASA Technical Reports Server (NTRS)

    Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Lai, R.

    2008-01-01

    Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.

  16. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    NASA Astrophysics Data System (ADS)

    Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

    2017-04-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz–800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

  17. Wafer sub-layer impact in OPC/ORC models for advanced node implant layers

    NASA Astrophysics Data System (ADS)

    Le-Denmat, Jean-Christophe; Michel, Jean-Christophe; Sungauer, Elodie; Yesilada, Emek; Robert, Frederic; Lan, Song; Feng, Mu; Wang, Lei; Depre, Laurent; Kapasi, Sanjay

    2014-03-01

    From 28 nm technology node and below optical proximity correction (OPC) needs to take into account light scattering effects from prior layers when bottom anti-reflective coating (BARC) is not used, which is typical for ionic implantation layers. These effects are complex, especially when multiple sub layers have to be considered: for instance active and poly structures need to be accounted for. A new model form has been developed to address this wafer topography during model calibration called the wafer 3D+ or W3D+ model. This model can then be used in verification (using Tachyon LMC) and during model based OPC to increase the accuracy of mask correction and verification. This paper discusses an exploration of this new model results using extended wafer measurements (including SEM). Current results show good accuracy on various representative structures.

  18. Fabrication of high-density cantilever arrays and through-wafer interconnects

    SciTech Connect

    A. Harley, J.; Abdollahi-Alibeik, S.; Chow, E. M.; Kenney, T. W.; McCarthy, A. M.; McVittie, J. P.; Partridge; Quate, C. F.; Soh, H. T.

    1998-11-03

    Processes to fabricate dense, dry released microstructures with electrical connections on the opposite side of the wafer are described. A 10 x 10 array of silicon and polysilicon cantilevers with high packing density (5 tips/mm2) and high uniformity (<10 µm length variation across the wafer) are demonstrated. The cantilever release process uses a deep SF6/C4F8, plasma etch followed by a HBr plasma etch to accurately release cantilevers. A process for fabricating electrical contacts through the backside of the wafer is also described. Electrodeposited resist, conformal CVD metal deposition and deep SF6/C4F8 plasma etching are used to make 30 µm/side square vias each of which has a resistance of 50 m(omega).

  19. Vertically Conductive Single-Crystal SiC-Based Bragg Reflector Grown on Si Wafer

    PubMed Central

    Massoubre, David; Wang, Li; Hold, Leonie; Fernandes, Alanna; Chai, Jessica; Dimitrijev, Sima; Iacopi, Alan

    2015-01-01

    Single-crystal silicon carbide (SiC) thin-films on silicon (Si) were used for the fabrication and characterization of electrically conductive distributed Bragg reflectors (DBRs) on 100 mm Si wafers. The DBRs, each composed of 3 alternating layers of SiC and Al(Ga)N grown on Si substrates, show high wafer uniformity with a typical maximum reflectance of 54% in the blue spectrum and a stopband (at 80% maximum reflectance) as large as 100 nm. Furthermore, high vertical electrical conduction is also demonstrated resulting to a density of current exceeding 70 A/cm2 above 1.5 V. Such SiC/III-N DBRs with high thermal and electrical conductivities could be used as pseudo-substrate to enhance the efficiency of SiC-based and GaN-based optoelectronic devices on large Si wafers. PMID:26601894

  20. Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer

    SciTech Connect

    Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

    1999-09-07

    We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.