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Sample records for wafer scale liga

  1. A Batch Wafer Scale LIGA Assembly and Packaging Technique vai Diffusion Bonding

    SciTech Connect

    Christenson, T.R.; Schmale, D.T.

    1999-01-27

    A technique using diffusion bonding (or solid-state welding) has been used to achieve batch fabrication of two- level nickel LIGA structures. Interlayer alignment accuracy of less than 1 micron is achieved using press-fit gauge pins. A mini-scale torsion tester was built to measure the diffusion bond strength of LIGA formed specimens that has shown successful bonding at temperatures of 450"C at 7 ksi pressure with bond strength greater than 100 Mpa. Extensions to this basic process to allow for additional layers and thereby more complex assemblies as well as commensurate packaging are discussed.

  2. LIGA Scanner Control Software

    1999-02-01

    The LIGA Scanner Software is a graphical user interface package that facilitates controlling the scanning operation of x-rays from a synchrotron and sample manipulation for making LIGA parts. The process requires scanning of the LIGA mask and the PMMA resist through a stationary x-ray beam to provide an evenly distributed x-ray exposure over the wafer. This software package has been written specifically to interface with Aerotech motor controllers.

  3. Wafer-scale graphene integrated circuit.

    PubMed

    Lin, Yu-Ming; Valdes-Garcia, Alberto; Han, Shu-Jen; Farmer, Damon B; Meric, Inanc; Sun, Yanning; Wu, Yanqing; Dimitrakopoulos, Christos; Grill, Alfred; Avouris, Phaedon; Jenkins, Keith A

    2011-06-10

    A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

  4. Wafer-scale micro-optics fabrication

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  5. Parallel Assembly of LIGA Components

    SciTech Connect

    Christenson, T.R.; Feddema, J.T.

    1999-03-04

    In this paper, a prototype robotic workcell for the parallel assembly of LIGA components is described. A Cartesian robot is used to press 386 and 485 micron diameter pins into a LIGA substrate and then place a 3-inch diameter wafer with LIGA gears onto the pins. Upward and downward looking microscopes are used to locate holes in the LIGA substrate, pins to be pressed in the holes, and gears to be placed on the pins. This vision system can locate parts within 3 microns, while the Cartesian manipulator can place the parts within 0.4 microns.

  6. Eutectic bonds on wafer scale by thin film multilayers

    NASA Astrophysics Data System (ADS)

    Christensen, Carsten; Bouwstra, Siebe

    1996-09-01

    The use of gold based thin film multilayer systems for forming eutectic bonds on wafer scale is investigated and preliminary results will be presented. On polished 4 inch wafers different multilayer systems are developed using thin film techniques and bonded afterwards under reactive atmospheres and different bonding temperatures and forces. Pull tests are performed to extract the bonding strengths.

  7. Wafer-scale aluminum nano-plasmonics

    NASA Astrophysics Data System (ADS)

    George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

    2014-09-01

    The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

  8. Liga developer apparatus system

    DOEpatents

    Boehme, Dale R.; Bankert, Michelle A.; Christenson, Todd R.

    2003-01-01

    A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration. It has been found that by moving a patterned wafer, through a specific sequence of developer/rinse solutions, where an intermediate rinse solution completes development of those portions of the exposed resist left undeveloped after the development solution, by agitating the solutions with a source of high frequency sonic vibration, and by adjusting and closely controlling the temperatures and continuously filtering and recirculating these solutions, it is possible to maintain the kinetic dissolution of the exposed PMMA polymer as the rate limiting step.

  9. Wafer-scale plasmonic and photonic crystal sensors

    NASA Astrophysics Data System (ADS)

    George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

    2015-08-01

    200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

  10. Wafer-scale fabrication of penetrating neural microelectrode arrays

    NASA Astrophysics Data System (ADS)

    Bhandari, Rajmohan

    In order to have an efficient neural interface, uniformity and predictability of electrodes electrical, and mechanical characteristics are desired. Furthermore, the electrodes should have small active sites to selectively record or stimulate neural signals. Also, there should be close geometrical match between the electrode array and the targeted tissue for long-term stability. Currently the Utah electrode array (UEA) is in either constant electrode length (UEA) or varying length configurations (Utah slant electrode array: USEA). The current processes used to fabricate the UEAs impose limitations in the tolerances of the electrode array geometry. Furthermore, the flat architecture of the UEA and convoluted geometry of the targeted tissue results in poor coupling between the two "mating" surfaces, leading in active electrode tips that are not in proximity to the neuronal tissue. Therefore, a robust, flexible and high precision fabrication technology is needed that can produce (a) uniformly shaped microelectrodes (b) small and uniformly exposed active tip sites and (c) convoluted electrode arrays for better geometrical match. This dissertation presents a wafer-scale fabrication process for both the UEA and the USEA. A wafer-scale etching method has been developed and optimum etching conditions are established to achieve uniform shape electrode arrays. Also, the etching rate of silicon columns, produced by dicing, is studied as a function of temperature, etching time and stirring rate in the acid solution. Furthermore, a novel photoresist based masking technique for procuring extremely small active area has been developed on wafer-scale. In this technique, the tip exposure is controlled by varying the spin speed during photoresist coating. The technique allows fabrication of uniformly exposed tip lengths, over a range of 30 to 350 microm in length. Lastly, a novel array fabrication technique is developed for building a variety of neural interface devices having

  11. Wafer-scale fabrication of nanoapertures using corner lithography

    NASA Astrophysics Data System (ADS)

    Burouni, Narges; Berenschot, Erwin; Elwenspoek, Miko; Sarajlic, Edin; Leussink, Pele; Jansen, Henri; Tas, Niels

    2013-07-01

    Several submicron probe technologies require the use of apertures to serve as electrical, optical or fluidic probes; for example, writing precisely using an atomic force microscope or near-field sensing of light reflecting from a biological surface. Controlling the size of such apertures below 100 nm is a challenge in fabrication. One way to accomplish this scale is to use high resolution tools such as deep UV or e-beam. However, these tools are wafer-scale and expensive, or only provide series fabrication. For this reason, in this study a versatile method adapted from conventional micromachining is investigated to fabricate protruding apertures on wafer-scale. This approach is called corner lithography and offers control of the size of the aperture with diameter less than 50 nm using a low-budget lithography tool. For example, by tuning the process parameters, an estimated mean size of 44.5 nm and an estimated standard deviation of 2.3 nm are found. The technique is demonstrated—based on a theoretical foundation including a statistical analysis—with the nanofabrication of apertures at the apexes of micromachined pyramids. Besides apertures, the technique enables the construction of wires, slits and dots into versatile three-dimensional structures.

  12. Wrinkled bilayer graphene with wafer scale mechanical strain

    NASA Astrophysics Data System (ADS)

    Mikael, Solomon; Seo, Jung-Hun; Javadi, Alireza; Gong, Shaoqin; Ma, Zhenqiang

    2016-05-01

    Wafer-scale strained bilayer graphene is demonstrated by employing a silicon nitride (Si3N4) stressor layer. Different magnitudes of compressive stress up to 840 MPa were engineered by adjusting the Si3N4 deposition recipes, and different strain conditions were analyzed using Raman spectroscopy. The strained graphene displayed significant G peak shifts and G peak splitting with 16.2 cm-1 and 23.0 cm-1 of the G band and two-dimensional band shift, which corresponds to 0.26% of strain. Raman mapping of large regions of the graphene films found that the largest shifts/splitting occurred near the bilayer regions of the graphene films. The significance of our approach lies in the fact that it can be performed in a conventional microfabrication process, i.e., the plasma enhanced chemical vapor deposition system, and thus easily implemented for large scale production.

  13. Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

    NASA Technical Reports Server (NTRS)

    Jhabvala, Murzy; Franz, David E.; Ewin, Audrey J.; Jhabvala, Christine; Babu, Sachi; Snodgrass, Stephen; Costen, Nicholas; Zincke, Christian

    2009-01-01

    The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture

  14. Video-rate fuzzy Golay processor for wafer scale integration

    SciTech Connect

    Steinvorth, R.H.

    1987-01-01

    The fuzzy Golay transformation is a novel approach for gray-level image processing. Fuzzy-set theory is used to modify the binary image processing techniques developed by M. J. Golay to permit direct gray-level image processing without thresholding. The comparison between gray-level pixels is accomplished with the Pixel Closeness Value (PCV) while comparison between gray-level neighborhoods uses the Neighborhood Closeness Value (NCV). Feature extraction is done by comparing the gray-level image neighborhood to a subset of the fourteen Golay neighborhoods using the NCV function. The Fuzzy Golay Processor (FGP) is an architecture designed to implement the fuzzy Golay transformation. The design of the FGP has been optimized to permit a successful implementation in Wafer Scale Integration (WSI). A system containing four FGPs is capable of performing thirty fuzzy Golay transformations per second on a 256 by 256 eight-bit pixel image. Such a system could fit on a four-inch wafer with enough redundant dies to allow a 30% die yield. The required dies are four Input-Output Modules (IOM) and 56 Neighborhood Evaluation Modules (NEM).

  15. Investigations of Wafer Scale Etching with Xenon Difluoride

    NASA Astrophysics Data System (ADS)

    Chen, K. N.; Hoivik, N.; Lin, C. Y.; Young, A.; Ieong, M.; Shahidi, G.

    2006-03-01

    A good and uniform bulk silicon wafer etching method can be applied to the wafer thinning process in MEMS and 3D applications. In this study, the use of a Xenon Difluoride (XeF2) gas-phase etching system, operating at room temperature, has been investigated for bulk silicon wafer thinning. We investigated the Si-wafer surface morphology and profile following each XeF2 etching process cycle. Theoretical results are used to compare with the experimental results as well. A clean wafer surface by proper surface treatments is significant to achieve a uniform surface profile and morphology for XeF2 etching. A proper design of etching cycle with nitrogen ambient during etching is necessary to achieve the fastest and uniform silicon etching rate. The silicon etching rate is reported as a function of etching pressure, nitrogen pressure, and etching duration.

  16. Wafer-Scale Microwire Transistor Array Fabricated via Evaporative Assembly.

    PubMed

    Park, Jae Hoon; Sun, Qijun; Choi, Yongsuk; Lee, Seungwoo; Lee, Dong Yun; Kim, Yong Hoon; Cho, Jeong Ho

    2016-06-22

    One-dimensional (1D) nano/microwires have attracted significant attention as promising building blocks for various electronic and optical device applications. The integration of these elements into functional device networks with controlled alignment and density presents a significant challenge for practical device applications. Here, we demonstrated the fabrication of wafer-scale microwire field-effect transistor (FET) arrays based on well-aligned inorganic semiconductor microwires (indium-gallium-zinc-oxide (IGZO)) and organic polymeric insulator microwires fabricated via a simple and large-area evaporative assembly technique. This microwire fabrication method offers a facile approach to precisely manipulating the channel dimensions of the FETs. The resulting solution-processed monolithic IGZO microwire FETs exhibited a maximum electron mobility of 1.02 cm(2) V(-1) s(-1) and an on/off current ratio of 1 × 10(6). The appropriate choice of the polymeric microwires used to define the channel lengths enabled fine control over the threshold voltages of the devices, which were employed to fabricate high-performance depletion-load inverters. Low-voltage-operated microwire FETs were successfully fabricated on a plastic substrate using a high-capacitance ion gel gate dielectric. The microwire fabrication technique involving evaporative assembly provided a facile, effective, and reliable method for preparing flexible large-area electronics.

  17. Wafer-Scale Microwire Transistor Array Fabricated via Evaporative Assembly.

    PubMed

    Park, Jae Hoon; Sun, Qijun; Choi, Yongsuk; Lee, Seungwoo; Lee, Dong Yun; Kim, Yong Hoon; Cho, Jeong Ho

    2016-06-22

    One-dimensional (1D) nano/microwires have attracted significant attention as promising building blocks for various electronic and optical device applications. The integration of these elements into functional device networks with controlled alignment and density presents a significant challenge for practical device applications. Here, we demonstrated the fabrication of wafer-scale microwire field-effect transistor (FET) arrays based on well-aligned inorganic semiconductor microwires (indium-gallium-zinc-oxide (IGZO)) and organic polymeric insulator microwires fabricated via a simple and large-area evaporative assembly technique. This microwire fabrication method offers a facile approach to precisely manipulating the channel dimensions of the FETs. The resulting solution-processed monolithic IGZO microwire FETs exhibited a maximum electron mobility of 1.02 cm(2) V(-1) s(-1) and an on/off current ratio of 1 × 10(6). The appropriate choice of the polymeric microwires used to define the channel lengths enabled fine control over the threshold voltages of the devices, which were employed to fabricate high-performance depletion-load inverters. Low-voltage-operated microwire FETs were successfully fabricated on a plastic substrate using a high-capacitance ion gel gate dielectric. The microwire fabrication technique involving evaporative assembly provided a facile, effective, and reliable method for preparing flexible large-area electronics. PMID:27228025

  18. Designing defect spins for wafer-scale quantum technologies

    SciTech Connect

    Koehl, William F.; Seo, Hosung; Galli, Giulia; Awschalom, David D.

    2015-11-27

    The past decade has seen remarkable progress in the development of the nitrogen-vacancy (NV) defect center in diamond, which is one of the leading candidates for quantum information technologies. The success of the NV center as a solid-state qubit has stimulated an active search for similar defect spins in other technologically important and mature semiconductors, such as silicon carbide. If successfully combined with the advanced microfabrication techniques available to such materials, coherent quantum control of defect spins could potentially lead to semiconductor-based, wafer-scale quantum technologies that make use of exotic quantum mechanical phenomena like entanglement. In this article, we describe the robust spin property of the NV center and the current status of NV center research for quantum information technologies. We then outline first-principles computational modeling techniques based on density functional theory to efficiently search for potential spin defects in nondiamond hosts suitable for quantum information applications. The combination of computational modeling and experimentation has proven invaluable in this area, and we describe the successful interplay between theory and experiment achieved with the divacancy spin qubit in silicon carbide.

  19. Wafer-scale fabrication of plasmonic crystals from patterned silicon templates prepared by nanosphere lithography.

    PubMed

    Hall, Anthony Shoji; Friesen, Stuart A; Mallouk, Thomas E

    2013-06-12

    By combining nanosphere lithography with template stripping, silicon wafers were patterned with hexagonal arrays of nanowells or pillars. These silicon masters were then replicated in gold by metal evaporation, resulting in wafer-scale hexagonal gratings for plasmonic applications. In the nanosphere lithography step, two-dimensional colloidal crystals of 510 nm diameter polystyrene spheres were assembled at the air-water interface and transferred to silicon wafers. The spheres were etched in oxygen plasma in order to define their size for masking of the silicon wafer. For fabrication of metallic nanopillar arrays, an alumina film was grown over the nanosphere layer and the spheres were then removed by bath sonication. The well pattern was defined in the silicon wafer by reactive ion etching in a chlorine plasma. For fabrication of metal nanowell arrays, the nanosphere monolayer was used directly as a mask and exposed areas of the silicon wafer were plasma-etched anisotropically in SF6/Ar. Both techniques could be used to produce subwavelength metal replica structures with controlled pillar or well diameter, depth, and profile, on the wafer scale, without the use of direct writing techniques to fabricate masks or masters.

  20. Wafer-scale growth of VO2 thin films using a combinatorial approach

    NASA Astrophysics Data System (ADS)

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

    2015-10-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that `electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems.

  1. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    PubMed

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  2. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    NASA Astrophysics Data System (ADS)

    Esposito, M.; Anaxagoras, T.; Konstantinidis, A. C.; Zheng, Y.; Speller, R. D.; Evans, P. M.; Allinson, N. M.; Wells, K.

    2014-07-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  3. Facile Transferring of Wafer-Scale Ultrathin Alumina Membranes onto Substrates for Nanostructure Patterning.

    PubMed

    Al-Haddad, Ahmed; Zhan, Zhibing; Wang, Chengliang; Tarish, Samar; Vellacheria, Ranjith; Lei, Yong

    2015-08-25

    Ordered nanostructure arrays have attracted intensive attention because of their various applications. However, it is still a great challenge to achieve ordered nanostructure patterning over a large area (such as wafer-scale) by a technique that allows high throughput, large pattern area and low equipment costs. Here, through a unique design of the fabrication and transferring processes, we achieve a facile transferring of wafer-scale ultrathin alumina membranes (UTAMs) onto substrates without any twisting, folding, cracking and contamination. The most important in our method is fixing the UTAM onto the wafer-scale substrate before removing the backside Al and alumina barrier layer. It is also demonstrated that the thickness and surface smoothing of UTAMs play crucial roles in this transferring process. By using these perfectly transferred UTAMs as masks, various nanostructure patterning including nanoparticle, nanopore (nanomesh) and nanowire arrays are fabricated on wafer-scale substrates with tunable and uniform dimension. Because there are no requirements for UTAMs, substrates and materials to be deposited, the method presented here shall provide a cost-effective platform for the fabrication of ordered nanostructures on large substrates for various applications in nanotechnology.

  4. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates.

    PubMed

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-19

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes.

  5. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates

    NASA Astrophysics Data System (ADS)

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-01

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes.

  6. Wafer-scale growth of VO2 thin films using a combinatorial approach

    PubMed Central

    Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

    2015-01-01

    Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that ‘electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

  7. Overview of LIGA Microfabrication

    NASA Astrophysics Data System (ADS)

    Hruby, Jill

    2002-08-01

    This paper is an overview of the LIGA technique, an increasingly accepted approach for fabricating metal, ceramic or plastic microdevices. The LIGA technique was invented in Germany in the early 1980s and the acronym derives from the words LIthographie, Galvanoformung, Abformung meaning Lithography, Electroplating, and Molding in English. The paper is presented as an abbreviated set of annotated overheads used for the conference presentation and some summary remarks.

  8. Fabrication of wafer-scale nanopatterned sapphire substrate through phase separation lithography

    NASA Astrophysics Data System (ADS)

    Guo, Xu; Ni, Mengyang; Zhuang, Zhe; Dai, Jiangping; Wu, Feixiang; Cui, Yushuang; Yuan, Changsheng; Ge, Haixiong; Chen, Yanfeng

    2016-04-01

    A phase separation lithography (PSL) based on polymer blend provides an extremely simple, low-cost, and high-throughput way to fabricate wafer-scale disordered nanopatterns. This method was introduced to fabricate nanopatterned sapphire substrates (NPSSs) for GaN-based light-emitting diodes (LEDs). The PSL process only involved in spin-coating of polystyrene (PS)/polyethylene glycol (PEG) polymer blend on sapphire substrate and followed by a development with deionized water to remove PEG moiety. The PS nanoporous network was facilely obtained, and the structural parameters could be effectively tuned by controlling the PS/PEG weight ratio of the spin-coating solution. 2-in. wafer-scale NPSSs were conveniently achieved through the PS nanoporous network in combination with traditional nanofabrication methods, such as O2 reactive ion etching (RIE), e-beam evaporation deposition, liftoff, and chlorine-based RIE. In order to investigate the performance of such NPSSs, typical blue LEDs with emission wavelengths of ~450 nm were grown on the NPSS and a flat sapphire substrate (FSS) by metal-organic chemical vapor deposition, respectively. The integral photoluminescence (PL) intensity of the NPSS LED was enhanced by 32.3 % compared to that of the FSS-LED. The low relative standard deviation of 4.7 % for PL mappings of NPSS LED indicated the high uniformity of PL data across the whole 2-in. wafer. Extremely simple, low cost, and high throughput of the process and the ability to fabricate at the wafer scale make PSL a potential method for production of nanopatterned sapphire substrates.

  9. LIGA Micromachining: Infrastructure Establishment

    SciTech Connect

    Alfredo M. Morales; Barry V. Hess; Dale R. Boehme; Jill M. Hruby; John S. Krafcik; Robert H. Nilson; Stewart K. Griffiths; William D. Bonivert

    1999-02-01

    LIGA is a micromachining technology that uses high energy x-rays from a synchrotron to create patterns with small lateral dimensions in a deep, non-conducting polymeric resist. Typical dimensions for LIGA parts are microns to tens of microns in lateral size, and hundreds of microns to millimeters in depth. Once the resist is patterned, metal is electrodeposited in the features to create metal microparts, or to create a metal mold for subsequent replication. The acronym LIGA comes from the German words for lithography, electroforming, and molding, and the technology has been under worldwide development for more than a decade. over the last five years, a full-service capability to produce metal microparts using the LIGA process has been established at Sandia national Laboratories, California. This report describes the accomplishments made during the past two years in infrastructure establishment funded by a Laboratory Directed Research and Development (LDRD) project entitled ''LIGA Micromachining.'' Specific topics include photoresist processing for LIGA mask making, x-ray scanning equipment, plating bath instrumentation, plating uniformity, and software architecture.

  10. Self-adaptive phosphor coating technology for wafer-level scale chip packaging

    NASA Astrophysics Data System (ADS)

    Linsong, Zhou; Haibo, Rao; Wei, Wang; Xianlong, Wan; Junyuan, Liao; Xuemei, Wang; Da, Zhou; Qiaolin, Lei

    2013-05-01

    A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.

  11. Wafer scale interdigitated nanoelectrode devices functionalized using a MEMS-based deposition system

    NASA Astrophysics Data System (ADS)

    Martinez-Rivas, A.; Carcenac, F.; Saya, D.; Séverac, C.; Nicu, L.; Vieu, C.

    2012-03-01

    This paper reports on a methodology to elaborate interdigitated nanoelectrode devices (INDs) at the wafer scale, relying on a mix-and-match process which combines proximity optical lithography and electron beam lithography. An optimum exposure dose allowed fabricating nanodevices, at the wafer level, with a successful yield of 97%. The final devices are bonded onto conventional TO-8 packages. Electrical characterization in a short-circuited nanoelectrode is performed, revealing a 230 µΩ cm resistivity value at 23 °C. A MEMS-based spotter made of cantilevers (called Bioplume) has been used to obtain precise functionalization of the INDs with sub-picoliter volume solutions. These INDs are the basis of multiple tunnel junction nanodevices, intended to serve as novel highly sensitive nanobiosensors.

  12. Microfluidic design and fabrication of wafer-scale varifocal liquid lens

    NASA Astrophysics Data System (ADS)

    Lee, Jeong-Yub; Choi, Seung-Tae; Lee, Seung-Wan; Kim, Woonbae

    2009-08-01

    Microfluidic design and fabrication was developed for wafer-scale varifocal liquid lens which is slim less than 0.9mm. The liquid-filled varifocal lens has advanced functions such as auto macro and focusing to obtain a high quality of image. This varifocal lens is similar to human eye and it consists of main Si frame which has penetrated inner hole, upside-bonded PDMS (polydimethylsiloxane) elastomer membrane, downside-bonded glass plate and optical fluid confined by these structures. Si frame, which has a circular hole for tunable lens chamber, several holes for actuator chamber and micro-fluidic channels between chambers, is fabricated using thin Si wafer and microelectromechanical system (MEMS) processes. When optical fluid is filled the internal cavity by conventional injection, void trapping which degrades optical performance or filling impossibility happens because of high aspect ratio between lens diameter and thickness for slim liquid lens. To prevent these problems, we developed wafer-based microfabrications of seal line dispensing, accurate dropping of optical fluid, pressing & bonding process in vacuum and UV sealant curing. Afterward, electro-active polymer actuators, which push the optical fluid to change the lens shape, was attached on the PDMS membrane of liquid lens wafer and sawing process of 9.4mm*9.0mm chip size followed. Finally, the varifocal liquid lens which is slim less than 0.6mm thickness (0.9mm included actuators), tunable more than 20diopter changes of refractive power, guaranteed reliability of 300,000 repetitions and suitable for mass production, was realized.

  13. Growth of wafer-scale MoS2 monolayer by magnetron sputtering

    NASA Astrophysics Data System (ADS)

    Tao, Junguang; Chai, Jianwei; Lu, Xin; Wong, Lai Mun; Wong, Ten It; Pan, Jisheng; Xiong, Qihua; Chi, Dongzhi; Wang, Shijie

    2015-01-01

    The two-dimensional layer of molybdenum disulfide (MoS2) exhibits promising prospects in the applications of optoelectronics and valleytronics. Herein, we report a successful new process for synthesizing wafer-scale MoS2 atomic layers on diverse substrates via magnetron sputtering. Spectroscopic and microscopic results reveal that these synthesized MoS2 layers are highly homogeneous and crystallized; moreover, uniform monolayers at wafer scale can be achieved. Raman and photoluminescence spectroscopy indicate comparable optical qualities of these as-grown MoS2 with other methods. The transistors composed of the MoS2 film exhibit p-type performance with an on/off current ratio of ~103 and hole mobility of up to ~12.2 cm2 V-1 s-1. The strategy reported herein paves new ways towards the large scale growth of various two-dimensional semiconductors with the feasibility of controllable doping to realize desired p- or n-type devices.The two-dimensional layer of molybdenum disulfide (MoS2) exhibits promising prospects in the applications of optoelectronics and valleytronics. Herein, we report a successful new process for synthesizing wafer-scale MoS2 atomic layers on diverse substrates via magnetron sputtering. Spectroscopic and microscopic results reveal that these synthesized MoS2 layers are highly homogeneous and crystallized; moreover, uniform monolayers at wafer scale can be achieved. Raman and photoluminescence spectroscopy indicate comparable optical qualities of these as-grown MoS2 with other methods. The transistors composed of the MoS2 film exhibit p-type performance with an on/off current ratio of ~103 and hole mobility of up to ~12.2 cm2 V-1 s-1. The strategy reported herein paves new ways towards the large scale growth of various two-dimensional semiconductors with the feasibility of controllable doping to realize desired p- or n-type devices. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr06411a

  14. Wafer-Scale, Homogeneous MoS2 Layers on Plastic Substrates for Flexible Visible-Light Photodetectors.

    PubMed

    Lim, Yi Rang; Song, Wooseok; Han, Jin Kyu; Lee, Young Bum; Kim, Sung Jun; Myung, Sung; Lee, Sun Sook; An, Ki-Seok; Choi, Chel-Jong; Lim, Jongsun

    2016-07-01

    An appropriate solution is suggested for synthesizing wafer-scale, continuous, and stoichiometric MoS2 layers with spatial homogeneity at the low temperature of 450 °C. It is also demonstrated that the MoS2 -based visible-light photodetector arrays are both fabricated on 4 inch SiO2 /Si wafer and polyimide films, revealing 100% active devices with a narrow photocurrent distribution and excellent mechanical durability.

  15. Assembly of LIGA using Electric Fields

    SciTech Connect

    FEDDEMA, JOHN T.; WARNE, LARRY K.; JOHNSON, WILLIAM A.; OGDEN, ALLISON J.; ARMOUR, DAVID L.

    2002-04-01

    The goal of this project was to develop a device that uses electric fields to grasp and possibly levitate LIGA parts. This non-contact form of grasping would solve many of the problems associated with grasping parts that are only a few microns in dimensions. Scaling laws show that for parts this size, electrostatic and electromagnetic forces are dominant over gravitational forces. This is why micro-parts often stick to mechanical tweezers. If these forces can be controlled under feedback control, the parts could be levitated, possibly even rotated in air. In this project, we designed, fabricated, and tested several grippers that use electrostatic and electromagnetic fields to grasp and release metal LIGA parts. The eventual use of this tool will be to assemble metal and non-metal LIGA parts into small electromechanical systems.

  16. Wafer-scale assembly of highly ordered semiconductor nanowire arrays by contact printing.

    PubMed

    Fan, Zhiyong; Ho, Johnny C; Jacobson, Zachery A; Yerushalmi, Roie; Alley, Robert L; Razavi, Haleh; Javey, Ali

    2008-01-01

    Controlled and uniform assembly of "bottom-up" nanowire (NW) materials with high scalability presents one of the significant bottleneck challenges facing the integration of nanowires for electronic applications. Here, we demonstrate wafer-scale assembly of highly ordered, dense, and regular arrays of NWs with high uniformity and reproducibility through a simple contact printing process. The assembled NW pitch is shown to be readily modulated through the surface chemical treatment of the receiver substrate, with the highest density approaching approximately 8 NW/mum, approximately 95% directional alignment, and wafer-scale uniformity. Such fine control in the assembly is attained by applying a lubricant during the contact printing process which significantly minimizes the NW-NW mechanical interactions, therefore enabling well-controlled transfer of nanowires through surface chemical binding interactions. Furthermore, we demonstrate that our printing approach enables large-scale integration of NW arrays for various device structures on both rigid silicon and flexible plastic substrates, with a controlled semiconductor channel width ranging from a single NW ( approximately 10 nm) up to approximately 250 microm, consisting of a parallel array of over 1250 NWs and delivering over 1 mA of ON current.

  17. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    PubMed

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

  18. Wafer-scale high-throughput ordered growth of vertically aligned ZnO nanowire arrays.

    PubMed

    Wei, Yaguang; Wu, Wenzhuo; Guo, Rui; Yuan, Dajun; Das, Suman; Wang, Zhong Lin

    2010-09-01

    This article presents an effective approach for patterned growth of vertically aligned ZnO nanowire (NW) arrays with high throughput and low cost at wafer scale without using cleanroom technology. Periodic hole patterns are generated using laser interference lithography on substrates coated with the photoresist SU-8. ZnO NWs are selectively grown through the holes via a low-temperature hydrothermal method without using a catalyst and with a superior control over orientation, location/density, and as-synthesized morphology. The development of textured ZnO seed layers for replacing single crystalline GaN and ZnO substrates extends the large-scale fabrication of vertically aligned ZnO NW arrays on substrates of other materials, such as polymers, Si, and glass. This combined approach demonstrates a novel method of manufacturing large-scale patterned one-dimensional nanostructures on various substrates for applications in energy harvesting, sensing, optoelectronics, and electronic devices.

  19. A Method to Pattern Silver Nanowires Directly on Wafer-Scale PDMS Substrate and Its Applications.

    PubMed

    Chou, Namsun; Kim, Youngseok; Kim, Sohee

    2016-03-01

    This study describes a fabrication method of microsized AgNW patterns based on poly dimethylsiloxane (PDMS) substrate using a poly(p-xylylene) (parylene) stencil technique. Various patterns of AgNW conductive sheets were created on the wafer scale area in the forms of straight and serpentine lines, texts, and symbols, which dimensions ranged from a few tens of micrometers to hundreds of micrometers. We demonstrated the electrical performance of straight line and serpentine line patterned AgNW electrodes when subjected to mechanical strains. The gauge factor and stretchability ranged from 0.5 to 55.2 at 2% uniaxial strain and from 4.7 to 55.7%, respectively, depending on the shapes and structures of the AgNW electrodes. Using the developed AgNW patterning technique, we fabricated strain sensors to detect small body signals epidermally such as hand motion, eye blink and heart rate. Also, tactile sensors were fabricated and exhibited the sensitivity of 3.91 MPa(-1) in the pressure range lower than 50 kPa, and 0.28 MPa(-1) in the pressure range greater than 50 kPa up to 1.3 MPa. From these results, we concluded that the proposed technique enables the fabrication of reliable AgNW patterns on wafer-scale PDMS substrate and the potential applications for various flexible electronic devices. PMID:26882099

  20. A Method to Pattern Silver Nanowires Directly on Wafer-Scale PDMS Substrate and Its Applications.

    PubMed

    Chou, Namsun; Kim, Youngseok; Kim, Sohee

    2016-03-01

    This study describes a fabrication method of microsized AgNW patterns based on poly dimethylsiloxane (PDMS) substrate using a poly(p-xylylene) (parylene) stencil technique. Various patterns of AgNW conductive sheets were created on the wafer scale area in the forms of straight and serpentine lines, texts, and symbols, which dimensions ranged from a few tens of micrometers to hundreds of micrometers. We demonstrated the electrical performance of straight line and serpentine line patterned AgNW electrodes when subjected to mechanical strains. The gauge factor and stretchability ranged from 0.5 to 55.2 at 2% uniaxial strain and from 4.7 to 55.7%, respectively, depending on the shapes and structures of the AgNW electrodes. Using the developed AgNW patterning technique, we fabricated strain sensors to detect small body signals epidermally such as hand motion, eye blink and heart rate. Also, tactile sensors were fabricated and exhibited the sensitivity of 3.91 MPa(-1) in the pressure range lower than 50 kPa, and 0.28 MPa(-1) in the pressure range greater than 50 kPa up to 1.3 MPa. From these results, we concluded that the proposed technique enables the fabrication of reliable AgNW patterns on wafer-scale PDMS substrate and the potential applications for various flexible electronic devices.

  1. Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

    PubMed Central

    Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

    2014-01-01

    In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

  2. Wafer scale integration of reduced graphene oxide by novel laser processing at room temperature in air

    NASA Astrophysics Data System (ADS)

    Bhaumik, Anagh; Narayan, Jagdish

    2016-09-01

    Physical properties of reduced graphene oxide (rGO) strongly depend on the ratio of sp2 to sp3 hybridized carbon atoms, the presence of different functional groups, and the characteristics of the substrates. This research for the very first time illustrates successful wafer scale integration of 2D rGO with Cu/TiN/Si, employing pulsed laser deposition followed by laser annealing of carbon-doped copper layers using nanosecond excimer lasers. The XRD, SEM, and Raman spectroscopy measurements indicate the presence of large area rGO onto Si having Raman active vibrational modes: D, G, and 2D. A high resolution SEM depicts the morphology and formation of rGO from zone-refined carbon formed after nanosecond laser annealing. Temperature-dependent resistance data of rGO thin films follow the Efros-Shklovskii variable range hopping (VRH) model in the low-temperature region and Arrhenius conduction in the high-temperature regime. The photoluminescence spectra also reveal a less intense and broader blue fluorescence spectra, indicating the presence of miniature sized sp2 domains in the near vicinity of π* electronic states which favor the VRH transport phenomena. This wafer scale integration of rGO with Si employing a laser annealing technique will be useful for multifunctional integrated electronic devices and will open a new frontier for further extensive research in these functionalized 2D materials.

  3. Face-to-face transfer of wafer-scale graphene films.

    PubMed

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying

  4. Face-to-face transfer of wafer-scale graphene films

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Ni, Guang-Xin; Liu, Yanpeng; Liu, Bo; Castro Neto, Antonio H.; Loh, Kian Ping

    2014-01-01

    Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying

  5. Resolution enhancement using plasmonic metamask for wafer-scale photolithography in the far field.

    PubMed

    Baek, Seunghwa; Kang, Gumin; Kang, Min; Lee, Chang-Won; Kim, Kyoungsik

    2016-01-01

    Resolution enhancement in far-field photolithography is demonstrated using a plasmonic metamask in the proximity regime, in which Fresnel diffraction is dominant. The transverse magnetic component of the diffracted wave from the photomask, which reduces the pattern visibility and lowers the resolution, was successfully controlled by coupling with the anti-symmetric mode of the excited surface plasmon. We obtained a consistently finely-patterned photoresist surface at a distance of up to 15 μm from the mask surface for 3-μm-pitch slits because of conserved field visibility when propagating from the near-field to the proximity regime. We confirmed that sharp edge patterning is indeed possible when using a wafer-scale photomask in the proximity photolithography regime. Our plasmonic metamask method produces cost savings for ultra-large-scale high-density display fabrication by maintaining longer photomask lifetimes and by allowing sufficient tolerance for the distance between the photomask and the photoresist.

  6. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

    PubMed Central

    Berman, Diana; Deshmukh, Sanket A.; Narayanan, Badri; Sankaranarayanan, Subramanian K. R. S.; Yan, Zhong; Balandin, Alexander A.; Zinovev, Alexander; Rosenmann, Daniel; Sumant, Anirudha V.

    2016-01-01

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the process can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. In addition, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics. PMID:27373740

  7. Resolution enhancement using plasmonic metamask for wafer-scale photolithography in the far field

    NASA Astrophysics Data System (ADS)

    Baek, Seunghwa; Kang, Gumin; Kang, Min; Lee, Chang-Won; Kim, Kyoungsik

    2016-07-01

    Resolution enhancement in far-field photolithography is demonstrated using a plasmonic metamask in the proximity regime, in which Fresnel diffraction is dominant. The transverse magnetic component of the diffracted wave from the photomask, which reduces the pattern visibility and lowers the resolution, was successfully controlled by coupling with the anti-symmetric mode of the excited surface plasmon. We obtained a consistently finely-patterned photoresist surface at a distance of up to 15 μm from the mask surface for 3-μm-pitch slits because of conserved field visibility when propagating from the near-field to the proximity regime. We confirmed that sharp edge patterning is indeed possible when using a wafer-scale photomask in the proximity photolithography regime. Our plasmonic metamask method produces cost savings for ultra-large-scale high-density display fabrication by maintaining longer photomask lifetimes and by allowing sufficient tolerance for the distance between the photomask and the photoresist.

  8. Wafer-scale fabrication and growth dynamics of suspended graphene nanoribbon arrays.

    PubMed

    Suzuki, Hiroo; Kaneko, Toshiro; Shibuta, Yasushi; Ohno, Munekazu; Maekawa, Yuki; Kato, Toshiaki

    2016-06-02

    Adding a mechanical degree of freedom to the electrical and optical properties of atomically thin materials can provide an excellent platform to investigate various optoelectrical physics and devices with mechanical motion interaction. The large scale fabrication of such atomically thin materials with suspended structures remains a challenge. Here we demonstrate the wafer-scale bottom-up synthesis of suspended graphene nanoribbon arrays (over 1,000,000 graphene nanoribbons in 2 × 2 cm(2) substrate) with a very high yield (over 98%). Polarized Raman measurements reveal graphene nanoribbons in the array can have relatively uniform-edge structures with near zigzag orientation dominant. A promising growth model of suspended graphene nanoribbons is also established through a comprehensive study that combined experiments, molecular dynamics simulations and theoretical calculations with a phase-diagram analysis. We believe that our results can contribute to pushing the study of graphene nanoribbons into a new stage related to the optoelectrical physics and industrial applications.

  9. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale.

    PubMed

    Berman, Diana; Deshmukh, Sanket A; Narayanan, Badri; Sankaranarayanan, Subramanian K R S; Yan, Zhong; Balandin, Alexander A; Zinovev, Alexander; Rosenmann, Daniel; Sumant, Anirudha V

    2016-01-01

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the process can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. In addition, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics. PMID:27373740

  10. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

    NASA Astrophysics Data System (ADS)

    Berman, Diana; Deshmukh, Sanket A.; Narayanan, Badri; Sankaranarayanan, Subramanian K. R. S.; Yan, Zhong; Balandin, Alexander A.; Zinovev, Alexander; Rosenmann, Daniel; Sumant, Anirudha V.

    2016-07-01

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the process can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. In addition, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.

  11. Wafer-scale fabrication and growth dynamics of suspended graphene nanoribbon arrays

    NASA Astrophysics Data System (ADS)

    Suzuki, Hiroo; Kaneko, Toshiro; Shibuta, Yasushi; Ohno, Munekazu; Maekawa, Yuki; Kato, Toshiaki

    2016-06-01

    Adding a mechanical degree of freedom to the electrical and optical properties of atomically thin materials can provide an excellent platform to investigate various optoelectrical physics and devices with mechanical motion interaction. The large scale fabrication of such atomically thin materials with suspended structures remains a challenge. Here we demonstrate the wafer-scale bottom-up synthesis of suspended graphene nanoribbon arrays (over 1,000,000 graphene nanoribbons in 2 × 2 cm2 substrate) with a very high yield (over 98%). Polarized Raman measurements reveal graphene nanoribbons in the array can have relatively uniform-edge structures with near zigzag orientation dominant. A promising growth model of suspended graphene nanoribbons is also established through a comprehensive study that combined experiments, molecular dynamics simulations and theoretical calculations with a phase-diagram analysis. We believe that our results can contribute to pushing the study of graphene nanoribbons into a new stage related to the optoelectrical physics and industrial applications.

  12. Wafer-scale epitaxial graphene on SiC for sensing applications

    NASA Astrophysics Data System (ADS)

    Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

    2015-12-01

    The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

  13. Wafer scale fabrication of submicron chessboard gratings using phase masks in proximity lithography

    NASA Astrophysics Data System (ADS)

    Stuerzebecher, Lorenz; Harzendorf, Torsten; Fuchs, Frank; Zeitner, Uwe D.

    2012-03-01

    One and two dimensional grating structures with submicron period have a huge number of applications in optics and photonics. Such structures are conventionally fabricated using interference or e-beam lithography. However, both technologies have significant drawbacks. Interference lithography is limited to rather simple geometries and the sequential writing scheme of e-beam lithography leads to time consuming exposures for each grating. We present a novel fabrication technique for this class of microstructures which is based on proximity lithography in a mask aligner. The technology is capable to pattern a complete wafer within less than one minute of exposure time and offers thereby high lateral resolution and a reliable process. Our advancements compared to standard mask aligner lithography are twofold: First of all, we are using periodic binary phase masks instead of chromium masks to generate an aerial image of high resolution and exceptional light efficiency at certain distances behind the mask. Second, a special mask aligner illumination set-up is employed which allows to precisely control the incidence angles of the exposure light. This degree of freedom allows both, to shape the aerial image (e. g. transformation of a periodic spot pattern into a chessboard pattern) and to increase its depth of focus considerably. That way, our technology enables the fabrication of high quality gratings with arbitrary geometry in a fast and stable wafer scale process.

  14. Wafer-scale growth of MoS2 thin films by atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Pyeon, Jung Joon; Kim, Soo Hyun; Jeong, Doo Seok; Baek, Seung-Hyub; Kang, Chong-Yun; Kim, Jin-Sang; Kim, Seong Keun

    2016-05-01

    The wafer-scale synthesis of MoS2 layers with precise thickness controllability and excellent uniformity is essential for their application in the nanoelectronics industry. Here, we demonstrate the atomic layer deposition (ALD) of MoS2 films with Mo(CO)6 and H2S as the Mo and S precursors, respectively. A self-limiting growth behavior is observed in the narrow ALD window of 155-175 °C. Long H2S feeding times are necessary to reduce the impurity contents in the films. The as-grown MoS2 films are amorphous due to the low growth temperature. Post-annealing at high temperatures under a H2S atmosphere efficiently improves the film properties including the crystallinity and chemical composition. An extremely uniform film growth is achieved even on a 4 inch SiO2/Si wafer. These results demonstrate that the current ALD process is well suited for the synthesis of MoS2 layers for application in industry.

  15. Wafer-scale design of lightweight and transparent electronics that wraps around hairs.

    PubMed

    Salvatore, Giovanni A; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

    2014-01-01

    Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

  16. Wafer-scale design of lightweight and transparent electronics that wraps around hairs.

    PubMed

    Salvatore, Giovanni A; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

    2014-01-01

    Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease. PMID:24399363

  17. High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity.

    PubMed

    Kang, Kibum; Xie, Saien; Huang, Lujie; Han, Yimo; Huang, Pinshane Y; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-04-30

    The large-scale growth of semiconducting thin films forms the basis of modern electronics and optoelectronics. A decrease in film thickness to the ultimate limit of the atomic, sub-nanometre length scale, a difficult limit for traditional semiconductors (such as Si and GaAs), would bring wide benefits for applications in ultrathin and flexible electronics, photovoltaics and display technology. For this, transition-metal dichalcogenides (TMDs), which can form stable three-atom-thick monolayers, provide ideal semiconducting materials with high electrical carrier mobility, and their large-scale growth on insulating substrates would enable the batch fabrication of atomically thin high-performance transistors and photodetectors on a technologically relevant scale without film transfer. In addition, their unique electronic band structures provide novel ways of enhancing the functionalities of such devices, including the large excitonic effect, bandgap modulation, indirect-to-direct bandgap transition, piezoelectricity and valleytronics. However, the large-scale growth of monolayer TMD films with spatial homogeneity and high electrical performance remains an unsolved challenge. Here we report the preparation of high-mobility 4-inch wafer-scale films of monolayer molybdenum disulphide (MoS2) and tungsten disulphide, grown directly on insulating SiO2 substrates, with excellent spatial homogeneity over the entire films. They are grown with a newly developed, metal-organic chemical vapour deposition technique, and show high electrical performance, including an electron mobility of 30 cm(2) V(-1) s(-1) at room temperature and 114 cm(2) V(-1) s(-1) at 90 K for MoS2, with little dependence on position or channel length. With the use of these films we successfully demonstrate the wafer-scale batch fabrication of high-performance monolayer MoS2 field-effect transistors with a 99% device yield and the multi-level fabrication of vertically stacked transistor devices for three

  18. Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale

    PubMed Central

    2013-01-01

    We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production. PMID:24289275

  19. Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale

    NASA Astrophysics Data System (ADS)

    Ho, Jian-Wei; Wee, Qixun; Dumond, Jarrett; Tay, Andrew; Chua, Soo-Jin

    2013-12-01

    We report on a method of fabricating variable patterns of periodic, high aspect ratio silicon nanostructures with sub-50-nm resolution on a wafer scale. The approach marries step-and-repeat nanoimprint lithography (NIL) and metal-catalyzed electroless etching (MCEE), enabling near perfectly ordered Si nanostructure arrays of user-defined patterns to be controllably and rapidly generated on a wafer scale. Periodic features possessing circular, hexagonal, and rectangular cross-sections with lateral dimensions down to sub-50 nm, in hexagonal or square array configurations and high array packing densities up to 5.13 × 107 structures/mm2 not achievable by conventional UV photolithography are fabricated using this top-down approach. By suitably tuning the duration of catalytic etching, variable aspect ratio Si nanostructures can be formed. As the etched Si pattern depends largely on the NIL mould which is patterned by electron beam lithography (EBL), the technique can be used to form patterns not possible with self-assembly methods, nanosphere, and interference lithography for replication on a wafer scale. Good chemical resistance of the nanoimprinted mask and adhesion to the Si substrate facilitate good pattern transfer and preserve the smooth top surface morphology of the Si nanostructures as shown in TEM. This approach is suitable for generating Si nanostructures of controlled dimensions and patterns, with high aspect ratio on a wafer level suitable for semiconductor device production.

  20. Wafer-scale fabrication and growth dynamics of suspended graphene nanoribbon arrays

    PubMed Central

    Suzuki, Hiroo; Kaneko, Toshiro; Shibuta, Yasushi; Ohno, Munekazu; Maekawa, Yuki; Kato, Toshiaki

    2016-01-01

    Adding a mechanical degree of freedom to the electrical and optical properties of atomically thin materials can provide an excellent platform to investigate various optoelectrical physics and devices with mechanical motion interaction. The large scale fabrication of such atomically thin materials with suspended structures remains a challenge. Here we demonstrate the wafer-scale bottom–up synthesis of suspended graphene nanoribbon arrays (over 1,000,000 graphene nanoribbons in 2 × 2 cm2 substrate) with a very high yield (over 98%). Polarized Raman measurements reveal graphene nanoribbons in the array can have relatively uniform-edge structures with near zigzag orientation dominant. A promising growth model of suspended graphene nanoribbons is also established through a comprehensive study that combined experiments, molecular dynamics simulations and theoretical calculations with a phase-diagram analysis. We believe that our results can contribute to pushing the study of graphene nanoribbons into a new stage related to the optoelectrical physics and industrial applications. PMID:27250877

  1. Wafer-Scale Monolayer Films of Semiconducting Metal Dichalcogenides for High-Performance Electronics

    NASA Astrophysics Data System (ADS)

    Xie, Saien; Kang, Kibum; Huang, Lujie; Han, Yimo; Huang, Pinshane; Mak, Kin Fai; Kim, Cheol-Joo; Muller, David; Park, Jiwoong

    2015-03-01

    Two-dimensional semiconducting transition metal dichalcogenides (TMDs) have shown their potential in electronics, optoelectronic and valleytronis. However, large-scale growth methods reported to date have only produced materials with limited structural and electrical uniformity, hindering further technological applications. Here we present a 4-inch scale growth of continuous monolayer molybdenum disulfide (MoS2) and tungsten disulfide (WS2) films that show excellent structural and electrical uniformity over the entire wafer using metal-organic chemical vapor deposition. The resulting monolayer films show high mobility of 30 cm2/Vs at room temperature, as well as the phonon-limited transport for MoS2, regardless of the channel length and device location. They allow for the batch fabrication of monolayer MoS2 field effect transistors with a 99% yield, which display spatially-uniform n-type transistor operation with a high on/off ratio. We further demonstrate the multi-level growth and fabrication of vertically-stacked monolayer MoS2 films and devices, which could enable the development of novel three-dimensional circuitry and device integration.

  2. Resolution enhancement using plasmonic metamask for wafer-scale photolithography in the far field

    PubMed Central

    Baek, Seunghwa; Kang, Gumin; Kang, Min; Lee, Chang-Won; Kim, Kyoungsik

    2016-01-01

    Resolution enhancement in far-field photolithography is demonstrated using a plasmonic metamask in the proximity regime, in which Fresnel diffraction is dominant. The transverse magnetic component of the diffracted wave from the photomask, which reduces the pattern visibility and lowers the resolution, was successfully controlled by coupling with the anti-symmetric mode of the excited surface plasmon. We obtained a consistently finely-patterned photoresist surface at a distance of up to 15 μm from the mask surface for 3-μm-pitch slits because of conserved field visibility when propagating from the near-field to the proximity regime. We confirmed that sharp edge patterning is indeed possible when using a wafer-scale photomask in the proximity photolithography regime. Our plasmonic metamask method produces cost savings for ultra-large-scale high-density display fabrication by maintaining longer photomask lifetimes and by allowing sufficient tolerance for the distance between the photomask and the photoresist. PMID:27457127

  3. Wafer-scale high-resolution patterning of reduced graphene oxide films for detection of low concentration biomarkers in plasma.

    PubMed

    Kim, Jinsik; Chae, Myung-Sic; Lee, Sung Min; Jeong, Dahye; Lee, Byung Chul; Lee, Jeong Hoon; Kim, YoungSoo; Chang, Suk Tai; Hwang, Kyo Seon

    2016-01-01

    Given that reduced graphene oxide (rGO)-based biosensors allow disposable and repeatable biomarker detection at the point of care, we developed a wafer-scale rGO patterning method with mass productivity, uniformity, and high resolution by conventional micro-electro-mechanical systems (MEMS) techniques. Various rGO patterns were demonstrated with dimensions ranging from 5 μm up to several hundred μm. Manufacture of these patterns was accomplished through the optimization of dry etching conditions. The axis-homogeneity and uniformity were also measured to verify the uniform patternability in 4-inch wafer with dry etching. Over 66.2% of uniform rGO patterns, which have deviation of resistance within range of ±10%, formed the entire wafer. We selected amyloid beta (Aβ) peptides in the plasma of APP/PS1 transgenic mice as a study model and measured the peptide level by resistance changes of highly uniform rGO biosensor arrays. Aβ is a pathological hallmark of Alzheimer's disease and its plasma concentration is in the pg mL(-1) range. The sensor detected the Aβ peptides with ultra-high sensitivity; the LOD was at levels as low as 100 fg mL(-1). Our results provide biological evidences that this wafer-scale high-resolution patterning method can be used in rGO-based electrical diagnostic devices for detection of low-level protein biomarkers in biofluids. PMID:27506288

  4. Wafer-scale high-resolution patterning of reduced graphene oxide films for detection of low concentration biomarkers in plasma

    PubMed Central

    Kim, Jinsik; Chae, Myung-Sic; Lee, Sung Min; Jeong, Dahye; Lee, Byung Chul; Lee, Jeong Hoon; Kim, YoungSoo; Chang, Suk Tai; Hwang, Kyo Seon

    2016-01-01

    Given that reduced graphene oxide (rGO)-based biosensors allow disposable and repeatable biomarker detection at the point of care, we developed a wafer-scale rGO patterning method with mass productivity, uniformity, and high resolution by conventional micro-electro-mechanical systems (MEMS) techniques. Various rGO patterns were demonstrated with dimensions ranging from 5 μm up to several hundred μm. Manufacture of these patterns was accomplished through the optimization of dry etching conditions. The axis-homogeneity and uniformity were also measured to verify the uniform patternability in 4-inch wafer with dry etching. Over 66.2% of uniform rGO patterns, which have deviation of resistance within range of ±10%, formed the entire wafer. We selected amyloid beta (Aβ) peptides in the plasma of APP/PS1 transgenic mice as a study model and measured the peptide level by resistance changes of highly uniform rGO biosensor arrays. Aβ is a pathological hallmark of Alzheimer’s disease and its plasma concentration is in the pg mL−1 range. The sensor detected the Aβ peptides with ultra-high sensitivity; the LOD was at levels as low as 100 fg mL−1. Our results provide biological evidences that this wafer-scale high-resolution patterning method can be used in rGO-based electrical diagnostic devices for detection of low-level protein biomarkers in biofluids. PMID:27506288

  5. Wafer-scale high-resolution patterning of reduced graphene oxide films for detection of low concentration biomarkers in plasma

    NASA Astrophysics Data System (ADS)

    Kim, Jinsik; Chae, Myung-Sic; Lee, Sung Min; Jeong, Dahye; Lee, Byung Chul; Lee, Jeong Hoon; Kim, Youngsoo; Chang, Suk Tai; Hwang, Kyo Seon

    2016-08-01

    Given that reduced graphene oxide (rGO)-based biosensors allow disposable and repeatable biomarker detection at the point of care, we developed a wafer-scale rGO patterning method with mass productivity, uniformity, and high resolution by conventional micro-electro-mechanical systems (MEMS) techniques. Various rGO patterns were demonstrated with dimensions ranging from 5 μm up to several hundred μm. Manufacture of these patterns was accomplished through the optimization of dry etching conditions. The axis-homogeneity and uniformity were also measured to verify the uniform patternability in 4-inch wafer with dry etching. Over 66.2% of uniform rGO patterns, which have deviation of resistance within range of ±10%, formed the entire wafer. We selected amyloid beta (Aβ) peptides in the plasma of APP/PS1 transgenic mice as a study model and measured the peptide level by resistance changes of highly uniform rGO biosensor arrays. Aβ is a pathological hallmark of Alzheimer’s disease and its plasma concentration is in the pg mL‑1 range. The sensor detected the Aβ peptides with ultra-high sensitivity; the LOD was at levels as low as 100 fg mL‑1. Our results provide biological evidences that this wafer-scale high-resolution patterning method can be used in rGO-based electrical diagnostic devices for detection of low-level protein biomarkers in biofluids.

  6. Wafer-scale design of lightweight and transparent electronics that wraps around hairs

    NASA Astrophysics Data System (ADS)

    Salvatore, Giovanni A.; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

    2014-01-01

    Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

  7. Wafer-scale synthesis of multi-layer graphene by high-temperature carbon ion implantation

    SciTech Connect

    Kim, Janghyuk; Lee, Geonyeop; Kim, Jihyun

    2015-07-20

    We report on the synthesis of wafer-scale (4 in. in diameter) high-quality multi-layer graphene using high-temperature carbon ion implantation on thin Ni films on a substrate of SiO{sub 2}/Si. Carbon ions were bombarded at 20 keV and a dose of 1 × 10{sup 15 }cm{sup −2} onto the surface of the Ni/SiO{sub 2}/Si substrate at a temperature of 500 °C. This was followed by high-temperature activation annealing (600–900 °C) to form a sp{sup 2}-bonded honeycomb structure. The effects of post-implantation activation annealing conditions were systematically investigated by micro-Raman spectroscopy and transmission electron microscopy. Carbon ion implantation at elevated temperatures allowed a lower activation annealing temperature for fabricating large-area graphene. Our results indicate that carbon-ion implantation provides a facile and direct route for integrating graphene with Si microelectronics.

  8. Wafer-scale highly-transparent and superhydrophilic sapphires for high-performance optics.

    PubMed

    Leem, Jung Woo; Yu, Jae Su

    2012-11-19

    We reported the wafer-scale highly-transparent and superhydrophilic sapphires with antireflective subwavelength structures (SWSs) which were fabricated by dry etching using thermally dewetted gold (Au) nanomasks. Their optical transmittance properties were experimentally and theoretically investigated. The density, size, and period of the thermally dewetted Au nanopatterns can be controlled by the Au film thickness. For the sapphire with both-side SWSs at 5 nm of Au film, the average total transmittance (T(avg)) of ~96.5% at 350-800 nm was obtained, indicating a higher value than those of the flat sapphire (T(avg)~85.6%) and the sapphire with one-side SWSs (T(avg)~91%), and the less angle-dependent transmittance property was observed. The calculated transmittance results also showed a similar tendency to the measured data. The SWSs enhanced significantly the surface hydrophilicity of sapphires, exhibiting a water contact angle (θ(c)) of < 5° for Au film of 5 nm compared to θ(c)~37° of the flat sapphire. PMID:23187471

  9. Surface plasmon assisted hot electron collection in wafer-scale metallic-semiconductor photonic crystals.

    PubMed

    Chou, Jeffrey B; Li, Xin-Hao; Wang, Yu; Fenning, David P; Elfaer, Asmaa; Viegas, Jaime; Jouiad, Mustapha; Shao-Horn, Yang; Kim, Sang-Gook

    2016-09-01

    Plasmon assisted photoelectric hot electron collection in a metal-semiconductor junction can allow for sub-bandgap optical to electrical energy conversion. Here we report hot electron collection by wafer-scale Au/TiO2 metallic-semiconductor photonic crystals (MSPhC), with a broadband photoresponse below the bandgap of TiO2. Multiple absorption modes supported by the 2D nano-cavity structure of the MSPhC extend the photon-metal interaction time and fulfill a broadband light absorption. The surface plasmon absorption mode provides access to enhanced electric field oscillation and hot electron generation at the interface between Au and TiO2. A broadband sub-bandgap photoresponse centered at 590 nm was achieved due to surface plasmon absorption. Gold nanorods were deposited on the surface of MSPhC to study localized surface plasmon (LSP) mode absorption and subsequent injection to the TiO2 catalyst at different wavelengths. Applications of these results could lead to low-cost and robust photo-electrochemical applications such as more efficient solar water splitting.

  10. Wafer-scale highly-transparent and superhydrophilic sapphires for high-performance optics.

    PubMed

    Leem, Jung Woo; Yu, Jae Su

    2012-11-19

    We reported the wafer-scale highly-transparent and superhydrophilic sapphires with antireflective subwavelength structures (SWSs) which were fabricated by dry etching using thermally dewetted gold (Au) nanomasks. Their optical transmittance properties were experimentally and theoretically investigated. The density, size, and period of the thermally dewetted Au nanopatterns can be controlled by the Au film thickness. For the sapphire with both-side SWSs at 5 nm of Au film, the average total transmittance (T(avg)) of ~96.5% at 350-800 nm was obtained, indicating a higher value than those of the flat sapphire (T(avg)~85.6%) and the sapphire with one-side SWSs (T(avg)~91%), and the less angle-dependent transmittance property was observed. The calculated transmittance results also showed a similar tendency to the measured data. The SWSs enhanced significantly the surface hydrophilicity of sapphires, exhibiting a water contact angle (θ(c)) of < 5° for Au film of 5 nm compared to θ(c)~37° of the flat sapphire.

  11. A wafer-scale graphene and ferroelectric multilayer for flexible and fast-switched modulation applications.

    PubMed

    Zhu, Minmin; Wu, Jing; Du, Zehui; Tay, Roland Yingjie; Li, Hongling; Özyilmaz, Barbarous; Teo, Edwin Hang Tong

    2015-09-21

    Here we report a wafer-scale graphene/P(VDF-TrFE)/graphene multilayer for light-weight, flexible and fast-switched broadband modulation applications. The P(VDF-TrFE) film not only significantly reduces the sheet resistance of graphene throughout heavy doping of ∼0.8 × 10(13) cm(-2) by nonvolatile ferroelectric dipoles, but also acts as an efficient electro-optic (EO) layer. Such multilayered structural integration with remarkable ferroelectric polarization, high transparency (>90%), low sheet resistance (∼302 Ω□(-1)), and excellent mechanic flexibility shows the potential of a flexible modulation application over a broad range of wavelengths. Moreover, the derived device also exhibits strong field-induced EO modulation even under bending and one large Pockels coefficient (∼54.3 pm V(-1)) is obtained. Finally, the graphene and ferroelectric hybrid demonstrates a fast switching time (∼2 μs) and works well below low sheet resistance level over a long time. This work gives insights into the potential of graphene and ferroelectric hybrid structures, enabling future exploration on next-generation high-performance, flexible transparent electronics and photonics.

  12. Wafer-scale self-organized InP nanopillars with controlled orientation for photovoltaic devices.

    PubMed

    Sanatinia, Reza; Berrier, Audrey; Dhaka, Veer; Perros, Alexander P; Huhtio, Teppo; Lipsanen, Harri; Anand, Srinivasan

    2015-10-16

    A unique wafer-scale self-organization process for generation of InP nanopillars is demonstrated, which is based on maskless ion-beam etching (IBE) of InP developed to obtain the nanopillars, where the height, shape, and orientation of the nanopillars can be varied by controlling the processing parameters. The fabricated InP nanopillars exhibit broadband suppression of the reflectance, 'black InP,' a property useful for solar cells. The realization of a conformal p-n junction for carrier collection, in the fabricated solar cells, is achieved by a metalorganic vapor phase epitaxy (MOVPE) overgrowth step on the fabricated pillars. The conformal overgrowth retains the broadband anti-reflection property of the InP nanopillars, indicating the feasibility of this technology for solar cells. Surface passivation of the formed InP nanopillars using sulfur-oleylamine solution resulted in improved solar-cell characteristics. An open-circuit voltage of 0.71 V and an increase of 0.13 V compared to the unpassivated device were achieved. PMID:26403979

  13. Surface plasmon assisted hot electron collection in wafer-scale metallic-semiconductor photonic crystals.

    PubMed

    Chou, Jeffrey B; Li, Xin-Hao; Wang, Yu; Fenning, David P; Elfaer, Asmaa; Viegas, Jaime; Jouiad, Mustapha; Shao-Horn, Yang; Kim, Sang-Gook

    2016-09-01

    Plasmon assisted photoelectric hot electron collection in a metal-semiconductor junction can allow for sub-bandgap optical to electrical energy conversion. Here we report hot electron collection by wafer-scale Au/TiO2 metallic-semiconductor photonic crystals (MSPhC), with a broadband photoresponse below the bandgap of TiO2. Multiple absorption modes supported by the 2D nano-cavity structure of the MSPhC extend the photon-metal interaction time and fulfill a broadband light absorption. The surface plasmon absorption mode provides access to enhanced electric field oscillation and hot electron generation at the interface between Au and TiO2. A broadband sub-bandgap photoresponse centered at 590 nm was achieved due to surface plasmon absorption. Gold nanorods were deposited on the surface of MSPhC to study localized surface plasmon (LSP) mode absorption and subsequent injection to the TiO2 catalyst at different wavelengths. Applications of these results could lead to low-cost and robust photo-electrochemical applications such as more efficient solar water splitting. PMID:27607726

  14. Wafer-scale synthesis of single-crystal zigzag silicon nanowire arrays with controlled turning angles.

    PubMed

    Chen, Huan; Wang, Hui; Zhang, Xiao-Hong; Lee, Chun-Sing; Lee, Shuit-Tong

    2010-03-10

    Silicon nanowires (SiNWs) having curved structures may have unique advantages in device fabrication. However, no methods are available to prepare curved SiNWs controllably. In this work, we report the preparation of three types of single-crystal SiNWs with various turning angles via metal-assisted chemical etching using (111)-oriented silicon wafers near room temperature. The zigzag SiNWs are single crystals and can be p- or n-doped using corresponding Si wafer as substrate. The controlled growth direction is attributed to the preferred movement of Ag nanoparticles along 001 and other directions in Si wafer. Our results demonstrate that metal-assisted chemical etching may be a viable approach to fabricate SiNWs with desired turning angles by utilizing the various crystalline directions in a Si wafer.

  15. Field-effect transistors based on wafer-scale, highly uniform few-layer p-type WSe2

    NASA Astrophysics Data System (ADS)

    Campbell, Philip M.; Tarasov, Alexey; Joiner, Corey A.; Tsai, Meng-Yen; Pavlidis, Georges; Graham, Samuel; Ready, W. Jud; Vogel, Eric M.

    2016-01-01

    The synthesis of few-layer tungsten diselenide (WSe2) via chemical vapor deposition typically results in highly non-uniform thickness due to nucleation initiated growth of triangular domains. In this work, few-layer p-type WSe2 with wafer-scale thickness and electrical uniformity is synthesized through direct selenization of thin films of e-beam evaporated W on SiO2 substrates. Raman maps over a large area of the substrate show small variations in the main peak position, indicating excellent thickness uniformity across several square centimeters. Additionally, field-effect transistors fabricated from the wafer-scale WSe2 films demonstrate uniform electrical performance across the substrate. The intrinsic field-effect mobility of the films at a carrier concentration of 3 × 1012 cm-2 is 10 cm2 V-1 s-1. The unprecedented uniformity of the WSe2 on wafer-scale substrates provides a substantial step towards producing manufacturable materials that are compatible with conventional semiconductor fabrication processes.

  16. Field-effect transistors based on wafer-scale, highly uniform few-layer p-type WSe2.

    PubMed

    Campbell, Philip M; Tarasov, Alexey; Joiner, Corey A; Tsai, Meng-Yen; Pavlidis, Georges; Graham, Samuel; Ready, W Jud; Vogel, Eric M

    2016-01-28

    The synthesis of few-layer tungsten diselenide (WSe2) via chemical vapor deposition typically results in highly non-uniform thickness due to nucleation initiated growth of triangular domains. In this work, few-layer p-type WSe2 with wafer-scale thickness and electrical uniformity is synthesized through direct selenization of thin films of e-beam evaporated W on SiO2 substrates. Raman maps over a large area of the substrate show small variations in the main peak position, indicating excellent thickness uniformity across several square centimeters. Additionally, field-effect transistors fabricated from the wafer-scale WSe2 films demonstrate uniform electrical performance across the substrate. The intrinsic field-effect mobility of the films at a carrier concentration of 3 × 10(12) cm(-2) is 10 cm(2) V(-1) s(-1). The unprecedented uniformity of the WSe2 on wafer-scale substrates provides a substantial step towards producing manufacturable materials that are compatible with conventional semiconductor fabrication processes. PMID:26743173

  17. Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

    SciTech Connect

    Kim, SangHyeon E-mail: sh-kim@kist.re.kr; Ikku, Yuki; Takenaka, Mitsuru; Takagi, Shinichi; Yokoyama, Masafumi; Nakane, Ryosho; Li, Jian; Kao, Yung-Chung

    2014-07-28

    Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm{sup 2}/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

  18. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    NASA Astrophysics Data System (ADS)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  19. Inspection strategy for LIGA microstructures using a programmable optical microscope.

    SciTech Connect

    Kurfess, Thomas R; Aigeldinger, Georg; Ceremuga, Joseph T.

    2004-07-01

    The LIGA process has the ability to fabricate very precise, high aspect ratio mesoscale structures with microscale features [l]. The process consists of multiple steps before a final part is produced. Materials native to the LIGA process include metals and photoresists. These structures are routinely measured for quality control and process improvement. However, metrology of LIGA structures is challenging because of their high aspect ratio and edge topography. For the scale of LIGA structures, a programmable optical microscope is well suited for lateral (XU) critical dimension measurements. Using grayscale gradient image processing with sub-pixel interpolation, edges are detected and measurements are performed. As with any measurement, understanding measurement uncertainty is necessary so that appropriate conclusions are drawn from the data. Therefore, the abilities of the inspection tool and the obstacles presented by the structures under inspection should be well understood so that precision may be quantified. This report presents an inspection method for LIGA microstructures including a comprehensive assessment of the uncertainty for each inspection scenario.

  20. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking

    PubMed Central

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-01-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process. PMID:22400126

  1. Stationary Optical Concentrator Designs and Wafer Scale Monolithic Integration of Semiconductor Devices for Next Generation Photovoltaic Panels

    NASA Astrophysics Data System (ADS)

    Kim, Jung Min

    A major barrier in utilizing solar energy for large scale deployment is the cost of the photovoltaic (PV) systems. Several approaches have been used for the cost reduction such as by modifying PV system designs in addition to enhancing the efficiency of solar cells. Due to the high cost of materials, minimizing the use of solar cells such as in concentrator type systems is highly attractive for reducing the cost of the PV modules by focusing the incident light onto the PV cell. However concentrator PV systems (CPV) require constant tracking of the sun and hence are complex in design and expensive to operate, except in limited situations such as large scale PV power plants. It is desirable to design new concentrator type systems that do not require continuous tracking of the sun. These systems could ultimately reduce the PV system cost to a minimum while maximizing the power conversion efficiency. In this thesis we propose a simple design for a stationary concentrator photovoltaic (SCPV) system that could significantly reduce the cost of generating electricity using PV devices. Using optical ray tracing simulations, we have been able to design SCPV systems that could reduce the PV module cost by 2--10 times without compromising on the power conversion efficiency of the system. Another alternative approach for sustainable high efficiency PV system design is to develop low cost PV cells for terrestrial applications. To meet the demands of low cost and large scale production, larger and thinner (or flexible) substrates are required. We demonstrated the feasibility of fabricating monolithic interconnected PV devices at the wafer scale (2 inch wafers). In this study, GaSb PV cells grown on semi-insulating GaAs were used as the model material. Crucial device fabrication steps such as a selective etching process have been developed that is necessary for isolating individual devices on the wafer and interconnecting them with sub-micron scale accuracy. Selective etching of

  2. Wafer scale fabrication of highly dense and uniform array of sub-5 nm nanogaps for surface enhanced Raman scatting substrates.

    PubMed

    Cai, Hongbing; Wu, YuKun; Dai, Yanmeng; Pan, Nan; Tian, Yangchao; Luo, Yi; Wang, Xiaoping

    2016-09-01

    Metallic nanogap is very important for a verity of applications in plasmonics. Although several fabrication techniques have been proposed in the last decades, it is still a challenge to produce uniform nanogaps with a few nanometers gap distance and high throughput. Here we present a simple, yet robust method based on the atomic layer deposition (ALD) and lift-off technique for patterning ultranarrow nanogaps array. The ability to accurately control the thickness of the ALD spacer layer enables us to precisely define the gap size, down to sub-5 nm scale. Moreover, this new method allows to fabricate uniform nanogaps array along different directions densely arranged on the wafer-scale substrate. It is demonstrated that the fabricated array can be used as an excellent substrate for surface enhanced Raman scatting (SERS) measurements of molecules, even on flexible substrates. This uniform nanogaps array would also find its applications for the trace detection and biosensors. PMID:27607684

  3. Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

    NASA Astrophysics Data System (ADS)

    Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

    2014-02-01

    Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

  4. Highly Transparent Wafer-Scale Synthesis of Crystalline WS2 Nanoparticle Thin Film for Photodetector and Humidity-Sensing Applications.

    PubMed

    Pawbake, Amit S; Waykar, Ravindra G; Late, Dattatray J; Jadkar, Sandesh R

    2016-02-10

    In the present investigation, we report a one-step synthesis method of wafer-scale highly crystalline tungsten disulfide (WS2) nanoparticle thin film by using a modified hot wire chemical vapor deposition (HW-CVD) technique. The average size of WS2 nanoparticle is found to be 25-40 nm over an entire 4 in. wafer of quartz substrate. The low-angle XRD data of WS2 nanoparticle shows the highly crystalline nature of sample along with orientation (002) direction. Furthermore, Raman spectroscopy shows two prominent phonon vibration modes of E(1)2g and A1g at ∼356 and ∼420 cm(-1), respectively, indicating high purity of material. The TEM analysis shows good crystalline quality of sample. The synthesized WS2 nanoparticle thin film based device shows good response to humidity and good photosensitivity along with good long-term stability of the device. It was found that the resistance of the films decreases with increasing relative humidity (RH). The maximum humidity sensitivity of 469% along with response time of ∼12 s and recovery time of ∼13 s were observed for the WS2 thin film humidity sensor device. In the case of photodetection, the response time of ∼51 s and recovery time of ∼88 s were observed with sensitivity ∼137% under white light illumination. Our results open up several avenues to grow other transition metal dichalcogenide nanoparticle thin film for large-area nanoelectronics as well as industrial applications. PMID:26771049

  5. Wafer-scale, conformal and direct growth of MoS2 thin films by atomic layer deposition

    NASA Astrophysics Data System (ADS)

    Jang, Yujin; Yeo, Seungmin; Lee, Han-Bo-Ram; Kim, Hyungjun; Kim, Soo-Hyun

    2016-03-01

    Molybdenum disulfide (MoS2) thin films were grown directly on SiO2 covered wafers by atomic layer deposition (ALD) at the deposition temperatures ranging from 175 to 225 °C using molybdenum hexacarbonyl [Mo(CO)6] and H2S plasma as the precursor and reactant, respectively. Self-limited film growth on the thermally-grown SiO2 substrate was observed with both the precursor and reactant pulsing time. The growth rate was ∼0.05 nm/cycle and a short incubation cycle of around 13 was observed at a deposition temperature of 175 °C. The MoS2 films formed nanocrystalline microstructure with a hexagonal crystal system (2H-MoS2), which was confirmed by X-ray diffraction and transmission electron microscopy. Single crystal MoS2 nanosheets, ∼20 nm in size, were fabricated by controlling the number of ALD cycles. The ALD-MoS2 thin films exhibited good stoichiometry with negligible C impurities, approximately 0.1 at.% from Rutherford backscattering spectrometry (RBS). X-ray photoelectron spectroscopy confirmed the formation of chemical bonding from MoS2. The step coverage of ALD-MoS2 was approximately 75% at a 100 nm sized trench. Overall, the ALD-MoS2 process made uniform deposition possible on the wafer-scale (4 in. in diameter).

  6. Modeling electrodeposition for LIGA microdevice fabrication

    SciTech Connect

    Griffiths, S.K.; Nilson, R.H.; Bradshaw, R.W.

    1998-02-01

    To better understand and to help optimize the electroforming portion of the LIGA process, we have developed one and two-dimensional numerical models describing electrode-position of metal into high aspect-ratio molds. The one-dimensional model addresses dissociation, diffusion, electromigration, and deposition of multiple ion species. The two-dimensional model is limited to a single species, but includes transport induced by forced flow of electrolyte outside the mold and by buoyancy associated with metal ion depletion within the mold. To guide model development and to validate these models, we have also conducted a series of laboratory experiments using a sulfamate bath to deposit nickel in cylindrical molds having aspect ratios up to twenty-five. The experimental results indicate that current densities well in excess of the diffusion-limited currents may still yield metal deposits of acceptable morphology. However, the numerical models demonstrate that such large ion fluxes cannot be sustained by convection within the mold resulting from flow across the mold top. Instead, calculations suggest that the observed enhancement of transport probably results from natural convection within the molds, and that buoyancy-driven flows may be critical to metal ion transport even in micron-scale features having very large aspect ratios. Taking advantage of this enhanced ion transport may allow order-of-magnitude reductions in electroforming times for LIGA microdevice fabrication. 42 refs., 14 figs., 1 tab.

  7. C- and L-band erbium-doped waveguide lasers with wafer-scale silicon nitride cavities.

    PubMed

    Purnawirman; Sun, J; Adam, T N; Leake, G; Coolbaugh, D; Bradley, J D B; Shah Hosseini, E; Watts, M R

    2013-06-01

    We report on integrated erbium-doped waveguide lasers designed for silicon photonic systems. The distributed Bragg reflector laser cavities consist of silicon nitride waveguide and grating features defined by wafer-scale immersion lithography and a top erbium-doped aluminum oxide layer deposited as the final step in the fabrication process. The resulting inverted ridge waveguide yields high optical intensity overlap with the active medium for both the 0.98 μm pump (89%) and 1.5 μm laser (87%) wavelengths with a pump-laser intensity overlap of >93%. We obtain output powers of up to 5 mW and show lasing at widely spaced wavelengths within both the C and L bands of the erbium gain spectrum (1536, 1561, and 1596 nm).

  8. Wafer-level-scale package of MEMS device by eutectic bonding method

    NASA Astrophysics Data System (ADS)

    Chen, Sihai; Ma, Hong; Chen, Mingxiang; Xiong, Tao; Liu, Sheng; Yi, Xinjian

    2003-12-01

    This paper reports the preliminary results for an on-going program in wafer-level MEMS package. In this particular paper, three closed-loop microheaters of 5μm, 7μm and 9μm width were designed. By reactive ion sputtering technique, two classes of samples were presented. The first one was first co-sputtered with nickel / chromium (Ni/Cr) alloy and then sputtered with gold(Au) metal as heating material; the second one was sputtered with Cr, tin (Sn) and Au respectively as heating material. The bonding of the former sample based on the Ni/Cr and Au heating material failed. The eutectic bonding experiment of the later sample based on the Cr, Sn and Au heating material by global heating method was completed in annealing oven at temperature of about 400 for 20 minutes. The SEM testing result showed the eutectic bonding of Au-Sn by global heating was successful. More results will be reported in future.

  9. Wafer-level scale package of MEMS device by eutectic bonding method

    NASA Astrophysics Data System (ADS)

    Chen, Sihai; Ma, Hong; Chen, Mingxiang; Xiong, Tao; Liu, Sheng; Yi, Xinjian

    2004-01-01

    This paper reports the preliminary results for an on-going program in wafer-level MEMS package. In this particular paper, three closed-loop microheaters of 5μm, 7μm and 9μm width were designed. By reactive ion sputtering technique, two classes of samples were presented. The first one was first co-sputtered with nickel / chromium (Ni/Cr) alloy and then sputtered with gold(Au) metal as heating material; the second one was sputtered with Cr, tin (Sn) and Au respectively as heating material. The bonding of the former sample based on the Ni/Cr and Au heating material failed. The eutectic bonding experiment of the later sample based on the Cr, Sn and Au heating material by global heating method was completed in annealing oven at temperature of about 400 deg. C. for 20 minutes. The SEM testing result showed the eutectic bonding of Au-Sn by global heating was successful. More results will be reported in future.

  10. Self-Aligned Multichannel Graphene Nanoribbon Transistor Arrays Fabricated at Wafer Scale.

    PubMed

    Jeong, Seong-Jun; Jo, Sanghyun; Lee, Jooho; Yang, Kiyeon; Lee, Hyangsook; Lee, Chang-Seok; Park, Heesoon; Park, Seongjun

    2016-09-14

    We present a novel method for fabricating large-area field-effect transistors (FETs) based on densely packed multichannel graphene nanoribbon (GNR) arrays using advanced direct self-assembly (DSA) nanolithography. The design of our strategy focused on the efficient integration of the FET channel and using fab-compatible processes such as thermal annealing and chemical vapor deposition. We achieved linearly stacked DSA nanopattern arrays with sub-10 nm half-pitch critical dimensions (CD) by controlling the thickness of topographic Au confinement patterns. Excellent roughness values (∼10% of CD) were obtained, demonstrating the feasibility of integrating sub-10 nm GNRs into commercial semiconductor processes. Based on this facile process, FETs with such densely packed multichannel GNR arrays were successfully fabricated on 6 in. silicon wafers. With these high-quality GNR arrays, we achieved FETs showing the highest performance reported to date (an on-to-off ratio larger than 10(2)) for similar devices produced using conventional photolithography and block-copolymer lithography.

  11. Erasable diffractive grating couplers in silicon on insulator for wafer scale testing

    NASA Astrophysics Data System (ADS)

    Topley, R.; Martinez-Jimenez, G.; O'Faolain, L.; Healy, N.; Mailis, S.; Thomson, D. J.; Gardes, F. Y.; Peacock, A. C.; Payne, D. N. R.; Mashanovich, G. Z.; Reed, G. T.

    2014-03-01

    Test points are essential in allowing optical circuits on a wafer to be autonomously tested after selected manufacturing steps, hence allowing poor performance or device failures to be detected early and to be either repaired using direct write methods, or a cessation of further processing to reduce fabrication costs. Grating couplers are a commonly used method for efficiently coupling light from an optical fibre to a silicon waveguide. They are relatively easy to fabricate and they allow light to be coupled into/out from any location on the device without the need for polishing, making them good candidates for an optical test point. A fixed test point can be added for this purpose, although traditionally these grating devices are fabricated by etching the silicon waveguide, and hence this permanently adds loss and leads to a poor performing device when placed into use after testing. We demonstrate a similar device utilising a refractive index change induced by lattice disorder. Raman data collected suggests this lattice damage is reversible, allowing a laser to subsequently erase the grating coupler.

  12. Self-Aligned Multichannel Graphene Nanoribbon Transistor Arrays Fabricated at Wafer Scale.

    PubMed

    Jeong, Seong-Jun; Jo, Sanghyun; Lee, Jooho; Yang, Kiyeon; Lee, Hyangsook; Lee, Chang-Seok; Park, Heesoon; Park, Seongjun

    2016-09-14

    We present a novel method for fabricating large-area field-effect transistors (FETs) based on densely packed multichannel graphene nanoribbon (GNR) arrays using advanced direct self-assembly (DSA) nanolithography. The design of our strategy focused on the efficient integration of the FET channel and using fab-compatible processes such as thermal annealing and chemical vapor deposition. We achieved linearly stacked DSA nanopattern arrays with sub-10 nm half-pitch critical dimensions (CD) by controlling the thickness of topographic Au confinement patterns. Excellent roughness values (∼10% of CD) were obtained, demonstrating the feasibility of integrating sub-10 nm GNRs into commercial semiconductor processes. Based on this facile process, FETs with such densely packed multichannel GNR arrays were successfully fabricated on 6 in. silicon wafers. With these high-quality GNR arrays, we achieved FETs showing the highest performance reported to date (an on-to-off ratio larger than 10(2)) for similar devices produced using conventional photolithography and block-copolymer lithography. PMID:27532894

  13. Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

    PubMed Central

    Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

    2016-01-01

    The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

  14. Fabrication of miniaturized electrostatic deflectors using LIGA

    SciTech Connect

    Jackson, K.H.; Khan-Malek, C.; Muray, L.P.

    1997-04-01

    Miniaturized electron beam columns ({open_quotes}microcolumns{close_quotes}) have been demonstrated to be suitable candidates for scanning electron microscopy (SEM), e-beam lithography and other high resolution, low voltage applications. In the present technology, microcolumns consist of {open_quotes}selectively scaled{close_quotes} micro-sized lenses and apertures, fabricated from silicon membranes with e-beam lithography, reactive ion beam etching and other semiconductor thin-film techniques. These miniaturized electron-optical elements provide significant advantages over conventional optics in performance and ease of fabrication. Since lens aberrations scale roughly with size, it is possible to fabricate simple microcolumns with extremely high brightness sources and electrostatic objective lenses, with resolution and beam current comparable to conventional e-beam columns. Moreover since microcolumns typically operate at low voltages (1 KeV), the proximity effects encountered in e-beam lithography become negligible. For high throughput applications, batch fabrication methods may be used to build large parallel arrays of microcolumns. To date, the best reported performance with a 1 keV cold field emission cathode, is 30 nm resolution at a working distance of 2mm in a 3.5mm column. Fabrication of the microcolumn deflector and stigmator, however, have remained beyond the capabilities of conventional machining operations and semiconductor processing technology. This work examines the LIGA process as a superior alternative to fabrication of the deflectors, especially in terms of degree of miniaturization, dimensional control, placement accuracy, run-out, facet smoothness and choice of suitable materials. LIGA is a combination of deep X-ray lithography, electroplating, and injection molding processes which allow the fabrication of microstructures.

  15. Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics.

    PubMed

    Heo, Jinseong; Byun, Kyung-Eun; Lee, Jaeho; Chung, Hyun-Jong; Jeon, Sanghun; Park, Seongjun; Hwang, Sungwoo

    2013-01-01

    Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.

  16. Integration of hexagonal boron nitride with quasi-freestanding epitaxial graphene: toward wafer-scale, high-performance devices.

    PubMed

    Bresnehan, Michael S; Hollander, Matthew J; Wetherington, Maxwell; LaBella, Michael; Trumbull, Kathleen A; Cavalero, Randal; Snyder, David W; Robinson, Joshua A

    2012-06-26

    Hexagonal boron nitride (h-BN) is a promising dielectric material for graphene-based electronic devices. Here we investigate the potential of h-BN gate dielectrics, grown by chemical vapor deposition (CVD), for integration with quasi-freestanding epitaxial graphene (QFEG). We discuss the large scale growth of h-BN on copper foil via a catalytic thermal CVD process and the subsequent transfer of h-BN to a 75 mm QFEG wafer. X-ray photoelectron spectroscopy (XPS) measurements confirm the absence of h-BN/graphitic domains and indicate that the film is chemically stable throughout the transfer process, while Raman spectroscopy indicates a 42% relaxation of compressive stress following removal of the copper substrate and subsequent transfer of h-BN to QFEG. Despite stress-induced wrinkling observed in the films, Hall effect measurements show little degradation (<10%) in carrier mobility for h-BN coated QFEG. Temperature dependent Hall measurements indicate little contribution from remote surface optical phonon scattering and suggest that, compared to HfO(2) based dielectrics, h-BN can be an excellent material for preserving electrical transport properties. Graphene transistors utilizing h-BN gates exhibit peak intrinsic cutoff frequencies >30 GHz (2.4× that of HfO(2)-based devices). PMID:22545808

  17. Wafer scale fabrication of carbon nanotube thin film transistors with high yield

    NASA Astrophysics Data System (ADS)

    Tian, Boyuan; Liang, Xuelei; Yan, Qiuping; Zhang, Han; Xia, Jiye; Dong, Guodong; Peng, Lianmao; Xie, Sishen

    2016-07-01

    Carbon nanotube thin film transistors (CNT-TFTs) are promising candidates for future high performance and low cost macro-electronics. However, most of the reported CNT-TFTs are fabricated in small quantities on a relatively small size substrate. The yield of large scale fabrication and the performance uniformity of devices on large size substrates should be improved before the CNT-TFTs reach real products. In this paper, 25 200 devices, with various geometries (channel width and channel length), were fabricated on 4-in. size ridged and flexible substrates. Almost 100% device yield were obtained on a rigid substrate with high out-put current (>8 μA/μm), high on/off current ratio (>105), and high mobility (>30 cm2/V.s). More importantly, uniform performance in 4-in. area was achieved, and the fabrication process can be scaled up. The results give us more confidence for the real application of the CNT-TFT technology in the near future.

  18. Wafer-scale monodomain films of spontaneously aligned single-walled carbon nanotubes.

    PubMed

    He, Xiaowei; Gao, Weilu; Xie, Lijuan; Li, Bo; Zhang, Qi; Lei, Sidong; Robinson, John M; Hároz, Erik H; Doorn, Stephen K; Wang, Weipeng; Vajtai, Robert; Ajayan, Pulickel M; Adams, W Wade; Hauge, Robert H; Kono, Junichiro

    2016-07-01

    The one-dimensional character of electrons, phonons and excitons in individual single-walled carbon nanotubes leads to extremely anisotropic electronic, thermal and optical properties. However, despite significant efforts to develop ways to produce large-scale architectures of aligned nanotubes, macroscopic manifestations of such properties remain limited. Here, we show that large (>cm(2)) monodomain films of aligned single-walled carbon nanotubes can be prepared using slow vacuum filtration. The produced films are globally aligned within ±1.5° (a nematic order parameter of ∼1) and are highly packed, containing 1 × 10(6) nanotubes in a cross-sectional area of 1 μm(2). The method works for nanotubes synthesized by various methods, and film thickness is controllable from a few nanometres to ∼100 nm. We use the approach to create ideal polarizers in the terahertz frequency range and, by combining the method with recently developed sorting techniques, highly aligned and chirality-enriched nanotube thin-film devices. Semiconductor-enriched devices exhibit polarized light emission and polarization-dependent photocurrent, as well as anisotropic conductivities and transistor action with high on/off ratios. PMID:27043199

  19. Wafer-scale monodomain films of spontaneously aligned single-walled carbon nanotubes

    NASA Astrophysics Data System (ADS)

    He, Xiaowei; Gao, Weilu; Xie, Lijuan; Li, Bo; Zhang, Qi; Lei, Sidong; Robinson, John M.; Hároz, Erik H.; Doorn, Stephen K.; Wang, Weipeng; Vajtai, Robert; Ajayan, Pulickel M.; Adams, W. Wade; Hauge, Robert H.; Kono, Junichiro

    2016-07-01

    The one-dimensional character of electrons, phonons and excitons in individual single-walled carbon nanotubes leads to extremely anisotropic electronic, thermal and optical properties. However, despite significant efforts to develop ways to produce large-scale architectures of aligned nanotubes, macroscopic manifestations of such properties remain limited. Here, we show that large (>cm2) monodomain films of aligned single-walled carbon nanotubes can be prepared using slow vacuum filtration. The produced films are globally aligned within ±1.5° (a nematic order parameter of ∼1) and are highly packed, containing 1 × 106 nanotubes in a cross-sectional area of 1 μm2. The method works for nanotubes synthesized by various methods, and film thickness is controllable from a few nanometres to ∼100 nm. We use the approach to create ideal polarizers in the terahertz frequency range and, by combining the method with recently developed sorting techniques, highly aligned and chirality-enriched nanotube thin-film devices. Semiconductor-enriched devices exhibit polarized light emission and polarization-dependent photocurrent, as well as anisotropic conductivities and transistor action with high on/off ratios.

  20. Wafer-scale synthesis of thickness-controllable MoS2 films via solution-processing using a dimethylformamide/n-butylamine/2-aminoethanol solvent system

    NASA Astrophysics Data System (ADS)

    Yang, Jaehyun; Gu, Yeahyun; Lee, Eunha; Lee, Hyangsook; Park, Sang Han; Cho, Mann-Ho; Kim, Yong Ho; Kim, Yong-Hoon; Kim, Hyoungsub

    2015-05-01

    The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the synthesized MoS2 film has wafer-scale homogeneity with excellent crystalline quality and a stoichiometric chemical composition. To further demonstrate possible device applications, a mostly penta-layered MoS2 thin film was integrated into a top-gated field-effect transistor as the channel layer and we also successfully transferred our films onto transparent/flexible substrates.The wafer-scale synthesis of two-dimensional molybdenum disulfide (MoS2) films, with high layer-controllability and uniformity, remains a significant challenge in the fields of nano and optoelectronics. Here, we report the highly thickness controllable growth of uniform MoS2 thin films on the wafer-scale via a spin-coating route. Formulation of a dimethylformamide-based MoS2 precursor solution mixed with additional amine- and amino alcohol-based solvents (n-butylamine and 2-aminoethanol) allowed for the formation of a uniform coating of MoS2 thin films over a 2 inch wafer-scale SiO2/Si substrate. In addition, facile control of the average number of stacking layers is demonstrated by simply manipulating the concentration of the precursor solution. Various characterization results reveal that the

  1. Slip, Crystal Orientation, and Damage Evolution During Thermal Cycling in High-Strain Wafer-Level Chip-Scale Packages

    NASA Astrophysics Data System (ADS)

    Zhou, Bite; Zhou, Quan; Bieler, Thomas R.; Lee, Tae-kyu

    2015-03-01

    Wafer-level chip-scale package samples with pre-cross-sectioned edge rows were thermally cycled to study microstructure evolution and damage development. Electron backscattered diffraction (EBSD) and high-energy x-ray diffraction were used to obtain Sn grain orientations and the average coefficient of thermal expansion normal to the board in every joint of the package for samples in the as-fabricated and thermally cycled conditions. The results indicated a near-random distribution of joint orientation. Optical, scanning electron microscopy, and EBSD methods were used to characterize microstructure changes in pre-cross-sectioned samples due to thermal cycling. Slip trace analysis and Orientation Imaging Microscopy™ (OIM) show that slip systems with high Schmid factors (estimated global shear stress based on the package neutral point) are responsible for the observed microstructure evolution during thermal cycling, which provides information about slip systems that are more easily activated. Two joints were analyzed in detail to evaluate slip activity at different stages of their thermal history. The first case showed that a solidification twin grain boundary misorientation deviated from the twin relationship due to slip activity during thermal cycling, which can influence damage development and the path of crack propagation. The second case showed a new grain orientation developing due to gradual lattice rotation about the Sn [110] axis by a continuous recrystallization mechanism. This rotation was correlated with the operation of slip system . Small tin whiskers emerged from the initially polished chip interface and grew with increasing thermal cycles until a crack developed in the solder that relieved the stress. As the local stresses are not known experimentally, this analysis provides observations that can be compared with a crystal plasticity model simulation.

  2. Si nanowire directly grown on a liquid metal substrate--towards wafer scale transferable nanowire arrays with improved visible-light sterilization.

    PubMed

    Wang, Hui; Wang, Jian-Tao; Ou, Xue-Mei; Lee, Chun-Sing; Zhang, Xiao-Hong

    2014-04-11

    Integrating vertically aligned nanowires (NWs) on a functional substrate is important for the application of NWs in wafer scale assemblies and functional devices. However, vertically aligned NWs via the current epitaxial growth route can only be prepared on crystalline wafers. A convenient method is thus presented to overcome NW substrate limitations. Liquid metal is proposed to serve as a substrate for the initial growth of vertically aligned NWs. NWs could then be harvested from the growth substrate and integrated with functional substrates. Fabricated vertically aligned silicon NWs (SiNWs) were grown on molten Sn and then integrated into a flexible transparent poly(dimethylsiloxane) film to obtain a SiNW/functional substrate device. The device showed enhanced visible-light absorption ability and refreshable visible-light bactericidal activities with a bacterial reduction rate of close to 100%, indicating that growth with molten metal as a substrate could be a promising approach for extending the function and application of NWs.

  3. Microfabrication: LIGA-X and applications

    NASA Astrophysics Data System (ADS)

    Kupka, R. K.; Bouamrane, F.; Cremers, C.; Megtert, S.

    2000-09-01

    X-ray LIGA (Lithography, Electrogrowth, Moulding) is one of today's key technologies in microfabrication and upcoming modern (meso)-(nano) fabrication, already used and anticipated for micromechanics (micromotors, microsensors, spinnerets, etc.), micro-optics, micro-hydrodynamics (fluidic devices), microbiology, in medicine, in biology, and in chemistry for microchemical reactors. It compares to micro-electromechanical systems (MEMS) technology, offering a larger, non-silicon choice of materials and better inherent precision. X-ray LIGA relies on synchrotron radiation to obtain necessary X-ray fluxes and uses X-ray proximity printing. Inherent advantages are its extreme precision, depth of field and very low intrinsic surface roughness. However, the quality of fabricated structures often depends on secondary effects during exposure and effects like resist adhesion. UV-LIGA, relying on thick UV resists is an alternative for projects requiring less precision. Modulating the spectral properties of synchrotron radiation, different regimes of X-ray lithography lead to (a) the mass-fabrication of classical nanostructures, (b) the fabrication of high aspect ratio nanostructures (HARNST), (c) the fabrication of high aspect ratio microstructures (HARMST), and (d) the fabrication of high aspect ratio centimeter structures (HARCST). Reviewing very recent activities around X-ray LIGA, we show the versatility of the method, obviously finding its region of application there, where it is best and other competing microtechnologies are less advantageous. An example of surface-based X-ray and particle lenses (orthogonal reflection optics (ORO)) made by X-ray LIGA is given.

  4. Laser wafering for silicon solar.

    SciTech Connect

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  5. Optimization and scale-down of wafer-based resist strip and rinse processes for photomask production

    NASA Astrophysics Data System (ADS)

    Aggus, Brant L.; Weaver, Gene

    2002-03-01

    Retrofitting of wafer processing equipment is a common scenario in the photomask industry, as most available tools are built to accommodate the high throughput and substrate size of wafers. The acid process tanks in use at most mask shops are built to suit a single rack of 25 8 inch wafers, each coated with roughly two microns of photoresist. Conversely, a typical photomask shop sends one to two masks at a time through the resist strip line, each coated with 4500 angstroms of resist. The amount of unused volume of active chemical within an 8 inch X 8.5 inch X 10 inch acid tank when it is dumped is enough to warrant a hardware change. Experimentation has shown that it is possible to decrease Piranha usage by 43 percent by optimizing tank size for photomasks. The same logic applies to quick dump rinsers (QDRs). Additionally, water is wasted with 'spray down' processes, whereby masks are sprayed via perforated bars or nozzles. Because a < 0.5 μm viscous sublayer can not be practically achieved through spraying the mask, better cleaning performance is obtained with a bottom-filled weiring process. This is demonstrated through experimental results and theoretical mass transfer models.

  6. Nano-scale origins of recombination activity and optical properties of extended defects in mc-Si wafers and PV cells

    NASA Astrophysics Data System (ADS)

    Guthrey, Harvey L., IV

    Multicrystalline silicon (mc-Si) is the most used absorber in photovoltaic (PV) cells at present. If efficiencies are to improve in this established technology a better understanding of how minority carrier lifetimes are reduced is necessary. The capture of minority carriers by states associated with extended defects is known to play a major role in reducing minority carrier lifetimes. Energy levels introduced into the silicon bandgap often have electrical activity or optical signatures that can provide clues as to the structural or chemical origin of a particular level. This work utilizes electron beam induced current (EBIC), cathodoluminescence (CL) imaging and spectroscopy, photoluminescence (PL) imaging, and nano-scale chemical analysis to provide new insight into the origin of the electrical and optical properties of extended defects in mc-Si wafers and PV cells. A new interpretation of the temperature dependence of EBIC contrast is formulated based on observations of an anomalous form of the contrast vs. temperature curves as well as evidence of high impurity content. In addition an attempt is made to determine the origin of specific types of defect related emission as well as how this emission is influenced by processing steps applied to mc-Si wafers. Nano-scale chemical analysis is used to reveal the origin of the observed luminescence.

  7. Understanding and Tailoring the Mechanical Properties of LIGA Fabricated Materials

    SciTech Connect

    Buchheit, T.E.; Christenson, T.R.; Lavan, D.A.; Schmale, D.T.

    1999-01-25

    LIGA fabricated materials and components exhibit several processing issues affecting their metallurgical and mechanical properties, potentially limiting their usefulness for MEMS applications. For example, LIGA processing by metal electrodeposition is very sensitive to deposition conditions which causes significant processing lot variations of mechanical and metallurgical properties. Furthermore, the process produces a material with a highly textured lenticular rnicrostructural morphology suggesting an anisotropic material response. Understanding and controlling out-of-plane anisotropy is desirable for LIGA components designed for out-of-plane flexures. Previous work by the current authors focused on results from a miniature servo-hydraulic mechanical test frame constructed for characterizing LIGA materials. Those results demonstrated microstructural and mechanical properties dependencies with plating bath current density in LIGA fabricated nickel (LIGA Ni). This presentation builds on that work and fosters a methodology for controlling the properties of LIGA fabricated materials through processing. New results include measurement of mechanical properties of LIGA fabricated copper (LIGA Cu), out-of-plane and localized mechanical property measurements using compression testing and nanoindentation of LIGA Ni and LIGA Cu.

  8. Large-area, wafer-scale epitaxial growth of germanium on silicon and integration of high-performance transistors

    NASA Astrophysics Data System (ADS)

    Ghosh, Swapnadip

    Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the ˜105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress

  9. Wafer-scale double-layer stacked Au/Al2O3@Au nanosphere structure with tunable nanospacing for surface-enhanced Raman scattering.

    PubMed

    Hu, Zhaosheng; Liu, Zhe; Li, Lin; Quan, Baogang; Li, Yunlong; Li, Junjie; Gu, Changzhi

    2014-10-15

    Fabricating perfect plasmonic nanostructures has been a major challenge in surface enhanced Raman scattering (SERS) research. Here, a double-layer stacked Au/Al2O3@Au nanosphere structures is designed on the silicon wafer to bring high density, high intensity "hot spots" effect. A simply reproducible high-throughput approach is shown to fabricate feasibly this plasmonic nanostructures by rapid thermal annealing (RTA) and atomic layer deposition process (ALD). The double-layer stacked Au nanospheres construct a three-dimensional plasmonic nanostructure with tunable nanospacing and high-density nanojunctions between adjacent Au nanospheres by ultrathin Al2O3 isolation layer, producing highly strong plasmonic coupling so that the electromagnetic near-field is greatly enhanced to obtain a highly uniform increase of SERS with an enhancement factor (EF) of over 10(7). Both heterogeneous nanosphere group (Au/Al2O@Ag) and pyramid-shaped arrays structure substrate can help to increase the SERS signals further, with a EF of nearly 10(9). These wafer-scale, high density homo/hetero-metal-nanosphere arrays with tunable nanojunction between adjacent shell-isolated nanospheres have significant implications for ultrasensitive Raman detection, molecular electronics, and nanophotonics.

  10. Wafer-scale epitaxial lift-off of optoelectronic grade GaN from a GaN substrate using a sacrificial ZnO interlayer

    NASA Astrophysics Data System (ADS)

    Rajan, Akhil; Rogers, David J.; Ton-That, Cuong; Zhu, Liangchen; Phillips, Matthew R.; Sundaram, Suresh; Gautier, Simon; Moudakir, Tarik; El-Gmili, Youssef; Ougazzaden, Abdallah; Sandana, Vinod E.; Teherani, Ferechteh H.; Bove, Philippe; Prior, Kevin A.; Djebbour, Zakaria; McClintock, Ryan; Razeghi, Manijeh

    2016-08-01

    Full 2 inch GaN epilayers were lifted off GaN and c-sapphire substrates by preferential chemical dissolution of sacrificial ZnO underlayers. Modification of the standard epitaxial lift-off (ELO) process by supporting the wax host with a glass substrate proved key in enabling full wafer scale-up. Scanning electron microscopy and x-ray diffraction confirmed that intact epitaxial GaN had been transferred to the glass host. Depth-resolved cathodoluminescence (CL) analysis of the bottom surface of the lifted-off GaN layer revealed strong near-band-edge (3.33 eV) emission indicating a superior optical quality for the GaN which was lifted off the GaN substrate. This modified ELO approach demonstrates that previous theories proposing that wax host curling was necessary to keep the ELO etch channel open do not apply to the GaN/ZnO system. The unprecedented full wafer transfer of epitaxial GaN to an alternative support by ELO offers the perspective of accelerating industrial adoption of the expensive GaN substrate through cost-reducing recycling.

  11. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    NASA Astrophysics Data System (ADS)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  12. Fast and robust hydrogen sensors based on discontinuous palladium films on polyimide, fabricated on a wafer scale.

    PubMed

    Kiefer, T; Villanueva, L G; Fargier, F; Favier, F; Brugger, J

    2010-12-17

    Fast hydrogen sensors based on discontinuous palladium (Pd) films on supporting polyimide layers, fabricated by a cost-efficient and full-wafer compatible process, are presented. The films, deposited by electron-beam evaporation with a nominal thickness of 1.5 nm, consist of isolated Pd islands that are separated by nanoscopic gaps. On hydrogenation, the volume expansion of Pd brings initially separated islands into contact which leads to the creation of new electrical pathways through the film. The supporting polyimide layer provides both sufficient elasticity for the Pd nanoclusters to expand on hydrogenation and a sufficiently high surface energy for good adhesion of both film and contacting electrodes. The novel order of the fabrication processes involves a dicing step prior to the Pd deposition and stencil lithography for the patterning of microelectrodes. This allows us to preserve the as-deposited film properties. The devices work at room temperature, show response times of a few seconds and have a low power consumption of some tens of nW. PMID:21098952

  13. LIGA microsystems aging : evaluation and mitigation.

    SciTech Connect

    Cadden, Charles H.; Yang, Nancy Y. C.; San Marchi, Christopher W.

    2003-12-01

    The deployment of LIGA structures in DP applications requires a thorough understanding of potential long term physical and chemical changes that may occur during service. While these components are generally fabricated from simple metallic systems such as copper, nickel and nickel alloys, the electroplating process used to form them creates microstructural features which differ from those found in conventional (e.g. ingot metallurgy) processing of such materials. Physical changes in non-equilibrium microstructures may occur due to long term exposure to temperatures sufficient to permit atomic and vacancy mobility. Chemical changes, particularly at the surfaces of LIGA parts, may occur in the presence of gaseous chemical species (e.g. water vapor, HE off-gassing compounds) and contact with other metallic structures. In this study, we have characterized the baseline microstructure of several nickel-based materials that are used to fabricate LIGA structures. Solute content and distribution was found to have a major effect on the electroplated microstructures. Microstructural features were correlated to measurements of hardness and tensile strength. Dormancy testing was conducted on one of the baseline compositions, nickel-sulfamate. Groups of specimens were exposed to controlled thermal cycles; subsequent examinations compared properties of 'aged' specimens to the baseline conditions. Results of our testing indicate that exposure to ambient temperatures (-54 C to 71 C) do not result in microstructural changes that might be expected to significantly effect mechanical performance. Additionally, no localized changes in surface appearance were found as a result of contact between electroplated parts.

  14. LigaSure Hemorrhoidectomy for Symptomatic Hemorrhoids: First Pediatric Experience.

    PubMed

    Grossmann, Ole; Soccorso, Giampiero; Murthi, Govind

    2015-08-01

    Hemorrhoids are uncommon in children. Third and fourth degree symptomatic hemorrhoids may be surgically excised. We describe the first experience of using LigaSure (Covidien, Mansfield, Massachusetts, United States) to perform hemorrhoidectomies in children. LigaSure hemorrhoidectomy has been well described in adults and is found to be superior in patient tolerance as compared with conventional hemorrhoidectomy.

  15. Wafer-scale monolayer MoS2 grown by chemical vapor deposition using a reaction of MoO3 and H2S

    NASA Astrophysics Data System (ADS)

    Kim, Youngchan; Bark, Hunyoung; Ryu, Gyeong Hee; Lee, Zonghoon; Lee, Changgu

    2016-05-01

    Monolayer MoS2 nanosheets are potentially useful in optoelectronics, photoelectronics, and nanoelectronics due to their flexibility, mechanical strength, and direct band gap of 1.89 eV. Experimentalists have studied the synthesis of MoS2 using chemical vapor deposition (CVD) methods in an effort to fabricate wafer-scale nanofilms with a high uniformity and continuity for practical electronic applications. In this work, we applied the CVD method to a reaction of MoO3 powder and H2S gas to grow high-quality polycrystalline monolayer MoS2 sheets with unprecedented uniformity over an area of several centimeters. The monolayer MoS2 was characterized using Raman spectroscopy, photoluminescence (PL) spectroscopy, atomic force microscopy (AFM), x-ray photoemission spectroscopy (XPS), and transmission electron microscopy (TEM). The top-gate field-effect transistor prepared with a 30 nm HfO2 capping layer displayed an electrical mobility of 1 cm2 v-1 s-1 and an I on/off of ~105. This method paves the way for the development of practical devices with MoS2 monolayers and advances fundamental research.

  16. Wafer-scale monolayer MoS2 grown by chemical vapor deposition using a reaction of MoO3 and H2S

    NASA Astrophysics Data System (ADS)

    Kim, Youngchan; Bark, Hunyoung; Ryu, Gyeong Hee; Lee, Zonghoon; Lee, Changgu

    2016-05-01

    Monolayer MoS2 nanosheets are potentially useful in optoelectronics, photoelectronics, and nanoelectronics due to their flexibility, mechanical strength, and direct band gap of 1.89 eV. Experimentalists have studied the synthesis of MoS2 using chemical vapor deposition (CVD) methods in an effort to fabricate wafer-scale nanofilms with a high uniformity and continuity for practical electronic applications. In this work, we applied the CVD method to a reaction of MoO3 powder and H2S gas to grow high-quality polycrystalline monolayer MoS2 sheets with unprecedented uniformity over an area of several centimeters. The monolayer MoS2 was characterized using Raman spectroscopy, photoluminescence (PL) spectroscopy, atomic force microscopy (AFM), x-ray photoemission spectroscopy (XPS), and transmission electron microscopy (TEM). The top-gate field-effect transistor prepared with a 30 nm HfO2 capping layer displayed an electrical mobility of 1 cm2 v‑1 s‑1 and an I on/off of ~105. This method paves the way for the development of practical devices with MoS2 monolayers and advances fundamental research.

  17. Wafer-scale monolayer MoS2 grown by chemical vapor deposition using a reaction of MoO3 and H2S.

    PubMed

    Kim, Youngchan; Bark, Hunyoung; Ryu, Gyeong Hee; Lee, Zonghoon; Lee, Changgu

    2016-05-11

    Monolayer MoS2 nanosheets are potentially useful in optoelectronics, photoelectronics, and nanoelectronics due to their flexibility, mechanical strength, and direct band gap of 1.89 eV. Experimentalists have studied the synthesis of MoS2 using chemical vapor deposition (CVD) methods in an effort to fabricate wafer-scale nanofilms with a high uniformity and continuity for practical electronic applications. In this work, we applied the CVD method to a reaction of MoO3 powder and H2S gas to grow high-quality polycrystalline monolayer MoS2 sheets with unprecedented uniformity over an area of several centimeters. The monolayer MoS2 was characterized using Raman spectroscopy, photoluminescence (PL) spectroscopy, atomic force microscopy (AFM), x-ray photoemission spectroscopy (XPS), and transmission electron microscopy (TEM). The top-gate field-effect transistor prepared with a 30 nm HfO2 capping layer displayed an electrical mobility of 1 cm(2) v(-1) s(-1) and an I on/off of ~10(5). This method paves the way for the development of practical devices with MoS2 monolayers and advances fundamental research.

  18. X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

    NASA Astrophysics Data System (ADS)

    Cha, Bo Kyung; Jeon, Seongchae; Seo, Chang-Woo

    2016-09-01

    This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 μm 1-poly/4-metal CMOS process. The pixel size is 100 μm×100 μm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd2O2S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

  19. Final-part metrology for LIGA springs, Build Group 1.

    SciTech Connect

    Aigeldinger, Georg; Skala, Dawn M.; Ceremuga, Joseph T.; Mills, Bernice E.

    2004-03-01

    The LIGA spring is a recently designed part for defense program applications. The Sandia California LIGA team has produced an initial group build of these nickel alloy parts. These are distinctive in having a macroscopic lateral size of about 1 cm, while requiring microscopic dimensional precision on the order of a few micrometers. LIGA technology capabilities at Sandia are able to manufacture such precise structures. While certain aspects of the LIGA process and its production capabilities have been dimensionally characterized in the past, [1-6] the present work is exclusive in defining a set of methods and techniques to inspect and measure final LIGA nickel alloy parts in large prototype quantities. One hundred percent inspection, meaning that every single LIGA part produced needs to be measured, ensures quality control and customer satisfaction in this prototype production run. After a general visual inspection of the parts and an x-ray check for voids, high precision dimensional metrology tools are employed. The acquired data is analyzed using both in house and commercially available software. Examples of measurements illustrating these new metrology capabilities are presented throughout the report. These examples furthermore emphasize that thorough inspection of every final part is not only essential to characterize but also improve the LIGA manufacturing process.

  20. Cantilevered multilevel LIGA devices and methods

    DOEpatents

    Morales, Alfredo Martin; Domeier, Linda A.

    2002-01-01

    In the formation of multilevel LIGA microstructures, a preformed sheet of photoresist material, such as polymethylmethacrylate (PMMA) is patterned by exposure through a mask to radiation, such as X-rays, and developed using a developer to remove the exposed photoresist material. A first microstructure is then formed by electroplating metal into the areas from which the photoresist has been removed. Additional levels of microstructure are added to the initial microstructure by covering the first microstructure with a conductive polymer, machining the conductive polymer layer to reveal the surface of the first microstructure, sealing the conductive polymer and surface of the first microstructure with a metal layer, and then forming the second level of structure on top of the first level structure. In such a manner, multiple layers of microstructure can be built up to allow complex cantilevered microstructures to be formed.

  1. Miniature Scroll Pumps Fabricated by LIGA

    NASA Technical Reports Server (NTRS)

    Wiberg, Dean; Shcheglov, Kirill; White, Victor; Bae, Sam

    2009-01-01

    Miniature scroll pumps have been proposed as roughing pumps (low - vacuum pumps) for miniature scientific instruments (e.g., portable mass spectrometers and gas analyzers) that depend on vacuum. The larger scroll pumps used as roughing pumps in some older vacuum systems are fabricated by conventional machining. Typically, such an older scroll pump includes (1) an electric motor with an eccentric shaft to generate orbital motion of a scroll and (2) conventional bearings to restrict the orbital motion to a circle. The proposed miniature scroll pumps would differ from the prior, larger ones in both design and fabrication. A miniature scroll pump would include two scrolls: one mounted on a stationary baseplate and one on a flexure stage (see figure). An electromagnetic actuator in the form of two pairs of voice coils in a push-pull configuration would make the flexure stage move in the desired circular orbit. The capacitance between the scrolls would be monitored to provide position (gap) feedback to a control system that would adjust the drive signals applied to the voice coils to maintain the circular orbit as needed for precise sealing of the scrolls. To minimize power consumption and maximize precision of control, the flexure stage would be driven at the frequency of its mechanical resonance. The miniaturization of these pumps would entail both operational and manufacturing tolerances of <1 m. Such tight tolerances cannot be achieved easily by conventional machining of high-aspect-ratio structures like those of scroll-pump components. In addition, the vibrations of conventional motors and ball bearings exceed these tight tolerances by an order of magnitude. Therefore, the proposed pumps would be fabricated by the microfabrication method known by the German acronym LIGA ( lithographie, galvanoformung, abformung, which means lithography, electroforming, molding) because LIGA has been shown to be capable of providing the required tolerances at large aspect ratios.

  2. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis

    NASA Astrophysics Data System (ADS)

    Zhao, C.; Konstantinidis, A. C.; Zheng, Y.; Anaxagoras, T.; Speller, R. D.; Kanicki, J.

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm-1 and a DQE of around 0.5 at spatial frequencies  <1 mm-1. In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered.

  3. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    PubMed

    Zhao, C; Konstantinidis, A C; Zheng, Y; Anaxagoras, T; Speller, R D; Kanicki, J

    2015-12-01

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm(-1) and a DQE of around 0.5 at spatial frequencies  <1 mm(-1). In addition, the modeling results were used to calculate the image signal-to-noise ratio (SNRi) of microcalcifications at various mean glandular dose (MGD). For an average breast (5 cm thickness, 50% glandular fraction), 165 μm microcalcifications can be distinguished at a MGD of 27% lower than the clinical value (~1.3 mGy). To detect 100 μm microcalcifications, further optimizations of the CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered. PMID:26540090

  4. Microstructural Evolution of SAC305 Solder Joints in Wafer Level Chip-Scale Packaging (WLCSP) with Continuous and Interrupted Accelerated Thermal Cycling

    NASA Astrophysics Data System (ADS)

    Zhou, Quan; Zhou, Bite; Lee, Tae-Kyu; Bieler, Thomas

    2016-06-01

    Four high-strain design wafer level chip scale packages were given accelerated thermal cycling with a 10°C/min ramp rate and 10 min hold times between 0°C and 100°C to examine the effects of continuous and interrupted thermal cycling on the number of cycles to failure. The interruptions given two of the samples were the result of periodic examinations using electron backscattered pattern mapping, leading to room temperature aging of 30 days-2.5 years after increments of about 100 cycles at several stages of the cycling history. The continuous thermal cycling resulted in solder joints with a much larger degree of recrystallization, whereas the interrupted thermal cycling tests led to much less recrystallization, which was more localized near the package side, and the crack was more localized near the interface and had less branching. The failure mode for both conditions was still the same, with cracks nucleating along the high angle grain boundaries formed during recrystallization. In conditions where there were few recrystallized grains, recovery led to formation of subgrains that strengthened the solder, and the higher strength led to a larger driving force for crack growth through the solder, leading to failure after less than half of the cycles in the continuous accelerated thermal cycling condition. This work shows that there is a critical point where sufficient strain energy accumulation will trigger recrystallization, but this point depends on the rate of strain accumulation in each cycle and various recovery processes, which further depends on local crystal orientations, stress state evolution, and specific activated slip and twinning systems.

  5. Wafer characteristics via reflectometry

    DOEpatents

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  6. Wafer scale micromachine assembly method

    DOEpatents

    Christenson, Todd R.

    2001-01-01

    A method for fusing together, using diffusion bonding, micromachine subassemblies which are separately fabricated is described. A first and second micromachine subassembly are fabricated on a first and second substrate, respectively. The substrates are positioned so that the upper surfaces of the two micromachine subassemblies face each other and are aligned so that the desired assembly results from their fusion. The upper surfaces are then brought into contact, and the assembly is subjected to conditions suited to the desired diffusion bonding.

  7. Stable wafer-carrier system

    DOEpatents

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  8. Wafer level reliability testing: An idea whose time has come

    NASA Technical Reports Server (NTRS)

    Trapp, O. D.

    1987-01-01

    Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

  9. Wafer screening device and methods for wafer screening

    DOEpatents

    Sopori, Bhushan; Rupnowski, Przemyslaw

    2014-07-15

    Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

  10. Laser-LIGA for Ni microcantilevers

    NASA Astrophysics Data System (ADS)

    Jin, Hengyi; Harvey, Erol C.; Hayes, Jason P.; Ghantasala, Muralidhar K.; Fu, Yao; Jolic, Karlo; Solomon, Matthew; Graves, Kynan

    2002-11-01

    This paper presents our design and experimental results of nickel microcantilevers, which were fabricated using a laser-LIGA process, based on KrF (248 nm) excimer laser micromachining. A chrome-on-quartz mask, containing the desired mask patterns was prepared for this work. The substrate of copper (30 μm thick) clad printed circuit board (PCB) was laminated with Laminar 5038 photopolymer to be laser patterned. Following laser patterning and laser cleaning, all the samples were electroformed with nickel on top of the copper layer. To release the Ni microcantilevers, the excimer laser was employed again to remove the polymer in the localised area to facilitate Cu selective etching. Here, copper acted as the sacrificial layer as well. The Cu selective etching was carried out with ~ 20 % (wt) aqueous solution of ammonium persulfate. Because the Cu selective etching is isotropic, some undercuts happened next to the anchor area. The samples were characterised using optical microscope, confocal laser scanning microscope and SEM, and some of Ni cantilevers were tested electro-thermally. Their performance was analyzed with respect to the simulation results.

  11. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-11-25

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  12. Structured wafer for device processing

    SciTech Connect

    Okandan, Murat; Nielson, Gregory N

    2014-05-20

    A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

  13. Within-wafer CD variation induced by wafer shape

    NASA Astrophysics Data System (ADS)

    Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

    2016-03-01

    In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer

  14. Recent Developments in Microsystems Fabricated by the Liga-Technique

    NASA Technical Reports Server (NTRS)

    Schulz, J.; Bade, K.; El-Kholi, A.; Hein, H.; Mohr, J.

    1995-01-01

    As an example of microsystems fabricated by the LIGA-technique (x-ray lithography, electroplating and molding), three systems are described and characterized: a triaxial acceleration sensor system, a micro-optical switch, and a microsystem for the analysis of pollutants. The fabrication technologies are reviewed with respect to the key components of the three systems: an acceleration sensor, and electrostatic actuator, and a spectrometer made by the LIGA-technique. Aa micro-pump and micro-valve made by using micromachined tools for molding and optical fiber imaging are made possible by combining LIGA and anisotropic etching of silicon in a batch process. These examples show that the combination of technologies and components is the key to complex microsystems. The design of such microsystems will be facilitated is standardized interfaces are available.

  15. Minimum wafer thickness by rotated ingot ID wafering. [Inner Diameter

    NASA Technical Reports Server (NTRS)

    Chen, C. P.; Leipold, M. H.

    1984-01-01

    The efficient utilization of materials is critical to certain device applications such as silicon for photovoltaics or diodes and gallium-gadolinium-garnet for memories. A variety of slicing techniques has been investigated to minimize wafer thickness and wafer kerf. This paper presents the results of analyses of ID wafering of rotated ingots based on predicted fracture behavior of the wafer as a result of forces during wafering and the properties of the device material. The analytical model indicated that the minimum wafer thickness is controlled by the depth of surface damage and the applied cantilever force. Both of these factors should be minimized. For silicon, a minimum thickness was found to be approximately 200 x 10 - 6th m for conventional sizes of rotated ingot wafering. Fractures through the thickness of the wafer rather than through the center supporting column were found to limit the minimum wafer thickness. The model suggested that the use of a vacuum chuck on the wafer surface to enhance cleavage fracture of the center supporting core and, with silicon, by using 111-line-type ingots could have potential for reducing minimum wafer thickness.

  16. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    SciTech Connect

    Lorenz, Adam

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the

  17. Wafer-scale crack-free AlGaN on GaN through two-step selective-area growth for optically pumped stimulated emission

    NASA Astrophysics Data System (ADS)

    Ko, Young-Ho; Bae, Sung-Bum; Kim, Sung-Bock; Kim, Dong Churl; Leem, Young Ahn; Cho, Yong-Hoon; Nam, Eun-Soo

    2016-07-01

    Crack-free AlGaN template has been successfully grown over entire 2-in. wafer by using 2-step selective-area growth (SAG). The GaN truncated structure was obtained by vertical growth mode with low growth temperature. AlGaN of second step was grown under lateral growth mode. Low pressure enhanced the relative ratio of lateral to vertical growth rate as well as absolute overall growth rate. High V/III ratio was favorable for lateral growth mode. Crack-free planar AlGaN was obtained under low pressure of 30 Torr and high V/III ratio of 4400. The AlGaN was crack-free over entire 2-in. wafer and had quite uniform Al-mole fraction. The dislocation density of the AlGaN with 20% Al-composition was as low as ~7.6×108 /cm2, measured by cathodoluminescence. GaN/AlGaN multi-quantum well (MQW) with cladding and waveguide layers were grown on the crack-free AlGaN template with low dislocation density. It was confirmed that the MQW on the AlGaN template emitted the stimulated emission at 355.5 nm through optical pumping experiment. The AlGaN obtained by 2-step SAG would provide high crystal quality for highly-efficient optoelectronic devices as well as the ultraviolet laser diode.

  18. Atomic scale fabrication of dangling bond structures on hydrogen passivated Si(0 0 1) wafers processed and nanopackaged in a clean room environment

    NASA Astrophysics Data System (ADS)

    Kolmer, Marek; Godlewski, Szymon; Zuzak, Rafal; Wojtaszek, Mateusz; Rauer, Caroline; Thuaire, Aurélie; Hartmann, Jean-Michel; Moriceau, Hubert; Joachim, Christian; Szymonski, Marek

    2014-01-01

    Specific surfaces allowing the ultra-high vacuum (UHV) creation of electronic interconnects and atomic nanostructures are required for the successful development of novel nanoscale electronic devices. Atomically flat and reconstructed Si(0 0 1):H surfaces are serious candidates for that role. In this work such Si:H surfaces were prepared in a cleanroom environment on 200 mm silicon wafers with a hydrogen bake and were subsequently bonded together to ensure the surface protection, and allow their transportation and storage for several months in air. Given the nature of the bonding, which was hydrophobic with weak van der Waals forces, we were then able to de-bond them in UHV. We show that the quality of the de-bonded Si:H surface enables the "at will" construction of sophisticated and complex dangling bond (DB) nanostructures by atomically precise scanning tunneling microscope (STM) tip induced desorption of hydrogen atoms. The DB structures created on slightly doped Si:H samples were characterized by scanning tunneling microscopy and spectroscopy (STM/STS) performed at 4 K. Our results demonstrate that DB nanostructures fabricated on UHV de-bonded Si(0 0 1):H wafers could be directly incorporated in future electronics as interconnects and parts of nanoscale logic circuits.

  19. Plastic micro-optical components with the LIGA technology

    NASA Astrophysics Data System (ADS)

    Singleton, Laurence; Detemple, Peter; Frese, I.; Klotzbuecher, Thomas; Bauer, Hans-Dieter

    2003-01-01

    Moulding of plastics enables optical features to be integrated into a single unit. This is particularly an advantage for product designs that impose space and weight constraints. Therefore, the use of plastic for biomedical and non telecommunications orientated optical applications continues to grow as design engineers take advantage of the ease of fabrication and the material flexibility. Deep X-ray LIGA presents itself as a method ideally suited for the production of moulds for the manufacture of plastic microcomponents. LIGA is synonymous for the lithography preferably carried out with synchrotron radiation X-rays, although many other lithography and non-lithography methods for master production have been developed in the last few years. Nevertheless, the exceptional resist heights, the enormous accuracy and low runout as well as the low sidewall roughnesses cannot be copied by these other methods of master production. In particular, the low sidewall roughnesses achieved through deep X-ray LIGA is essential for the manufacture of waveguide coupling systems based on polymers. The design and conceptualisation of such waveguides systems is presented here. In addition however, the exceptional resist heights and low runout can be employed to produce passive structures for the packaging of optical components. This paper provides an overview of the deep X-ray LIGA technology, emphasizing its strengths and application areas. Considerations for the design and manufacture of the plastic structures are also elucidated.

  20. Wafer level warpage characterization of 3D interconnect processing wafers

    NASA Astrophysics Data System (ADS)

    Chang, Po-Yi; Ku, Yi-Sha

    2012-03-01

    We present a new metrology system based on a fringe reflection method for warpage characterizations during wafer thinning and temporary bonding processes. A set of periodic fringe patterns is projected onto the measuring wafer and the reflected fringe images are captured by a CCD camera. The fringe patterns are deformed due to the slope variation of the wafer surface. We demonstrate the use of phase-shit algorithms, the wafer surface slope variation and quantitative 3D surface profile even tiny dimples and dents on a wafer can be reconstructed. The experimental results show the warpages of the bonded wafer are below 20 μm after thinning down to the nominal thickness of 75 μm and 50 μm. The measurement precision is better than 2 um.

  1. Great enhancement in the excitonic recombination and light extraction of highly ordered InGaN/GaN elliptic nanorod arrays on a wafer scale.

    PubMed

    Zhuang, Zhe; Guo, Xu; Liu, Bin; Hu, Fengrui; Dai, Jiangping; Zhang, Yun; Li, Yi; Tao, Tao; Zhi, Ting; Xie, Zili; Ge, Haixiong; Wang, Xiaoyong; Xiao, Min; Wang, Tao; Shi, Yi; Zheng, Youdou; Zhang, Rong

    2016-01-01

    A series of highly ordered c-plane InGaN/GaN elliptic nanorod (NR) arrays were fabricated by our developed soft UV-curing nanoimprint lithography on a wafer. The photoluminescence (PL) integral intensities of NR samples show a remarkable enhancement by a factor of up to two orders of magnitude compared with their corresponding as-grown samples at room temperature. The radiative recombination in NR samples is found to be greatly enhanced due to not only the suppressed non-radiative recombination but also the strain relaxation and optical waveguide effects. It is demonstrated that elliptic NR arrays improve the light extraction greatly and have polarized emission, both of which possibly result from the broken structure symmetry. Green NR light-emitting diodes have been finally realized, with good current-voltage performance and uniform luminescence.

  2. A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications

    NASA Astrophysics Data System (ADS)

    Geng, Fei; Ding, Xiao-yun; Xu, Gao-wei; Luo, Le

    2009-10-01

    A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 °C W-1. The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S21) is below 0.4 dB from 0 to 40 GHz and the return loss (S11) is less than -20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S21 shifting caused by the packaging structure is below 0.5 dB, and S11 is less than -10 dB from 8 GHz to 14 GHz.

  3. Fabrication of Uniform Nanoscale Cavities via Silicon Direct Wafer Bonding

    PubMed Central

    Thomson, Stephen R. D.; Perron, Justin K.; Kimball, Mark O.; Mehta, Sarabjit; Gasparini, Francis M.

    2014-01-01

    Measurements of the heat capacity and superfluid fraction of confined 4He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments3, bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned2 in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water4. The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale. PMID:24457563

  4. Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

    PubMed

    Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

    2014-01-01

    Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

  5. Wafer-scale controlled exfoliation of metal organic vapor phase epitaxy grown InGaN/GaN multi quantum well structures using low-tack two-dimensional layered h-BN

    NASA Astrophysics Data System (ADS)

    Ayari, Taha; Sundaram, Suresh; Li, Xin; El Gmili, Youssef; Voss, Paul L.; Salvestrini, Jean Paul; Ougazzaden, Abdallah

    2016-04-01

    Recent advances in epitaxial growth have led to the growth of III-nitride devices on 2D layered h-BN. This advance has the potential for wafer-scale transfer to arbitrary substrates, which could improve the thermal management and would allow III-N devices to be used more flexibly in a broader range of applications. We report wafer scale exfoliation of a metal organic vapor phase epitaxy grown InGaN/GaN Multi Quantum Well (MQW) structure from a 5 nm thick h-BN layer that was grown on a 2-inch sapphire substrate. The weak van der Waals bonds between h-BN atomic layers break easily, allowing the MQW structure to be mechanically lifted off from the sapphire substrate using a commercial adhesive tape. This results in the surface roughness of only 1.14 nm on the separated surface. Structural characterizations performed before and after the lift-off confirm the conservation of structural properties after lift-off. Cathodoluminescence at 454 nm was present before lift-off and 458 nm was present after. Electroluminescence near 450 nm from the lifted-off structure has also been observed. These results show that the high crystalline quality ultrathin h-BN serves as an effective sacrificial layer—it maintains performance, while also reducing the GaN buffer thickness and temperature ramps as compared to a conventional two-step growth method. These results support the use of h-BN as a low-tack sacrificial underlying layer for GaN-based device structures and demonstrate the feasibility of large area lift-off and transfer to any template, which is important for industrial scale production.

  6. Design Study of Wafer Seals for Future Hypersonic Vehicles

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  7. Gettering Silicon Wafers with Phosphorus

    NASA Technical Reports Server (NTRS)

    Daiello, R. V.

    1983-01-01

    Silicon wafers subjected to gettering in phosphorus atmosphere have longer diffusion lengths and higher solar-cell efficiencies than untreated wafers. Gettering treatment improves properties of solar cells manufactured from impure silicon and is compatible with standard solar-cell processing.

  8. W-band LiGA fabricated klystron

    NASA Astrophysics Data System (ADS)

    Song, Liqun

    2002-01-01

    Klystrino-W-band klystron was proposed by scientists at SLAC to satisfy recent applications in advanced accelerators, medical treatment, radars and communications. LiGA (a German acronym for lithographe, galvanoformung, and abformung) is introduced in the fabrication of klystrino for the first time in the history of microwave tube fabrication. The cold test experiments show that LiGA fabrication yields best surface smoothness compared with an alternative way EDM (Electrical Discharge Machining). Resultantly LiGA fabricated klystrino has the smallest wall loss which maximizes the circuit efficiency of the output structure. A multiple-gap coupled cavity is motivated to be employed as the klystrino output cavity for maximizing the efficiency. Klytrino is simulated by 1-D, 2-D and 3-D simulation codes. Particularly a complete klystrino is simulated intensively using 2-D MAGIC Particle-in-Cell (PIC) code either for beam absence or beam presence. Many simulation techniques are developed such as model transformation from 3-D to 2-D, circuit parameter simulation, dispersion characteristic analysis, pre bunched electron beam mode and so on. Klystrino, as a 3-D structure, is modeled by 3-D MAFIA for analyzing the cold circuit properties. 3-D MAGIC is explored to simulate klystrino for the actual structure analysis and actual beam interaction process observation.

  9. Variants of LIGA technology for the production of plastic microcomponents

    NASA Astrophysics Data System (ADS)

    Singleton, Laurence; Detemple, Peter; Loewe, Holger

    2003-03-01

    Moulding of plastics enables fluidic and optical features to be integrated into a single element. This is particularly an advantage for product designs that impose space and weight constraints. Therefore, the use of plastic for biomedical and non telecommunications orientated optical applications continues to grow as design engineers take advantage of the ease of fabrication and the material flexibility. LIGA presents itself as a method ideally suited for the production of moulds for the manufacture of plastic microcomponents. Although LIGA is synonymous for lithography using synchrotron radiation x-rays, many other lithography and non-lithography methods for master production have been developed in the last few years, offering cost effective solutions to template production. These include UV LIGA methods, where deep resists such as SU-8 and AZ 4562, are employed for the master production. In addition, excimer laser micromachining offers a cost effective and efficient method for master fabrication, which later forms a template for electroforming. Furthermore, the use of Advanced Silicon Etching methods to prestructure silicon templates for electroforming, allows to the production of stepped mould inserts, which are particularly useful for microfluidic applications. This paper provides an overview of the different technologies, emphasizing the strengths and application areas of the different master structuring technologies. Considerations for the electroforming of microstructured mould inserts are also presented.

  10. [Thyroidectomy with LigaSure versus traditional thyroidectomy: our experience].

    PubMed

    Marrazzo, Antonio; Casà, Luigi; David, Massimo; Lo Gerfo, Domenico; Noto, Antonio; Riili, Ignazio; Taormina, Pietra

    2007-01-01

    Over the past few decades the surgical strategy for both benign and malignant thyroid diseases has undergone several changes. In particular, total thyroidectomy today has become the routine operation for most thyroid diseases. The complications of this surgical procedure, though of multifactorial aetiopathogenesis, are often related to the efficacy of the haemostasis. Our aim in this study was to verify whether the use of the new LigaSure haemostatic system is capable of reducing the incidence of these complications as well as operative times and length of hospital stay as compared to the conventional haemostatic procedures. Twenty-five patients were randomly assigned to thyroidectomy with LigaSureTM (group A), and 25 to total thyroidectomy using the conventional haemostasis procedures (group B). Of these, 39 were women and 11 men, with a mean age +/- standard deviation of 52.26 +/- 13.57 years. In both groups the thyroidectomy was performed according to the standard total thyroidectomy surgical technique entailing the placement of two aspiration drainages at the end of the operation. As regards the assessment of operative times, these were significantly lower in thyroidectomy with LigaSureTM compared to traditional thyroidectomy (duration: 60 +/- 14.8 min [range: 60-105) in group A versus 92.4 +/- 27.5 min [range: 70-150] in group B, p = 0.02). The total amount of fluid drained postoperatively was substantially similar in the two groups (145 +/- 80 cc in group A versus 140 +/- 64.1 cc in group B). The incidence of postoperative complications was also similar in the two groups. We had only one case of haemorrhage in a patient submitted to thyroidectomy with LigaSureTM, 8 cases of transitory hypocalcaemia, 3 of which in patients with LigaSure thyroidectomy and 5 in patients treated with traditional thyroidectomy (p = 0.42), 2 cases of stupor of the recurrent nerve (1 in group A and 1 in group B) and a single definitive recurrent lesion in a group B patient with

  11. Mask registration and wafer overlay

    NASA Astrophysics Data System (ADS)

    Lee, Chulseung; Bang, Changjin; Kim, Myoungsoo; Kang, Hyosang; Lee, Dohwa; Jeong, Woonjae; Lim, Ok-Sung; Yoon, Seunghoon; Jung, Jaekang; Laske, Frank; Parisoli, Lidia; Roeth, Klaus-Dieter; Robinson, John C.; Jug, Sven; Izikson, Pavel; Dinu, Berta; Widmann, Amir; Choi, DongSub

    2010-03-01

    Overlay continues to be one of the key challenges for lithography in advanced semiconductor manufacturing. It becomes even more challenging due to the continued shrinking of the device node. Some low k1 techniques, such as Double Exposure and Double Patterning also add additional loss of the overlay margin due to the fact that the single layer pattern is created based on more than 1 exposure. Therefore, the overlay between 2 exposures requires very tight overlay specification. Mask registration is one of the major contributors to wafer overlay, especially field related overlay. We investigated mask registration and wafer overlay by co-analyzing the mask data and the wafer overlay data. To achieve the accurate cohesive results, we introduced the combined metrology mark which can be used for both mask registration measurement as well as for wafer overlay measurement. Coincidence of both metrology marks make it possible to subtract mask signature from wafer overlay without compromising the accuracy due to the physical distance between measurement marks, if we use 2 different marks for both metrologies. Therefore, it is possible to extract pure scanner related signatures, and to analyze the scanner related signatures in details to in order to enable root cause analysis and ultimately drive higher wafer yield. We determined the exact mask registration error in order to decompose wafer overlay into mask, scanner, process and metrology. We also studied the impact of pellicle mounting by comparison of mask registration measurement pre-pellicle mounting and post-pellicle mounting in this investigation.

  12. Wafer handling and placement tool

    DOEpatents

    Witherspoon, Linda L.

    1988-01-05

    A spring arm tool is provided for clamp engaging and supporting wafers while the tool is hand held. The tool includes a pair of relatively swingable jaw element supporting support arms and the jaw elements are notched to enjoy multiple point contact with a wafer peripheral portion. Also, one disclosed form of the tool includes remotely operable workpiece ejecting structure carried by the jaw elements thereof.

  13. Note: Near infrared interferometric silicon wafer metrology.

    PubMed

    Choi, M S; Park, H M; Joo, K N

    2016-04-01

    In this investigation, two near infrared (NIR) interferometric techniques for silicon wafer metrology are described and verified with experimental results. Based on the transparent characteristic of NIR light to a silicon wafer, the fiber based spectrally resolved interferometry can measure the optical thickness of the wafer and stitching low coherence scanning interferometry can reconstruct entire surfaces of the wafer. PMID:27131722

  14. Spinner For Etching Of Semiconductor Wafers

    NASA Technical Reports Server (NTRS)

    Lombardi, Frank

    1989-01-01

    Simple, inexpensive apparatus coats semiconductor wafers uniformly with hydrofluoric acid for etching. Apparatus made in part from small commercial electric-fan motor. Features bowl that collects acid. Silicon wafer placed on platform and centered on axis; motor switched on. As wafer spins, drops of hydrofluoric acid applied from syringe. Centrifugal force spreads acid across wafer in fairly uniform sheet.

  15. GaAs wafer overlay performance affected by annealing heat treatment: II

    NASA Astrophysics Data System (ADS)

    Liu, Ying; Black, Iain

    2002-07-01

    Further analysis on how wafer distortion affecting the overlay performance during annealing treatment in GaAs wafer fabrication was conducted quantitatively using MONO-LITH software. The experimental results were decomposed as wafer translation, scaling at X and Y direction, rotation and orthogonality. The grid residual was used to describe non- correctable distortion of the wafers, which fits the equations given below: Residual equals Measured - Modeled, which is not a modeled component. The Vector Map displays distribution of error vectors over the wafer or field for various components or overall effect. Based on the component analysis that the misalignment caused by translation and scaling can be compensated by heat treatment if the wafer is placed at a favorable orientation. This can help mitigate the effects of substrate quality in manufactory.

  16. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    DOEpatents

    Bajikar, Sateesh S.; De Carlo, Francesco; Song, Joshua J.

    2001-01-01

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  17. Enhanced adhesion for LIGA microfabrication by using a buffer layer

    DOEpatents

    Bajikar, Sateesh S.; De Carlo, Francesco; Song, Joshua J.

    2004-01-27

    The present invention is an improvement on the LIGA microfabrication process wherein a buffer layer is applied to the upper or working surface of a substrate prior to the placement of a resist onto the surface of the substrate. The buffer layer is made from an inert low-Z material (low atomic weight), a material that absorbs secondary X-rays emissions from the substrate that are generated from the substrate upon exposure to a primary X-rays source. Suitable materials for the buffer layer include polyamides and polyimide. The preferred polyimide is synthesized form pyromellitic anhydride and oxydianiline (PMDA-ODA).

  18. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    NASA Astrophysics Data System (ADS)

    Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

    2014-08-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

  19. Wafer-Scale Precise Patterning of Organic Single-Crystal Nanowire Arrays via a Photolithography-Assisted Spin-Coating Method.

    PubMed

    Deng, Wei; Zhang, Xiujuan; Wang, Liang; Wang, Jincheng; Shang, Qixun; Zhang, Xiaohong; Huang, Liming; Jie, Jiansheng

    2015-12-01

    A photolithography-assisted spin-coating approach is developed to produce single-crystal organic nanowire (NW) arrays at designated locations with high precision and high efficiency. This strategy enables the large-scale fabrication of organic NW arrays with nearly the same accuracy, reliability, and flexibility as photolithography. The high mobilities of the organic NWs enable the control of the switch of multicolored light-emitting devices with good stability.

  20. Development of Megasonic cleaning for silicon wafers. Final report

    SciTech Connect

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  1. Fabrication of Compound Refractive X-ray Lenses Using LIGA Process and Performance Tests

    SciTech Connect

    Lee, Jin Pyoung; Kim, Guk Bae; Kim, Jong Hyun; Chang, Suk Sang; Lee, Sang Joon

    2007-01-19

    Recent advances of X-ray microscopy technology enable the visualization of some micro/nano-scale objects which optical microscopy and electron microscopy cannot be used to observe. The X-ray microscopy can be applied to observe the internal structure of a thicker sample than the electron microscopy can, and its spatial resolution is higher than that of the optical microscopy. Moreover, it has a powerful element specific imaging ability. For further improving the X-ray microscope, it is indispensable to make X-ray optics for focusing X-rays more effectively. Recently, various X-ray lenses such as diffraction lenses of FZP(Fresnel zone plate) and spatter-sliced FZT, total reflection lenses of K-B(Kirkpatrick-Baez) mirror and Wolter mirror, and refractive lens of CRL(compound refractive lens) were introduced. Compared with the other types of lenses, CRL is easy to fabricate and handle. In this study, we designed and fabricated various types of CRLs using LIGA(LIthographie, Galvanoformung, Abformtechnik) process, and used PMMA(Poly(methyl methacrylate)) material as the material of CRL. Their performances are tested with varying parameters such as parabolic/kinoform shape, radius of curvature, wall thickness between adjacent lenses, and width of lenses. The performance tests were carried out by using a simple synchrotron X-ray imaging method. The tests results revealed that hard x-rays could be condensed well by the CRL of PMMA material at the focal point we expect We captured sample images one-dimensionally magnified by CRLs. Furthermore, we found which parameter is more effective for enhancing focus efficiency and which parameter should be considered more carefully in the fabrication process of LIGA.

  2. Wafer sampling by regression for systematic wafer variation detection

    NASA Astrophysics Data System (ADS)

    Moon, Byungsool; McNames, James; Whitefield, Bruce; Rudolph, Paul; Zola, Jeff

    2005-05-01

    In-line measurements are used to monitor semiconductor manufacturing processes for excessive variation using statistical process control (SPC) chart techniques. Systematic spatial wafer variation often occurs in a recognizable pattern across the wafer that is characteristic of a particular manufacturing step. Visualization tools are used to associate these patterns with specific manufacturing steps preceding the measurement. Acquiring the measurements is an expensive and slow process. The number of sites measured on a wafer must be minimized while still providing sufficient data to monitor the process. We address two key challenges to effective wafer-level monitoring. The first challenge is to select a small sample of inspection sites that maximize detection sensitivity to the patterns of interest, while minimizing the confounding effects of other types of wafer variation. The second challenge is to develop a detection algorithm that maximizes sensitivity to the patterns of interest without exceeding a user-specified false positive rate. We propose new sampling and detection methods. Both methods are based on a linear regression model with distinct and orthogonal components. The model is flexible enough to include many types of systematic spatial variation across the wafer. Because the components are orthogonal, the degree of each type of variation can be estimated and detected independently with very few samples. A formal hypothesis test can then be used to determine whether specific patterns are present. This approach enables one to determine the sensitivity of a sample plan to patterns of interest and the minimum number of measurements necessary to adequately monitor the process.

  3. GEM-type detectors using LIGA and etchable glass technologies

    SciTech Connect

    Ahn, S.K.; Kim, J.G.; Perez-Mendez, V.; Chang, S.; Jackson, K.H.; Kadyk, J.A.; Wenzel, W.A.; Cho, G.

    2001-11-02

    Gas electron multipliers (GEMS) have been made by a deep X-ray lithography technique (LIGA process) using synchrotron radiation on polymethylmethacrylate (PMMA) and by UV processes using a UV etchable glass. Gain, stability and rate capability for these detectors are described.The LIGA detectors described consist of PMMA sheets of various thicknesses, 125mm to 350mm, and have 150mm x 150mm square holes spaced with a pitch of 300mm. Thin copper electrodes are plated on the top and bottom surfaces using a Damascene method, followed by electroless plating of the copper onto a palladium-tin base layer. For various thicknesses of PMMA measurements have been made of absolute gain vs. voltage, time stability of gain, and rate capability. The operating gas mixture was usually Ar/CO2 (70/30) gas, but some tests were also done using P10 gas. We also made GEM-like detectors using the UV etchable glass called Foturan, patterned by exposure to UV light and subsequent etching. A few measurements using these detectors will be reported, including avalanche gain and time stability.

  4. Characterization of Sidewall and Planar Surfaces of Electroformed LIGA Parts

    SciTech Connect

    PRASAD,SOMURI V.; HALL,AARON C.; DUGGER,MICHAEL T.

    2000-10-01

    The nature of surfaces and the way they interact with each other during sliding contact can have a direct bearing on the performance of a microelectromechanical (MEMS) device. Therefore, a study was undertaken to characterize the surfaces of LIGA fabricated Ni and Cu components. Sidewall and planar surfaces were examined by scanning electron microscopy (SEM) and atomic force microscopy (AFM). Surface roughness was quantified using the AFM. Post-processing (e.g. lapping, removal of polymer film) can profoundly influence the morphology of LIGA components. Edge rounding and smearing of ductile materials during lapping can result in undesirable sidewall morphologies. By judicious selection of AFM scan sizes, the native roughness ({approximately}10 nm RMS) can be distinguished from that arising due to post processing, e.g. scratches, debris, polymer films. While certain processing effects on morphology such as those due to lapping or release etch can be controlled, the true side wall morphology appears to be governed by the morphology of the polymer mold or by the electroforming process itself, and may be much less amenable to modification.

  5. Wafer characteristics via reflectometry and wafer processing apparatus and method

    DOEpatents

    Sopori, Bhushan L.

    2007-07-03

    An exemplary system includes a measuring device to acquire non-contact thickness measurements of a wafer and a laser beam to cut the wafer at a rate based at least in part on one or more thicknesses measurements. An exemplary method includes illuminating a substrate with radiation, measuring at least some radiation reflected from the substrate, determining one or more cutting parameters based at least in part on the measured radiation and cutting the substrate using the one or more cutting parameters. Various other exemplary methods, devices, systems, etc., are also disclosed.

  6. Heating device for semiconductor wafers

    DOEpatents

    Vosen, S.R.

    1999-07-27

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernible pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light. 4 figs.

  7. Heating device for semiconductor wafers

    DOEpatents

    Vosen, Steven R.

    1999-01-01

    An apparatus for heat treating semiconductor wafers is disclosed. The apparatus includes a heating device which contains an assembly of light energy sources for emitting light energy onto a wafer. In particular, the light energy sources are positioned such that many different radial heating zones are created on a wafer being heated. For instance, in one embodiment, the light energy sources form a spiral configuration. In an alternative embodiment, the light energy sources appear to be randomly dispersed with respect to each other so that no discernable pattern is present. In a third alternative embodiment of the present invention, the light energy sources form concentric rings. Tuning light sources are then placed in between the concentric rings of light.

  8. Selective area growth of InP in shallow trench isolation on large scale Si(001) wafer using defect confinement technique

    NASA Astrophysics Data System (ADS)

    Merckling, C.; Waldron, N.; Jiang, S.; Guo, W.; Richard, O.; Douhard, B.; Moussa, A.; Vanhaeren, D.; Bender, H.; Collaert, N.; Heyns, M.; Thean, A.; Caymax, M.; Vandervorst, W.

    2013-07-01

    Heterogeneous integration of III-V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III-V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III-V virtual substrates on large-scale Si substrates.

  9. LIGA-based microsystem manufacturing:the electrochemistry of through-mold depostion and material properties.

    SciTech Connect

    Kelly, James J. (Sandia National Laboratories, Livermore, CA); Goods, Steven Howard (Sandia National Laboratories, Livermore, CA)

    2005-06-01

    The report presented below is to appear in ''Electrochemistry at the Nanoscale'', Patrik Schmuki, Ed. Springer-Verlag, (ca. 2005). The history of the LIGA process, used for fabricating dimensional precise structures for microsystem applications, is briefly reviewed, as are the basic elements of the technology. The principal focus however, is on the unique aspects of the electrochemistry of LIGA through-mask metal deposition and the generation of the fine and uniform microstructures necessary to ensure proper functionality of LIGA components. We draw from both previously published work by external researchers in the field as well as from published and unpublished studies from within Sandia.

  10. Smoother Scribing of Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Danyluk, S.

    1986-01-01

    Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

  11. Fabrication of Spiral Micro-Coil Utilizing LIGA Process

    NASA Astrophysics Data System (ADS)

    Shimada, Osamu; Kusumi, Shinji; Mekaru, Harutaka; Sato, Noriaki; Shimizu, Masami; Yamashita, Michiru; Hattori, Tadashi

    We developed a method for fabricating a three-dimensional spiral micro-inductor with high inductance using the LIGA process. The spiral inductor created had a diameter of 0.5mm, and a length of 1mm. The width of the spiral line was 10µm, the pitch was 20µm, and the number of turns was 15. It was made of plated copper. The master was a brass round bar coated with PMMA resist. Deep X-ray lithography was employed to fabricate a master for a metallic mold at the NewSUBARU synchrotron radiation facility, University of Hyogo. The inductor core was made of resin by injection molding. It has a spiral micro flute on the surface. We chose the worm injection molding technique in order to avoid the parting line across the spiral line. The worm injection molding was the method─for demolding the work such as that used in loosening a screw.

  12. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    NASA Technical Reports Server (NTRS)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  13. Low-loss LIGA-micromachined conductor-backed coplanar waveguide.

    SciTech Connect

    Forman, Michael A.

    2004-12-01

    A mesoscale low-loss LIGA-micromachined conductor-backed coplanar waveguide is presented. The 517 {micro}m lines are the tallest uniplanar LIGA-fabricated microwave transmission lines to date, as well as the first to be constructed of copper rather than nickel. The conductor-backed micromachined CPW on quartz achieves a measured attenuation of 0.064 dB/cm at 15.5 GHz.

  14. Temperature Dependent Electrical Properties of PZT Wafer

    NASA Astrophysics Data System (ADS)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  15. Deposition uniformity inspection in IC wafer surface

    NASA Astrophysics Data System (ADS)

    Li, W. C.; Lin, Y. T.; Jeng, J. J.; Chang, C. L.

    2014-03-01

    This paper focuses on the task of automatic visual inspection of color uniformity on the surface of integrated circuits (IC) wafers arising from the layering process. The oxide thickness uniformity within a given wafer with a desired target thickness is of great importance for modern semiconductor circuits with small oxide thickness. The non-uniform chemical vapor deposition (CVD) on a wafer surface will proceed to fail testing in Wafer Acceptance Test (WAT). Early detection of non-uniform deposition in a wafer surface can reduce material waste and improve production yields. The fastest and most low-priced inspection method is a machine vision-based inspection system. In this paper, the proposed visual inspection system is based on the color representations which were reflected from wafer surface. The regions of non-uniform deposition present different colors from the uniform background in a wafer surface. The proposed inspection technique first learns the color data via color space transformation from uniform deposition of normal wafer surfaces. The individual small region statistical comparison scheme then proceeds to the testing wafers. Experimental results show that the proposed method can effectively detect the non-uniform deposition regions on the wafer surface. The inspection time of the deposited wafers is quite compatible with the atmospheric pressure CVD time.

  16. Support apparatus for semiconductor wafer processing

    DOEpatents

    Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

    2003-06-10

    A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

  17. Wafer Manufacturing and Slicing Using Wiresaw

    NASA Astrophysics Data System (ADS)

    Kao, Imin; Chung, Chunhui; Moreno Rodriguez, Roosevelt

    Wafer manufacturing (or wafer production) refers to a series of modern manufacturing processes of producing single-crystalline or poly-crystalline wafers from crystal ingot (or boule) of different sizes and materials. The majority of wafers are single-crystalline silicon wafers used in microelectronics fabrication although there is increasing importance in slicing poly-crystalline photovoltaic (PV) silicon wafers as well as wafers of different materials such as aluminum oxide, lithium niobate, quartz, sapphire, III-V and II-VI compounds, and others. Slicing is the first major post crystal growth manufacturing process toward wafer production. The modern wiresaw has emerged as the technology for slicing various types of wafers, especially for large silicon wafers, gradually replacing the ID saw which has been the technology for wafer slicing in the last 30 years of the 20th century. Modern slurry wiresaw has been deployed to slice wafers from small to large diameters with varying wafer thickness characterized by minimum kerf loss and high surface quality. The needs for slicing large crystal ingots (300 mm in diameter or larger) effectively with minimum kerf losses and high surface quality have made it indispensable to employ the modern slurry wiresaw as the preferred tool for slicing. In this chapter, advances in technology and research on the modern slurry wiresaw manufacturing machines and technology are reviewed. Fundamental research in modeling and control of modern wiresaw manufacturing process are required in order to understand the cutting mechanism and to make it relevant for improving industrial processes. To this end, investigation and research have been conducted for the modeling, characterization, metrology, and control of the modern wiresaw manufacturing processes to meet the stringent precision requirements of the semiconductor industry. Research results in mathematical modeling, numerical simulation, experiments, and composition of slurry versus wafer

  18. An aluminum resist substrate for microfabrication by LIGA.

    SciTech Connect

    Kelly, James J.; Boehme, Dale R.; Hauck, Cheryl A.; Yang, Chu-Yeu Peter; Hunter, Luke L.; Griffiths, Stewart K.; McLean, Dorrance E.; Aigeldinger, Georg; Hekmaty, Michelle A.; Hachman, John T.; Losey, Matthew W.; Skala, Dawn M.; Korellis, John S.; Friedmann, Thomas Aquinas; Yang, Nancy Y. C.; Lu, Wei-Yang

    2005-04-01

    Resist substrates used in the LIGA process must provide high initial bond strength between the substrate and resist, little degradation of the bond strength during x-ray exposure, acceptable undercut rates during development, and a surface enabling good electrodeposition of metals. Additionally, they should produce little fluorescence radiation and give small secondary doses in bright regions of the resist at the substrate interface. To develop a new substrate satisfying all these requirements, we have investigated secondary resist doses due to electrons and fluorescence, resist adhesion before exposure, loss of fine features during extended development, and the nucleation and adhesion of electrodeposits for various substrate materials. The result of these studies is a new anodized aluminum substrate and accompanying methods for resist bonding and electrodeposition. We demonstrate successful use of this substrate through all process steps and establish its capabilities via the fabrication of isolated resist features down to 6 {micro}m, feature aspect ratios up to 280 and electroformed nickel structures at heights of 190 to 1400 {micro}m. The minimum mask absorber thickness required for this new substrate ranges from 7 to 15 {micro}m depending on the resist thickness.

  19. Micro cycloid-gear system fabricated by multiexposure LIGA technique

    NASA Astrophysics Data System (ADS)

    Hirata, Toru; Chung, Song-Jo; Hein, Herbert; Akashi, Tomoyuki; Mohr, Juergen

    1999-09-01

    In this paper, a prototype of 2 mm-diameter micro-cycloid gear system fabricated by the multi-exposure LIGA technique is presented. The entire gear system consists of a casing and three vertically stacked disks and gears. Each part is composed of three different levels. The first level, 40 micrometers high, was fabricated by UV-lithography, and the second as well as the third level, 195 micrometers and 250 micrometers high respectively, were processed by aligned deep X-ray lithography (DXL). The alignment error between two DXL- processed layers was measured, and the results have turned out to be within +/- 5 micrometers range. As a result of the height control process by the mechanical surface machining, the deviation of structural height has been maintained within +/- 3 micrometers range for the UV-lithography-processed structures, and +/- 10 micrometers for the DXL-processed structures. Further the tests of gear assembly were implemented with 125 micrometers -diameter glass fiber, by using a die-bonding machine with vacuum gripper under stereo- microscope. Finally the dynamic tests of the gear system were successfully conducted with the mechanical torque input by an electrical motor. A proper rotational speed reduction was observed in the operational input range of 3 to 1500 rpm with the designed gear ratio of 18.

  20. Phase shift reflectometry for wafer inspection

    NASA Astrophysics Data System (ADS)

    Peng, Kuang; Cao, Yiping; Li, Hongru; Sun, Jianfei; Bourgade, Thomas; Asundi, Anand Krishna

    2015-07-01

    In 3D measurement, specular surfaces can be reconstructed by phase shift reflectometry and the system configuration is simple. In this paper, a wafer is measured for industrial inspection to make sure the quality of the wafer by calibrating, phase unwrapping, slope calculation and integration. The profile result of the whole wafer can be reconstructed and it is a curve. As the height of the structures on the wafer is the target we are interested in, by fitting and subtracting the curve surface, the structures on the wafer can be observed on the flat surface. To confirm the quality farther, a part of the wafer is captured and zoomed in to be detected so that the difference between two structures can be observed better.

  1. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    DOEpatents

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  2. Performance Evaluations of Ceramic Wafer Seals

    NASA Technical Reports Server (NTRS)

    Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

    2006-01-01

    Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

  3. Stress Voiding During Wafer Processing

    SciTech Connect

    Yost, F.G.

    1999-03-01

    Wafer processing involves several heating cycles to temperatures as high as 400 C. These thermal excursions are known to cause growth of voids that limit reliability of parts cut from the wafer. A model for void growth is constructed that can simulate the effect of these thermal cycles on void growth. The model is solved for typical process steps and the kinetics and extent of void growth are determined for each. It is shown that grain size, void spacing, and conductor line width are very important in determining void and stress behavior. For small grain sizes, stress relaxation can be rapid and can lead to void shrinkage during subsequent heating cycles. The effect of rapid quenching from process temperatures is to suppress void growth but induce large remnant stress in the conductor line. This stress can provide the driving force for void growth during storage even at room temperature. For isothermal processes the model can be solved analytically and estimates of terminal void size a nd lifetime are obtained.

  4. A model for reaction-assisted polymer dissolution in LIGA.

    SciTech Connect

    Larson, Richard S.

    2004-05-01

    A new chemically-oriented mathematical model for the development step of the LIGA process is presented. The key assumption is that the developer can react with the polymeric resist material in order to increase the solubility of the latter, thereby partially overcoming the need to reduce the polymer size. The ease with which this reaction takes place is assumed to be determined by the number of side chain scissions that occur during the x-ray exposure phase of the process. The dynamics of the dissolution process are simulated by solving the reaction-diffusion equations for this three-component, two-phase system, the three species being the unreacted and reacted polymers and the solvent. The mass fluxes are described by the multicomponent diffusion (Stefan-Maxwell) equations, and the chemical potentials are assumed to be given by the Flory-Huggins theory. Sample calculations are used to determine the dependence of the dissolution rate on key system parameters such as the reaction rate constant, polymer size, solid-phase diffusivity, and Flory-Huggins interaction parameters. A simple photochemistry model is used to relate the reaction rate constant and the polymer size to the absorbed x-ray dose. The resulting formula for the dissolution rate as a function of dose and temperature is ?t to an extensive experimental data base in order to evaluate a set of unknown global parameters. The results suggest that reaction-assisted dissolution is very important at low doses and low temperatures, the solubility of the unreacted polymer being too small for it to be dissolved at an appreciable rate. However, at high doses or at higher temperatures, the solubility is such that the reaction is no longer needed, and dissolution can take place via the conventional route. These results provide an explanation for the observed dependences of both the dissolution rate and its activation energy on the absorbed dose.

  5. Mechanics of the pad-abrasive-wafer contact in chemical mechanical polishing

    NASA Astrophysics Data System (ADS)

    Bozkaya, Dincer

    2009-12-01

    In chemical mechanical polishing (CMP), a rigid wafer is forced on a rough, elastomeric polishing pad, while a slurry containing abrasive particles flows through the interface. The applied pressure on the wafer is carried partially by the 2-body pad-wafer contact (direct contact) and partially by the 3-body contact of pad, wafer and abrasive particles ( particle contact). The fraction of the applied pressure carried by particle contacts is an important factor affecting the material removal rate (MRR) as the majority of the material is removed by the abrasive particles trapped between the pad asperities and the wafer. In this thesis, the contact of a rough, deformable pad and a smooth, rigid wafer in the presence of rigid abrasive particles at the contact interface is investigated by using contact mechanics and finite element (FE) modeling. The interactions between the pad, the wafer and the abrasive particles are modeled at different scales of contact, starting from particle level interactions, and gradually expanding the contact scale to the multi-asperity contact of pad and wafer. The effect of surface forces consisting of van der Waals and electrical double layer forces acting between the wafer and the abrasive particles are also investigated in this work. The wear rate due to each abrasive particle is calculated based on the wafer-abrasive particle contact force, and by considering adhesive and abrasive wear mechanisms. A passivated layer on the wafer surface with a hardness and thickness determined by the chemical effects is modeled, in order to characterize the effect of chemical reactions between slurry and wafer on the MRR. The model provides accurate predictions for the MRR as a function of pad related parameters; pad elastic modulus, pad porosity and pad topography, particle related parameters; particle size and concentration, and slurry related parameters; slurry pH, thickness and hardness of the passivated surface layer of wafer. A good qualitative

  6. A MEMS-Based Micro Biopsy Actuator for the Capsular Endoscope Using LiGA Process

    NASA Astrophysics Data System (ADS)

    Park, Sunkil; Koo, Kyo-In; Kim, Gil-Sub; Bang, Seoung Min; Song, Si Young; Chu, Chong Nam; Jeon, Doyoung; Cho, Dongil ``Dan''

    2007-01-01

    This paper presents a LiGA (German acronym for LIthografie, Galvanoformung, Abformung) based micro biopsy actuator for the capsular endoscope. The proposed fabricated actuator aims to extract sample tissues inside small gastric intestines, that cannot be reached by conventional biopsy. The actuator size is 10 mm in diameter and 1.8 mm in length. The mechanism is of a slider-crank type. The actuator consists of trigger, rotational module, and micro biopsy tool. The core components are fabricated using the LiGA process, for overcoming the limitations in accuracy of conventional precision machining.

  7. Methane production using resin-wafer electrodeionization

    DOEpatents

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  8. Cryogenic wafer prober for Josephson devices

    SciTech Connect

    Geary, J.; Vella-Coleiro, G.

    1983-05-01

    A wafer probing system has been built for the testing of Josephson junction devices at helium temperature. A mechanism moves a probe card from one position to another on a two inch wafer while immersed in liquid helium. The mechanism is actuated by shafts which connect to stepper motors positioned above the helium dewar. A positioning accuracy of + or - 50 ..mu..m at the probe tips is achieved. The replaceable probe card is all ceramic and carries 120 rigidly mounted palladium-alloy needles, arranged in signal-ground pairs and positioned in an array which matches the pad design of the particular device under test. Controlled impedance transmission lines are maintained all the way to the wafer's surface. A computer interface is included so that probing of a whole wafer can be conducted under software control. The system is intended for routine testing of Josephson devices in wafer form as well as for testing very large numbers of individual junctions.

  9. Models to relate wafer geometry measurements to in-plane distortion of wafers

    NASA Astrophysics Data System (ADS)

    Turner, Kevin T.; Vukkadala, Pradeep; Sinha, Jaydeep K.

    2016-04-01

    Achieving satisfactory overlay is increasingly challenging as feature sizes are reduced and allowable overlay budgets shrink to several nanometers and below. Overlay errors induced by wafer processing, such as film deposition and etching, constitute a meaningful fraction of overlay budgets. Wafer geometry measurements provide the opportunity to quantify stress-induced distortions at the wafer level and provide information that can be used in a feedback mode to alter wafer processing or in a feed-forward mode to set wafer-specific corrections in the lithography tool. In order for such feed-forward schemes based on wafer geometry to be realized, there is a need for mechanics models that relate in-plane distortion of a chucked wafer to the out-of-plane distortion of a wafer in a free state. Here, a simple analytical model is presented that shows the stress-induced component of overlay is correlated to a corrected local wafer slope metric for a wide range of cases. The analytical model is validated via finite element (FE) simulations of wafers with nonuniform stress distributions. Furthermore, FE modeling is used here to examine the effect of the spatial wavelength of stress variation on the connection between slope and the wafer stress-induced component of overlay.

  10. Harmonic versus LigaSure hemostasis technique in thyroid surgery: A meta-analysis

    PubMed Central

    Upadhyaya, Arun; Hu, Tianpeng; Meng, Zhaowei; Li, Xue; He, Xianghui; Tian, Weijun; Jia, Qiang; Tan, Jian

    2016-01-01

    Harmonic scalpel and LigaSure vessel sealing systems have been suggested as options for saving surgical time and reducing postoperative complications. The aim of the present meta-analysis was to compare surgical time, postoperative complications and other parameters between them in for the open thyroidectomy procedure. Studies were retrieved from MEDLINE, Cochrane Library, EMBASE and ISI Web of Science until December 2015. All the randomized controlled trials (RCTs) comparing Harmonic scalpel and LigaSure during open thyroidectomy were selected. Following data extraction, statistical analyses were performed. Among the 24 studies that were evaluated for eligibility, 7 RCTs with 981 patients were included. The Harmonic scalpel significantly reduced surgical time compared with LigaSure techniques (8.79 min; 95% confidence interval, −15.91 to −1.67; P=0.02). However, no significant difference was observed for the intraoperative blood loss, postoperative blood loss, duration of hospital stay, thyroid weight and serum calcium level postoperatively in either group. The present meta-analysis indicated superiority of Harmonic Scalpel only in terms of surgical time compared with LigaSure hemostasis techniques in open thyroid surgery. PMID:27446546

  11. Three wafer stacking for 3D integration.

    SciTech Connect

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  12. Development of megasonic cleaning for silicon wafers

    NASA Technical Reports Server (NTRS)

    Mayer, A.

    1980-01-01

    A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

  13. Total x-ray power measurements in the Sandia LIGA program.

    SciTech Connect

    Malinowski, Michael E. (Sandia National Laboratories, Livermore, CA); Ting, Aili (Sandia National Laboratories, Livermore, CA)

    2005-08-01

    Total X-ray power measurements using aluminum block calorimetry and other techniques were made at LIGA X-ray scanner synchrotron beamlines located at both the Advanced Light Source (ALS) and the Advanced Photon Source (APS). This block calorimetry work was initially performed on the LIGA beamline 3.3.1 of the ALS to provide experimental checks of predictions of the LEX-D (LIGA Exposure- Development) code for LIGA X-ray exposures, version 7.56, the version of the code in use at the time calorimetry was done. These experiments showed that it was necessary to use bend magnet field strengths and electron storage ring energies different from the default values originally in the code in order to obtain good agreement between experiment and theory. The results indicated that agreement between LEX-D predictions and experiment could be as good as 5% only if (1) more accurate values of the ring energies, (2) local values of the magnet field at the beamline source point, and (3) the NIST database for X-ray/materials interactions were used as code inputs. These local magnetic field value and accurate ring energies, together with NIST database, are now defaults in the newest release of LEX-D, version 7.61. Three dimensional simulations of the temperature distributions in the aluminum calorimeter block for a typical ALS power measurement were made with the ABAQUS code and found to be in good agreement with the experimental temperature data. As an application of the block calorimetry technique, the X-ray power exiting the mirror in place at a LIGA scanner located at the APS beamline 10 BM was measured with a calorimeter similar to the one used at the ALS. The overall results at the APS demonstrated the utility of calorimetry in helping to characterize the total X-ray power in LIGA beamlines. In addition to the block calorimetry work at the ALS and APS, a preliminary comparison of the use of heat flux sensors, photodiodes and modified beam calorimeters as total X-ray power

  14. Temperature Sensitivity Conferred by ligA Alleles from Psychrophilic Bacteria upon Substitution in Mesophilic Bacteria and a Yeast Species

    PubMed Central

    Pankowski, Jarosław A.; Puckett, Stephanie M.

    2016-01-01

    We have assembled a collection of 13 psychrophilic ligA alleles that can serve as genetic elements for engineering mesophiles to a temperature-sensitive (TS) phenotype. When these ligA alleles were substituted into Francisella novicida, they conferred a TS phenotype with restrictive temperatures between 33 and 39°C. When the F. novicida ligA hybrid strains were plated above their restrictive temperatures, eight of them generated temperature-resistant variants. For two alleles, the mutations that led to temperature resistance clustered near the 5′ end of the gene, and the mutations increased the predicted strength of the ribosome binding site at least 3-fold. Four F. novicida ligA hybrid strains generated no temperature-resistant variants at a detectable level. These results suggest that multiple mutations are needed to create temperature-resistant variants of these ligA gene products. One ligA allele was isolated from a Colwellia species that has a maximal growth temperature of 12°C, and this allele supported growth of F. novicida only as a hybrid between the psychrophilic and the F. novicida ligA genes. However, the full psychrophilic gene alone supported the growth of Salmonella enterica, imparting a restrictive temperature of 27°C. We also tested two ligA alleles from two Pseudoalteromonas strains for their ability to support the viability of a Saccharomyces cerevisiae strain that lacked its essential gene, CDC9, encoding an ATP-dependent DNA ligase. In both cases, the psychrophilic bacterial alleles supported yeast viability and their expression generated TS phenotypes. This collection of ligA alleles should be useful in engineering bacteria, and possibly eukaryotic microbes, to predictable TS phenotypes. PMID:26773080

  15. Adhesive wafer bonding using a molded thick benzocyclobutene layer for wafer-level integration of MEMS and LSI

    NASA Astrophysics Data System (ADS)

    Makihata, M.; Tanaka, S.; Muroyama, M.; Matsuzaki, S.; Yamada, H.; Nakayama, T.; Yamaguchi, U.; Mima, K.; Nonomura, Y.; Fujiyoshi, M.; Esashi, M.

    2011-08-01

    This paper describes a wafer bonding process using a 50 µm thick benzocyclobutene (BCB) layer which has vias and metal electrodes. The vias were fabricated by molding BCB using a glass mold. During the molding, worm-like voids grew between BCB and the mold due to the shrinkage of polymerizing BCB. They were completely removed by subsequent reflowing in N2. After patterning Al on the reflowed BCB for the electrodes and via connections, bonding with a glass substrate was performed. Voidless bonding without damage in the vias and electrodes was achieved. Through the process, the control of the polymerization degree of BCB is important, and thus the polymerization degree was evaluated by Fourier transform infrared spectroscopy. The developed process is useful for the wafer-bonding-based integration of different devices, e.g. micro electro mechanical systems and large-scale integrated circuits.

  16. Forming electrical interconnections through semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Anthony, T. R.

    1981-01-01

    An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

  17. Modelling deformation and fracture in confectionery wafers

    NASA Astrophysics Data System (ADS)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  18. Modelling deformation and fracture in confectionery wafers

    SciTech Connect

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  19. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    NASA Technical Reports Server (NTRS)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  20. Analyzes Data from Semiconductor Wafers

    2002-07-23

    This program analyzes reflectance data from semiconductor wafers taken during the deposition or evolution of a thin film, typically via chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). It is used to determine the growth rate and optical constants of the deposited thin films using a virtual interface concept. Growth rates and optical constants of multiple-layer structures is possible by selecting appropriate sections in the reflectance vs time waveform. No prior information or estimatesmore » of growth rates and materials properties is required if an absolute reflectance waveform is used. If the optical constants of a thin film are known, then the growth rate may be extracted from a relative reflectance data set. The analysis is valid for either s or p polarized light at any incidence angle and wavelength. The analysis package is contained within an easy-to-use graphical user interface. The program is based on the algorighm described in the following two publications: W.G. Breiland and K.P. Killen, J. Appl. Phys. 78 (1995) 6726, and W. G. Breiland, H.Q. Hou, B.E. Hammons, and J.F. Klem, Proc. XXVIII SOTAPOCS Symp. Electrochem. Soc. San Diego, May 3-8, 1998. It relies on the fact that any multiple-layer system has a reflectance spectrum that is mathematically equivalent to a single-layer thin film on a virtual substrate. The program fits the thin film reflectance with five adjustable parameters: 1) growth rate, 2) real part of complex refractive index, 3) imaginary part of refractive index, 4) amplitude of virtual interface reflectance, 5) phase of virtual interface reflectance.« less

  1. The Imaging Properties of a Silicon Wafer X-Ray Telescope

    NASA Technical Reports Server (NTRS)

    Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

    1994-01-01

    Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

  2. Porous solid ion exchange wafer for immobilizing biomolecules

    DOEpatents

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  3. Meta-analysis of randomized controlled trials comparing outcomes for stapled hemorrhoidopexy versus LigaSure hemorrhoidectomy for symptomatic hemorrhoids in adults.

    PubMed

    Lee, Ko-Chao; Chen, Hong-Hwa; Chung, Kuan-Chih; Hu, Wan-Hsiang; Chang, Chia-Lo; Lin, Shung-Eing; Tsai, Kai-Lung; Lu, Chien-Chang

    2013-01-01

    This purpose of the meta-analysis was to compare treatment outcomes for adult patients with symptomatic hemorrhoids treated by stapled hemorrhoidopexy or LigaSure hemorrhoidectomy. A search of public medical databases was made to identify randomized controlled trials (RCTs) comparing stapled hemorrhoidopexy (SH) with LigaSure hemorrhoidectomy (LH) for the treatment of adult patients with symptomatic grade 3 and grade 4 hemorrhoids. Postoperative pain as measured using a visual analog scale was the primary outcome, and rate of recurrent prolapse and postoperative bleeding were secondary outcome measures. Four RCTs were identified that met the inclusion criteria. Data for the pooled outcomes were analyzed using odds ratio (OR) analysis. None of the studies in the analysis indicated a significant difference between SH and LH for the outcomes VAS pain score, recurrence rate, or postoperative bleeding. Pooled analysis revealed a significant OR in favor of the SH method for recurrent prolapse (OR = 5.529, P = 0.016) for up to 2 years after surgery. No significant differences between the two methods were identified for VAS pain scores (OR = -1.060, P = 0.149) or postoperative bleeding OR = 1.188, P = 0.871). Pooled analysis of RCT results comparing SH to LH for symptomatic hemorrhoids revealed a significantly greater incidence of recurrent prolapse for SH. The two techniques were associated with similar levels of postoperative pain and postoperative bleeding.

  4. Design and simulation of non-resonant 1-DOF drive mode and anchored 2-DOF sense mode gyroscope for implementation using UV-LIGA process

    NASA Astrophysics Data System (ADS)

    Verma, Payal; Gopal, Ram; Butt, M. A.; Khonina, Svetlana N.; Skidanov, Roman V.

    2016-03-01

    This paper presents the design and simulation of a 3-DOF (degree-of-freedom) MEMS gyroscope structure with 1-DOF drive mode and anchored 2-DOF sense mode, based on UV-LIGA technology. The 3-DOF system has the drive resonance located in the flat zone between the two sense resonances. It is an inherently robust structure and offers a high sense frequency band width and high gain without much scaling down the mass on which the sensing comb fingers are attached and it is also immune to process imperfections and environmental conditions. The design is optimized to be compatible with the UV-LIGA process, having 9 μm thick nickel as structural layer. The electrostatic gap between the drive comb fingers is 4 μm and sense comb fingers gap are 4 μm/12 μm. The damping effect is considered by assuming the flexures and the proof mass suspended about 6 μm over the substrate. Accordingly, mask is designed in L-Edit software.

  5. Improvement of focus accuracy on processed wafer

    NASA Astrophysics Data System (ADS)

    Higashibata, Satomi; Komine, Nobuhiro; Fukuhara, Kazuya; Koike, Takashi; Kato, Yoshimitsu; Hashimoto, Kohji

    2013-04-01

    As feature size shrinkage in semiconductor device progress, process fluctuation, especially focus strongly affects device performance. Because focus control is an ongoing challenge in optical lithography, various studies have sought for improving focus monitoring and control. Focus errors are due to wafers, exposure tools, reticles, QCs, and so on. Few studies are performed to minimize the measurement errors of auto focus (AF) sensors of exposure tool, especially when processed wafers are exposed. With current focus measurement techniques, the phase shift grating (PSG) focus monitor 1) has been already proposed and its basic principle is that the intensity of the diffraction light of the mask pattern is made asymmetric by arranging a π/2 phase shift area on a reticle. The resist pattern exposed at the defocus position is shifted on the wafer and shifted pattern can be easily measured using an overlay inspection tool. However, it is difficult to measure shifted pattern for the pattern on the processed wafer because of interruptions caused by other patterns in the underlayer. In this paper, we therefore propose "SEM-PSG" technique, where the shift of the PSG resist mark is measured by employing critical dimension-scanning electron microscope (CD-SEM) to measure the focus error on the processed wafer. First, we evaluate the accuracy of SEM-PSG technique. Second, by applying the SEM-PSG technique and feeding the results back to the exposure, we evaluate the focus accuracy on processed wafers. By applying SEM-PSG feedback, the focus accuracy on the processed wafer was improved from 40 to 29 nm in 3σ.

  6. Integrating III-V compound semiconductors with silicon using wafer bonding

    NASA Astrophysics Data System (ADS)

    Zhou, Yucai

    2000-12-01

    From Main Street to Wall Street, everyone has felt the effects caused by the Internet revolution. The Internet has created a new economy in the New Information Age and has brought significant changes in both business and personal life. This revolution has placed strong demands for higher bandwidth and higher computing speed due to high data traffic on today's information highway. In order to alleviate this problem, growing interconnection bottlenecks in digital designs have to be solved. The most feasible and practical way is to replace the conventional electrical interconnect with an optical interconnect. Since silicon does not have the optical properties necessary to accommodate these optical interconnect requirements, III-V based devices, most of which are GaAs-based or InP-based, must be intimately interconnected with the Si circuit at chip level. This monolithic integration technology enables the development of both intrachip and interchip optical connectors to take advantage of the enormous bandwidth provided by both high-performance very-large-scale integrated (VLSI) circuits and allied fiber and free-space optical technologies. However, lattice mismatch and thermal expansion mismatches between III-V materials and Si create enormous challenges for developing a feasible technology to tackle this problem. Among all the available approaches today, wafer bonding distinguishes itself as the most promising technology for integration due to its ability to overcome the constraints of both lattice constant mismatch and thermal expansion coefficient differences and even strain due to the crystal orientation. We present our development of wafer bonding technology for integrating III-V with Si in my dissertation. First, the pick-and-place multiple-wafer bonding technology was introduced. Then we systematically studied the wafer bonding of GaAs and InP with Si. Both high temperature wafer fusion and low/room temperature (LT/RT) wafer bonding have been investigated for

  7. Intra-lot wafer by wafer overlay control using integrated and standalone metrology combined sampling

    NASA Astrophysics Data System (ADS)

    Choi, Young Sin; Nam, Young Sun; Lee, Dong Han; Lee, Jae Il; Kang, Young Seog; Jang, Se Yeon; Kong, Jeong Heung

    2016-03-01

    As overlay margin is getting tighter, traditional overlay correction method is not enough to secure more overlay margin without extended correction potential on lithography tool. Timely, the lithography tool has a capability of wafer to wafer correction. From these well-timed industry's preparations, the uncorrected overlay error from current sampling in a lot could be corrected for yield enhancement. In this paper, overlay budget break was performed prior to experiments with the purpose of estimating amount of overlay improvement. And wafer to wafer correction was simulated to the specified layer of a 2x node DRAM device. As a result, not only maximum 94.4% of residual variation improvement is estimated, but also recognized that more samplings to cover all wafer's behavior is inevitable. Integrated metrology with optimized sampling scheme was also introduced as a supportive method for more samplings.

  8. Cost-Effective Silicon Wafers for Solar Cells: Direct Wafer Enabling Terawatt Photovoltaics

    SciTech Connect

    2010-01-15

    Broad Funding Opportunity Announcement Project: 1366 is developing a process to reduce the cost of solar electricity by up to 50% by 2020—from $0.15 per kilowatt hour to less than $0.07. 1366’s process avoids the costly step of slicing a large block of silicon crystal into wafers, which turns half the silicon to dust. Instead, the company is producing thin wafers directly from molten silicon at industry-standard sizes, and with efficiencies that compare favorably with today’s state-of-the-art technologies. 1366’s wafers could directly replace wafers currently on the market, so there would be no interruptions to the delivery of these products to market. As a result of 1366’s technology, the cost of silicon wafers could be reduced by 80%.

  9. Wafer-size free-standing single-crystalline graphene device arrays

    NASA Astrophysics Data System (ADS)

    Li, Peng; Jing, Gaoshan; Zhang, Bo; Sando, Shota; Cui, Tianhong

    2014-08-01

    We report an approach of wafer-scale addressable single-crystalline graphene (SCG) arrays growth by using pre-patterned seeds to control the nucleation. The growth mechanism and superb properties of SCG were studied. Large array of free-standing SCG devices were realized. Characterization of SCG as nano switches shows excellent performance with life time (>22 000 times) two orders longer than that of other graphene nano switches reported so far. This work not only shows the possibility of producing wafer-scale high quality SCG device arrays but also explores the superb performance of SCG as nano devices.

  10. Wafer-fused semiconductor radiation detector

    DOEpatents

    Lee, Edwin Y.; James, Ralph B.

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  11. LIGA fabrication of high-aspect-ratio lobster-eye optics

    NASA Astrophysics Data System (ADS)

    Peele, Andrew G.; Irving, Thomas H.; Nugent, Keith A.; Mancini, Derrick C.; Moldovan, Nicolai A.; Christenson, Todd R.

    2001-11-01

    Lobster-eye optics are an exciting advance in the field of x-ray astronomy, specifically as focusing optics for wide field of view telescopes. In its simplest form the optic is a square packed array of square-channels. Typical channel dimensions are width 10 - 30 mm, length 300 - 1000 mm, and wall thickness of ~2 - 5 mm. These dimensions raise the question of whether such devices can be made in the deep x-ray LIGA regime. Following recent success in fabricating a low aspect ratio Lobster-eye structure, we discuss some of the parameters for, and production issues involved in making, a useful high aspect ratio Lobster-eye prototype. We report on our initial attempts to produce high aspect ratio Lobster-eye optics using the LIGA process with a Graphite substrate.

  12. Diamond-like nanocomposite coatings for LIGA-fabricated nickel alloy parts.

    SciTech Connect

    Prasad, Somuri V.; Scharf, Thomas W.

    2005-03-01

    A commercial plasma enhanced chemical vapor deposition (PECVD) technique with planetary substrate rotation was used to apply a thin (200-400 nm thick) conformal diamond-like carbon (DLC) coating (known as a diamond-like nanocomposite (DLN)) on LIGA fabricated Ni-Mn alloy parts. The PECVD technique is known to overcome the drawbacks associated with the line-of-sight nature of physical vapor deposition (PVD) and substrate heating inherent with traditional chemical vapor deposition (CVD). The purpose of the present study is to characterize the coverage, adhesion, and tribological (friction and wear) behavior of DLN coatings applied to planar and sidewall surfaces of small featured LIGA Ni-Mn fabricated parts, e.g. 280 {micro}m thick sidewalls. Friction and wear tests were performed in dry nitrogen, dry air, and air with 50% RH at Hertzian contact pressures ranging from 0.3 to 0.6 GPa. The friction coefficient of bare Ni-Mn alloy was determined to be 0.9. In contrast, low friction coefficients ({approx}0.02 in dry nitrogen and {approx}0.2 in 50% RH air) and minimal amount of wear were exhibited for the DLN coated LIGA Ni-Mn alloy parts and test coupons. This behavior was due to the ability of the coating to transfer to the rubbing counterface providing low interfacial shear at the sliding contact; resultantly, coating one surface was adequate for low friction and wear. In addition, a 30 nm thick titanium bond layer was determined to be necessary for good adhesion of DLN coating to Ni-Mn alloy substrates. Raman spectroscopy and cross-sectional SEM with energy dispersive x-ray analysis revealed that the DLN coatings deposited by the PECVD with planetary substrate rotation covered both the planar and sidewall surfaces of LIGA fabricated parts, as well as narrow holes of 300 {micro}m (0.012 inch) diameter.

  13. Environmentally benign processing of YAG transparent wafers

    NASA Astrophysics Data System (ADS)

    Yang, Yan; Wu, Yiquan

    2015-12-01

    Transparent yttrium aluminum garnet (YAG) wafers were successfully produced via aqueous tape casting and vacuum sintering techniques using a new environmentally friendly binder, a copolymer of isobutylene and maleic anhydride with the commercial name ISOBAM (noted as ISOBAM). Aqueous YAG slurries were mixed by ball-milling, which was followed by de-gassing and tape casting of wafers. The final YAG green tapes were homogenous and flexible, and could be bent freely without cracking. After the drying and sintering processes, transparent YAG wafers were achieved. The microstructures of both the green tape and vacuum-sintered YAG ceramic were observed by scanning electronic microscopy (SEM). Phase compositions were examined by X-ray diffraction (XRD). Optical transmittance was measured in UV-VIS regions with the result that the transmittance is 82.6% at a wavelength of 800 nm.

  14. Laser furnace and method for zone refining of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

    1988-01-01

    A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

  15. Semiconducting wafer form shaping with an electric discharge machine

    NASA Astrophysics Data System (ADS)

    Yang, Yu-Tung

    1988-09-01

    Gallium can be used as a temporary glue for semiconducting wafer mounting. The good electric contact between the electrode, the gallium layer, and the semiconducting wafer makes the spark cutting and the semiconducting wafer form shaping much easier. After wafer spark cutting, the residual gallium can be easily removed by a cotton swab from the surface of the wafer in warm isopropyl alcohol (IPA). Also, in this report, improved circuitry of the electric discharge machine for easy and economical construction is described. Gallium arsenide wafers have been form shaped by the present method.

  16. Making Porous Luminescent Regions In Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  17. Automated 3D IR defect mapping system for CZT wafer and tile inspection and characterization

    NASA Astrophysics Data System (ADS)

    Liao, Yi; Heidari, Esmaeil; Abramovich, Gil; Nafis, Christopher; Butt, Amer; Czechowski, Joseph; Harding, Kevin; Tkaczyk, J. Eric

    2011-08-01

    In this paper, the design and evaluation of a 3D stereo, near infrared (IR), defect mapping system for CZT inspection is described. This system provides rapid acquisition and data analysis that result in detailed mapping of CZT crystal defects across the area of wafers up to 100 millimeter diameter and through thicknesses of up to 20 millimeter. In this paper, system characterization has been performed including a close evaluation of the bright field and dark field illumination configurations for both wafer-scale and tile-scale inspection. A comparison of microscope image and IR image for the same sample is performed. As a result, the IR inspection system has successfully demonstrated the capability of detecting and localizing inclusions within minutes for a whole CZT wafer. Important information is provided for selecting defect free areas out of a wafer and thereby ensuring the quality of the tile. This system would support the CZT wafer dicing and assembly techniques that enable the economical production of CZT detectors. This capability can improve the yield and reduce the cost of the thick detector devices that are rarely produced today.

  18. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu

  19. Silicon waveguides produced by wafer bonding

    SciTech Connect

    Poulsen, M.; Jensen, F.; Bunk, O.; Feidenhans'l, R.; Breiby, D.W.

    2005-12-26

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 {mu}m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides to excite single guided modes at typical x-ray energies.

  20. Apparatus for edge etching of semiconductor wafers

    NASA Technical Reports Server (NTRS)

    Casajus, A.

    1986-01-01

    A device for use in the production of semiconductors, characterized by etching in a rapidly rotating etching bath is described. The fast rotation causes the surface of the etching bath to assume the form of a paraboloid of revolution, so that the semiconductor wafer adjusted at a given height above the resting bath surface is only attacked by etchant at the edges.

  1. Methanol Steam Reformer on a Silicon Wafer

    SciTech Connect

    Park, H; Malen, J; Piggott, T; Morse, J; Sopchak, D; Greif, R; Grigoropoulos, C; Havstad, M; Upadhye, R

    2004-04-15

    A study of the reforming rates, heat transfer and flow through a methanol reforming catalytic microreactor fabricated on a silicon wafer are presented. Comparison of computed and measured conversion efficiencies are shown to be favorable. Concepts for insulating the reactor while maintaining small overall size and starting operation from ambient temperature are analyzed.

  2. Scanning holographic scatterometer for wafer surface inspection

    NASA Astrophysics Data System (ADS)

    Klooster, Alex; Marks, James; Hanson, Kael; Sawatari, Takeo

    2004-05-01

    The semiconductor industry requires ever smaller semiconductor structures with faster response times and more function per unit area of each chip. In addition, the industry is changing from 200 mm to 300 mm diameter wafers with fewer defects and rapid detection at all processing stages. To meet these needs, defect data must be processed in near-real-time to expedite correction of processing problems at the earliest possible stage. Under a Small Business Innovation Research (SBIR) program, sponsored by the Air Force Manufacturing Technology Division at Wright Laboratory, Dayton, Ohio, Sentec Corporation has developed a revolutionary technology for contaminant particle detection on unpatterned semiconductor wafers. A key to the Sentec technology is detection, not of the intensity of backscattered energy from particles or defects, but of the amplitude of the electro-magneitc field of this backscattered energy. This new technology will allow the detection of particles that are significantly smaller than those which can be reliably located using current scatterometers. The technical concepts for a stand-alone particle detection tool have been created. It uses a continuous scanning mechanism to perform high-speed examinations of target wafers. This tool, also, has the capability of quantifying the microroughness or background haze of a subject wafer and presenting that information separate from the contamination particle data. During the course of this project, three patent applications were filed.

  3. Bubble-domain circuit wafer evaluation coil set

    NASA Technical Reports Server (NTRS)

    Chen, T. T.; Williams, J. L.

    1975-01-01

    Coil structures have been designed to permit nondestructive testing of bubble wafers. Wafers can be electrically or optically inspected and operated from quasi-static frequency to maximum device operating frequency.

  4. Multi-dimensional multi-species modeling of transient electrodeposition in LIGA microfabrication.

    SciTech Connect

    Evans, Gregory Herbert; Chen, Ken Shuang

    2004-06-01

    This report documents the efforts and accomplishments of the LIGA electrodeposition modeling project which was headed by the ASCI Materials and Physics Modeling Program. A multi-dimensional framework based on GOMA was developed for modeling time-dependent diffusion and migration of multiple charged species in a dilute electrolyte solution with reduction electro-chemical reactions on moving deposition surfaces. By combining the species mass conservation equations with the electroneutrality constraint, a Poisson equation that explicitly describes the electrolyte potential was derived. The set of coupled, nonlinear equations governing species transport, electric potential, velocity, hydrodynamic pressure, and mesh motion were solved in GOMA, using the finite-element method and a fully-coupled implicit solution scheme via Newton's method. By treating the finite-element mesh as a pseudo solid with an arbitrary Lagrangian-Eulerian formulation and by repeatedly performing re-meshing with CUBIT and re-mapping with MAPVAR, the moving deposition surfaces were tracked explicitly from start of deposition until the trenches were filled with metal, thus enabling the computation of local current densities that potentially influence the microstructure and frictional/mechanical properties of the deposit. The multi-dimensional, multi-species, transient computational framework was demonstrated in case studies of two-dimensional nickel electrodeposition in single and multiple trenches, without and with bath stirring or forced flow. Effects of buoyancy-induced convection on deposition were also investigated. To further illustrate its utility, the framework was employed to simulate deposition in microscreen-based LIGA molds. Lastly, future needs for modeling LIGA electrodeposition are discussed.

  5. EUVL mask substrate specifications (wafer-type)

    SciTech Connect

    Tong, W

    1999-07-01

    The Extreme Ultraviolet Lithography (EUVL) program currently is constructing an alpha-class exposure tool known as the Engineering Test Stand (ETS) that will employ 200mm wafer format masks. This report lists and explains the current specifications for the EUVL mask substrates suitable for use on the ETS. The shape and size of the mask are the same as those of a standard 200mm Si wafer. The flatness requirements are driven by the potential image placement distortion caused by the non-telecentric illumination of EUVL. The defect requirements are driven by the printable-defect size and desired yield for mask blank fabrication. Surface roughness can cause both a loss of light throughput and image speckle. The EUVL mask substrate must be made of low-thermal-expansion material because 40% of the light is absorbed by the multilayers and causes some uncorrectable thermal distortion during printing.

  6. Devices using resin wafers and applications thereof

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.; St. Martin, Edward; Arora, Michelle; de la Garza, Linda

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  7. Optical cavity furnace for semiconductor wafer processing

    DOEpatents

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  8. Simple method for decreasing wafer topography effect for implant mask

    NASA Astrophysics Data System (ADS)

    You, Taejun; Lee, Taehyeong; Yoo, Gyun; Park, Youngjoon; Kim, Cheolkyun; Yim, Donggyu

    2016-03-01

    Controlling critical dimension (CD) of implant blocking layers during photolithography has been challenging due to reflection caused by wafer topography. Unexpected reflection which comes from wafer topography makes severe CD variation on mask patterns of implant layer. Using bottom antireflective coatings(BARCs) can reduce the topography effect, but it could also damage wafer surface during BARCs dry etching. Developable BARCs(D-BARCs) could be alternative solution for wafer topography effect. However there are some issues that should be considered in D-BARCs process such as sensitive temperature control and managing defects. There are also papers introducing model based topography aware OPC as a solution for wafer topography effect implant layer. But building topography aware OPC model is very complex and it takes too much time to build. In this paper, we will introduce experimental results of wafer topography effect using various test patterns and propose a simple method that could effectively reduce wafer topography effect.

  9. Precipitating Chromium Impurities in Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Salama, A. M.

    1982-01-01

    Two new treatments for silicon wafers improve solar-cell conversion efficiency by precipitating electrically-active chromium impurities. One method is simple heat treatment. Other involves laser-induced damage followed by similar heat treatment. Chromium is one impurity of concern in metallurgical-grade silicon for solar cells. In new treatment, chromium active centers are made electrically inactive by precipitating chromium from solid solution, enabling use of lower grade, lower cost silicon in cell manufacture.

  10. VLED for Si wafer-level packaging

    NASA Astrophysics Data System (ADS)

    Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

    2012-03-01

    In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

  11. Mask-to-wafer alignment system

    DOEpatents

    Sweatt, William C.; Tichenor, Daniel A.; Haney, Steven J.

    2003-11-04

    A modified beam splitter that has a hole pattern that is symmetric in one axis and anti-symmetric in the other can be employed in a mask-to-wafer alignment device. The device is particularly suited for rough alignment using visible light. The modified beam splitter transmits and reflects light from a source of electromagnetic radiation and it includes a substrate that has a first surface facing the source of electromagnetic radiation and second surface that is reflective of said electromagnetic radiation. The substrate defines a hole pattern about a central line of the substrate. In operation, an input beam from a camera is directed toward the modified beam splitter and the light from the camera that passes through the holes illuminates the reticle on the wafer. The light beam from the camera also projects an image of a corresponding reticle pattern that is formed on the mask surface of the that is positioned downstream from the camera. Alignment can be accomplished by detecting the radiation that is reflected from the second surface of the modified beam splitter since the reflected radiation contains both the image of the pattern from the mask and a corresponding pattern on the wafer.

  12. Wafer level test solutions for IR sensors

    NASA Astrophysics Data System (ADS)

    Giessmann, Sebastian; Werner, Frank-Michael

    2014-05-01

    Wafer probers provide an established platform for performing electrical measurements at wafer level for CMOS and similar process technologies. For testing IR sensors, the requirements are beyond the standard prober capabilities. This presentation will give an overview about state of the art IR sensor probing systems reaching from flexible engineering solutions to automated production needs. Cooled sensors typically need to be tested at a target temperature below 80 K. Not only is the device temperature important but also the surrounding environment is required to prevent background radiation from reaching the device under test. To achieve that, a cryogenic shield is protecting the movable chuck. By operating that shield to attract residual gases inside the chamber, a completely contamination-free test environment can be guaranteed. The use of special black coatings are furthermore supporting the removal of stray light. Typically, probe card needles are operating at ambient (room) temperature when connecting to the wafer. To avoid the entrance of heat, which can result in distorted measurements, the probe card is fully embedded into the cryogenic shield. A shutter system, located above the probe field, is designed to switch between the microscope view to align the sensor under the needles and the test relevant setup. This includes a completely closed position to take dark current measurements. Another position holds a possible filter glass with the required aperture opening. The necessary infrared sources to stimulate the device are located above.

  13. Wafer weak point detection based on aerial images or WLCD

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Philipp, Peter; Litt, Lloyd C.; Ackmann, Paul; Crell, Christian; Chen, Norman

    2015-10-01

    Aerial image measurement is a key technique for model based optical proximity correction (OPC) verification. Actual aerial images obtained by AIMS (aerial image measurement system) or WLCD (wafer level critical dimension) can detect printed wafer weak point structures in advance of wafer exposure and defect inspection. Normally, the potential wafer weak points are determined based on optical rule check (ORC) simulation in advance. However, the correlation to real wafer weak points is often not perfect due to the contribution of mask three dimension (M3D) effects, actual mask errors, and scanner lens effects. If the design weak points can accurately be detected in advance, it will reduce the wafer fab cost and improve cycle time. WLCD or AIMS tools are able to measure the aerial images CD and bossung curve through focus window. However, it is difficult to detect the wafer weak point in advance without defining selection criteria. In this study, wafer weak points sensitive to mask mean-to-nominal values are characterized for a process with very high MEEF (normally more than 4). Aerial image CD uses fixed threshold to detect the wafer weak points. By using WLCD through threshold and focus window, the efficiency of wafer weak point detection is also demonstrated. A novel method using contrast range evaluation is shown in the paper. Use of the slope of aerial images for more accurate detection of the wafer weak points using WLCD is also discussed. The contrast range can also be used to detect the wafer weak points in advance. Further, since the mean to nominal of the reticle contributes to the effective contrast range in a high MEEF area this work shows that control of the mask error is critical for high MEEF layers such as poly, active and metal layers. Wafer process based weak points that cannot be detected by wafer lithography CD or WLCD will be discussed.

  14. Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size

    NASA Astrophysics Data System (ADS)

    Kim, Hee Yeoun; Yang, Chungmo; Park, Jae Hong; Jung, Ho; Kim, Taehyun; Kim, Kyung Tae; Lim, Sung Kyu; Lee, Sang Woo; Mitchell, Jay; Hwang, Wook Joong; Lee, Kwyro

    2013-06-01

    For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.

  15. Equipment for On-Wafer Testing From 220 to 325 GHz

    NASA Technical Reports Server (NTRS)

    Samoska, Lorene; Peralta, Alejandro; Dawson, Douglas; Lee, Karen; Boll, Greg; Oleson, Chuck

    2006-01-01

    A system of electronic instrumentation, constituting the equivalent of a two-port vector network analyzer, has been developed for use in on-wafer measurement of key electrical characteristics of semiconductor devices at frequencies from 220 to 325 GHz. A prior system designed according to similar principles was reported in Equipment for On-Wafer Testing at Frequencies Up to 220 GHz (NPO-20760), NASA Tech Briefs, Vol. 25, No. 11 (November 2001), page 42. As one would expect, a major source of difficulty in progressing to the present higher-frequency-range system was the need for greater mechanical precision as wavelengths shorten into the millimeter range, approaching the scale of mechanical tolerances of prior systems. The system (see figure) includes both commercial off-the-shelf and custom equipment. As in the system of the cited prior article, the equipment includes test sets that are extended versions of commercial network analyzers that function in a lower frequency range. The extension to the higher frequency range is accomplished by use of custom frequency-extension modules that contain frequency multipliers and harmonic mixers. On-wafer measurement is made possible by waveguide wafer probes that were custom designed and built for this wavelength range, plus an on-wafer calibration substrate designed for use with these probes. In this case, the calibration substrate was specially fabricated by laser milling. The system was used to make the first on-wafer measurements of a semiconductor device in the frequency range from 220 to 320 GHz. Some of the measurement results showed that the device had gain.

  16. Randomized clinical trial of LigaSure versus conventional suture ligation in thyroid surgery

    PubMed Central

    2012-01-01

    Background In thyroid surgery vessel division and haemostasis make up an important and time consuming part of the operation. While the presence of the recurrent laryngeal nerve limits the liberal use of diathermia, the many arterial and venous branches to and from the thyroid gland necessitates the use of numerous conventional suture ligatures.This study evaluates the effect of using a vessel sealing system on operation time during thyroid surgery. Methods A randomized clinical trial was performed between September 2005 and October 2008 in a teaching hospital. Forty patients undergoing total hemithyroidectomy participated in the trial. Twenty were randomized to the intraoperative use of the LigaSure Precise™ vessel sealing system, and twenty to the use of conventional suture ligatures. Results The total median operation time was 10 minutes shorter in the LigaSure group (56 versus 66 minutes, P = 0.001). No significant differences in complications were noticed. Conclusion Using an electrothermal vessel sealing system during thyroid surgery is time saving. Trial registration This trial was registered in the international standard randomized controlled trials number register (ISRCTNR) under number ISRCTNR82389535. PMID:22257756

  17. Design of electrostatically levitated micromachined rotational gyroscope based on UV-LIGA technology

    NASA Astrophysics Data System (ADS)

    Cui, Feng; Chen, Wenyuan; Su, Yufeng; Zhang, Weiping; Zhao, Xiaolin

    2004-12-01

    The prevailing micromachined vibratory gyroscope typically has a proof mass connected to the substrate by a mechanical suspension system, which makes it face a tough challenge to achieve tactical or inertial grade performance levels. With a levitated rotor as the proof mass, a micromachined rotational gyroscope will potentially have higher performance than vibratory gyroscope. Besides working as a moment rebalance dual-axis gyroscope, the micromachined rotational gyroscope based on a levitated rotor can simultaneously work as a force balance tri-axis accelerometer. Micromachined rotational gyroscope based on an electrostatically levitated silicon micromachined rotor has been notably developed. In this paper, factors in designing a rotational gyro/accelerometer based on an electrostatically levitated disc-like rotor, including gyroscopic action of micro rotor, methods of stable levitation, micro displacement detection and control, rotation drive and speed control, vacuum packaging and microfabrication, are comprehensively considered. Hence a design of rotational gyro/accelerometer with an electroforming nickel rotor employing low cost UV-LIGA technology is presented. In this design, a wheel-like flat rotor is proposed and its basic dimensions, diameter and thickness, are estimated according to the required loading capability. Finally, its micromachining methods based on UV-LIGA technology and assembly technology are discussed.

  18. Compliant membranes improve resolution in full-wafer micro/nanostencil lithography.

    PubMed

    Sidler, Katrin; Villanueva, Luis G; Vazquez-Mena, Oscar; Savu, Veronica; Brugger, Juergen

    2012-02-01

    This work reports on a considerable resolution improvement of micro/nanostencil lithography when applied on full-wafer scale by using compliant membranes to reduce gap-induced pattern blurring. Silicon nitride (SiN) membranes are mechanically decoupled from a rigid silicon (Si) frame by means of four compliant, protruding cantilevers. When pressing the stencil into contact with a surface to be patterned, the membranes thus adapt to the surface independently and reduce the gap between the membrane and the substrate even over large, uneven surfaces. Finite element modeling (FEM) simulations show that compliant membranes can deflect vertically 40 μm which is a typical maximal non-planarity observed in standard Si wafers, due to polishing. Microapertures in the stencil membrane are defined by UV lithography and nanoapertures, down to 200 nm in diameter, using focused ion beam (FIB). A thin aluminium (Al) layer is deposited through both compliant and non-compliant membranes on a Si wafer, for comparison. The blurring in the case of compliant membranes is up to 95% reduced on full-wafer scale compared to standard (non-compliant) membranes. PMID:22170588

  19. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    NASA Astrophysics Data System (ADS)

    Kulshreshtha, Prashant Kumar

    the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu

  20. Super-flat wafer chucks: from simulation and testing to a complete 300mm wafer chuck with low wafer deformation between pins

    NASA Astrophysics Data System (ADS)

    Müller, Renate; Afanasiev, Kanstantin; Ziemann, Marcel; Schmidt, Volker

    2014-04-01

    Berliner Glas is a privately owned, mid-sized manufacturer of precision opto-mechanics in Germany. One specialty of Berliner Glas is the design and production of high performance vacuum and electrostatic wafer chucks. Driven by the need of lithography and inspection for smaller overlay values, we pursue the production of an ideally flat wafer chuck. An ideally flat wafer chuck holds a wafer with a completely flat backside and without lateral distortion within the wafer surface. Key parameters in influencing the wafer chucks effective flatness are thermal performance and thermal management, roughness of the surface, choice of materials and the contact area between wafer and wafer chuck. In this presentation we would like to focus on the contact area. Usually this is decreased as much as possible to avoid sticking effects and the chance of trapped particles between the chuck surface and the backside of the wafer. This can be realized with a pin structure on the chuck surface. Making the pins smaller and moving pins further apart from each other makes the contact area ever smaller but also adds new challenges to achieve a flat and undistorted wafer on the chuck. We would like to address methods of designing and evaluating such a pin structure. This involves not only the capability to simulate the ideal pattern of pins on the chuck's surface, for which we will present 2D and 3D simulation results. As well, we would like to share first results of our functional models. Finally, measurement capability has to be ensured, which means improving and further development of Fizeau flatness test interferometers.

  1. LIGA20, a lyso derivative of ganglioside GM1, given orally after cortical thrombosis reduces infarct size and associated cognition deficit.

    PubMed Central

    Kharlamov, A; Zivkovic, I; Polo, A; Armstrong, D M; Costa, E; Guidotti, A

    1994-01-01

    A bilateral photochemically induced thrombotic lesion of rat sensorimotor cortex (approximately 3 mm in diameter and 25 mm3 in volume) is associated with a persistent cognition (learning and memory) deficit, which was evaluated with water maze tasks. The N-dichloroacetylsphingosine derivative of lysoGM1 (LIGA20) administered after the lesion either i.v. or per or reduces the infarct size by 30-40% and attenuates the associated cognition deficits, presumably by limiting the extent of damage of neurons at risk located in the surroundings of the infarcted core (i.e., area penumbra). The LIGA20 protection is dose and time dependent. Maximal protection is afforded by a single dose of LIGA20 of 34 mumol/kg i.v. 1 hr after lesion or by a dose of 270 mumol/kg per os when administered 1 hr and 24 hr after the lesion. The protective effect of LIGA20 can be observed when the drug is administered i.v. up to 6 hr after the lesion. The protective efficacy of the oral administration of LIGA20 is related to its physiochemical properties, which, unlike those of GM1, allow absorption from the gastrointestinal tract. LIGA20 given orally reaches the brain promptly and rapidly inserts into the neuronal membranes. Here, by an unknown molecular mechanism, LIGA20 selectively reduces the pathological amplification of Ca2+ signaling elicited by persistent stimulation of ionotropic glutamate receptors in the area penumbra. PMID:8022776

  2. Wafer temperature measurement: Status utilizing optical fibers

    SciTech Connect

    Schietinger, C.; Jensen, E.

    1996-12-01

    This paper reviews the current status and problems of optical fiber temperature measurements for RTP and single wafer processing. Included is a discussion of a range of fiber based options available and currently being utilized today. The advantages and disadvantages of the options are presented. In addition new data from the use of the Ripple Technique pyrometer is presented. Included are data from AT and T (Lucent Technologies) ripple pyrometer development. Lucent Technologies is evaluating and improving the ripple pyrometer on a number of different style production RTP furnaces. Recent advances in signal processing for very low level photo diode currents in the range of 10 e-14 amps, also is presented.

  3. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  4. Dominant factors of the laser gettering of silicon wafers

    SciTech Connect

    Bokhan, Yu. I. E-mail: yuibokhan@gmail.com; Kamenkov, V. S.; Tolochko, N. K.

    2015-02-15

    The laser gettering of silicon wafers is experimentally investigated. The typical gettering parameters are considered. The surfaces of laser-treated silicon wafers are investigated by microscopy. When studying the effect of laser radiation on silicon wafers during gettering, a group of factors determining the conditions of interaction between the laser beam and silicon-wafer surface and affecting the final result of treatment are selected. The main factors determining the gettering efficiency are revealed. Limitations on the desired value of the getter-layer capacity on surfaces with insufficiently high cleanness (for example, ground or matte) are established.

  5. Micro-miniature gas chromatograph column disposed in silicon wafers

    DOEpatents

    Yu, Conrad M.

    2000-01-01

    A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

  6. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, G.S.

    1998-12-15

    Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

  7. The impact of wafering on organic and inorganic surface contaminations

    NASA Astrophysics Data System (ADS)

    Meyer, S.; Wahl, S.; Timmel, S.; Köpge, R.; Jang, B.-Y.

    2016-08-01

    Beside the silicon feedstock material, the crystallization process and the cell processing itself, the wafer sawing process can strongly determine the final solar cell quality. Especially surface contamination is introduced in this process step because impurities from sawing meet with a virgin silicon surface which is highly reactive until the oxide layer is formed. In this paper we quantitatively analysed both, the organic and inorganic contamination on wafer surfaces and show that changes of process parameters during wafering may cause dramatic changes in surface purity. We present powerful techniques for the monitoring of wafer surface quality which is essential for the production of high efficiency and high quality solar cells.

  8. Temperature rise of the mask-resist assembly during LIGA exposure.

    SciTech Connect

    Ting, Aili

    2004-11-01

    Deep X-ray lithography on PMMA resist is used in the LIGA process. The resist is exposed to synchrotron X-rays through a patterned mask and then is developed in a liquid developer to make high aspect ratio microstructures. The limitations in dimensional accuracies of the LIGA generated microstructure originate from many sources, including synchrotron and X-ray physics, thermal and mechanical properties of mask and resist, and from the kinetics of the developer. This work addresses the thermal analysis and temperature rise of the mask-resist assembly during exposure in air at the Advanced Light Source (ALS) synchrotron. The concern is that dimensional errors generated at the mask and the resist due to thermal expansion will lower the accuracy of the lithography. We have developed a three-dimensional finite-element model of the mask and resist assembly that includes a mask with absorber, a resist with substrate, three metal holders, and a water-cooling block. We employed the LIGA exposure-development software LEX-D to calculate volumetric heat sources generated in the assembly by X-ray absorption and the commercial software ABAQUS to calculate heat transfer including thermal conduction inside the assembly, natural and forced convection, and thermal radiation. at assembly outer and/or inner surfaces. The calculations of assembly maximum temperature. have been compared with temperature measurements conducted at ALS. In some of these experiments, additional cooling of the assembly was produced by forced nitrogen flow ('nitrogen jets') directed at the mask surface. The temperature rise in the silicon mask and the mask holder comes directly from the X-ray absorption, but nitrogen jets carry away a significant portion of heat energy from the mask surface, while natural convection carries away negligibly small amounts energy from the holder. The temperature rise in PMMA resist is mainly from heat conducted from the silicon substrate backward to the resist and from the inner

  9. Fully-vectorial simulation and tolerancing of optical systems for wafer inspection by field tracing

    NASA Astrophysics Data System (ADS)

    Asoubar, Daniel; Schweitzer, Hagen; Hellmann, Christian; Kuhn, Michael; Wyrowski, Frank

    2015-06-01

    The simulation, design and tolerancing of optical systems for wafer inspection is a challenging task due to the different feature sizes, which are involved in these systems. On the one hand light is propagated through macroscopic lens systems and on the other hand light is diffracted at microscopic structures with features in the range of the wavelength of light. Due to this variety of scale plenty of different physical effects like refraction, diffraction, interference and polarization have to be taken into account for a realistic analysis of such inspection systems. We show that all of these effects can be included in a system simulation by field tracing, which combines physical and geometrical optics. The main idea is the decomposition of the complex optical setup in a sequence of subdomains. Per subdomain a different approximative or rigorous solution of Maxwell's equations is applied to propagate the light. In this work the different modeling techniques for the analysis of an exemplary wafer inspection system are discussed in detail. These techniques are mainly geometrical optics for the light propagation through macroscopic lenses, a rigorous Fourier Modal Method (FMM) for the modeling of light diffraction at the wafer microstructure and different free-space diffraction integrals. In combination with a numerically efficient algorithm for the coordinate transformation of electromagnetic fields, field tracing enables position and fabrication tolerancing. As an example different tilt tolerance effects on the polarization state and image contrast of a simple wafer inspection system are shown.

  10. Molecular and ionic contamination monitoring for cleanroom air and wafer surfaces

    NASA Astrophysics Data System (ADS)

    Sun, Peng; Adams, Marty; Shive, Larry; Pirooz, Saeed

    1997-09-01

    Advances in the electronic industry toward large-scale integration of semiconductor devices have placed strict demands on the ability to measure and monitor ultratrace levels of impurities. Even though they have been found to have increasingly detrimental impacts on the performance and yield of semiconductor products, organic and non-metal ionic contaminants have not received the same attention as particles and metallics. Method developments for ultratrace measurements of molecular and ionic contamination are far behind the demands. This paper describes the use of different sampling and analytical techniques to assess and monitor molecular and ionic contaminants in cleanroom ambient air and on wafer surfaces. Thermal desorption gas chromatography mass spectrometry/nitrogen phosphorous detector is used for the identification and quantification of organic contaminants. Ammonium (NH4+) and inorganic anions are analyzed by using capillary electrophoresis with indirect UV detection methods. The identification and quantification of specific organic compounds, which outgas from cleanroom ULPA filters and wafer package boxes and tend to adsorb on silicon wafers, will be demonstrated. Ammonium and anion contamination for different wafer cleaning processes will be compared. The capabilities, applications, and limitations of these techniques will be discussed in further details.

  11. "Performance Of A Wafer Stepper With Automatic Intra-Die Registration Correction."

    NASA Astrophysics Data System (ADS)

    van den Brink, M. A.; Wittekoek, S.; Linders, H. F. D.; van Hout, F. J.; George, R. A.

    1987-01-01

    An evaluation of a wafer stepper with the new improved Philips/ASM-L phase grating alignment system is reported. It is shown that an accurate alignment system needs an accurate X-Y-0 wafer stage and an accurate reticle Z stage to realize optimum overlay accuracy. This follows from a discussion of the overlay budget and an alignment procedure model. The accurate wafer stage permits high overlay accuracy using global alignment only, thus eliminating the throughput penalty of align-by-field schemes. The accurate reticle Z stage enables an intra-die magnification control with respect to the wafer scale. Various overlay data are reported, which have been measured with the automatic metrology program of the stepper. It is demonstrated that the new dual alignment system (with the external spatial filter) has improved the ability to align to weakly reflecting layers. The results are supported by a Fourier analysis of the alignment signal. Resolution data are given for the PAS 2500 projection lenses, which show that the high overlay accuracy of the system is properly matched with submicron linewidth control. The results of a recently introduced 20mm i-line lens with a numerical aperture of 0.4 (Zeiss 10-78-58) are included.

  12. Mask qualification strategies in a wafer fab

    NASA Astrophysics Data System (ADS)

    Jaehnert, Carmen; Kunowski, Angela

    2007-02-01

    Having consistent high quality photo masks is one of the key factors in lithography in the wafer fab. Combined with stable exposure- and resist processes, it ensures yield increases in production and fast learning cycles for technology development and design evaluation. Preventive controlling of incoming masks and quality monitoring while using the mask in production is essential for the fab to avoid yield loss or technical problems caused by mask issues, which eventually result in delivery problems to the customer. In this paper an overview of the procedures used for mask qualification and production release, for both logic and DRAM, at Infineon Dresden is presented. Incoming qualification procedures, such as specification checks, incoming inspection, and inline litho process window evaluation, are described here. Pinching and electrical tests, including compatibility tests for mask copies for high volume products on optimized litho processes, are also explained. To avoid mask degradation over lifetime, re-inspection checks are done for re-qualification while using the mask in production. The necessity of mask incoming inspection and re-qualification, due to the repeater printing from either the processing defects of the original mask or degrading defects of being used in the fab (i.e. haze, ESD, and moving particles, etc.), is demonstrated. The need and impact of tight mask specifications, such as CD uniformity signatures and corresponding electrical results, are shown with examples of mask-wafer CD correlation.

  13. Fundamental limitations of LIGA x-ray lithography : sidewall offset, slope and minimum feature size.

    SciTech Connect

    Griffiths, Stewart K.

    2004-01-01

    Analytical and numerical methods are used to examine photoelectron doses and their effect on the dimensions of features produced by deep x-ray lithography. New analytical models describing electron doses are presented and used to compute dose distributions for several feature geometries. The history of development and final feature dimensions are also computed, taking into account the dose field, dissolution kinetics based on measured development rates, and the transport of PMMA fragments away from the dissolution front. We find that sidewall offsets, sidewall slope and producible feature sizes all exhibit at least practical minima and that these minima represent fundamental limitations of the LIGA process. The minimum values under optimum conditions are insensitive to the synchrotron spectrum, but depend strongly on resist thickness. This dependence on thickness is well approximated by simple analytical expressions describing the minimum offset, minimum sidewall slope, minimum producible size of positive and negative features, maximum aspect ratio and minimum radius of inside and outside corners.

  14. LIGA fabrication of mm-wave accelerating cavity structures at the Advanced Photon Source (APS)

    SciTech Connect

    Song, J.J.; Bajikar, S.; Kang, Y.W.

    1997-08-01

    Recent microfabrication technologies based on the LIGA (German acronym for Lithographe, Galvanoformung, und Abformung) process have been applied to build high-aspect-ratio, metallic or dielectric planar structures suitable for high-frequency rf cavity structures. The cavity structures would be used as parts of linear accelerators, microwave undulators, and mm-wave amplifiers. The microfabrication process includes manufacture of precision x-ray masks, exposure of positive resist x-rays through the mask, resist development, and electroforming of the final microstructure. Prototypes of a 32-cell, 108-GHz constant-impedance cavity and a 66-cell, 94-GHz constant-gradient cavity were fabricated with the synchrotron radiation sources at APS and NSLS. This paper will present an overview of the new technology and details of the mm-wave cavity fabrication.

  15. PMMA microstructure as KrF excimer-laser LIGA material

    NASA Astrophysics Data System (ADS)

    Yang, Chii-Rong; Chou, Bruce C. S.; Chou, Hsiao-Yu; Lin, Frank H. S.; Kuo, Wen-Kai; Luo, Roger G. S.; Chang, Jer-Wei; Wei, Z. J.

    1998-08-01

    PMMA (polymethyl methacrylate) has been widely used as x-ray LIGA material for its good features of electrical acid plating of all common metals to industrial applications. Unlike the tough characteristics of polyimide in almost all alkaline and acid solutions, PMMA is easily removed in chemical etchants after electroplating process. For this reason, ablation- etching characteristics of PMMA material for 3D microstructures fabrication using a 248 nm KrF excimer laser were investigated. Moreover, the uses of the laminated dry film were also studied in this work. Experimental results show that PMMA microstructures can produce the near-vertical side- wall profile as the laser fluence up to 2.5 J/cm2. PMMA templates with high aspect ratio of around 25 were demonstrated, and the sequential electroplating processes have realized the metallic microstructures. Moreover, the microstructures fabricated in dry film show the perfect side- wall quality, and no residues of debris were found.

  16. UV-LIGA microfabrication process for sub-terahertz waveguides utilizing multiple layered SU-8 photoresist

    NASA Astrophysics Data System (ADS)

    Malekabadi, Ali; Paoloni, Claudio

    2016-09-01

    A microfabrication process based on UV LIGA (German acronym of lithography, electroplating and molding) is proposed for the fabrication of relatively high aspect ratio sub-terahertz (100-1000 GHz) metal waveguides, to be used as a slow wave structure in sub-THz vacuum electron devices. The high accuracy and tight tolerances required to properly support frequencies in the sub-THz range can be only achieved by a stable process with full parameter control. The proposed process, based on SU-8 photoresist, has been developed to satisfy high planar surface requirements for metal sub-THz waveguides. It will be demonstrated that, for a given thickness, it is more effective to stack a number of layers of SU-8 with lower thickness rather than using a single thick layer obtained at lower spin rate. The multiple layer approach provides the planarity and the surface quality required for electroforming of ground planes or assembly surfaces and for assuring low ohmic losses of waveguides. A systematic procedure is provided to calculate soft and post-bake times to produce high homogeneity SU-8 multiple layer coating as a mold for very high quality metal waveguides. A double corrugated waveguide designed for 0.3 THz operating frequency, to be used in vacuum electronic devices, was fabricated as test structure. The proposed process based on UV LIGA will enable low cost production of high accuracy sub-THz 3D waveguides. This is fundamental for producing a new generation of affordable sub-THz vacuum electron devices, to fill the technological gap that still prevents a wide diffusion of numerous applications based on THz radiation.

  17. UV-LIGA microfabrication process for sub-terahertz waveguides utilizing multiple layered SU-8 photoresist

    NASA Astrophysics Data System (ADS)

    Malekabadi, Ali; Paoloni, Claudio

    2016-09-01

    A microfabrication process based on UV LIGA (German acronym of lithography, electroplating and molding) is proposed for the fabrication of relatively high aspect ratio sub-terahertz (100–1000 GHz) metal waveguides, to be used as a slow wave structure in sub-THz vacuum electron devices. The high accuracy and tight tolerances required to properly support frequencies in the sub-THz range can be only achieved by a stable process with full parameter control. The proposed process, based on SU-8 photoresist, has been developed to satisfy high planar surface requirements for metal sub-THz waveguides. It will be demonstrated that, for a given thickness, it is more effective to stack a number of layers of SU-8 with lower thickness rather than using a single thick layer obtained at lower spin rate. The multiple layer approach provides the planarity and the surface quality required for electroforming of ground planes or assembly surfaces and for assuring low ohmic losses of waveguides. A systematic procedure is provided to calculate soft and post-bake times to produce high homogeneity SU-8 multiple layer coating as a mold for very high quality metal waveguides. A double corrugated waveguide designed for 0.3 THz operating frequency, to be used in vacuum electronic devices, was fabricated as test structure. The proposed process based on UV LIGA will enable low cost production of high accuracy sub-THz 3D waveguides. This is fundamental for producing a new generation of affordable sub-THz vacuum electron devices, to fill the technological gap that still prevents a wide diffusion of numerous applications based on THz radiation.

  18. Diamond MEMS: wafer scale processing, devices, and technology insertion

    NASA Astrophysics Data System (ADS)

    Carlisle, J. A.

    2009-05-01

    Diamond has long held the promise of revolutionary new devices: impervious chemical barriers, smooth and reliable microscopic machines, and tough mechanical tools. Yet it's been an outsider. Laboratories have been effectively growing diamond crystals for at least 25 years, but the jump to market viability has always been blocked by the expense of diamond production and inability to integrate with other materials. Advances in chemical vapor deposition (CVD) processes have given rise to a hierarchy of carbon films ranging from diamond-like carbon (DLC) to vapor-deposited diamond coatings, however. All have pros and cons based on structure and cost, but they all share some of diamond's heralded attributes. The best performer, in theory, is the purest form of diamond film possible, one absent of graphitic phases. Such a material would capture the extreme hardness, high Young's modulus and chemical inertness of natural diamond. Advanced Diamond Technologies Inc., Romeoville, Ill., is the first company to develop a distinct chemical process to create a marketable phase-pure diamond film. The material, called UNCD® (for ultrananocrystalline diamond), features grain sizes from 3 to 300 nm in size, and layers just 1 to 2 microns thick. With significant advantages over other thin films, UNCD is designed to be inexpensive enough for use in atomic force microscopy (AFM) probes, microelectromechanical machines (MEMS), cell phone circuitry, radio frequency devices, and even biosensors.

  19. Analysis of wafer heating in 14nm DUV layers

    NASA Astrophysics Data System (ADS)

    Subramany, Lokesh; Chung, Woong Jae; Samudrala, Pavan; Gao, Haiyong; Aung, Nyan; Gomez, Juan Manuel; Minghetti, Blandine; Lee, Shawn

    2016-03-01

    To further shrink the contact and trench dimensions, Negative Tone Development (NTD) has become the de facto process at these layers. The NTD process uses a positive tone resist and an organic solvent-based negative tone developer which leads to improved image contrast, larger process window and smaller Mask Error Enhancement Factor (MEEF)[1]. The NTD masks have high transmission values leading to lens heating and as observed here wafer heating as well. Both lens and wafer heating will contribute to overlay error, however the effects of lens heating can be mitigated by applying lens heating corrections while no such corrections exist for wafer heating yet. Although the magnitude of overlay error due to wafer heating is low relative to lens heating; ever tightening overlay requirements imply that the distortions due to wafer heating will quickly become a significant part of the overlay budget. In this work the effects, analysis and observations of wafer heating on contact and metal layers of the 14nm node are presented. On product wafers it manifests as a difference in the scan up and scan down signatures between layers. An experiment to further understand wafer heating is performed with a test reticle that is used to monitor scanner performance.

  20. Effects of Wafer Emissivity on Rapid Thermal Processing Temperature Measurement

    NASA Astrophysics Data System (ADS)

    Chen, D. H.; DeWitt, D. P.; Tsai, B. K.; Kreider, K. G.; Kimes, W. A.

    2003-09-01

    Lightpipe radiation thermometers (LPRTs) are widely used to measure wafer temperatures in rapid thermal processing (RTP) tools. To use blackbody-calibrated LPRTs to infer the wafer temperature, it is necessary to build a model to predict the effective emissivity accounting for the wafer and chamber radiative properties as well as geometrical features of the chamber. The uncertainty associated with model-corrected temperatures can be investigated using test wafers instrumented with thin-film thermocouples (TFTCs) on which the LPRT target spot has been coated with films of different emissivity. A finite-element model of the wafer-chamber arrangement was used to investigate the effects of Pt spot (ɛs = 0.25) and Au spot (ɛs = 0.05) on the temperature distribution of test wafers with spectral emissivities of 0.65 and 0.84. The effects of the shield reflectivity and the cool lightpipe (LP) tip on the wafer temperature were evaluated. A radiance analysis method was developed, and a comparison of model-based predictions with experimental observations was made on a 200 mm diameter wafer in the NIST RTP test bed. The temperature rises caused by the low-emissivity spot were predicted and the cooling effect of the LP tip was determined. The results of the study are important for developing the model-based corrections for temperature measurements and related uncertainties using LPRTs in semiconductor thermal processes.

  1. Particulate contamination removal from wafers using plasmas and mechanical agitation

    DOEpatents

    Selwyn, Gary S.

    1998-01-01

    Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

  2. Wafer Mapping Using Deuterium Enhanced Defect Characterization

    NASA Astrophysics Data System (ADS)

    Hossain, K.; Holland, O. W.; Hellmer, R.; Vanmil, B.; Bubulac, L. O.; Golding, T. D.

    2010-07-01

    Deuterium (as well as other hydrogen isotopes) binds with a wide range of morphological defects in semiconductors and, as such, becomes distributed similarly to those defects. Thus, the deuterium profile within the sample serves as the basis of a technique for defect mapping known as amethyst wafer mapping (AWM). The efficiency of this technique has been demonstrated by evaluation of ion-induced damage in implanted Si, as well as as-grown defects in HgCdTe (MCT) epilayers. The defect tagging or decoration capability of deuterium is largely material independent and applicable to a wide range of defect morphologies. A number of analytical techniques including ion channeling and etch pit density measurements were used to evaluate the AWM results.

  3. Backside EBR process performance with various wafer properties

    NASA Astrophysics Data System (ADS)

    Goto, Tomohiro; Shigemori, Kazuhito; Vangheluwe, Rik; Erich, Daub; Sanada, Masakazu

    2009-03-01

    In immersion lithography process, film stacking architecture will be necessary to avoid top coat film peeling. To achieve suitable stacking architecture for immersion lithography process, an EBR process that delivers tightly controlled film edge position and good uniformity around the wafer circumference is needed. We demonstrated a new bevel rinse system on a SOKUDO RF3 coat-and-develop track for immersion lithography. The performance of the new bevel rinse system for various wafer properties was evaluated. It was found that the bevel rinse system has a good controllability of film edge position and good uniformity around the wafer circumference. The results indicate that the bevel rinse system has a large margin for wafer centering accuracy, back side particles, wafer shape and substrates with good film edge position controllability, uniformity and clean apex. The system has been demonstrated to provide a suitable film stacking architecture for immersion lithography mass production process.

  4. Reduction of Thermal Conductivity in Wafer-Bonded Silicon

    SciTech Connect

    ZL Liau; LR Danielson; PM Fourspring; L Hu; G Chen; GW Turner

    2006-11-27

    Blocks of silicon up to 3-mm thick have been formed by directly bonding stacks of thin wafer chips. These stacks showed significant reductions in the thermal conductivity in the bonding direction. In each sample, the wafer chips were obtained by polishing a commercial wafer to as thin as 36 {micro}m, followed by dicing. Stacks whose starting wafers were patterned with shallow dots showed greater reductions in thermal conductivity. Diluted-HF treatment of wafer chips prior to bonding led to the largest reduction of the effective thermal conductivity, by approximately a factor of 50. Theoretical modeling based on restricted conduction through the contacting dots and some conduction across the planar nanometer air gaps yielded fair agreement for samples fabricated without the HF treatment.

  5. Interferometric metrology of wafer nanotopography for advanced CMOS process integration

    NASA Astrophysics Data System (ADS)

    Valley, John F.; Koliopoulos, Chris L.; Tang, Shouhong

    2001-12-01

    According to industry standards (SEMI M43, Guide for Reporting Wafer Nanotopography), Nanotopography is the non- planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). The need for precision metrology of wafer nanotopography is being actively addressed by interferometric technology. In this paper we present an approach to mapping the whole wafer front surface nanotopography using an engineered coherence interferometer. The interferometer acquires a whole wafer raw topography map. The raw map is then filtered to remove the long spatial wavelength, high amplitude shape contributions and reveal the nanotopography in the filtered map. Filtered maps can be quantitatively analyzed in a variety of ways to enable statistical process control (SPC) of nanotopography parameters. The importance of tracking these parameters for CMOS gate level processes at 180-nm critical dimension, and below, is examined.

  6. Overlay Tolerances For VLSI Using Wafer Steppers

    NASA Astrophysics Data System (ADS)

    Levinson, Harry J.; Rice, Rory

    1988-01-01

    In order for VLSI circuits to function properly, the masking layers used in the fabrication of those devices must overlay each other to within the manufacturing tolerance incorporated in the circuit design. The capabilities of the alignment tools used in the masking process determine the overlay tolerances to which circuits can be designed. It is therefore of considerable importance that these capabilities be well characterized. Underestimation of the overlay accuracy results in unnecessarily large devices, resulting in poor utilization of wafer area and possible degradation of device performance. Overestimation will result in significant yield loss because of the failure to conform to the tolerances of the design rules. The proper methodology for determining the overlay capabilities of wafer steppers, the most commonly used alignment tool for the production of VLSI circuits, is the subject of this paper. Because cost-effective manufacturing process technology has been the driving force of VLSI, the impact on productivity is a primary consideration in all discussions. Manufacturers of alignment tools advertise the capabilities of their equipment. It is notable that no manufacturer currently characterizes his aligners in a manner consistent with the requirements of producing very large integrated circuits, as will be discussed. This has resulted in the situation in which the evaluation and comparison of the capabilities of alignment tools require the attention of a lithography specialist. Unfortunately, lithographic capabilities must be known by many other people, particularly the circuit designers and the managers responsible for the financial consequences of the high prices of modern alignment tools. All too frequently, the designer or manager is confronted with contradictory data, one set coming from his lithography specialist, and the other coming from a sales representative of an equipment manufacturer. Since the latter generally attempts to make his

  7. Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage.

    PubMed

    Rack, Alexander; Scheel, Mario; Danilewsky, Andreas N

    2016-03-01

    Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1-2 ms followed by jumps faster than 2-6 m s(-1), leading to a macroscopically observed average velocity of 0.028-0.055 m s(-1). The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound. PMID:27006774

  8. Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

    2014-01-01

    This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

  9. Thermal spray and cold spray analysis of density, porosity, and tensile Specimens for use with LIGA applications

    SciTech Connect

    DECKER,MERLIN K.; SMITH,MARK F.

    2000-02-01

    This analysis provides a preliminary investigation into using Twin-Wire Arc Thermal Spray and Cold Spray as material deposition processes for LIGA applications. These spray material processes were studied to make an initial determination of their potential as alternatives to producing mechanical parts via the electroplating process. Three materials, UltraMachinable{reg_sign} Stainless Steel, BondArc{reg_sign}, and aluminum, were sprayed using Thermal Spray. Only aluminum was sprayed using the Cold Spray process. Following the spray procedure, the test specimens were released from a copper mold and then tested. Three tests, density, tensile strength, and porosity, were performed on the specimens to determine the spray effect on material properties. Twin-Wire Arc Thermal Spray did not demonstrate adequate deposition properties and does not appear to be a good process candidate for LIGA. However, Cold Spray yielded better density results and warrants further investigation to analyze the minimum feature size produced by the process.

  10. Development of optical automatic positioning and wafer defect detection system

    NASA Astrophysics Data System (ADS)

    Tien, Chuen-Lin; Lai, Qun-Huang; Lin, Chern-Sheng

    2016-02-01

    The data of a wafer with defects can provide engineers with very important information and clues to improve the yield rate and quality in manufacturing. This paper presents a microscope automatic positioning and wafer detection system with human-machine interface based on image processing and fuzzy inference algorithms. In the proposed system, a XY table is used to move the position of each die on 6 inch or 8 inch wafers. Then, a high-resolution CCD and one set of two-axis optical linear encoder are used to accurately measure the position on the wafer. Finally, the developed human-machine interface is used to display the current position of an actual wafer in order to complete automatic positioning, and a wafer map database can be created. In the process of defect detection, CCD is used for image processing, and during preprocessing, it is required to filter noise, acquire the defect characteristics, define the defective template, and then take the characteristic points of the defective template as the reference input for fuzzy inference. A high-accuracy optical automatic positioning and wafer defect detection system is thus constructed. This study focused on automatic detection of spots, scratches, and bruises, and attempted to reduce the time to detect defective die and improve the accuracy of determining the defects of semiconductor devices.

  11. Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

    PubMed

    Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

    2014-06-01

    Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing.

  12. Optima XE Single Wafer High Energy Ion Implanter

    SciTech Connect

    Satoh, Shu; Ferrara, Joseph; Bell, Edward; Patel, Shital; Sieradzki, Manny

    2008-11-03

    The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowing the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.

  13. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    NASA Astrophysics Data System (ADS)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

    2016-08-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

  14. Analysis of the interdigitated back contact solar cells: The n-type substrate lifetime and wafer thickness

    NASA Astrophysics Data System (ADS)

    Zhang, Wei; Chen, Chen; Jia, Rui; Sun, Yun; Xing, Zhao; Jin, Zhi; Liu, Xin-Yu; Liu, Xiao-Wen

    2015-10-01

    The n-type silicon integrated-back contact (IBC) solar cell has attracted much attention due to its high efficiency, whereas its performance is very sensitive to the wafer of low quality or the contamination during high temperature fabrication processing, which leads to low bulk lifetime τbulk. In order to clarify the influence of bulk lifetime on cell characteristics, two-dimensional (2D) TCAD simulation, combined with our experimental data, is used to simulate the cell performances, with the wafer thickness scaled down under various τbulk conditions. The modeling results show that for the IBC solar cell with high τbulk, (such as 1 ms-2 ms), its open-circuit voltage Voc almost remains unchanged, and the short-circuit current density Jsc monotonically decreases as the wafer thickness scales down. In comparison, for the solar cell with low τbulk (for instance, < 500 μs) wafer or the wafer contaminated during device processing, the Voc increases monotonically but the Jsc first increases to a maximum value and then drops off as the wafer’s thickness decreases. A model combing the light absorption and the minority carrier diffusion is used to explain this phenomenon. The research results show that for the wafer with thinner thickness and high bulk lifetime, the good light trapping technology must be developed to offset the decrease in Jsc. Project supported by the Chinese Ministry of Science and Technology Projects (Grant Nos. 2012AA050304 and Y0GZ124S01), the National Natural Science Foundation of China (Grant Nos. 11104319, 11274346, 51202285, 51402347, and 51172268), and the Fund of the Solar Energy Action Plan from the Chinese Academy of Sciences (Grant Nos. Y3ZR044001 and Y2YF014001).

  15. Assessment of patients’ quality of life after haemorrhoidectomy using the LigaSure device

    PubMed Central

    Leksowski, Krzysztof

    2015-01-01

    Introduction Haemorrhoids are small anatomical structures within the anal canal that are involved in the proper functioning of the lower gastrointestinal tract. Factors favouring the development of haemorrhoidal disease are insufficient physical activity, prolonged sitting and hence a shortage of physical activity, as well as poor diet which lacks adequate amounts of fibre. The main symptom of this disease is bleeding with bright red blood just after defecation. Haemorrhoidal disease occurs when the ligamentous apparatus comes loose and the internal haemorrhoidal plexus translocates down, whereas haemorrhoids enlarge and move out of the anal canal. Haemorrhoidal disease treatment includes conservative, instrumental and surgical therapy. Aim To assess treatment and satisfaction in particular life domains after haemorrhoidectomy. Material and methods The research was undertaken in the General, Thoracic and Vascular Surgery Clinic of the 10th Military Clinical Hospital with Polyclinic in Bydgoszcz among 50 patients treated due to haemorrhoids and operated on in the period 2007–2008. The study evaluated quality of patients’ life after haemorrhoidectomy by Ferguson's method using a LigaSure appliance. Results The study investigated whether patients perceived a difference before and after surgery. The research proved that patients can describe disease symptoms and know the risk factors for haemorrhoids. In the studied group patients are able to describe characteristic signs of haemorrhoidal disease and also indicate differences in everyday life before and after the surgery. They can also describe and classify the pain before and 1 year after the haemorrhoidectomy, which was statistically significantly lower already 3 months after the operation. Conclusions Conducted examinations showed that sick people in the precise way were able to determine manifestations and know risk factors of the prevalence of disease hemorrhoidal. Operated sick people indicated the difference

  16. The uses of Man-Made diamond in wafering applications

    NASA Technical Reports Server (NTRS)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  17. Contamination control: removing small particles from increasingly large wafers

    NASA Astrophysics Data System (ADS)

    de Jong, A. J.; van der Donck, J. C. J.; Huijser, T.; Kievit, O.; Koops, R.; Koster, N. B.; Molkenboer, F. T.; Theulings, A. M. M. G.

    2012-03-01

    With the introduction of 450 mm wafers, which are considerably larger than the currently largest wafers of 300mm, handling with side grippers is no longer possible and backside grippers are required. Backside gripping increases the possible buildup of particles on the backside of the wafers with possible cross-contamination to the front-side. Therefore, regular backside cleaning is required. Three vacuum compatible cleaning methods were selected. Tacky rollers and highvoltage cleaning were selected for particles and plasma cleaning for molecular layers. A test-bench was designed and constructed implementing these three cleaning methods. The first experiments show promising results for the plasma cleaner and the tacky roller.

  18. Extraction and Analysis of Noise Parameters of On Wafer HEMTs up to 26.5 GHz

    SciTech Connect

    Caddemi, Alina; Crupi, Giovanni; Macchiarella, Alessio

    2009-04-23

    This paper presents a procedure for extracting the four noise parameters of on wafer scaled HEMTs based on AlGaAs/GaAs heterostructure. This procedure relies on 50-{omega} noise figure measurements up to 26.5 GHz by determining the equivalent temperatures associated to the intrinsic resistances of the small signal equivalent circuit. The non-quasi-static effect associated to the gate-drain resistance R{sub gd} is accounted for by the noise model. A good agreement between measured and simulated noise figure is obtained and scaling of the noise parameters is reported.

  19. Automated radiometric cryoprobe of IR focal plane array wafers

    NASA Astrophysics Data System (ADS)

    Whicker, Stephen L.

    1994-07-01

    Texas Instruments (TI) validated the feasibility of cryoprobing IRFPA arrays in late 1991. Since then, TI has developed a revolutionary automated cryoprobe for screening four and six inch wafers of IRFPAs. Generic prober automation features include cassette to cassette wafer load and unload, wafer alignment, black body selection, aperture selection, probe tip continuity test, and 77.5 degree(s) to 400 degree(s)K wafer temperature control. Modular construction of the prober enables placement of product specific components such as MWIR or LWIR bandpass filters, coldshield, coldfilter, probe card, and noise suppression circuitry on an easily removable `product specific' tooling plate. Prober operation is controlled through object oriented software. IRFPA specific software modules control array operation, data collection, and data reduction. In addition to describing the prober capabilities and versatility, this paper compares prober test data to lab dewar test data for 240 X 1 IRFPAs and projects benefits in reduced cycle time and labor savings.

  20. 9nm node wafer defect inspection using visible light

    NASA Astrophysics Data System (ADS)

    Zhou, Renjie; Edwards, Chris; Popescu, Gabriel; Goddard, Lynford L.

    2014-04-01

    Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

  1. Optical analysis on the wafer defect inspection for yield enhancement

    NASA Astrophysics Data System (ADS)

    Ahn, Jeongho; Lee, Byoungho; Lee, Dong-Ryul; Seong, Shijin; Kim, Hyungseop; Choi, Seongchae; Sunwoo, Heewon; Lee, Junbum; Ihm, Dongchul; Chin, Soobok; Kang, Ho-Kyu

    2013-04-01

    This paper presents a methodology for detecting defects more effectively that have a substantial yield impact on several critical layers using a simulation program, which is considerably helpful in analyzing defects on the wafer. First, this paper presents a simple analysis method that uses mathematical treatment for multi thin film layers. This instantly gives us a highly intuitive idea for selecting an inspection mode based on the reflectivity and transmittivity. Second, we introduce numerical method for wafer defect of interest with finite difference time domain (FDTD) method, and provide correlation between the expectation and experimental results. The goal of these studies is to determine the feasibility of implementing theoretical approaches with numerical method at wafer defect inspection. Overall, this paper discusses the effective wafer inspection methodology and the advantages of defect simulation with numerical analysis at semiconductor manufacturing for accelerated development of advanced design node devices.

  2. Proceedings of the Low-Cost Solar Array Wafering Workshop

    NASA Technical Reports Server (NTRS)

    Morrison, A. D.

    1982-01-01

    The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

  3. Efficient data transmission from silicon wafer strip detectors

    SciTech Connect

    Cooke, B.J.; Lackner, K.S.; Palounek, A.P.T.; Sharp, D.H.; Winter, L.; Ziock, H.J.

    1991-12-31

    An architecture for on-wafer processing is proposed for central silicon-strip tracker systems as they are currently designed for high energy physics experiments at the SSC, and for heavy ion experiments at RHIC. The data compression achievable with on-wafer processing would make it possible to transmit all data generated to the outside of the detector system. A set of data which completely describes the state of the wafer for low occupancy events and which contains important statistical information for more complex events can be transmitted immediately. This information could be used in early trigger decisions. Additional data packages which complete the description of the state of the wafer vary in size and are sent through a second channel. By buffering this channel the required bandwidth can be kept far below the peak data rates which occur in rate but interesting events. 18 refs.

  4. Dimensional errors in LIGA-produced metal structures due to thermal expansion and swelling of PMMA.

    SciTech Connect

    Kistler, Bruce L.; Dryden, Andrew S.; Crowell, Jeffrey A.W.; Griffiths, Stewart K.

    2004-04-01

    Numerical methods are used to examine dimensional errors in metal structures microfabricated by the LIGA process. These errors result from elastic displacements of the PMMA mold during electrodeposition and arise from thermal expansion of the PMMA when electroforming is performed at elevated temperatures and from PMMA swelling due to absorption of water from aqueous electrolytes. Both numerical solutions and simple analytical approximations describing PMMA displacements for idealized linear and axisymmetric geometries are presented and discussed. We find that such displacements result in tapered metal structures having sidewall slopes up to 14 {micro}m per millimeter of height for linear structures bounded by large areas of PMMA. Tapers for curved structures are of similar magnitude, but these structures are additionally skewed from the vertical. Potential remedies for reducing dimensional errors are also discussed. Here we find that auxiliary moat-like features patterned into the PMMA surrounding mold cavities can reduce taper by an order of magnitude or more. Such moats dramatically reduce tapers for all structures, but increase skew for curved structures when the radius of curvature is comparable to the structure height.

  5. Photoablation characteristics of novel polyimides synthesized for high-aspect-ratio excimer laser LIGA process

    NASA Astrophysics Data System (ADS)

    Yang, Chii-Rong; Hsieh, Yu-Sheng; Hwang, Guang-Yeu; Lee, Yu-Der

    2004-04-01

    The photoablation properties of two soluble polyimides DMDB/6FDA and OT/6FDA with thicknesses of over 300 µm, synthesized by the polycondensation of a hexafluoropropyl group contained in a dianhydride with two kinds of diamines, are investigated using a 248 nm krypton fluoride (KrF) laser. The incorporation of the hexafluoropropyl group into the chemical structure gives these two polyimides higher etching rates than Kapton (a commercial polyimide film which is difficult to dissolve). The etching rates of synthesized polyimides are about 0.1-0.5 µm/pulse over a fluence range of 0.25-2.25 J cm-2. The photothermal mechanism for DMDB/6FDA contributes about 19% of etching depth at a laser fluence of 0.82 J cm-2. Moreover, the number of laser pulses seriously affects the taper angle of microstructures, especially at low fluence. Near-vertical side-wall structures can be built at high fluence (~2 J cm-2). Fresnel patterns with a thickness of 300 µm and a linewidth of 10 µm were fabricated, with an attainable aspect ratio of around 30. After photoablation, the complementary metallic microstructures were also fabricated by a sequential electroplating procedure. Then, those two new polyimides could be dissolved easily in most common solvents (such as THF, DMSO, NMP and DMF). These results indicate that these two soluble polyimides are highly suitable for use in the KrF laser LIGA process.

  6. The influence of feature sidewall tolerance on minimum absorber thickness for LIGA x-ray masks

    SciTech Connect

    S. K. Griffiths; J. M. Hruby; A. Ting

    1999-02-01

    Minimizing mask absorber thickness is an important practical concern in producing very small features by the LIGA process. To assist in this minimization, the authors have developed coupled numerical models describing both the exposure and development of a thick PMMA resist. The exposure model addresses multi-wavelength, one-dimensional x-ray transmission through multiple beam filters, through the mask substrate and absorber, and the subsequent attenuation and photon absorption in the PMMA resist. The development model describes one-dimensional dissolution of a feature and its sidewalls, taking into account the variation in absorbed dose through the PMMA thickness. These exposure and development models are coupled in a single interactive code, permitting the automated adjustment of mask absorber thickness to yield a prescribed sidewall taper or dissolution distance. They have used this tool to compute the minimum required absorber thickness yielding a prescribed sidewall tolerance for exposures performed at the ALS, SSRL and NSLS synchrotron sources. Results are presented as a function of the absorbed dose for a range of the prescribed sidewall tolerance, feature size, PMMA thickness, mask substrate thickness and the development temperature.

  7. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-03-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  8. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2008-10-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  9. Automated reticle inspection data analysis for wafer fabs

    NASA Astrophysics Data System (ADS)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  10. Electrochemical method for defect delineation in silicon-on-insulator wafers

    DOEpatents

    Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

    1991-01-01

    An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

  11. Strategy optimization for mask rule check in wafer fab

    NASA Astrophysics Data System (ADS)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  12. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    NASA Astrophysics Data System (ADS)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  13. Development of a Whole-Wafer, Macroscale Inspection Software Method for Semiconductor Wafer Analysis

    SciTech Connect

    Tobin, K.W.

    2003-05-22

    This report describes the non CRADA-protected results of the project performed between Nova Measuring Systems, Ltd., and the Oak Ridge National Laboratory to test and prototype defect signature analysis method for potential incorporation into an in-situ wafer inspection microscope. ORNL's role in this activity was to collaborate with Nova on the analysis and software side of the effort, wile Nova's role was to build the physical microscope and provide data to ORNL for test and evaluation. The objective of this project was to adapt and integrate ORNL's SSA and ADC methods and technologies in the Nova imaging environment. ORNL accomplished this objective by modifying the existing SSA technology for use as a wide-area signature analyzer/classifier on the Nova macro inspection tool (whole-wafer analysis). During this effort ORNL also developed a strategy and methodology for integrating and presenting the results of SSA/ADC analysis to the tool operator and/or data management system (DMS) used by the semiconductor manufacturer (i.e., the end-user).

  14. A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

    PubMed

    Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

    2012-07-01

    We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

  15. A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

    PubMed

    Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

    2012-07-01

    We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging. PMID:22966554

  16. High Throughput, Noncontact System for Screening Silicon Wafers Predisposed to Breakage During Solar Cell Production

    SciTech Connect

    Sopori, B.; Rupnowski, P.; Basnyat, P.; Mehta, V.

    2011-01-01

    We describe a non-contact, on-line system for screening wafers that are likely to break during solar cell/module fabrication. The wafers are transported on a conveyor belt under a light source, which illuminates the wafers with a specific light distribution. Each wafer undergoes a dynamic thermal stress whose magnitude mimics the highest stress the wafer will experience during cell/module fabrication. As a result of the stress, the weak wafers break, leaving only the wafers that are strong enough to survive the production processes. We will describe the mechanism of wafer breakage, introduce the wafer system, and discuss the results of the time-temperature (t-T) profile of wafers with and without microcracks.

  17. Comparison and efficacy of LigaSure and rubber band ligature in closing the inflamed cecal stump in a rat model of acute appendicitis.

    PubMed

    Yeh, Chun-Chieh; Jan, Chia-Ing; Yang, Horng-Ren; Huang, Po-Han; Jeng, Long-Bin; Su, Wen-Pang; Chen, Hui-Chen

    2015-01-01

    Safety of either LigaSure or rubber band in closing inflamed appendiceal stump in acute appendicitis has been less investigated. In this study, cecal ligation followed by resecting inflamed cecum was performed to mimic appendectomy in a rat model of acute appendicitis. Rats were sacrificed immediately (Group A) and 7 days (Group B) after cecal resection, respectively. The cecal stumps were closed by silk ligature (S), 5 mm LigaSure (L), or rubber band (R). Seven days after cecal resection, the LigaSure (BL) and silk subgroups (BS) had significantly less intra-abdominal adhesion and better laparotomy wound healing than rubber band subgroup (BR). The initial bursting pressure at cecal stump was comparable among the three methods; along with tissue healing process, both BL and BS provided a higher bursting pressure than BR 7 days after appendectomy. BL subgroup had more abundant hydroxyproline deposition than BS and BR subgroup. Furthermore, serum TNF-α in BR group kept persistently increasing along with time after cecal resection. Thus, the finding that LigaSure but not rubber band is safe in sealing off the inflamed cecal stump in rat model of acute appendicitis suggests the possibility of applying LigaSure for appendectomy via single port procedure or natural orifice transluminal endoscopic surgery (NOTES).

  18. Fine Mapping of the Interaction between C4b-Binding Protein and Outer Membrane Proteins LigA and LigB of Pathogenic Leptospira interrogans.

    PubMed

    Breda, Leandro C D; Hsieh, Ching-Lin; Castiblanco Valencia, Mónica M; da Silva, Ludmila B; Barbosa, Angela S; Blom, Anna M; Chang, Yung-Fu; Yung-Fu, Chang; Isaac, Lourdes

    2015-01-01

    The complement system consists of more than 40 proteins that participate in the inflammatory response and in pathogen killing. Complement inhibitors are necessary to avoid the excessive consumption and activation of this system on host cells. Leptospirosis is a worldwide zoonosis caused by spirochetes from the genus Leptospira. Pathogenic leptospires are able to escape from complement activation by binding to host complement inhibitors Factor H [FH] and C4b-binding protein (C4BP) while non-pathogenic leptospires are rapidly killed in the presence of fresh serum. In this study, we demonstrate that complement control protein domains (CCP) 7 and 8 of C4BP α-chain interact with the outer membrane proteins LcpA, LigA and LigB from the pathogenic leptospire L. interrogans. The interaction between C4BP and LcpA, LigA and LigB is sensitive to ionic strength and inhibited by heparin. We fine mapped the LigA and LigB domains involved in its binding to C4BP and heparin and found that both interactions are mediated through the bacterial immunoglobulin-like (Big) domains 7 and 8 (LigA7-8 and LigB7-8) of both LigA and LigB and also through LigB9-10. Therefore, C4BP and heparin may share the same binding sites on Lig proteins.

  19. ILT based defect simulation of inspection images accurately predicts mask defect printability on wafer

    NASA Astrophysics Data System (ADS)

    Deep, Prakash; Paninjath, Sankaranarayanan; Pereira, Mark; Buck, Peter

    2016-05-01

    At advanced technology nodes mask complexity has been increased because of large-scale use of resolution enhancement technologies (RET) which includes Optical Proximity Correction (OPC), Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO). The number of defects detected during inspection of such mask increased drastically and differentiation of critical and non-critical defects are more challenging, complex and time consuming. Because of significant defectivity of EUVL masks and non-availability of actinic inspection, it is important and also challenging to predict the criticality of defects for printability on wafer. This is one of the significant barriers for the adoption of EUVL for semiconductor manufacturing. Techniques to decide criticality of defects from images captured using non actinic inspection images is desired till actinic inspection is not available. High resolution inspection of photomask images detects many defects which are used for process and mask qualification. Repairing all defects is not practical and probably not required, however it's imperative to know which defects are severe enough to impact wafer before repair. Additionally, wafer printability check is always desired after repairing a defect. AIMSTM review is the industry standard for this, however doing AIMSTM review for all defects is expensive and very time consuming. Fast, accurate and an economical mechanism is desired which can predict defect printability on wafer accurately and quickly from images captured using high resolution inspection machine. Predicting defect printability from such images is challenging due to the fact that the high resolution images do not correlate with actual mask contours. The challenge is increased due to use of different optical condition during inspection other than actual scanner condition, and defects found in such images do not have correlation with actual impact on wafer. Our automated defect simulation tool predicts

  20. Scales

    MedlinePlus

    Scales are a visible peeling or flaking of outer skin layers. These layers are called the stratum ... Scales may be caused by dry skin, certain inflammatory skin conditions, or infections. Eczema , ringworm , and psoriasis ...

  1. The Study of Deep Lithography and Moulding Process of LIGA Technique

    NASA Astrophysics Data System (ADS)

    Guo, Yuhua; Liu, Gang; Kan, Ya; Tian, Yangchao

    2007-01-01

    The knowledge of the development behavior, especially the development rate, is of primary importance for the study of deep x-ray lithography in LIGA technique. In the first part of this paper, we have measured the development rates of crosslinked PMMA foils irradiated in NSRL covering a wide dose range (bottom dose in the range:2.5-8.0 kJ/cm3). After the exposure, we use a so-called period-development method (to dip development in GG-developer for 20 minutes and clean in rinse solution for 40 minutes as a development period). For processing the experiment data, we get the KDβ model to describe our PMMA/GG-developer system. The aim of this work is to find out a stable experiment condition for deep X-ray lithography and development. The result shows that in small amount of dose (bottom dose range: 2.5-4 kJ/cm3), this model is very stable. While in large amount of dose (bottom dose range: 5-8kJ/cm3), the model becomes very sensitive and even unavailable. To verify the conclusion validity, the fixed dose range (bottom dose range: 3.5-4 kJ/cm3) is applied on PMMA microstructures. And the result shows an effective development process. In the following procedure, mold inserts can be produced by micro-electroforming and plastic replicas can be mass produced by hot embossing. To emboss high-aspect-ratio microstructures, the deformation of microstructures usually occurs due to the demolding forces between the sidewall of mold inserts and the thermoplastic (PMMA). To minimize the friction force the optimized experiment has been performed using Ni-PTFE compound material mold inserts. Typical defects like pull-up and damaged edges can be greatly reduced.

  2. Comparison of hemorrhoidectomy by LigaSure with conventional Milligan Morgan’s hemorrhoidectomy

    PubMed Central

    Bakhtiar, Nighat; Moosa, Foad Ali; Jaleel, Farhat; Qureshi, Naeem Akhtar; Jawaid, Masood

    2016-01-01

    Objective: To compare the efficacy of haemorrhoidectomy done by using LigaSure with conventional Milligan Morgan haemorrhoidectomy. Methods: This randomized controlled trial was done at Department of Surgery Dow University Hospital Karachi during January 2013 to September 2015. A total of 55 patients were included in the study. Patients were randomly allocated to group A (Haemorrhoidectomy by Ligasure) and group B (Milligan Morgan Haemorrhoiectomy). Efficacies of both procedures were compared by operative time, Blood loss, wound healing, and pain score on immediate, 1st and 7th post operative day. Results: Out of total 55 patients 23 were male and 32 were females. The most common group of age involved was between 40 – 60 years. Third degree Heamorrhoids were present in 37 (67.3%) of patients while remaining 18 (32.7%) had fourth degree Heamorrhoids. Group A included 29 cases while Group B included 26 cases. The mean operating time of Group A was 52.5 with standard deviation of 11.9 while it was 36.6± 9.8 in the other group. The mean blood loss in group A was 51.92 with standard deviation of 15.68 while it was 70.34±25.59 in group B. Overall pain score was less in those patients who underwent Heamorrhoidectomy by Ligasure method. Conclusion: The efficacy of Heamorrhoidectomy by Ligasure is better than the traditional Milligan Morgan Heamorrhoidectomy but we need more clinical trials with large sample size and long term follow ups. PMID:27375709

  3. Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering

    NASA Astrophysics Data System (ADS)

    Chen, Po-Ying; Tsai, Ming-Hsing; Yeh, Wen-Kuan; Jing, Ming-Haw; Chang, Yukon

    2009-12-01

    Silicon wafer breakage has become a major concern for all semiconductor fabrication lines because it is brittle, and thus high stresses are easily induced in its manufacture. The production cost of devices significantly increases even for a breakage loss of a few percent if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant. In this investigation, we develop a brand new approach to reducing breakage by using a charge-coupled device (CCD) to capture the cross-section image of the wafer at its edge; the data measured at the edge can be used to determine overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength, and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in the wafer bulk before failure. We also describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unidentified causes. Our analysis gives the optimal front size (B1), edge widths (A1,A2), and bevel angle (θ) for the edge profiles of wafers to prevent wafer breakage. Briefly, when a suitable material and suitable process control approaches are utilized, silicon wafer breakage can be prevented. This is the first investigation providing evidence that whole-wafer strength is an important issue. We present a physical model to explain why wafer fracture has become an increasingly serious problem as the diameter of wafers has increased. The control of wafer edge geometry has been demonstrated to be an effective means of protecting wafers with large diameters against breakage. This model reveals that the breakage rate of wafers can be reduced by controlling the uniformity of the differences between the front size and the rear edge widths during the wafer manufacturing process.

  4. Low-temperature titanium-based wafer bonding

    NASA Astrophysics Data System (ADS)

    Yu, Jian

    This thesis presents novel methods of metal-based wafer bonding at back-end-of-the-line (BEOL) compatible conditions (≤450°C). For the first time to our knowledge, 200 mm diameter oxidized Si wafers are bonded with prime Si wafers using 10-300 nm thick Ti as bonding intermediate at 300-450°C. Nearly void-free bonding with strong mechanical integrity has been confirmed. Moreover, microcavity formation has been demonstrated by bonding of patterned wafers. Both Rutherford backscattering spectroscopy (RBS) and Auger electron spectroscopy (AES) show clear evidence of Si and Ti interdiffusion, whereas high-resolution transmission electron microscopy (HRTEM) reveals an approximately 8 nm thick amorphous layer at the bonding interface. Those results indicate that the strong adhesion at the Ti/Si bonding interface is attributed to a solid-state amorphization (SSA) assisted by interdiffusion. A key effort is devoted to fundamental investigation of low-temperature transition metal(TM)/Si-based wafer bonding. With the extensive work on Ti/Si system, additional experiments are performed with six other TM/Si systems, namely Ni/Si, Co/Si, Pd/Si, Hf/Si, Au/Si and Ta/Si. The results indicate there are two principal requirements for TM/Si-based wafer bonding: (1) intimate contact (able to break through kinetic barriers), and (2) adequate chemical bonding. Three kinetic barriers addressed in this thesis are: (1) enclosed microvoids due to surface roughness, (2) gas molecules at the bonding interface, and (3) interfacial oxides. Presence of these barriers can prevent formation of intimate contact, consequently retarding or even blocking interfacial interactions for chemical bonding. The unique properties of Group IVA metals (e.g., Ti and Hf) to reduce native SiO2 on Si surfaces and their exceptionally large solid solubility for O2 and N2, help overcome those issues. Once kinetic barriers are surmounted, the key for strong metal/Si-based wafer bonding is formation of chemical bonds

  5. Quantitative phase measurement for wafer-level optics

    NASA Astrophysics Data System (ADS)

    Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

    2015-07-01

    Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

  6. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    NASA Astrophysics Data System (ADS)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  7. Simple and accurate optical height sensor for wafer inspection systems

    NASA Astrophysics Data System (ADS)

    Shimura, Kei; Nakai, Naoya; Taniguchi, Koichi; Itoh, Masahide

    2016-02-01

    An accurate method for measuring the wafer surface height is required for wafer inspection systems to adjust the focus of inspection optics quickly and precisely. A method for projecting a laser spot onto the wafer surface obliquely and for detecting its image displacement using a one-dimensional position-sensitive detector is known, and a variety of methods have been proposed for improving the accuracy by compensating the measurement error due to the surface patterns. We have developed a simple and accurate method in which an image of a reticle with eight slits is projected on the wafer surface and its reflected image is detected using an image sensor. The surface height is calculated by averaging the coordinates of the images of the slits in both the two directions in the captured image. Pattern-related measurement error was reduced by applying the coordinates averaging to the multiple-slit-projection method. Accuracy of better than 0.35 μm was achieved for a patterned wafer at the reference height and ±0.1 mm from the reference height in a simple configuration.

  8. WaferOptics® mass volume production and reliability

    NASA Astrophysics Data System (ADS)

    Wolterink, E.; Demeyer, K.

    2010-05-01

    The Anteryon WaferOptics® Technology platform contains imaging optics designs, materials, metrologies and combined with wafer level based Semicon & MEMS production methods. WaferOptics® first required complete new system engineering. This system closes the loop between application requirement specifications, Anteryon product specification, Monte Carlo Analysis, process windows, process controls and supply reject criteria. Regarding the Anteryon product Integrated Lens Stack (ILS), new design rules, test methods and control systems were assessed, implemented, validated and customer released for mass production. This includes novel reflowable materials, mastering process, replication, bonding, dicing, assembly, metrology, reliability programs and quality assurance systems. Many of Design of Experiments were performed to assess correlations between optical performance parameters and machine settings of all process steps. Lens metrologies such as FFL, BFL, and MTF were adapted for wafer level production and wafer mapping was introduced for yield management. Test methods for screening and validating suitable optical materials were designed. Critical failure modes such as delamination and popcorning were assessed and modeled with FEM. Anteryon successfully managed to integrate the different technologies starting from single prototypes to high yield mass volume production These parallel efforts resulted in a steep yield increase from 30% to over 90% in a 8 months period.

  9. Measuring Radiation Patterns of Reconfigurable Patch Antennas on Wafers

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.

    2004-01-01

    An apparatus and technique have been devised for measuring the radiation pattern of a microwave patch antenna that is one of a number of identical units that have been fabricated in a planar array on a high-resistivity silicon wafer. The apparatus and technique are intended, more specifically, for application to such an antenna that includes a DC-controlled microelectromechanical system (MEMS) actuator for switching the antenna between two polarization states or between two resonance frequencies. Prior to the development of the present apparatus and technique, patch antennas on wafers were tested by techniques and equipment that are more suited to testing of conventional printed-circuit antennas. The techniques included sawing of the wafers to isolate individual antennas for testing. The equipment included custom-built test fixtures that included special signal launchers and transmission-line transitions. The present apparatus and technique eliminate the need for sawing wafers and for custom-built test fixtures, thereby making it possible to test antennas in less time and at less cost. Moreover, in a production setting, elimination of the premature sawing of wafers for testing reduces loss from breakage, thereby enhancing yield.

  10. A benchmark investigation on cleaning photomasks using wafer cleaning technologies

    NASA Astrophysics Data System (ADS)

    Kindt, Louis; Burnham, Jay; Marmillion, Pat

    2004-12-01

    As new technologies are developed for smaller linewidths, the specifications for mask cleanliness become much stricter. Not only must the particle removal efficiency increase, but the largest allowable particle size decreases. Specifications for film thickness and surface roughness are becoming tighter and consequently the integrity of these films must be maintained in order to preserve the functionality of the masks. Residual contamination remaining on the surface of the mask after cleaning processes can lead to subpellicle defect growth once the mask is exposed in a stepper environment. Only during the last several years, has an increased focus been put on improving mask cleaning. Over the years, considerably more effort has been put into developing advanced wafer cleaning technologies. However, because of the small market involved with mask cleaning, wafer cleaning equipment vendors have been reluctant to invest time and effort into developing cleaning processes and adapting their toolset to accommodate masks. With the advent of 300 mm processing, wafer cleaning tools are now more easily adapted to processing masks. These wafer cleaning technologies may offer a solution to the difficulties of mask cleaning and need to be investigated to determine whether or not they warrant continued investigation. This paper focuses on benchmarking advanced wafer cleaning technologies applied to mask cleaning. Ozonated water, hydrogenated water, super critical fluids, and cryogenic cleaning have been investigated with regards to stripping resist and cleaning particles from masks. Results that include film thickness changes, surface contamination, and particle removal efficiency will be discussed.

  11. 100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices

    SciTech Connect

    OLIVER,ANDREW D.; MATZKE,CAROLYN M.

    2000-04-06

    A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

  12. Optical wafer metrology sensors for process-robust CD and overlay control in semiconductor device manufacturing

    NASA Astrophysics Data System (ADS)

    den Boef, Arie J.

    2016-06-01

    This paper presents three optical wafer metrology sensors that are used in lithography for robustly measuring the shape and position of wafers and device patterns on these wafers. The first two sensors are a level sensor and an alignment sensor that measure, respectively, a wafer height map and a wafer position before a new pattern is printed on the wafer. The third sensor is an optical scatterometer that measures critical dimension-variations and overlay after the resist has been exposed and developed. These sensors have different optical concepts but they share the same challenge that sub-nm precision is required at high throughput on a large variety of processed wafers and in the presence of unknown wafer processing variations. It is the purpose of this paper to explain these challenges in more detail and give an overview of the various solutions that have been introduced over the years to come to process-robust optical wafer metrology.

  13. White-light interferometric microscopy for wafer defect inspection

    NASA Astrophysics Data System (ADS)

    Zhou, Renjie; Edwards, Christopher; Bryniarski, Casey; Dallmann, Marjorie F.; Popescu, Gabriel; Goddard, Lynford L.

    2015-03-01

    White-light imaging systems are free of laser-speckle. Thus, they offer high sensitivity for optical defect metrology, especially when used with interferometry based quantitative phase imaging. This can be a potential solution for wafer inspection beyond the 9 nm node. Recently, we built a white-light epi-illumination diffraction phase microscopy (epi-wDPM) for wafer defect inspection. The system is also equipped with an XYZ scanning stage and real-time processing. Preliminary results have demonstrated detection of 15 nm by 90 nm in a 9 nm node densely patterned wafer with bright-field imaging. Currently, we are implementing phase imaging with epi-wDPM for additional sensitivity.

  14. Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

    NASA Astrophysics Data System (ADS)

    Ostapenko, S.; Tarasov, I.

    2000-04-01

    A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

  15. Growth of silver nanowires on GaAs wafers.

    PubMed

    Sun, Yugang

    2011-05-01

    Silver (Ag) nanowires with chemically clean surfaces have been directly grown on semi-insulating gallium arsenide (GaAs) wafers through a simple solution/solid interfacial reaction (SSIR) between the GaAs wafers themselves and aqueous solutions of silver nitrate (AgNO(3)) at room temperature. The success in synthesis of Ag nanowires mainly benefits from the low concentration of surface electrons in the semi-insulating GaAs wafers that can lead to the formation of a low-density of nuclei that facilitate their anisotropic growth into nanowires. The resulting Ag nanowires exhibit rough surfaces and reasonably good electric conductivity. These characteristics are beneficial to sensing applications based on single-nanowire surface-enhanced Raman scattering (SERS) and possible surface-adsorption-induced conductivity variation.

  16. Monitoring of acoustic emission activity using thin wafer piezoelectric sensors

    NASA Astrophysics Data System (ADS)

    Trujillo, Blaine; Zagrai, Andrei; Meisner, Daniel; Momeni, Sepand

    2014-03-01

    Acoustic emission (AE) is a well-known technique for monitoring onset and propagation of material damage. The technique has demonstrated utility in assessment of metallic and composite materials in applications ranging from civil structures to aerospace vehicles. While over the course of few decades AE hardware has changed dramatically with the sensors experiencing little changes. A traditional acoustic emission sensor solution utilizes a thickness resonance of the internal piezoelectric element which, coupled with internal amplification circuit, results in relatively large sensor footprint. Thin wafer piezoelectric sensors are small and unobtrusive, but they have seen limited AE applications due to low signal-to-noise ratio and other operation difficulties. In this contribution, issues and possible solutions pertaining to the utility of thin wafer piezoelectrics as AE sensors are discussed. Results of AE monitoring of fatigue damage using thin wafer piezoelectric and conventional AE sensors are presented.

  17. Microwave Induced Direct Bonding of Single Crystal Silicon Wafers

    NASA Technical Reports Server (NTRS)

    Budraa, N. K.; Jackson, H. W.; Barmatz, M.

    1999-01-01

    We have heated polished doped single-crystal silicon wafers in a single mode microwave cavity to temperatures where surface to surface bonding occurred. The absorption of microwaves and heating of the wafers is attributed to the inclusion of n-type or p-type impurities into these substrates. A cylindrical cavity TM (sub 010) standing wave mode was used to irradiate samples of various geometry's at positions of high magnetic field. This process was conducted in vacuum to exclude plasma effects. This initial study suggests that the inclusion of impurities in single crystal silicon significantly improved its microwave absorption (loss factor) to a point where heating silicon wafers directly can be accomplished in minimal time. Bonding of these substrates, however, occurs only at points of intimate surface to surface contact. The inclusion of a thin metallic layer on the surfaces enhances the bonding process.

  18. 450mm wafer patterning with jet and flash imprint lithography

    NASA Astrophysics Data System (ADS)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  19. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    SciTech Connect

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  20. Apparatus and method for measuring the thickness of a semiconductor wafer

    DOEpatents

    Ciszek, T.F.

    1995-03-07

    Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

  1. Wafer CD variation for random units of track and polarization

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Ackmann, Paul; Richter, Frank; Kurth, Karin; Maelzer, Stephanie; Hsieh, Michael; Schurack, Frank; GN, Fang Hong

    2012-03-01

    After wafer processing in a scanner the process of record (POR) flows in a photo track are characterized by a random correlation between post exposure bake (PEB) and development (DEV) units of the photo track. The variation of the critical dimensions (CD) of the randomly correlated units used for PEB and DEV should be as small as possible - especially for technology nodes of 28nm and below. Even a point-to-point error of only 1nm could affect the final product yield results due to the relatively narrow process window of 28nm tech-node. The correlation between reticle measurements to target (MTT) and wafer MTT may in addition be influenced by the random correlation between units used for PEB and DEV. The polarization of the light source of the scanner is one of the key points for the wafer CD performance too - especially for the critical dimensions uniformity (CDU) performance. We have investigated two track flows, one with fixed and one with random unit correlation. The reticle used for the experiments is a 28nm active layer sample reticle. The POR track flow after wafer process in the scanner is characterized by a random correlation between PEB- and DEV-units. The set-up of the engineering (ENG) process flow is characterized by a fixed unit correlation between PEB- and development-units. The critical dimension trough pitch (CDTP) and linearity performance is demonstrated; also the line-end performance for two dimensional (2D) structures is shown. The sub-die of intra-field CDU for isolated and dense structures is discussed as well as the wafer intra-field CD performance. The correlation between reticle MTT and wafer intra-field MTT is demonstrated for track POR and ENG processes. For different polarization conditions of the scanner source, the comparison of CDU for isolated and dense features has been shown. The dependency of the wafer intra-field MTT with respect to different polarization settings of the light source is discussed. The correlation between reticle

  2. Digital model planning and computerized fabrication of orthognathic surgery wafers.

    PubMed

    Cousley, Richard R J; Turner, Mark J A

    2014-03-01

    Conventional orthognathic wafers are made by a process involving manual movement of stone dental models and acrylic laboratory fabrication. In addition, a facebow record and semi-adjustable articulator system are required for maxillary osteotomy cases. This paper introduces a novel process of producing both intermediate and final orthognathic surgical wafers using a combination of computerized digital model simulation and three-dimensional print fabrication, without the need for either a facebow record or the additional ionizing radiation exposure associated with cone beam computerized tomography.

  3. An application of selective electrochemical wafer thinning for silicon characterization

    SciTech Connect

    Medernach, J.W.; Stein, H.J.; Stevenson, J.O.

    1990-01-01

    A new technique is reported for the rapid determination of interstitial oxygen (O{sub i}) in heavily doped n{sup +} and p{sup +} silicon. This technique includes application of a selective electrochemical thinning (SET) process and FTIR transmittance measurement on a limited area of a silicon wafer. The O{sub i} is calculated using ASTM F1188--88 with the IOC 88 calibration factor. An advantage of SET over mechanical thinning is that the original wafer thickness and diameter are maintained for additional processing. 1 tab.

  4. SUEX process optimization for ultra-thick high-aspect ratio LIGA imaging

    NASA Astrophysics Data System (ADS)

    Johnson, Donald W.; Goettert, Jost; Singh, Varshni; Yemane, Dawit

    2011-04-01

    The focus of this paper is on the use of SUEX Thick Dry Film Sheet (TDFS) laminates which DJ DevCorp is developing as a thick resist material in optical and X-ray lithography. Preliminary thick dry film sheets up to 1mm thickness were successfully prepared and patterned at the CAMD X-ray beamlines and presented at HARMST 2007. Recently, new results have been published using SUEX resist sheets in UV lithography showing great market potential including plating molds for metal microparts, polymer MEMS, multilayer microfluidics structures, BioMEMS, medical devices, wafer level packaging processes, and displays. The SUEX TDFS are available in a range of thicknesses from 100μm to 1mm or more and are pre-cut into a number of standard wafer sizes. This new material is a modified epoxy formulation containing an antimony-free photo acid generator (PAG) prepared under a highly controlled solvent-less process which provides uniform coatings between two throw-away layers of protective polyester film. As part of our initial studies resist layers of 250, 500 and 1000μm were laminated onto regular silicon wafers using a hot roll laminator at a speed of 1ft/min at 75°C. The entire substrate preparation takes about 1 hour and with practice users can prepare up to 10 substrates in this time which are typically ready to use within 2 hours. In our efforts to develop a commercially viable product we have conducted experiments using standard equipment available at CAMD (Quintel UV aligner and CAMD XRLM 1 and 4 beamline). Initial X-ray exposure tests were done with a bottom dose ranging between 100 and 400 J/cm3 and a top/bottom dose ratio of less than 3 for sheets up to 2mm in thickness. Exposure time for typical conditions of the CAMD storage ring (ring current ranging between 100 and 160mA, beam lifetime of about 10hrs at 100mA ring current) is about 10-15min for a 4' wafer. After exposure the samples were immediately post exposure baked between 70°C and 110°C using a convection

  5. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    NASA Technical Reports Server (NTRS)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  6. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    NASA Astrophysics Data System (ADS)

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, Sanghyeon; Choi, Won Jun

    2016-02-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

  7. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

    PubMed Central

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-01-01

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

  8. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications.

    PubMed

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-02-11

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called "Si photonics"). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

  9. A reclaiming process for solar cell silicon wafer surfaces.

    PubMed

    Pa, P S

    2011-01-01

    The low yield of epoxy film and Si3N4 thin-film deposition is an important factor in semiconductor production. A new design system using a set of three lamination-shaped electrodes as a machining tool and micro electro-removal as a precision reclaiming process of the Si3N4 layer and epoxy film removal from silicon wafers of solar cells surface is presented. In the current experiment, the combination of the small thickness of the anode and cathodes corresponds to a higher removal rate for the thin films. The combination of the short length of the anode and cathodes combined with enough electric power produces fast electroremoval. A combination of the small edge radius of the anode and cathodes corresponds to a higher removal rate. A higher feed rate of silicon wafers of solar cells combined with enough electric power produces fast removal. A precise engineering technology constructed a clean production approach for the removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers from solar cells that can reduce pollution and lower cost. PMID:21446525

  10. Ultra-Gradient Test Cavity for Testing SRF Wafer Samples

    SciTech Connect

    N.J. Pogue, P.M. McIntyre, A.I. Sattarov, C. Reece

    2010-11-01

    A 1.3 GHz test cavity has been designed to test wafer samples of superconducting materials. This mushroom shaped cavity, operating in TE01 mode, creates a unique distribution of surface fields. The surface magnetic field on the sample wafer is 3.75 times greater than elsewhere on the Niobium cavity surface. This field design is made possible through dielectrically loading the cavity by locating a hemisphere of ultra-pure sapphire just above the sample wafer. The sapphire pulls the fields away from the walls so the maximum field the Nb surface sees is 25% of the surface field on the sample. In this manner, it should be possible to drive the sample wafer well beyond the BCS limit for Niobium while still maintaining a respectable Q. The sapphire's purity must be tested for its loss tangent and dielectric constant to finalize the design of the mushroom test cavity. A sapphire loaded CEBAF cavity has been constructed and tested. The results on the dielectric constant and loss tangent will be presented

  11. Fabricating a Microcomputer on a Single Silicon Wafer

    NASA Technical Reports Server (NTRS)

    Evanchuk, V. L.

    1983-01-01

    Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

  12. Crack propagation and fracture in silicon wafers under thermal stress

    PubMed Central

    Danilewsky, Andreas; Wittge, Jochen; Kiefl, Konstantin; Allen, David; McNally, Patrick; Garagorri, Jorge; Elizalde, M. Reyes; Baumbach, Tilo; Tanner, Brian K.

    2013-01-01

    The behaviour of microcracks in silicon during thermal annealing has been studied using in situ X-ray diffraction imaging. Initial cracks are produced with an indenter at the edge of a conventional Si wafer, which was heated under temperature gradients to produce thermal stress. At temperatures where Si is still in the brittle regime, the strain may accumulate if a microcrack is pinned. If a critical value is exceeded either a new or a longer crack will be formed, which results with high probability in wafer breakage. The strain reduces most efficiently by forming (hhl) or (hkl) crack planes of high energy instead of the expected low-energy cleavage planes like {111}. Dangerous cracks, which become active during heat treatment and may shatter the whole wafer, can be identified from diffraction images simply by measuring the geometrical dimensions of the strain-related contrast around the crack tip. Once the plastic regime at higher temperature is reached, strain is reduced by generating dislocation loops and slip bands and no wafer breakage occurs. There is only a small temperature window within which crack propagation is possible during rapid annealing. PMID:24046487

  13. Interaction of an argon plasma jet with a silicon wafer

    NASA Astrophysics Data System (ADS)

    Engelhardt, Max; Pothiraja, Ramasamy; Kartaschew, Konstantin; Bibinov, Nikita; Havenith, Martina; Awakowicz, Peter

    2016-04-01

    A filamentary discharge is ignited in an argon plasma jet under atmospheric pressure conditions. The gas discharge is characterized with voltage-current measurements, optical emission spectroscopy and an ICCD-camera with a high temporal resolution down to 10 ns. In the effluent of the plasma jet, filaments come into contact with the surface of a silicon wafer and modify it, namely etching traces are produced and microcrystals are deposited. These traces are studied with optical and electron microscopes. The material of the deposited microcrystals and the surface modifications of the silicon wafer are analyzed with Raman microspectroscopy. Amorphous silicon is found within the etching traces. The largest part of the deposited microcrystals are composed of nitratine (NaNO3) and some of them are calcite (CaCO3). Analyzing the possible reasons for the silicon wafer modifications we come to the conclusion that plasmoids, which are produced near the substrate surface by interaction with ionization waves, are a plausible explanation for the observed surface modifications of the silicon wafer.

  14. National solar technology roadmap: Wafer-silicon PV

    SciTech Connect

    Sopori, Bhushan

    2007-06-01

    This report applies to all bulk-silicon-based PV technologies, including those based on Czochralski, multicrystalline, float-zone wafers, and melt-grown crystals that are 100 μm or thicker, such as ribbons, sheet, or spheral silicon.

  15. Bonding silicon-on-insulator to glass wafers for integrated bio-electronic circuits

    NASA Astrophysics Data System (ADS)

    Kim, Hyun S.; Blick, Robert H.; Kim, D. M.; Eom, C. B.

    2004-09-01

    We report a method for bonding silicon-on-insulator wafers onto glass wafers. After pre-cleaning the wafers by an ozone and ultraviolet exposure, followed by mega-sonic water rinse, the SOI wafers are bonded to glass wafers in a vacuum chamber. This is performed at a temperature of 400 °C under an applied voltage of 700 V. The interface between the glass and SOI wafer is tested mechanically and inspected by electron beam microscopy. Furthermore, we demonstrate removal of the silicon bulk layer after wafer bonding. The quality of the single crystalline Si thin film on the glass wafers has been verified by four-circle x-ray diffraction and scanning electron microscopy. This process will allow us the integration of thin-film electronics in biological sensor applications.

  16. Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

    NASA Astrophysics Data System (ADS)

    Calaway, M. J.; Rodriguez, M. C.; Allton, J. H.; Stansbery, E. K.

    2009-03-01

    The cleaning efficiency of the Genesis Ultra-pure Water Megasonic Wafer Spin Cleaner will be presented. Results show the effectiveness of the new cleaner removing particle contamination from Genesis silicon wafers implanted with solar wind.

  17. Correlation of the structural properties of a Pt seed layer with the perpendicular magnetic anisotropy features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 junctions via a 12-inch scale Si wafer process

    NASA Astrophysics Data System (ADS)

    Chae, Kyo-Suk; Lee, Du-Yeong; Shim, Tae-Hun; Hong, Jin-Pyo; Park, Jea-Gun

    2013-10-01

    We elucidated the interfacial-perpendicular magnetic anisotropy (i-PMA) features of full Heusler-based Co2FeAl/MgO/Co2Fe6B2 magnetic-tunnel-junctions as functions of the structural properties of the Pt seed layer including its thickness and ex situ annealing temperature. All of the samples were prepared in a 12-inch silicon wafer process for real industry applications. The observations of the M-H loops emphasize that a thinner Pt seed layer and a high ex situ annealing temperature enhance the surface roughness of the seed layer, providing better i-PMA characteristics. HR-TEM images of the samples were evaluated to understand the structural effects of thin and thick Pt seed layers.

  18. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    SciTech Connect

    Qiusheng, Y. Senkai, C. Jisheng, P.

    2015-03-30

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  19. Scale

    ERIC Educational Resources Information Center

    Schaffhauser, Dian

    2009-01-01

    The common approach to scaling, according to Christopher Dede, a professor of learning technologies at the Harvard Graduate School of Education, is to jump in and say, "Let's go out and find more money, recruit more participants, hire more people. Let's just keep doing the same thing, bigger and bigger." That, he observes, "tends to fail, and fail…

  20. Mask blank defect printability comparison using optical and SEM mask and wafer inspection and bright field actinic mask imaging

    NASA Astrophysics Data System (ADS)

    Mangat, Pawitter; Verduijn, Erik; Wood, Obert R.; Benk, Markus P.; Wojdyla, Antoine; Goldberg, Kenneth A.

    2015-07-01

    Despite significant enhancements in defect detection using optical and e-beam methodology, the smaller length scales and increasing challenges of future technology nodes motivate ongoing research into the need and associated cost of actinic inspection for EUV masks. This paper reports an extensive study of two EUV patterned masks, wherein the mask blank defectivity was characterized using optical (mask and wafer) methods and bright-field mask imaging (using the SHARP actinic microscope) of previously identified blank defects. We find that the bright field actinic imaging tool microscope captures and images many defects that are not seen by the automated optical inspection of patterned masks and printed wafers. In addition, actinic review reveals the impact of multilayer damage and depicts the printability profile which can be used as an added metric to define the patterned mask repair and defect compensation strategies.

  1. Height inspection of wafer bumps without explicit 3D reconstruction

    NASA Astrophysics Data System (ADS)

    Dong, Mei; Chung, Ronald; Zhao, Yang; Lam, Edmund Y.

    2006-02-01

    The shrunk dimension of electronic devices leads to more stringent requirement on process control and quality assurance of their fabrication. For instance, direct die-to-die bonding requires placement of solder bumps not on PCB but on the wafer itself. Such wafer solder bumps, which are much miniaturized from the counterparts on PCB, still need to have their heights meet the specification, or else the electrical connection could be compromised, or the dies be crushed, or even the manufacturing equipments be damaged. Yet the tiny size, typically tens of microns in diameter, and the textureless and mirror nature of the bumps pose great challenge to the 3D inspection process. This paper addresses how a large number of such wafer bumps could have their heights massively checked against the specification. We assume ball bumps in this work. We propose a novel inspection measure about the collection of bump heights that possesses these advantages: (1) it is sensitive to global and local disturbances to the bump heights, thus serving the bump height inspection purpose; (2) it is invariant to how individual bumps are locally displaced against one another on the substrate surface, thus enduring 2D displacement error in soldering the bumps onto the wafer substrate; and (3) it is largely invariant to how the wafer itself is globally positioned relative to the imaging system, thus having tolerance to repeatability error in wafer placement. This measure makes use of the mirror nature of the bumps, which used to cause difficulty in traditional inspection methods, to capture images of two planes. One contains the bump peaks and the other corresponds to the substrate. With the homography matrices of these two planes and fundamental matrix of the camera, we synthesize a matrix called Biplanar Disparity Matrix. This matrix can summarize the bumps' heights in a fast and direct way without going through explicit 3D reconstruction. We also present a design of the imaging and

  2. Wafer-level packaging with compression-controlled seal ring bonding

    DOEpatents

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  3. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    NASA Astrophysics Data System (ADS)

    Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

    2016-02-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

  4. Scales

    SciTech Connect

    Murray Gibson

    2007-04-27

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain — a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  5. Scales

    ScienceCinema

    Murray Gibson

    2016-07-12

    Musical scales involve notes that, sounded simultaneously (chords), sound good together. The result is the left brain meeting the right brain — a Pythagorean interval of overlapping notes. This synergy would suggest less difference between the working of the right brain and the left brain than common wisdom would dictate. The pleasing sound of harmony comes when two notes share a common harmonic, meaning that their frequencies are in simple integer ratios, such as 3/2 (G/C) or 5/4 (E/C).

  6. Characterization of Boron Diffusion Phenomena According to the Specific Resistivity of N-Type Si Wafer.

    PubMed

    Lee, Woo-Jin; Choi, Chel-Jong; Park, Gye-Choon; Yang, O-Bong

    2016-02-01

    This paper is directed to characterize the boron diffusion process according to the specific resistivity of the Si wafer. N-type Si wafers were used with the specific resistivity of 0.5-3.2 omega-cm, 1.0-6.5 omega-cm and 2.0-8.0 omega-cm. The boron tribromide (BBr3) was used as boron source to create the PN junction on N-type Si wafer. The boron diffusion in N-type Si wafer was characterized by sheet resistance of wafer surface, secondary ion mass spectroscopy measurements (SIMS) and surface life time analysis. The degree of boron diffusion was depended on the variation in specific resistivity and sheet resistance of the bare N-type Si wafer. The boron diffused N-Si wafer exhibited the average junction depth of 750 nm and boron concentration of 1 x 10(19). N-type Si wafer with the different specific resistance considerably affected the boron diffusion length and life time of Si wafer. It was found that the lifetime of boron diffused wafer was proportional to the sheet resistance and resistivity. However, optimization process may necessary to achieve the high efficiency through the high sheet resistance wafer, because the metallization process control is very sensitive.

  7. A silicon wafer packaging solution for HB-LEDs

    NASA Astrophysics Data System (ADS)

    Murphy, Tom; Weichel, Steen; Isaacs, Steven; Kuhmann, Jochen

    2007-09-01

    In this paper we present HyLED, a silicon wafer packaging solution for high-brightness LEDs. The associated technology is batch micro-machining/metallisation processing of silicon wafers allowing significant reduction of the final device size. The presented package is multi-functional where the micro-machined cavity acts as reflector, thermal conductor and reservoir for the silicone/colour conversion substance. The base material, silicon, has excellent mechanical and thermal properties and enables direct integration of intelligence. We present customer specific solutions, open tool samples and performance data for optical and thermal parameters and reliability testing. Thermal resistance values of R<5 K/W, junction-to-board are demonstrated.

  8. Chemical method for producing smooth surfaces on silicon wafers

    DOEpatents

    Yu, Conrad

    2003-01-01

    An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

  9. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    SciTech Connect

    Montoya, Angela C.; Maji, Arup K.

    2010-02-22

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  10. Surface shape control of the workpiece in a double-spindle triple-workstation wafer grinder

    NASA Astrophysics Data System (ADS)

    Xianglong, Zhu; Renke, Kang; Zhigang, Dong; Guang, Feng

    2011-10-01

    Double-spindle triple-workstation (DSTW) ultra precision grinders are mainly used in production lines for manufacturing and back thinning large diameter (>= 300 mm) silicon wafers for integrated circuits. It is important, but insufficiently studied, to control the wafer shape ground on a DSTW grinder by adjusting the inclination angles of the spindles and work tables. In this paper, the requirements of the inclination angle adjustment of the grinding spindles and work tables in DSTW wafer grinders are analyzed. A reasonable configuration of the grinding spindles and work tables in DSTW wafer grinders are proposed. Based on the proposed configuration, an adjustment method of the inclination angle of grinding spindles and work tables for DSTW wafer grinders is put forward. The mathematical models of wafer shape with the adjustment amount of inclination angles for both fine and rough grinding spindles are derived. The proposed grinder configuration and adjustment method will provide helpful instruction for DSTW wafer grinder design.

  11. Influence of the bonding front propagation on the wafer stack curvature

    SciTech Connect

    Navarro, E.; Bréchet, Y.; Barthelemy, A.; Radu, I.; Pardoen, T.; Raskin, J.-P.

    2014-08-11

    The influence of the dynamics of the direct wafer bonding process on the curvature of the final wafer stack is investigated. An analytical model for the final curvature of the bonded wafers is developed, as a function of the different load components acting during the bonding front propagation, using thin plate theory and considering a strain discontinuity locked at the bonding interface. Experimental profiles are measured for different bonding conditions and wafer thicknesses. A very good agreement with the model prediction is obtained and the influence of the thin air layer trapped in-between the two wafers is demonstrated. The proposed model contributes to further improvement of the bonding process, in particular, for the stacking of layers of electronic devices, which requires a high accuracy of wafer-to-wafer alignment and a very low distortion level.

  12. A photo-sensor on thin polysilicon membrane embedded in wafer level package LED

    NASA Astrophysics Data System (ADS)

    Kim, Jin Kwan; Lee, Hee Chul

    2012-06-01

    A wafer level packaging LED with photo-sensor which is fabricated on thin poly-silicon membrane located on the corner of silicon cavity is presented in this paper. The wafer substrate was fabricated with (100) orientation silicon wafer and a cavity was etched on the top of the wafer with wet chemical anisotropic etching process for mounting a LED chip. A thin polysilicon membrane was fabricated on the corner of the cavity and a MSM (Metal Semiconductor Metal) type photo-sensor was fabricated on the thin polysilicon membrane. The photo-sensor fabrication and LED packaging were completed on wafer level. The embedded photo-sensor in a wafer level packaging LED is designed to measure light intensity of a LED. The membrane structure photo-sensor can sense the light of the mounted LED directly, so it can measure accurate light intensity of the wafer level packing LED.

  13. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    NASA Astrophysics Data System (ADS)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  14. Towards reduced impact of EUV mask defectivity on wafer

    NASA Astrophysics Data System (ADS)

    Jonckheere, R.; Van den Heuvel, D.; Pacco, A.; Pollentier, I.; Baudemprez, B.; Jehoul, C.; Hermans, J.; Hendrickx, E.

    2014-07-01

    The defectivity challenges of extreme ultraviolet (EUV) masks, that need to be addressed before production readiness of EUV lithography is assured from the mask perspective, are twofold. First, the EUV-specific defect type relating to the multi-layer (ML) mirror, the so-called ML-defects, require to become more detectable than they are printable. This not only requires proven capability of blank inspection, but also the existence of satisfactory printability mitigation strategies (comprising avoidance, pattern shift methodology, compensation repair). Both these assets need to become available within the mask supply chain, as there is little that can still be done about such residual defects at the wafer fab. In a production phase, finding unexpected printing ML-defects is unacceptable. It is shown how the specific way-of-working in use at imec, starting from the printed wafer, contributes to related learning and identification of remaining gaps, in getting this issue fully dealt with. The second challenge relates to particle contamination during use of the reticle at the wafer fab. Avoiding overlaycritical particles on the backside of NXE3100 reticles is facilitated by the established way-of-working. Minimizing the occurrence of particles "hopping" between reticles via the electrostatic clamp of the scanner (so-called clamp-traveling particles) is a major driver for appropriate mask cleaning. The latter may not have negative impact by frequent use, in view of the highly vulnerable EUV mask stack, and especially for the present "black-border" solution in which the ML is etched away at the image border on the reticle. A lot of effort is spent into monitoring of NXE3100 reticles for particle adders on the pattern side. This is realized by comparing past and present mask defect maps obtained by inspection of printed wafers with subsequent repeater analysis.

  15. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, C.M.; Hui, W.C.

    1996-11-19

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

  16. Method for making circular tubular channels with two silicon wafers

    DOEpatents

    Yu, Conrad M.; Hui, Wing C.

    1996-01-01

    A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

  17. Physical mechanisms of copper-copper wafer bonding

    SciTech Connect

    Rebhan, B.; Hingerl, K.

    2015-10-07

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing.

  18. Bulk Laser Material Modification: Towards a Kerfless Laser Wafering Process

    NASA Astrophysics Data System (ADS)

    LeBeau, James

    Due to the ever increasing relevance of finer machining control as well as necessary reduction in material waste by large area semiconductor device manufacturers, a novel bulk laser machining method was investigated. Because the cost of silicon and sapphire substrates are limiting to the reduction in cost of devices in both the light emitting diode (LED) and solar industries, and the present substrate wafering process results in >50% waste, the need for an improved ingot wafering technique exists. The focus of this work is the design and understanding of a novel semiconductor wafering technique that utilizes the nonlinear absorption properties of band-gapped materials to achieve bulk (subsurface) morphological changes in matter using highly focused laser light. A method and tool was designed and developed to form controlled damage regions in the bulk of a crystalline sapphire wafer leaving the surfaces unaltered. The controllability of the subsurface damage geometry was investigated, and the effect of numerical aperture of the focusing optic, energy per pulse, wavelength, and number of pulses was characterized for a nanosecond pulse length variable wavelength Nd:YAG OPO laser. A novel model was developed to describe the geometry of laser induced morphological changes in the bulk of semiconducting materials for nanosecond pulse lengths. The beam propagation aspect of the model was based on ray-optics, and the full Keldysh multiphoton photoionization theory in conjuncture with Thornber's and Drude's models for impact ionization were used to describe high fluence laser light absorption and carrier generation ultimately resulting in permanent material modification though strong electron-plasma absorption and plasma melting. Although the electron-plasma description of laser damage formation is usually reserved for extremely short laser pulses (<20 ps), this work shows that it can be adapted for longer pulses of up to tens of nanoseconds. In addition to a model

  19. The optimization of FA/O barrier slurry with respect to removal rate selectivity on patterned Cu wafers

    NASA Astrophysics Data System (ADS)

    Yi, Hu; Yan, Li; Yuling, Liu; Yangang, He

    2016-02-01

    Because the polishing of different materials is required in barrier chemical mechanical planarization (CMP) processes, the development of a kind of barrier slurry with improved removal rate selectivity for Cu/barrier/TEOS would reduce erosion and dishing defects on patterned Cu wafers. In this study, we developed a new benzotriazole-free barrier slurry named FA/O barrier slurry, containing 20 mL/L of the chelating agent FA/O, 5 mL/L surfactant, and a 1:5 concentration of abrasive particles. By controlling the polishing slurry ingredients, the removal rate of different materials could be controlled. For process integration considerations, the effect of the FA/O barrier slurry on the dielectric layer of the patterned Cu wafer was investigated. After CMP processing by the FA/O barrier slurry, the characteristics of the dielectric material were tested. The results showed that the dielectric characteristics met demands for industrial production. The current leakage was of pA scale. The resistance and capacitance were 2.4 kω and 2.3 pF, respectively. The dishing and erosion defects were both below 30 nm in size. CMP-processed wafers using this barrier slurry could meet industrial production demands. Project supported by the Special Project Items No. 2 in National Long-Term Technology Development Plan (No. 2009ZX02308), the Natural Science Foundation of Hebei Province (No. F2012202094), and the Doctoral Program Foundation of Xinjiang Normal University Plan (No. XJNUBS1226).

  20. Classical Molecular Dynamics and Self-Consistent Tight-Binding Simulations of Si-Si Wafer Bonding.

    NASA Astrophysics Data System (ADS)

    Lepage, J. G.; Kim, Jeongnim; Wilkins, John W.; Kirchhoff, Florian

    2000-03-01

    We have carried out a series of atomistic simulations of the room temperature bonding of clean, defect-free Si wafers under UHV conditions using Classical Molecular Dynamics (CMD) and Self-Consistent Tight-Binding (SCTB) Our simulations indicate that even when the wafers are perfectly aligned, bonding does not typically result in the formation of bulk crystalline Si. Instead, the basic geometry of the original dimerized surface tends to persist, producing an interface characterized by linked dimers. As the wafers bond, considerable chemical energy is released resulting in rapid heating (up to 800 K) at the interface. However, this heat is rapidly conducted away from the interface and so does not have an appreciable annealing effect. Large-scale CMD calculations show that the ground state energy of the bonded system is sensitively dependent on twist angle. The SCTB calculations were performed using the using the parameterization of Lenosky et al.( Thomas J. Lenosky, Joel D. Kress, Inhee Kwon, Arthur F. Voter, Byard Edwards, David F. Richards, Sang Yang, and James B. Adams, Phys. Rev. B 55), 1528 (1997).

  1. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    SciTech Connect

    Daix, N. Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup −2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  2. Optical pressure sensor head fabrication using ultrathin silicon wafer anodic bonding

    NASA Astrophysics Data System (ADS)

    Beggans, Michael H.; Ivanov, Dentcho I.; Fu, Steven G.; Digges, Thomas G., III; Farmer, Kenneth R.

    1999-03-01

    A technology for fabricating fiber optically interrogated pressure sensors is described. This technology is based on anodic bonding of ultra-thin silicon wafers to patterned, micro-machined glass wafers, providing low-cost fabrication of optical pressure sensor heads that operate with reproducible technical characteristics in various dynamic ranges. Pressure sensors using 10, 20 and 50 micron thick silicon wafers for membranes have been fabricated on 10 cm diameter, 500-micron thick, Pyrex glass wafers. The glass wafers have been micro-machined using ultrasonic drilling in order to form cavities, optical fiber feedthrough holes and vent holes. One of the main challenges of the manufacturing process is the handling of the ultra-thin silicon wafers. Being extremely flexible, the thin silicon wafers cannot be cleaned, oxidized, or dried in the same way as normal since wafers with a thickness of the order of 400 microns. Specific handling techniques have been developed in order to achieve reproducible cleaning and oxidation processes. The anodic bonding was performed using an Electronic Visions EV501S bonder. The wafers were heated at 420 degrees C and a voltage of 1200 volts was applied in vacuum of 10-5 Torr. The bonded wafer stack was then fixed in a wax and diced. The resulting chips have been used to fabricate operating pressure sensors.

  3. Homogeneous transparent conductive ZnO:Ga by ALD for large LED wafers

    NASA Astrophysics Data System (ADS)

    Szabó, Zoltán; Baji, Zsófia; Basa, Péter; Czigány, Zsolt; Bársony, István; Wang, Hsin-Ying; Volk, János

    2016-08-01

    Highly conductive and uniform Ga doped ZnO (GZO) films were prepared by atomic layer deposition (ALD) as transparent conductive layers for InGaN/GaN LEDs. The optimal Ga doping concentration was found to be 3 at%. Even for 4" wafers, the TCO layer shows excellent homogeneity of film resistivity (0.8 %) according to Eddy current and spectroscopic ellipsometry mapping. This makes ALD a favourable technique over concurrent methods like MBE and PLD where the up-scaling is problematic. In agreement with previous studies, it was found that by an annealing treatment the quality of the GZO/p-GaN interface can be improved, although it causes the degradation of TCO conductivity. Therefore, a two-step ALD deposition technique was proposed and demonstrated: a "buffer layer" deposited and annealed first was followed by a second deposition step to maintain the high conductivity of the top layer.

  4. Thermomechanical Reliability Study of Benzocyclobutene Film in Wafer-Level Chip-Size Package

    NASA Astrophysics Data System (ADS)

    Lee, K.-O.

    2012-04-01

    A new wafer-level chip-scale package process for high-performance, low-cost packaging has been developed based on passivation with low dielectric constant. This process is simpler and shorter when using permanent photosensitive benzocyclobutene (BCB) compared with the conventional process. However, cracks nucleating on the BCB cause serious reliability problems. The major reasons for cracking of the BCB layer seem to be both thermal stress and a shortage of BCB cross-linking agent (cyclobutene). The stress was reduced by optimizing the thickness of the BCB layer and the underlying stress buffer layer. The BCB cracking resistance was improved by creating more cross-linking agent at the final curing process through modification of the photolithography processes.

  5. Photostimulated near-infrared persistent luminescence as a new optical read-out from Cr3+-doped LiGa5O8

    PubMed Central

    Liu, Feng; Yan, Wuzhao; Chuang, Yen-Jun; Zhen, Zipeng; Xie, Jin; Pan, Zhengwei

    2013-01-01

    In conventional photostimulable storage phosphors, the optical information written by x-ray or ultraviolet irradiation is usually read out as a visible photostimulated luminescence (PSL) signal under the stimulation of a low-energy light with appropriate wavelength. Unlike the transient PSL, here we report a new optical read-out form, photostimulated persistent luminescence (PSPL) in the near-infrared (NIR), from a Cr3+-doped LiGa5O8 NIR persistent phosphor exhibiting a super-long NIR persistent luminescence of more than 1,000 h. An intense PSPL signal peaking at 716 nm can be repeatedly obtained in a period of more than 1,000 h when an ultraviolet-light (250–360 nm) pre-irradiated LiGa5O8:Cr3+ phosphor is repeatedly stimulated with a visible light or a NIR light. The LiGa5O8:Cr3+ phosphor has promising applications in optical information storage, night-vision surveillance, and in vivo bio-imaging. PMID:23532003

  6. The terminal portion of leptospiral immunoglobulin-like protein LigA confers protective immunity against lethal infection in the hamster model of leptospirosis.

    PubMed

    Silva, Everton F; Medeiros, Marco A; McBride, Alan J A; Matsunaga, Jim; Esteves, Gabriela S; Ramos, João G R; Santos, Cleiton S; Croda, Júlio; Homma, Akira; Dellagostin, Odir A; Haake, David A; Reis, Mitermayer G; Ko, Albert I

    2007-08-14

    Subunit vaccines are a potential intervention strategy against leptospirosis, which is a major public health problem in developing countries and a veterinary disease in livestock and companion animals worldwide. Leptospiral immunoglobulin-like (Lig) proteins are a family of surface-exposed determinants that have Ig-like repeat domains found in virulence factors such as intimin and invasin. We expressed fragments of the repeat domain regions of LigA and LigB from Leptospira interrogans serovar Copenhageni. Immunization of Golden Syrian hamsters with Lig fragments in Freund's adjuvant induced robust antibody responses against recombinant protein and native protein, as detected by ELISA and immunoblot, respectively. A single fragment, LigANI, which corresponds to the six carboxy-terminal Ig-like repeat domains of the LigA molecule, conferred immunoprotection against mortality (67-100%, P<0.05) in hamsters which received a lethal inoculum of L. interrogans serovar Copenhageni. However, immunization with this fragment did not confer sterilizing immunity. These findings indicate that the carboxy-terminal portion of LigA is an immunoprotective domain and may serve as a vaccine candidate for human and veterinary leptospirosis. PMID:17629368

  7. Wafer-level manufacturing technology of glass microlenses

    NASA Astrophysics Data System (ADS)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  8. Generation and detection of guided waves using PZT wafer transducers.

    PubMed

    Nieuwenhuis, Jeroen H; Neumann, John J; Greve, David W; Oppenheim, Irving J

    2005-11-01

    We report here the use of finite element simulation and experiments to further explore the operation of the wafer transducer. We have separately modeled the emission and detection processes. In particular, we have calculated the wave velocities and the received voltage signals due to A0 and S0 modes at an output transducer as a function of pulse center frequency. These calculations include the effects of finite pulse width, pulse dispersion, and the detailed interaction between the piezoelectric element and the transmitting medium. We show that the received signals for A0 and S0 modes have maxima near the frequencies predicted from the previously published point-force model.

  9. THz quantum cascade lasers with wafer bonded active regions.

    PubMed

    Brandstetter, M; Deutsch, C; Benz, A; Cole, G D; Detz, H; Andrews, A M; Schrenk, W; Strasser, G; Unterrainer, K

    2012-10-01

    We demonstrate terahertz quantum-cascade lasers with a 30 μm thick double-metal waveguide, which are fabricated by stacking two 15 μm thick active regions using a wafer bonding process. By increasing the active region thickness more optical power is generated inside the cavity, the waveguide losses are decreased and the far-field is improved due to a larger facet aperture. In this way the output power is increased by significantly more than a factor of 2 without reducing the maximum operating temperature and without increasing the threshold current.

  10. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  11. Network analyzer calibration for cryogenic on-wafer measurements

    SciTech Connect

    Hietala, V.M.; Housel, M.S.; Caldwell, R.B.

    1994-04-01

    A cryogenic probe station for on-wafer microwave measurements has been developed at Sandia National Laboratories to explore the basic device physics and characterize advanced components for low-temperature applications. The station was designed to operate over a temperature range of 20 to 300 K with a frequency range of DC to 50 GHz. Due to the vacuum and the low temperature environment, the use of microwave probes and the calibration of network analyzer measurements are somewhat elaborate. This paper presents guidelines for probe use and calibration in this environment.

  12. Characterization of wafer charging mechanisms and oxide survival prediction methodology

    SciTech Connect

    Lukaszek, W.; Dixon, W.; Vella, M.; Messick, C.; Reno, S.; Shideler, J.

    1994-04-01

    Unipolar, EEPROM-based peak potential sensors and current sensors have been used to characterize the I-V relationship of charging transients which devices normally experience during the course of ion implantation. The results indicate that the charging sources may appear to behave like current-sources or voltage-sources, depending on the impedance of the load. This behavior may be understood in terms of plasma concepts. The ability to empirically characterize the I-V characteristics of charging sources using the CHARM-2 monitor wafers opens the way for prediction of failure rates of oxides subjected to specific processes, if the oxide Q{sub bd} distributions are known.

  13. Phosphorus-induced positive charge in native oxide of silicon wafers

    NASA Astrophysics Data System (ADS)

    Shimizu, Hirofumi; Munakata, Chusuke

    1994-06-01

    Alternating current surface photovoltage is enhanced in p-type silicon (Si) wafers, which are rinsed with a phosphorus (P)-contaminated water solution, whereas it is reduced in n-type Si wafers, indicating that the positive charge appears at wafer surfaces. This result suggests that P reacts with SiO2 in the form of (POSi)+ network, causing a positive charge in the native oxide.

  14. Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

    NASA Astrophysics Data System (ADS)

    Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

    2015-07-01

    Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

  15. Influence of temperature and backside roughness on the emissivity of Si wafers during rapid thermal processing

    NASA Astrophysics Data System (ADS)

    Vandenabeele, Peter; Maex, Karen

    1992-12-01

    The influence of temperature and roughness on the backside emissivity of Si wafers was studied. In situ measurements were done in two commercial rapid thermal processing systems. An experimental setup was built for in situ emissivity measurements of wafers with a polished or nonpolished backside. The emissivity of double-side polished wafers was measured for temperatures ranging from 300 to 700 °C and at wavelengths of 1.7 and 3.4 μm. It was found that the absorption coefficient α of lightly doped silicon is described by the equation α=4.15×10-5λ1.51T2.95 exp(-7000/T) cm-1, for wavelengths λ ranging from 1.5 to 5 μm and temperatures T ranging from 673 to 973 K (λ in μm, T in K). The backside emissivity of Si wafers with different roughnesses was measured. At temperatures above 600-700 °C the wafers are opaque and the emissivity is only slightly dependent on backside roughness. At lower temperatures the wafers are partially transparent and the emissivity is strongly dependent on the backside roughness of the wafer due to light trapping in the bulk of the wafer. For the latter case a new model was developed to simulate the emissivity of wafers with a rough backside at low temperatures.

  16. Growth of Catalyst-Free Epitaxial InAs Nanowires on Si Wafers Using Metallic Masks.

    PubMed

    Soo, M Teng; Zheng, Kun; Gao, Qiang; Tan, H Hoe; Jagadish, Chennupati; Zou, Jin

    2016-07-13

    Development of heteroepitaxy growth of catalyst-free vertical III-V nanowires on Si wafers is highly desirable for future nanoscale Si-based electronic and optoelectronic devices. In this study, a proof-of-concept approach is developed for catalyst-free heteroepitaxy growth of InAs nanowires on Si wafers. Before the growth of InAs nanowires, a Si-compatible metallic film with a thickness of several tens of nanometers was predeposited on a Si wafer and then annealed to form nanosize openings so as to obtain a metallic mask. These nano-openings exposed the surface of the Si wafer, which allowed subsequent nucleation and growth of epitaxial InAs nanowires directly on the surface of the Si wafer. The small size of the nano-openings limits the lateral growth of the nanostructures but promotes their axial growth. Through this approach, catalyst-free InAs nanowires were grown on both Si (111) and (001) wafers successfully at different growth temperatures. In particular, ultralong defect-free InAs nanowires with the wurtzite structure were grown the Si (111) wafers at 550 °C using the Ni mask. This study offers a simple, cost-effective, and scalable method to grow catalyst-free III-V nanowires on Si wafers. The simplicity of the approach opens a new avenue for the growth and integration of catalyst-free high-quality heteroepitaxial III-V nanowires on Si wafers.

  17. A practical approach to LWIR wafer-level optics for thermal imaging systems

    NASA Astrophysics Data System (ADS)

    Symmons, Alan; Pini, Ray

    2013-06-01

    The development and implementation of wafer level packaging for commercial microbolometers has opened the pathway towards full wafer-based thermal imaging systems. The next challenge in development is moving from discrete element LWIR imaging systems to a wafer based optical system, similar to lens assemblies found in cell phone cameras. This paper will compare a typical high volume thermal imaging design manufactured from discrete lens elements to a similar design optimized for manufacture through a wafer based approach. We will explore both performance and cost tradeoffs as well as review the manufacturability of all designs.

  18. Determination of wafer center position during the transfer process by using the beam-breaking method

    NASA Astrophysics Data System (ADS)

    Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

    2014-09-01

    A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human-machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions.

  19. Growth of Catalyst-Free Epitaxial InAs Nanowires on Si Wafers Using Metallic Masks.

    PubMed

    Soo, M Teng; Zheng, Kun; Gao, Qiang; Tan, H Hoe; Jagadish, Chennupati; Zou, Jin

    2016-07-13

    Development of heteroepitaxy growth of catalyst-free vertical III-V nanowires on Si wafers is highly desirable for future nanoscale Si-based electronic and optoelectronic devices. In this study, a proof-of-concept approach is developed for catalyst-free heteroepitaxy growth of InAs nanowires on Si wafers. Before the growth of InAs nanowires, a Si-compatible metallic film with a thickness of several tens of nanometers was predeposited on a Si wafer and then annealed to form nanosize openings so as to obtain a metallic mask. These nano-openings exposed the surface of the Si wafer, which allowed subsequent nucleation and growth of epitaxial InAs nanowires directly on the surface of the Si wafer. The small size of the nano-openings limits the lateral growth of the nanostructures but promotes their axial growth. Through this approach, catalyst-free InAs nanowires were grown on both Si (111) and (001) wafers successfully at different growth temperatures. In particular, ultralong defect-free InAs nanowires with the wurtzite structure were grown the Si (111) wafers at 550 °C using the Ni mask. This study offers a simple, cost-effective, and scalable method to grow catalyst-free III-V nanowires on Si wafers. The simplicity of the approach opens a new avenue for the growth and integration of catalyst-free high-quality heteroepitaxial III-V nanowires on Si wafers. PMID:27248817

  20. Fabrication of micro nickel/diamond abrasive pellet array lapping tools using a LIGA-like technology

    NASA Astrophysics Data System (ADS)

    Luo, Sheng-Yih; Yu, Tsung-Han; Hu, Yuh-Chung

    2007-06-01

    A manufacturing process of micro nickel/diamond abrasive pellet array lapping tools using a LIGA-like technology is reported here. The thickness of JSR THB-151N resist coated on an aluminum alloy substrate for micro lithography can reach up to 110 µm. During the lithography, different geometrical photomasks were used to create specific design patterns of the resist mold on the substrate. Micro roots, made by electrolytic machining on the substrate with guidance of the resist mold, can improve the adhesion of micro nickel abrasive pellets electroplated on the substrate. During the composite electroforming, the desired hardness of the nickel matrix inside the micro diamond abrasive pellets can be obtained by the addition of leveling and stress reducing agents. At moderate blade agitation and ultrasonic oscillation, higher concentration and more uniform dispersion of diamond powders deposited in the nickel matrix can be achieved. With these optimal experiment conditions of this fabrication process, the production of micro nickel/diamond abrasive pellet array lapping tools is demonstrated.

  1. Dual-Side Wafer Processing and Resonant Tunneling Transistor Applications

    SciTech Connect

    Moon, J.S.; Simmons, J.A.; Wendt, J.R.; Hietala, V.M.; Reno, J.L.; Baca, W.E.; Blount, M.A.

    1999-07-20

    We describe dual-side wafer processing and its application to resonant tunneling transistors in a planar configuration. The fabrication technique utilizes a novel flip-chip, wafer thinning process called epoxy-bond and stop-etch (EBASE) process, where the substrate material is removed by selective wet etching and stopped at an etch-stop layer. This EBASE method results in a semiconductor epitaxial layer that is typically less than a micron thick and has a mirror-finish, allowing backside gates to be placed in close proximity to frontside gates. Utilizing this technique, a resonant tunneling transistor--the double electron layer tunneling transistor (DELTT)--can be fabricated in a fully planar configuration, where the tunneling between two selectively-contacted 2DEGs in GaAs or InGaAs quantum wells is modulated by surface Schottky gate. Low temperature electrical characterization yields source-drain I-V curves with a gate-tunable negative differential resistance.

  2. Deposition and removal of sodium contamination on silicon wafers

    NASA Astrophysics Data System (ADS)

    Constant, I.; Tardif, F.; Derrien, J.

    2000-01-01

    In this paper investigations are performed in order to understand the source of sodium contamination in clean-room environments and to find different cleaning processes able to limit or suppress sodium deposition. In a clean-room environment, the human being has been identified as one of the major sources of sodium. The airborne sodium contamination is essentially transmitted in particle form. In order to limit sodium deposition from the air, the wafers awaiting subsequent processing need to be stored in a protective box or placed far from the human environment and should not be left for much more than 1 week in a class 1 clean room. Also, wet chemistries could cause sodium contamination on wafers particularly during the deionized water rinse. In order to limit the possible contamination, the sodium deposition mechanisms have been studied: they show the typical characteristics of Langmuir adsorption. Temperature and ionic concentration are both parameters which influence the deposition. In water, sodium deposition can be avoided by introducing acid or alkaline solutions or increasing the temperature: it can be drastically reduced by adding traces of HCl (0.01%). Finally, other cleaning chemistries such as SC1 (NH4 OH-H2 O2 -H2 O) in 0.25:1:5 proportion, SC2 (HCl-H2 O2 -H2 O) in 1:1:5 proportion, 0.1% HF and SPM (H2 SO4 -H2 O2 ) in 3:1 proportion reduce the contamination as well.

  3. Improving scanner wafer alignment performance by target optimization

    NASA Astrophysics Data System (ADS)

    Leray, Philippe; Jehoul, Christiane; Socha, Robert; Menchtchikov, Boris; Raghunathan, Sudhar; Kent, Eric; Schoonewelle, Hielke; Tinnemans, Patrick; Tuffy, Paul; Belen, Jun; Wise, Rich

    2016-03-01

    In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML's Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

  4. Process Performance of Optima XEx Single Wafer High Energy Implanter

    SciTech Connect

    Kim, J. H.; Yoon, Jongyoon; Kondratenko, S.; David, J.; Rubin, L. M.; Jang, I. S.; Cha, J. C.; Joo, Y. H.; Lee, A. B.; Jin, S. W.

    2011-01-07

    To meet the process requirements for well formation in future CMOS memory production, high energy implanters require more robust angle, dose, and energy control while maintaining high productivity. The Optima XEx high energy implanter meets these requirements by integrating a traditional LINAC beamline with a robust single wafer handling system. To achieve beam angle control, Optima XEx can control both the horizontal and vertical beam angles to within 0.1 degrees using advanced beam angle measurement and correction. Accurate energy calibration and energy trim functions accelerate process matching by eliminating energy calibration errors. The large volume process chamber and UDC (upstream dose control) using faraday cups outside of the process chamber precisely control implant dose regardless of any chamber pressure increase due to PR (photoresist) outgassing. An optimized RF LINAC accelerator improves reliability and enables singly charged phosphorus and boron energies up to 1200 keV and 1500 keV respectively with higher beam currents. A new single wafer endstation combined with increased beam performance leads to overall increased productivity. We report on the advanced performance of Optima XEx observed during tool installation and volume production at an advanced memory fab.

  5. Molded, wafer level optics for long wave infra-red applications

    NASA Astrophysics Data System (ADS)

    Franks, John

    2016-05-01

    For many years, the Thermal Imaging market has been driven by the high volume consumer market. The first signs of this came with the launch of night vision systems for cars, first by Cadillac and Honda and then, more successfully by BMW, Daimler and Audi. For the first time, simple thermal imaging systems were being manufactured at the rate of more than 10,000 units a year. This step change in volumes enabled a step change in system costs, with thermal imaging moving into the consumer's price range. Today we see that the consumer awareness and the consumer market continues to increase with the launch of a number of consumer focused smart phone add-ons. This has brought a further step change in system costs, with the possibility to turn your mobile phone into a thermal imager for under $250. As the detector technology has matured, the pixel pitches have dropped from 50μm in 2002 to 12 μm or even 10μm in today's detectors. This dramatic shrinkage in size has had an equally dramatic effect on the optics required to produce the image on the detector. A moderate field of view that would have required a focal length of 40mm in 2002 now requires a focal length of 8mm. For wide field of view applications and small detector formats, focal lengths in the range 1mm to 5mm are becoming common. For lenses, the quantity manufactured, quality and costs will require a new approach to high volume Infra-Red (IR) manufacturing to meet customer expectations. This, taken with the SwaP-C requirements and the emerging requirement for very small lenses driven by the new detectors, suggests that wafer scale optics are part of the solution. Umicore can now present initial results from an intensive research and development program to mold and coat wafer level optics, using its chalcogenide glass, GASIR®.

  6. Reticle process monitoring and qualification based on reticle CDU and wafer CDU correlation

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Choi, Byoung Il; Holfeld, Christian; Ngow, Yee Ta; Tan, Sia Kim; Tchikoulaeva, Anna; Gn, Fang Hong

    2011-11-01

    Reticle process of record (POR) sometimes needs fine tuning for some reasons such as multiple layer process, better critical dimension uniformity (CDU) or new etch chamber. The sidewall angle and corner rounding will be varied due to the reticle processing tuned comparing to previous POR. However, because the reticle critical dimension (CD) measurement is based on middle side lobe measurement or other algorithm, the reticle CD cannot reflect the changes of reticle sidewall angle and corner rounding variation which are critical for 65nm node and below. Each of the scanner, wafer process, reticle and metrology tool contributes to the intra-field wafer CD. Normally, the reticle contribution to the wafer CDU should be as small as possible, that is less than 33%. By averaging all wafer CD of individual features to obtain a wafer CD reference independent of feature location and wafer die, the correlation of wafer measurement to target (MTT) and reticle MTT can be obtained. The correlation can accurately qualify and monitor the tuning processing of reticle. We have manufactured two masks for active layer of 65nm tech node by different reticle process. One used the original POR process of active layer, while another used multi-layer-reticle (MLR) process. The correlations between wafer CDU and reticle CDU of these reticles are demonstrated for both isolated and dense features in vertical and horizontal direction, respectively. Similar experiments were implemented and the correlations for both dense and isolated structures are demonstrated as well, for two different POR process for first metal layer of 40nm tech node. Referring to the wafer and reticle MTT correlation, the contribution of reticle CDU to wafer CDU can be used as an evaluation methodology for reticle processing. The wafer and reticle CDU correlations for 45nm node poly and contact layers POR process are also demonstrated.

  7. New fabrication method of glass packages with inclined optical windows for micromirrors on wafer level

    NASA Astrophysics Data System (ADS)

    Stenchly, Vanessa; Quenzer, Hans-Joachim; Hofmann, Ulrich; Janes, Joachim; Jensen, Björn; Benecke, Wolfgang

    2013-03-01

    For many applications it is inevitable to protect MEMS devices against environmental impacts like humidity which can affect their performance. Moreover recent publications demonstrates that micro mirrors can achieve very large optical scan angles at moderate driving voltages even exceeding 100 degrees when hermetically sealed under vacuum. While discrete chips may be evacuated and sealed on single die level using small can packages like TO housings, it is obvious that for high volume production a much more economical solution for the realisation of transparent optical packages already on wafer level must be developed. However, since any laser beam crossing a transparent glass surface is partly reflected even when anti-reflective coatings are applied, the construction of a wafer level optical housing suitable for laser projection purpose requires more than the integration of simple plane glass cap. The use of inclined optical windows avoids the occurrence of intense reflections of the incident laser beam in the projected images. This paper describes a unique technology to fabricate glass packages with inclined optical windows for micro mirrors on 8 inch wafers. The new process uses a high temperature glass forming process based on subsequent wafer bonding. A borosilicate glass wafer is bonded together with two structured silicon wafers. By grinding both sides of the wafer stack, a pattern of isolated silicon structures is defined. This preprocessed glass wafer is bonded thereon on a third structured silicon wafer, wherein the silicon islands are inserted into the cavities. By setting a defined pressure level inside the cavities during the final wafer bonding, the silicon glass stack extruded and it is out of plane during a subsequent annealing process at temperatures above the softening point of the glass. Finally the silicon is selectively removed in a wet etching process. This technique allows the fabrication of 8 inch glass wafers with oblique optical surfaces

  8. Alternative fabrication process for edgeless detectors on 6 in. wafers

    NASA Astrophysics Data System (ADS)

    Kalliopuska, Juha; Eränen, Simo; Virolainen, Tuula

    2011-05-01

    VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150 μm thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 5×5 and 1×1 cm2 edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.4×1.4 cm2 Medipix2 edgeless pixel detectors were also fabricated.This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100 μm from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50-70 nA/cm2 and 580-660 pF/cm2 at, respectively, 40 V reverse bias for the p-on-n. For the n-on-n design these parameters were 116-118 nA/cm2 and 930-960 pF/cm2. The breakdown voltages were above 150 V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13-28 V.

  9. The application of a crosslinked pectin-based wafer matrix for gradual buccal drug delivery.

    PubMed

    Shaikh, Rubina P; Pillay, Viness; Choonara, Yahya E; Du Toit, Lisa C; Ndesendo, Valence M K; Kumar, Pradeep; Khan, Riaz A

    2012-05-01

    The purpose of this study was to develop crosslinked wafer matrices and establish the influence of the crosslinker type and processing sequence on achieving gradual buccal drug delivery. Three sets of drug-loaded crosslinked pectin wafers were produced employing the model water-soluble antihistamine, diphenhydramine and were compared with noncrosslinked wafers. The formulations were crosslinked with CaCl(2), BaCl(2), or ZnSO(4) pre- or postlyophilization (sets 1 and 2) as well as pre- and postlyophilization (set 3), respectively. The surface morphology, porositometry, molecular vibrational transitions, textural attributes, thermal and in vitro drug release were characterized and supported by in silico molecular mechanics simulations. Results revealed that crosslinked wafers produced smaller pore sizes (107.63 Å) compared with noncrosslinked matrices (180.53 Å) due to molecular crosslinks formed between pectin chains. Drug release performance was dependent on the wafer crosslinking production sequence. Noncrosslinked wafers displayed burst-release with 82% drug released at t(30min) compared with first-order kinetic profiles obtained for prelyophilized crosslinked matrices (50% released at t(30min) followed by steady release). Wafers crosslinked postlyophilization displayed superior control of drug release (40% at t(30min)). Molecular mechanics simulations corroborated with the experimental data and established that Ba(++), having the largest atomic radii (1.35 Å) formed a number of ionic bridges producing wafers of higher porosity (0.048 cm(2)/g) and had more influence on drug release. PMID:22323418

  10. Effect of lubricant environment on saw damage in silicon wafers

    NASA Technical Reports Server (NTRS)

    Kuan, T. S.; Shih, K. K.; Vanvechten, J. A.; Westdorp, W. A.

    1982-01-01

    The chemomechanical effect of lubricant environments on the inner diameter (ID) sawing induced surface damage in Si wafers was tested for four different lubricants: water, dielectric oil, and two commercial cutting solutions. The effects of applying different potential on Si crystals during the sawing were also tested. It is indicated that the number and depth of surface damage are sensitive to the chemical nature of the saw lubricant. It is determined that the lubricants that are good catalysts for breaking Si bonds can dampen the out of plane blade vibration more effectively and produce less surface damage. Correlations between the applied potential and the depth of damage in the dielectric oil and one of the commercial cutting solutions and possible mechanisms involved are discussed.

  11. Patterned wafer inspection using spatial filtering for the cluster environment.

    PubMed

    Taubenblatt, M A; Batchelder, J S

    1992-06-10

    Automated-process tool clusters are becoming increasingly prevalent in advanced semiconductor manufacturing plants, necessitating integrated inspection of patterned semiconductor wafers for defects and particulates. Integrated inspection tools must be small, sensitive, inexpensive, and fast in order to be compatible with the cluster environment. We show that intensity spatial filtering, with some refinements, can provide the required sensitivity and speed in a small, inexpensive package. By using dark-field illumination and a nonrectangular azimuthal orientation (e.g., 45 degrees ) to the primarily rectangular pattern, we show that the strongest diffraction from the pattern can be made to bypass the optical system entirely. This technique alleviates stringent scatter and antireflection requirements on the optics, and it permits the use of off-the-shelf components.

  12. Visible luminescence from silicon wafers subjected to stain etches

    NASA Technical Reports Server (NTRS)

    Fathauer, R. W.; George, T.; Ksendzov, A.; Vasquez, R. P.

    1992-01-01

    Etching of Si in a variety of solutions is known to cause staining. These stain layers consist of porous material similar to that produced by anodic etching of Si in HF solutions. In this work, photoluminescence peaked in the red from stain-etched Si wafers of different dopant types, concentrations, and orientations produced in solutions of HF:HNO3:H2O was observed. Luminescence is also observed in stain films produced in solutions of NaNO2 in HF, but not in stain films produced in solutions of CrO3 in HF. The luminescence spectra are similar to those reported recently for porous Si films produced by anodic etching in HF solutions. However, stain films are much easier to produce, requiring no special equipment.

  13. Wafer-level hysteresis-free resonant carbon nanotube transistors.

    PubMed

    Cao, Ji; Bartsch, Sebastian T; Ionescu, Adrian M

    2015-03-24

    We report wafer-level fabrication of resonant-body carbon nanotube (CNT) field-effect transistors (FETs) in a dual-gate configuration. An integration density of >10(6) CNTFETs/cm(2), an assembly yield of >80%, and nanoprecision have been simultaneously obtained. Through combined chemical and thermal treatments, hysteresis-free (in vacuum) suspended-body CNTFETs have been demonstrated. Electrostatic actuation by lateral gate and FET-based readout of mechanical resonance have been achieved at room temperature. Both upward and downward in situ frequency tuning has been experimentally demonstrated in the dual-gate architecture. The minuscule mass, high resonance frequency, and in situ tunability of the resonant CNTFETs offer promising features for applications in radio frequency signal processing and ultrasensitive sensing. PMID:25752991

  14. A Wafer Transfer Technology for MEMS Adaptive Optics

    NASA Technical Reports Server (NTRS)

    Yang, Eui-Hyeok; Wiberg, Dean V.

    2001-01-01

    Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

  15. Chemical strategies for die/wafer submicron alignment and bonding.

    SciTech Connect

    Martin, James Ellis; Baca, Alicia I.; Chu, Dahwey; Rohwer, Lauren Elizabeth Shea

    2010-09-01

    This late-start LDRD explores chemical strategies that will enable sub-micron alignment accuracy of dies and wafers by exploiting the interfacial energies of chemical ligands. We have micropatterned commensurate features, such as 2-d arrays of micron-sized gold lines on the die to be bonded. Each gold line is functionalized with alkanethiol ligands before the die are brought into contact. The ligand interfacial energy is minimized when the lines on the die are brought into registration, due to favorable interactions between the complementary ligand tails. After registration is achieved, standard bonding techniques are used to create precision permanent bonds. We have computed the alignment forces and torque between two surfaces patterned with arrays of lines or square pads to illustrate how best to maximize the tendency to align. We also discuss complex, aperiodic patterns such as rectilinear pad assemblies, concentric circles, and spirals that point the way towards extremely precise alignment.

  16. Non-contact defect diagnostics in Cz-Si wafers using resonance ultrasonic vibrations

    NASA Astrophysics Data System (ADS)

    Belyaev, A.; Kochelap, V. A.; Tarasov, I.; Ostapenko, S.

    2001-01-01

    A new resonance effect of generation of sub-harmonic acoustic vibrations was applied to characterize defects in as-grown and processed Cz-Si wafers. Ultrasonic vibrations were generated into standard 8″ wafers using an external ultrasonic transducer and their amplitude recorded in a non-contact mode using a scanning acoustic probe. By tuning the frequency, f, of the transducer we observed generation of intense sub-harmonic acoustic mode ("whistle" or w-mode) with f/2 frequency. The characteristics of the w-mode-amplitude dependence, frequency scans, spatial distribution allow a clear distinction versus harmonic vibrations of the same wafer. The origin of sub-harmonic vibrations observed on 8″ Cz-Si wafers is attributed to a parametric resonance of flexural vibrations in thin silicon circular plates. We present evidence that "whistle" effect shows a strong dependence on the wafer's growth and processing history and can be used for quality assurance purposes.

  17. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbrecher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-01-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  18. Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

    SciTech Connect

    Johnston, S.; Yan, F.; Zaunbracher, K.; Al-Jassim, M.; Sidelkheir, O.; Blosse, A.

    2011-07-01

    Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finished cell performance.

  19. Investigation of bidirectional reflectance and transmittance of rough silicon wafers

    NASA Astrophysics Data System (ADS)

    Shen, Yu-Jiun

    2002-01-01

    This research seeks to perform accurate measurements of bidirectional reflectance and transmittance of rough silicon wafers by a new benchtop scatterometer. An empirical model was developed according to the measurement data. The results will contribute to the application of radiative heat transfer modeling for a rapid thermal processing (RTP) system. In an RTP system, the radiation environment can greatly affect the reading of a lightpipe radiation thermometer. Knowledge of the bidirectional reflectance of rough silicon wafers is needed for the prediction of the reflected radiation into the radiometer, so that it can be used for accurate temperature measurement. The new scatterometer is capable of measuring out-of-plane scattering distribution at wavelengths of 635, 785, and 1550 nm from a diode laser system. Results were analyzed and compared to standard measurements at the National Institute of Standards and Technology. The relative difference is within the level of 5% for wavelengths of 635 and 785 nm and 10% for 1550 nm. An empirical model in the simple form of a two-parameter exponential function was proposed to fit the measured data. The results show that this approach can represent the measured data better than some other theoretical models discussed in this thesis. The empirical model can be used to estimate conical reflectance around a specular direction for different collecting half-cone angles. That provides a quick way to compare specular peak measurements from different instruments with varied collecting resolution. An in situ measurement in the mock-up RTP chamber was also performed. Results demonstrated the feasibility of compact optics setup, which mainly uses fiber-coupled devices.

  20. A universal process development methodology for complete removal of residues from 300mm wafer edge bevel

    NASA Astrophysics Data System (ADS)

    Randall, Mai; Linnane, Michael; Longstaff, Chris; Ueda, Kenichi; Winter, Tom

    2006-03-01

    Many yield limiting, etch blocking defects are attributed to "flake" type contamination from the lithography process. The wafer edge bevel is a prime location for generation of this type of defect. Wafer bevel quality is not readily observed with top down or even most off axis inspection equipment. Not all chemistries are removed with one "universal" cleaning process. IC manufacturers must maximize usable silicon area as well. These requirements have made traditional chemical treatments to clean the wafer edge inadequate for many chemistry types used in 193nm processing. IBM has evaluated a method to create a robust wafer bevel and backside cleaning process. An August Technology AXi TM Series advanced macro inspection tool with E20 TM edge inspection module has been used to check wafer bevel cleanliness. Process impact on the removal of post apply residues has been investigated. The new process used backside solvent rinse nozzles only and cleaned the wafer bevel completely. The use of the topside edge solvent clean nozzles was eliminated. Thickness, wet film defect measurements (wet FM), and pattern wafer defect monitors showed no difference between the new backside rinse edge bead removal process and the process of record. Solvent topside edge bead removal of both bottom anti-reflective coatings and resist materials showed better cut width control and uniformity. We conclude that the topside solvent edge bead removal nozzle can be removed from the process. Backside solvent rinse nozzles can clean the backside of the wafer, the wafer bevel, and can wrap to the front edge of the wafer to provide a uniform edge bead removal cut width that is not sensitive to coater module tolerances. Recommendations are made for changes to the typical preventive maintenance procedures.

  1. Effects of Lightpipe Proximity on Si Wafer Temperature in Rapid Thermal Processing Tools

    NASA Astrophysics Data System (ADS)

    Kreider, K. G.; Chen, D. H.; DeWitt, D. P.; Kimes, W. A.; Tsai, B. K.

    2003-09-01

    Lightpipe radiation thermometers (LPRTs) are used as temperature monitoring sensors in most rapid thermal processing (RTP) tools for semiconductor fabrication. These tools are used for dopant anneal, gate oxide formation, and other high temperature processing. In order to assure uniform wafer temperatures during processing these RTP tools generally have highly reflecting chamber walls to promote a uniform heat flux on the wafer. Therefore, only minimal disturbances in the chamber reflectivity are permitted for the sensors, and the small 2 mm diameter sapphire lightpipe is generally the temperature sensor of choice. This study was undertaken to measure and model the effect of LPRT proximity on the wafer temperature. Our experiments were performed in the NIST RTP test bed using a NIST thin-film thermocouple (TFTC) calibration wafer. We measured the spectral radiance temperature with the center lightpipe and compared these with the TFTC junctions and with the three LPRTs at the mid-radius of the wafer. We measured LPRT outputs from a position flush with the reflecting plate to within 2 mm of the stationary wafer under steady-state conditions with wafer-to-cold plate separation distances of 6 mm, 10 mm and 12.5 mm. Depressions in the wafer temperature up to 25 °C were observed. A finite-element radiation model of the wafer-chamber-lightpipe was developed to predict the temperature depression as a function of proximity distance and separation distance. The experimental results were compared with those from a model that accounts for lightpipe geometry and radiative properties, wafer emissivity and chamber cold plate reflectivity.

  2. Kinetic mechanism and fidelity of nick sealing by Escherichia coli NAD+-dependent DNA ligase (LigA)

    PubMed Central

    Chauleau, Mathieu; Shuman, Stewart

    2016-01-01

    Escherichia coli DNA ligase (EcoLigA) repairs 3′-OH/5′-PO4 nicks in duplex DNA via reaction of LigA with NAD+ to form a covalent LigA-(lysyl-Nζ)–AMP intermediate (step 1); transfer of AMP to the nick 5′-PO4 to form an AppDNA intermediate (step 2); and attack of the nick 3′-OH on AppDNA to form a 3′-5′ phosphodiester (step 3). A distinctive feature of EcoLigA is its stimulation by ammonium ion. Here we used rapid mix-quench methods to analyze the kinetic mechanism of single-turnover nick sealing by EcoLigA–AMP. For substrates with correctly base-paired 3′-OH/5′-PO4 nicks, kstep2 was fast (6.8–27 s−1) and similar to kstep3 (8.3–42 s−1). Absent ammonium, kstep2 and kstep3 were 48-fold and 16-fold slower, respectively. EcoLigA was exquisitely sensitive to 3′-OH base mispairs and 3′ N:abasic lesions, which elicited 1000- to >20000-fold decrements in kstep2. The exception was the non-canonical 3′ A:oxoG configuration, which EcoLigA accepted as correctly paired for rapid sealing. These results underscore: (i) how EcoLigA requires proper positioning of the nick 3′ nucleoside for catalysis of 5′ adenylylation; and (ii) EcoLigA's potential to embed mutations during the repair of oxidative damage. EcoLigA was relatively tolerant of 5′-phosphate base mispairs and 5′ N:abasic lesions. PMID:26857547

  3. A new LigaSure technique for the formation of segmental plane by intravenous indocyanine green fluorescence during thoracoscopic anatomical segmentectomy

    PubMed Central

    Dejima, Hitoshi; Mizumo, Tetsuya; Sakakura, Noriaki; Sakao, Yukinori

    2016-01-01

    Background The purpose of this study was to present a new approach to the formation of a segmental plane by LigaSure (Covidien, Mansfield, MA, USA) with indocyanine green (ICG) fluorescence system during thoracoscopic segmentectomy. Methods This was a consecutive study that compared 12 patients who underwent a new LigaSure technique (LT) for segmental plane formation during thoracoscopic anatomical segmentectomy with 38 patients who underwent conventional methods using the staple technique (ST). Eleven patients were followed up more than 3 months after discharge. Results The mean age of the patients was 66 years in the LT group and 67 years in ST. The mean duration for the formation of segmental plane and the mean number of staples was 22.8 min and 1.8 per surgery, respectively, in the LT group; and 16.2 min and 3.4 per surgery, respectively, in ST. No patient had a prolonged air leak (PAL) of more than 7 days. Minor air leak was identified early in two and was delayed in one. Two-thirds of patients with early minor air leak had low index of prolonged air leak (IPAL) score. There was no air leak in the patients with high IPAL score. Eventually, we deduced that the cause of the minor air leak was a technical problem. Conclusions In the formation of segmental plane during thoracoscopic segmentectomy, a combination of ICG fluorescence and LigaSure may be beneficial for patients. As a new operative instrument, LT constitutes, in our opinion, a feasible and easy alternative to other thoracoscopic techniques. PMID:27293839

  4. Creating a single twin boundary between two CdTe (111) wafers with controlled rotation angle by wafer bonding

    SciTech Connect

    Sun, Ce; Lu, Ning; Wang, Jinguo; Lee, Jihyung; Peng, Xin; Kim, Moon J.; Klie, Robert F.

    2013-12-16

    The single twin boundary with crystallographic orientation relationship (1{sup ¯}1{sup ¯}1{sup ¯})//(111) [01{sup ¯}1]//[011{sup ¯}] was created by wafer bonding. Electron diffraction patterns and high-resolution transmission electron microscopy images demonstrated the well control of the rotation angle between the bonded pair. At the twin boundary, one unit of wurtzite structure was found between two zinc-blende matrices. High-angle annular dark-field scanning transmission electron microscopy images showed Cd- and Te-terminated for the two bonded portions, respectively. The I-V curve across the twin boundary showed increasingly nonlinear behavior, indicating a potential barrier at the bonded twin boundary.

  5. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates

    PubMed Central

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-01-01

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the “melt-back” effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 μm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude. PMID:26487465

  6. Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates.

    PubMed

    Wang, Li; Walker, Glenn; Chai, Jessica; Iacopi, Alan; Fernandes, Alanna; Dimitrijev, Sima

    2015-10-21

    A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the "melt-back" effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 μm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude.

  7. Evaluation of the Technical Feasibility and Effective Cost of Various Wafer Thicknesses for the Manufacture of Solar Cells

    NASA Technical Reports Server (NTRS)

    1979-01-01

    Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.

  8. Evaluation of the technical feasibility and effective cost of various wafer thicknesses for the manufacture of solar cells

    NASA Technical Reports Server (NTRS)

    1978-01-01

    Three wafering demonstration runs were completed on the Yasunaga wire saw. Wafer thickness/taper uniformity is excellent. Many small problems were encountered with Yasunaga accessories, slowing the effort. A wafer characterization cycle was defined and will be initiated during the next period.

  9. Contact doping of silicon wafers and nanostructures with phosphine oxide monolayers.

    PubMed

    Hazut, Ori; Agarwala, Arunava; Amit, Iddo; Subramani, Thangavel; Zaidiner, Seva; Rosenwaks, Yossi; Yerushalmi, Roie

    2012-11-27

    Contact doping method for the controlled surface doping of silicon wafers and nanometer scale structures is presented. The method, monolayer contact doping (MLCD), utilizes the formation of a dopant-containing monolayer on a donor substrate that is brought to contact and annealed with the interface or structure intended for doping. A unique feature of the MLCD method is that the monolayer used for doping is formed on a separate substrate (termed donor substrate), which is distinct from the interface intended for doping (termed acceptor substrate). The doping process is controlled by anneal conditions, details of the interface, and molecular precursor used for the formation of the dopant-containing monolayer. The MLCD process does not involve formation and removal of SiO(2) capping layer, allowing utilization of surface chemistry details for tuning and simplifying the doping process. Surface contact doping of intrinsic Si wafers (i-Si) and intrinsic silicon nanowires (i-SiNWs) is demonstrated and characterized. Nanowire devices were formed using the i-SiNW channel and contact doped using the MLCD process, yielding highly doped SiNWs. Kelvin probe force microscopy (KPFM) was used to measure the longitudinal dopant distribution of the SiNWs and demonstrated highly uniform distribution in comparison with in situ doped wires. The MLCD process was studied for i-Si substrates with native oxide and H-terminated surface for three types of phosphorus-containing molecules. Sheet resistance measurements reveal the dependency of the doping process on the details of the surface chemistry used and relation to the different chemical environments of the P═O group. Characterization of the thermal decomposition of several monolayer types formed on SiO(2) nanoparticles (NPs) using TGA and XPS provides insight regarding the role of phosphorus surface chemistry at the SiO(2) interface in the overall MLCD process. The new MLCD process presented here for controlled surface doping

  10. Edge printability: techniques used to evaluate and improve extreme wafer edge printability

    NASA Astrophysics Data System (ADS)

    Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

    2004-05-01

    The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

  11. End station design and wafer quality control for a high current oxygen implanter

    NASA Astrophysics Data System (ADS)

    Douglas-Hamilton, D. H.; Ruffell, John P.; Kaim, R. E.; Izumi, K.

    The end station of the Eaton NV-200 high current oxygen implanter is described. In this machine the beam enters at 30° from the horizontal and the wafers are mounted on the inside surface of a slightly conical drum which rotates about a vertical axis. A cone half angle of 16° results in an implant angle of 14°. The drum rotates at a high speed and the beam is broadened into a line which fully illuminates the wafers without scanning, resulting in a uniform implant as the wafers pass through it on the rotating drum. By adjusting the ion source apertures and beam line optics implant uniformity within a few percent has been achieved over the whole wafer. The drum holds twenty-five 4 in. wafers per batch. Sampling holes located in the drum together with a Faraday plate in the end station are used to monitor beam uniformity. Dose measurement is done calorimetrically using the power into the end station to calculate the integrated dose. The end station is equipped with heater lamps which will preheat the wafers to the desired temperature before the implantation process is begun. These lamps are also utilized to maintain the wafers at an elevated temperature if the implant is interrupted.

  12. Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

    NASA Technical Reports Server (NTRS)

    Okojie, Robert S. (Inventor)

    2002-01-01

    A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

  13. Validation of thermodesorption method for analysis of semi-volatile organic compounds adsorbed on wafer surface.

    PubMed

    Hayeck, Nathalie; Gligorovski, Sasho; Poulet, Irène; Wortham, Henri

    2014-05-01

    To prevent the degradation of the device characteristics it is important to detect the organic contaminants adsorbed on the wafers. In this respect, a reliable qualitative and quantitative analytical method for analysis of semi-volatile organic compounds which can adsorb on wafer surfaces is of paramount importance. Here, we present a new analytical method based on Wafer Outgassing System (WOS) coupled to Automated Thermal Desorber-Gas chromatography-Mass spectrometry (ATD-GC-MS) to identify and quantify volatile and semi-volatile organic compounds from 6", 8" and 12" wafers. WOS technique allows the desorption of organic compounds from one side of the wafers. This method was tested on three important airborne contaminants in cleanroom i.e. tris-(2-chloroethyl) phosphate (TCEP), tris-(2-chloroisopropyl) phosphate (TCPP) and diethyl phthalate (DEP). In addition, we validated this method for the analysis and quantification of DEP, TCEP and TCPP and we estimated the backside organic contamination which may contribute to the front side of the contaminated wafers. We are demonstrating that WOS/ATD-GC-MS is a suitable and highly efficient technique for desorption and quantitative analysis of organophosphorous compounds and phthalate ester which could be found on the wafer surface.

  14. Kerfless Silicon Precursor Wafer Formed by Rapid Solidification: October 2009 - March 2010

    SciTech Connect

    Lorenz, A.

    2011-06-01

    1366 Direct Wafer technology is an ultra-low-cost, kerfless method of producing crystalline silicon wafers compatible with the existing dominant silicon PV supply chain. By doubling utilization of silicon and simplifying the wafering process and equipment, Direct Wafers will support drastic reductions in wafer cost and enable module manufacturing costs < $1/W. This Pre-Incubator subcontract enabled us to accelerate the critical advances necessary to commercialize the technology by 2012. Starting from a promising concept that was initially demonstrated using a model material, we built custom equipment necessary to validate the process in silicon, then developed sufficient understanding of the underlying physics to successfully fabricate wafers meeting target specifications. These wafers, 50 mm x 50 mm x 200 ..mu..m thick, were used to make prototype solar cells via standard industrial processes as the project final deliverable. The demonstrated 10% efficiency is already impressive when compared to most thin films, but still offers considerable room for improvement when compared to typical crystalline silicon solar cells.

  15. Therml & Gravitational Stress in Si Wafers; Lim. on Process Htg & Cool. Rates

    1997-01-14

    The MacWafer code determines maximum allowable processing temperatures and maximum heating and cooling rates for thermal processing of silicon semiconductor wafers in single and multiple wafer furnaces. The program runs interactively on Macintosh, PC, and workstation computers. Execution time is typically 20 seconds on a Macintosh 68040 processor operating at 33 MHz. Gravitational stresses and displacements are first calculated based on the user''s input of a support system consisting of a ring beneath the wafermore » and/or arbitrarily placed point supports. The maximum operating temperature is then deduced by comparing the calculated gravitational stresses with the temperature-dependent wafer strength. At lower temperatures, the difference between wafer strength and gravitational stress is used to determine the allowable thermal stress, and hence the allowable radial temperature difference across the wafer. Finally, an analytical model of radial heat transfer in a batch furnace yields the maximum heating or cooling rate as a function of the allowable temperature difference based on the user''s inputs of wafer spacing and furnace power. Outputs to the screen include plots of stress components and vertical displacement, as well as tables of maximum stresses and maximum heating and cooling rates as a function of temperature. All inputs and outputs may be directed to user-named files for further processing or graphical display.« less

  16. Fast-ramp rapid vertical processor for 300-mm Si wafer processing

    NASA Astrophysics Data System (ADS)

    Porter, Cole; Laser, Allan; Herring, Robert; Pandey, Pradeep

    1998-09-01

    Fast-ramp vertical furnace technology has been established on the 200-nm wafer platform providing higher capacity production, decreased cycle time and lower thermal budgets. Fast-ramp furnaces are capable of instantaneous temperature ramp rates up to 100 degrees C/min. This fast-ramp technology is now applied to 300-nm wafer processing on the SVG/Thermco Rapid Vertical Processor Vertical Furnace. 300- mm fast-ramp capability using the latest in real-time adaptive model based temperature control technology, Clairvoyant Control, is reported. Atmospheric Thermal Oxidation, LPCVD Nitride and Polysilicon Deposition, and LPCVD TEOS-based SiO2 Deposition results are discussed. 300- mm wafer Radial Delta Temperature dependence on temperature ramp rate, wafer pitch, and wafer support fixtures are discussed. Wafer throughput is calculated and reported. The Clairvoyant Control methodology of combining thermal, direct and virtually-sensed parameters to produce real-tim e estimation of wafer temperatures, thermal trajectory optimization, and feedback to minimize variations in film thickness and electrical properties is presented.

  17. Intentional defect array wafers: their practical use in semiconductor control and monitoring systems

    NASA Astrophysics Data System (ADS)

    Emami, Iraj; McIntyre, Michael; Retersdorf, Michael

    2003-07-01

    In the competitive world of semiconductor manufacturing today, control of the process and manufacturing equipment is paramount to success of the business. Consistent with the need for rapid development of process technology, is a need for development wiht respect to equipment control including defect metrology tools. Historical control methods for defect metrology tools included a raw count of defects detected on a characterized production or test wafer with little or not regard to the attributes of the detected defects. Over time, these characterized wafers degrade with multiple passes on the tools and handling requiring the tool owner to create and characterize new samples periodically. With the complex engineering software analysis systems used today, there is a strong reliance on the accuracy of defect size, location, and classification in order to provide the best value when correlating the in line to sort type of data. Intentional Defect Array (IDA) wafers were designed and manufacturered at International Sematech (ISMT) in Austin, Texas and is a product of collaboration between ISMT member companies and suppliers of advanced defect inspection equipment. These wafers provide the use with known defect types and sizes in predetermined locations across the entire wafer. The wafers are designed to incorporate several desired flows and use critical dimensions consistent with current and future technology nodes. This paper briefly describes the design of the IDA wafer and details many practical applications in the control of advanced defect inspection equipment.

  18. Mapping of Defects in Large-Area Silicon Carbide Wafers via Photoluminescence and its Correlation with Synchrotron White Beam X-Ray Topography

    SciTech Connect

    Chen, Yi; Balaji, R.; Dudley, Michael; Murthy, Madhu; Maximenko, Serguei I.; Freitas, Jamie A.

    2008-12-12

    Comparative studies of defect microstructure in 4H-SiC wafers have been carried out using photoluminescence (PL) imaging and grazing-incidence Synchrotron White Beam X-ray Topography. Images of low angle grain boundaries on the PL images correlate well with SWBXT observations, and similar correlation can be established for some micropipe images although the latter is complicated by the overall level of distortion and misorientation associated with the low angle grain boundaries and the fact that many of the micropipes are located in or close to the boundaries. This validation indicates that PL imaging may provide a rapid way of imaging such defect structures in large-scale SiC wafers.

  19. Identification and Characterization of Performance Limiting Regions in Poly-Si Wafers Used for PV Cells: Preprint

    SciTech Connect

    Guthrey, H.; Gorman, B.; Al-Jassim, M.

    2011-07-01

    As demand for silicon photovoltaic (PV) material increases, so does the need for cost-effective feedstock and production methods that will allow enhanced penetration of silicon PV into the total energy market. The focus on cost minimization for production of polycrystalline silicon (poly-Si) PV has led to relaxed feedstock purity requirements, which has also introduced undesirable characteristics into cast poly-Si PV wafers. To produce cells with the highest possible conversion efficiencies, it is crucial to understand how reduced purity requirements and defects that are introduced through the casting process can impair minority carrier properties in poly-Si PV cells. This is only possible by using multiple characterization techniques that give macro-scale information (such as the spatial distribution of performance-limiting regions), as well as micro and nano-scale information about the structural and chemical nature of such performance-limiting regions. This study demonstrates the usefulness of combining multiple techniques to analyze performance-limiting regions in the poly-Si wafers that are used for PV cells. This is done by first identifying performance-limiting regions using macro-scale techniques including photoluminescence (PL) imaging, microwave photoconductive decay (uPCD), and reflectometry), then using smaller-scale techniques such as scanning electron microscopy (SEM), electron backscattered diffraction (EBSD), laser ablation inductively coupled mass spectrometry (LA-ICP-MS), cathodoluminescence (CL), and transmission electron microscopy (TEM) to understand the nature of such regions. This analysis shows that structural defects as well as metallic impurities are present in performance-limiting regions, which together act to decrease conversion efficiencies in poly-Si PV cells.

  20. Wafer chamber having a gas curtain for extreme-UV lithography

    DOEpatents

    Kanouff, Michael P.; Ray-Chaudhuri, Avijit K.

    2001-01-01

    An EUVL device includes a wafer chamber that is separated from the upstream optics by a barrier having an aperture that is permeable to the inert gas. Maintaining an inert gas curtain in the proximity of a wafer positioned in a chamber of an extreme ultraviolet lithography device can effectively prevent contaminants from reaching the optics in an extreme ultraviolet photolithography device even though solid window filters are not employed between the source of reflected radiation, e.g., the camera, and the wafer. The inert gas removes the contaminants by entrainment.

  1. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

    NASA Astrophysics Data System (ADS)

    Lee, Honggoo; Lee, Jongsu; Kim, Sang Min; Lee, Changhwan; Han, Sangjun; Kim, Myoungsoo; Kwon, Wontaik; Park, Sung-Ki; Vukkadala, Pradeep; Awasthi, Amartya; Kim, J. H.; Veeraraghavan, Sathish; Choi, DongSub; Huang, Kevin; Dighe, Prasanna; Lee, Cheouljung; Byeon, Jungho; Dey, Soham; Sinha, Jaydeep

    2015-03-01

    Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes - which is directly related to

  2. The removal of deformed submicron particles from silicon wafers by spin rinse and megasonics

    NASA Astrophysics Data System (ADS)

    Zhang, Fan; Busnaina, Ahmed A.; Fury, Michael A.; Wang, Shi-Qing

    2000-02-01

    In order to successfully clean particulate contamination from wafer surfaces, it is necessary to understand the adhesion and deformation between the particles and the substrate in contact. The adhesion and removal mechanisms of deformed submicron particles have not been addressed in many previous studies. Submicron polystyrene latex particles (0.1-0.5 µm) were deposited on silicon wafers and removed by spin rinse and megasonic cleanings. Particle rolling is identified as the major removal mechanism for the deformed submicron particles from silicon wafers. Megasonics provides larger streaming velocity because of the extremely thin boundary layer resulting in a larger removal force that is capable of achieving complete removal of contamination particles.

  3. W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

    NASA Technical Reports Server (NTRS)

    Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

    1997-01-01

    Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

  4. Development of a fixed abrasive slicing technique (FAST) for reducing the cost of photovoltaic wafers

    SciTech Connect

    Schmid, F. )

    1991-12-01

    This report examines a wafer slicing technique developed by Crystal Systems, Inc. that reduces the cost of photovoltaic wafers. This fixed, abrasive slicing technique (FAST) uses a multiwire bladepack and a diamond-plated wirepack; water is the coolant. FAST is in the prototype production stage and reduces expendable material costs while retaining the advantages of a multiwire slurry technique. The cost analysis revealed that costs can be decreased by making more cuts per bladepack and slicing more wafers per linear inch. Researchers studied the degradation of bladepacks and increased wirepack life. 21 refs.

  5. SEMICONDUCTOR TECHNOLOGY: Material removal rate in chemical-mechanical polishing of wafers based on particle trajectories

    NASA Astrophysics Data System (ADS)

    Jianxiu, Su; Xiqu, Chen; Jiaxi, Du; Renke, Kang

    2010-05-01

    Distribution forms of abrasives in the chemical mechanical polishing (CMP) process are analyzed based on experimental results. Then the relationships between the wafer, the abrasive and the polishing pad are analyzed based on kinematics and contact mechanics. According to the track length of abrasives on the wafer surface, the relationships between the material removal rate and the polishing velocity are obtained. The analysis results are in accord with the experimental results. The conclusion provides a theoretical guide for further understanding the material removal mechanism of wafers in CMP.

  6. Low temperature solder process to join a copper tube to a silicon wafer

    NASA Astrophysics Data System (ADS)

    Versteeg, Christo; Scarpim de Souza, Marcio

    2014-06-01

    With the application for wafer level packages, which could be Complementary Metal-Oxide-Semiconductor (CMOS) based, and which requires a reduced atmosphere, a copper tube connection to a vacuum pump and the package is proposed. The method evaluated uses laser assisted brazing of a solder, to join the copper tube to a silicon wafer. The method was applied to a silicon wafer coated with a metallic interface to bond to the solder. The hermeticity of the joint was tested with a helium leak rate tester and the bonding energy thermal extent was verified with a thin layer of indium that melted wherever the substrate temperature rose above its melting temperature.

  7. Long persistent near infrared luminescence nanoprobes LiGa5O8:Cr3+-PEG-OCH3 for in vivo imaging

    NASA Astrophysics Data System (ADS)

    Fu, Xiaoyan; Liu, Chunlin; Shi, Junpeng; Man, Huizi; Xu, Jia; Zhang, Hongwu

    2014-09-01

    The Cr3+-doped LiGa5O8 nanoparticles (LGNPs) with long-persistent near-infrared phosphorescence were obtained through a sol-gel approach followed by heat treatment at 800 °C in air. The obtained results reveal that the nanoparticles with an average diameter of 100 nm are well defined and have pure structure of LiGa5O8. After illumination for 3 min using a 254 nm UV lamp, the LGNPs exhibit strong near-infrared peak at ca. 720 nm belonging to tissue transparency window which can last for more than 1 h. Via surface modified with PEG-5000-OCH3, the LGNPs-PEG-OCH3 exhibit excellent biocompatibility and low toxicity. Under in vitro pre-excitation using a 254 nm UV lamp for 3 min, the in vivo distribution of the LGNPs-PEG-OCH3 in the abdomen can be detected in real time for more than 1 h. All the results indicate that the LGNPs-PEG-OCH3 can be used as potential nanoprobes to realize in vivo, real time and long time imaging with high sensitivity.

  8. Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

    PubMed

    Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

    2008-07-30

    Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

  9. Evolution of grain structures during directional solidification of silicon wafers

    NASA Astrophysics Data System (ADS)

    Lin, H. K.; Wu, M. C.; Chen, C. C.; Lan, C. W.

    2016-04-01

    The evolution of grain structures, especially the types of grain boundaries (GBs), during directional solidification is crucial to the electrical properties of multicrystalline silicon used for solar cells. To study this, the electric molten zone crystallization (EMZC) of silicon wafers at different drift speeds from 2 to 6 mm/min was considered. It was found that <111> orientation was dominant at the lower drift velocity, while <112> orientation at the higher drift velocity. Most of the non-∑GBs tended to align with the thermal gradient, but some tilted toward the unfavorable grains having higher interfacial energies. On the other hand, the tilted ∑3GBs tended to decrease during grain competition, except at the higher speed, where the twin nucleation became frequent. The competition of grains separated by ∑GBs could be viewed as the interactions of GBs that two coherent ∑3n GBs turned into one ∑3nGB following certain relations as reported before. On the other hand, when ∑ GBs met non-∑ GBs, the non-∑ GBs remained which explained the decrease of ∑ GBs at the lower speed.

  10. Adhesive disbond detection using piezoelectric wafer active sensors

    NASA Astrophysics Data System (ADS)

    Roth, William; Giurgiutiu, Victor

    2015-04-01

    The aerospace industry continues to increase the use of adhesives for structural bonding due to the increased joint efficiency (reduced weight), even distribution of the load path and decreases in stress concentrations. However, the limited techniques for verifying the strength of adhesive bonds has reduced its use on primary structures and requires an intensive inspection schedule. This paper discusses a potential structural health monitoring (SHM) technique for the detection of disbonds through the in situ inspection of adhesive joints. This is achieved through the use of piezoelectric wafer active sensors (PWAS), thin unobtrusive sensors which are permanently bonded to the aircraft structure. The detection method discussed in this study is electromechanical impedance spectroscopy (EMIS), a local vibration method. This method detects disbonds from the change in the mechanical impedance of the structure surrounding the disbond. This paper will discuss how predictive modeling can provide valuable insight into the inspection method, and provide better results than empirical methods alone. The inspection scheme was evaluated using the finite element method, and the results were verified experimentally using a large aluminum test article, and included both pristine and disbond coupons.

  11. Cleanroom compatible anodization cell for 150 mm Si wafers

    NASA Astrophysics Data System (ADS)

    Bardwell, Jennifer A.; LeBrun, Les; Evans, R. James; Curry, Donald G.; Abbott, Roger

    1996-06-01

    A cleanroom compatible anodization cell for use with 150 mm Si wafers has been constructed and tested. The material of construction is polyvinylidene fluoride, Kynar■, with Chemraz■ (elastomeric polytetrafluoroethylene) O-rings used for sealing. The back contact is made through a dilute HF solution, thus eliminating the possibility for metallic contamination which exists for other forms of back contact. Pt electrodes immersed in the back contact and front contact solutions are the primary electrical connection sites. Ellipsometry, Fourier transform infrared spectroscopy (FTIR), and dilute HF etch rate experiments were used to characterize the as-grown and annealed anodic oxides produced in this cell. Ellipsometric thickness mapping showed excellent lateral oxide uniformity over the entire anodized area; the standard deviations were <2 Å (for oxides ≤100 Å in thickness), <6 Å (for oxides ≤400 Å in thickness), and <10 Å (for oxides <500 Å in thickness). The properties of the oxides, as evaluated by FTIR spectroscopy are essentially identical to those grown on small-area samples using conventional anodization with a metallic back contact.

  12. Development of thin edgeless silicon pixel sensors on epitaxial wafers

    NASA Astrophysics Data System (ADS)

    Boscardin, M.; Bosisio, L.; Contin, G.; Giacomini, G.; Manzari, V.; Orzan, G.; Rashevskaya, I.; Ronchin, S.; Zorzi, N.

    2014-09-01

    The paper reports on the development of novel p-on-n thin edgeless planar pixel sensors, compatible with ALICE front-end electronics, fabricated by FBK on epitaxial material. The focus of the activity is the minimization of the material budget required for hybrid pixel detectors. This goal has been addressed in two different stages. In the first one, planar pixel detectors fabricated on epitaxial wafers have been thinned and bonded to the readout chips. The second stage is described by the present paper: the `active edge' concept has been studied for the reduction of the dead area at the periphery of the devices. An overview of the key technological steps and of the electrical characterization of the fabricated sensors is given. In addition, the preliminary results on the static behavior of test sensors after neutron irradiation at different fluences (up to 2.5 × 1015 1 MeV-neq/cm2) are reported. The results demonstrate that these kinds of devices are a viable solution for the reduction of the material budget while maintaining the typical electrical characteristics expected from radiation silicon sensors.

  13. Fast wafer-level detection and control of interconnect reliability

    NASA Astrophysics Data System (ADS)

    Foley, Sean; Molyneaux, James; Mathewson, Alan

    2000-08-01

    Many of the technological advances in the semiconductor industry have led to dramatic increases in device density and performance in conjunction with enhanced circuit reliability. As reliability is improved, the time taken to characterize particular failure modes with traditional test methods is getting substantially longer. Furthermore, semiconductor customers expect low product cost and fast time-to-market. The limits of traditional reliability testing philosophies are being reached and new approaches need to be investigated to enable the next generation of highly reliable products to be tested. This is especially true in the area of IC interconnect, where significant challenges are predicted for the next decade. A number of fast, wafer level test methods exist for interconnect reliability evaluation. The relative abilities of four such methods to detect the quality and reliability of IC interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are bench-marked against conventional package level Median Time to Failure results. The Isothermal test method combine with SWEAT-type test structures is shown to be the most suitable combination for defect detection and interconnect reliability control over very short test times.

  14. High uniform growth of 4-inch GaN wafer via flow field optimization by HVPE

    NASA Astrophysics Data System (ADS)

    Cheng, Yutian; Liu, Peng; Wu, Jiejun; Xiang, Yong; Chen, Xinjuan; Ji, Cheng; Yu, Tongjun; Zhang, Guoyi

    2016-07-01

    The uniformity of flow field inner the reactor plays a crucial role for hydride vapor phase epitaxy (HVPE) crystal growth and its more important for large scale substrate. A new nozzle structure was designed by adding a push and dilution (PD) gas pipe in the center of gas channels for a 4-inch HVPE (PD-HVPE) system. Experimental results showed that the thickness inhomogeneity of 46 μm 4-inch GaN layer could reach ±1.8% by optimizing PD gas, greatly improved from ±14% grown with conventional nozzle. The simulations of the internal flow field were consistent with our experiment, and the enhancement in uniformity should be attributed to the redistribution of GaCl and NH3 upon the wafer induced by PD pipe. The full width at half maximum (FWHM) of X-ray diffraction rocking curves for the 4-inch GaN film were about 224 and 200 arcsec for (002) and (102) reflection. The dislocation density of as-grown GaN was about 6.4×107 cm-2.

  15. Fabrication of capacitive absolute pressure sensor using Si-Au eutectic bonding in SOI wafer

    NASA Astrophysics Data System (ADS)

    Ryeol Lee, Kang; Kim, Kunnyun; Park, Hyo-Derk; Kim, Yong Kook; Choi, Seung-Woo; Choi, Woo-Beom

    2006-04-01

    A capacitive absolute pressure sensor was fabricated using a large deflected diaphragm with a sealed vacuum cavity formed by removing handling silicon wafer and oxide layers from a SOI wafer after eutectic bonding of a silicon wafer to the SOI wafer. The deflected displacements of the diaphragm formed by the vacuum cavity in the fabricated sensor were similar to simulation results. Initial capacitance values were about 2.18pF and 3.65pF under normal atmosphere, where the thicknesses of the diaphragm used to fabricate the vacuum cavity were 20 µm and 30 µm, respectively. Also, it was confirmed that the differences of capacitance value from 1000hPa to 5hPa were about 2.57pF and 5.35pF, respectively.

  16. Diffusion length and resistivity distribution characteristics of silicon wafer by photoluminescence

    SciTech Connect

    Baek, Dohyun; Lee, Jaehyeong; Choi, Byoungdeog

    2014-10-15

    Highlights: • Analytical photoluminescence efficiency calculation and PL intensity ratio method are developed. • Wafer resistivity and diffusion length characteristics are investigated by PL intensity ratio. • PL intensity is well correlated with resistivity, diffusion length or defect density on wafer measurement. - Abstract: Photoluminescence is a convenient, contactless method to characterize semiconductors. Its use for room-temperature silicon characterization has only recently been implemented. We have developed the PL efficiency theory as a function of substrate doping densities, bulk trap density, photon flux density, and reflectance and compared it with experimental data initially for bulk Si wafers. New developed PL intensity ratio method is able to predict the silicon wafer properties, such as doping densities, minority carrier diffusion length and bulk trap density.

  17. Hydrogen-induced program threshold voltage degradation analysis in SONOS wafer

    NASA Astrophysics Data System (ADS)

    Lin, Qing; Zhao, Crystal; Sheng, Nan

    2016-02-01

    This paper studies the hydrogen-induced program state threshold voltage degradation in SONOS wafers, which ultimately impacts wafer sort test yield. During wafer sort step, all individual integrated circuits noted as die are tested for functional defects by applying special test patterns to them. The proportion between the passing die (good die) and the non-passing die (bad die) is sort yield. The different N2/H2 ratio in IMD1 alloy process yields differently at flash checkerboard test. And the SIMS curves were also obtained to depict the distribution profile of H+ in SONOS ONO stack structure. It is found that, the H+ accumulated in the interface between the Tunnel oxide and Si layer, contributes the charge loss in Oxynitride layer, which leads to the program threshold voltage degradation and even fall below lower specification limit, and then impacts the sort yield of SONOS wafers.

  18. Electromagnetic field modeling for defect detection in 7 nm node patterned wafers

    NASA Astrophysics Data System (ADS)

    Zhu, Jinlong; Zhang, Kedi; Davoudzadeh, Nima; Wang, Xiaozhen; Goddard, Lynford L.

    2016-03-01

    By 2017, the critical dimension in patterned wafers will shrink down to 7 nm, which brings great challenges to optics-based defect inspection techniques, due to the ever-decreasing signal to noise ratio with respect to defect size. To continue pushing forward the optics-based metrology technique, it is of great importance to analyze the full characteristics of the scattering field of a wafer with a defect and then to find the most sensitive signal type. In this article, the vector boundary element method is firstly introduced to calculate the scattering field of a patterned wafer at a specific objective plane, after which a vector imaging theory is introduced to calculate the field at an image plane for an imaging system with a high numerical aperture objective lens. The above methods enable the effective modeling of the image for an arbitrary vectorial scattering electromagnetic field coming from the defect pattern of the wafer.

  19. Silicon Wafer Surface-Temperature Monitoring System for Plasma Etching Process

    NASA Astrophysics Data System (ADS)

    Yamada, Y.; Ishii, J.; Nakaoka, A.; Mizojiri, Y.

    2011-08-01

    A thermoreflectance temperature measuring system was developed with the aim to realize monitoring of the silicon wafer surface temperature during plasma etching. The thermoreflectance detects variations in temperature through changes in optical reflectance. To overcome such difficulties as low sensitivity and limitation in installation space and position for in situ measurements, the differential thermoreflectance utilizing two orthogonal polarizations was introduced. Noise such as fluctuations in the incident beam intensity or changes of loss in the optical path would affect both polarizations equally and would not affect the measurement. The large angle of incidence of the beam allows measurement to be performed from outside the viewing ports of existing plasma etching process chambers through the gap between the plasma electrode and the silicon wafer. In this article, an off-line measurement result is presented, with results for bare wafers as well as for wafers with metal depositions. A prototype system developed for tests in plasma etching facilities in a production line is described.

  20. Eutectic bonding of a Ti sputter coated, carbon aerogel wafer to a Ni foil

    SciTech Connect

    Jankowski, A.F.; Hayes, J.P.; Kanna, R.L.

    1994-06-01

    The formation of high energy density, storage devices is achievable using composite material systems. Alternate layering of carbon aerogel wafers and Ni foils with rnicroporous separators is a prospective composite for capacitor applications. An inherent problem exists to form a physical bond between Ni and the porous carbon wafer. The bonding process must be limited to temperatures less than 1000{degrees}C, at which point the aerogel begins to degrade. The advantage of a low temperature eutectic in the Ni-Ti alloy system solves this problem. Ti, a carbide former, is readily adherent as a sputter deposited thin film onto the carbon wafer. A vacuum bonding process is then used to join the Ni foil and Ti coating through eutectic phase formation. The parameters required for successfld bonding are described along with a structural characterization of the Ni foil-carbon aerogel wafer interface.

  1. Influence of thermal load on 450 mm Si-wafer IPD during lithographic patterning

    NASA Astrophysics Data System (ADS)

    Peschel, Thomas; Kalkowski, Gerhard; Eberhardt, Ramona

    2012-03-01

    We report on Finite Element Modeling (FEM) of the influence of heat load due to the lithographic exposure on the inplane distortion (IPD) of 450 mm Si-wafers and hence on the effect of the heat load on the achievable image placement accuracy. Based on a scenario of electron beam writing at an exposure power of 20 mW, the thermo-mechanical behavior of the chuck and the attached Si wafer is modeled and used to derive corresponding IPD values. To account for the pin structured chuck surface, an effective layer model is derived. Different materials for the wafer chuck are compared with respect to their influence on wafer IPD and thermal characteristics of the exposure process. Guidelines for the selection of the chuck material und suggestions for its cooling and corrective strategies on e-beam steering during exposure are derived.

  2. Photocatalytic water disinfection by simple and low-cost monolithic and heterojunction ceramic wafers.

    PubMed

    Makwana, Neel M; Hazael, Rachael; McMillan, Paul F; Darr, Jawwad A

    2015-06-01

    In this work, the photocatalytic disinfection of Escherichia coli (E. coli) using dual layer ceramic wafers, prepared by a simple and low-cost technique, was investigated. Heterojunction wafers were prepared by pressing TiO2 and WO3 powders together into 2 layers within a single, self-supported monolith. Data modelling showed that the heterojunction wafers were able to sustain the formation of charged species (after an initial "charging" period). In comparison, a wafer made from pure TiO2 showed a less desirable bacterial inactivation profile in that the rate decreased with time (after being faster initially). The more favourable kinetics of the dual layer system was due to superior electron-hole vectorial charge separation and an accumulation of charges beyond the initial illumination period. The results demonstrate the potential for developing simplified photocatalytic devices for rapid water disinfection. PMID:25976167

  3. A study of defects on EUV mask using blank inspection, patterned mask inspection, and wafer inspection

    SciTech Connect

    Huh, S.; Ren, L.; Chan, D.; Wurm, S.; Goldberg, K. A.; Mochi, I.; Nakajima, T.; Kishimoto, M.; Ahn, B.; Kang, I.; Park, J.-O.; Cho, K.; Han, S.-I.; Laursen, T.

    2010-03-12

    The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing. yet link data is available for understanding native defects on real masks. In this paper, a full-field EUV mask is fabricated to investigate the printability of various defects on the mask. The printability of defects and identification of their source from mask fabrication to handling were studied using wafer inspection. The printable blank defect density excluding particles and patterns is 0.63 cm{sup 2}. Mask inspection is shown to have better sensitivity than wafer inspection. The sensitivity of wafer inspection must be improved using through-focus analysis and a different wafer stack.

  4. Photocatalytic water disinfection by simple and low-cost monolithic and heterojunction ceramic wafers.

    PubMed

    Makwana, Neel M; Hazael, Rachael; McMillan, Paul F; Darr, Jawwad A

    2015-06-01

    In this work, the photocatalytic disinfection of Escherichia coli (E. coli) using dual layer ceramic wafers, prepared by a simple and low-cost technique, was investigated. Heterojunction wafers were prepared by pressing TiO2 and WO3 powders together into 2 layers within a single, self-supported monolith. Data modelling showed that the heterojunction wafers were able to sustain the formation of charged species (after an initial "charging" period). In comparison, a wafer made from pure TiO2 showed a less desirable bacterial inactivation profile in that the rate decreased with time (after being faster initially). The more favourable kinetics of the dual layer system was due to superior electron-hole vectorial charge separation and an accumulation of charges beyond the initial illumination period. The results demonstrate the potential for developing simplified photocatalytic devices for rapid water disinfection.

  5. Rizatriptan wafer--sublingual vs. placebo at the onset of acute migraine.

    PubMed

    Klapper, J A; O'Connor, S

    2000-07-01

    Rizatriptan wafer is a 5HT1B/1D agonist for use in the acute treatment of migraine. It is a freeze-fried formulation, approved for oral administration, which dissolves on the tongue and is swallowed with saliva. In this study the efficacy of sublingually administered rizatriptan 10-mg wafer was evaluated in a randomized, double-blind, placebo-controlled, out-patient study involving 39 migraineurs. Patients were instructed to treat a migraine at the onset of pain in order to evaluate time of onset of pain relief and pain relief at 1 h. The average time to onset of relief was 25 min for patients treated with rizatriptan wafer and 27 min for patients treated with placebo. At 1 h, 50% of the patients receiving rizatriptan wafer and 50% of the patients receiving placebo experienced significant relief. Implications and potential reasons for a high placebo response are discussed.

  6. Characterization and control of wafer charging effects during high-current ion implantation

    SciTech Connect

    Current, M.I.; Lukaszek, W.; Dixon, W.; Vella, M.C.; Messick, C.; Shideler, J.; Reno, S.

    1994-02-01

    EEPROM-based sense and memory devices provide direct measures of the charge flow and potentials occurring on the surface of wafers during ion beam processing. Sensor design and applications for high current ion implantation are discussed.

  7. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.

    2011-07-12

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  8. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    DOEpatents

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.

    2008-11-18

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  9. Influence of the Viscoelastic Properties of the Polyimide Dielectric Coating on the Wafer Warpage

    NASA Astrophysics Data System (ADS)

    Zhu, Chunsheng; Ning, Wenguo; Xu, Gaowei; Luo, Le

    2014-09-01

    Polyimide is widely used as the dielectric material in wafer level packaging. One potential problem with its application is the warpage and stress generated in the curing process. This paper investigated the material properties of polyimide and its influence on the wafer warpage. The viscoelastic properties of polyimide film were measured and a mathematical model of the properties was developed. Finite element analysis of the wafer warpage was performed and this indicates that the viscoelastic material model gave the best prediction. To better understand the causation of the warpage, curvature evolution of the polyimide-coated silicon wafer during its curing process was measured by a multi-beam optical sensor system. It was found that the warpage was mainly induced by the coefficient of thermal expansion mismatch and that the cure shrinkage of polyimide had little effect. Additionally, the effect of the cooling rate on the wafer warpage was also studied. Both simulation and experiment results showed that a slower cooling rate in the temperature range around the glass transition temperature ( T g) of polyimide will help to reduce the final wafer warpage.

  10. A novel nanoglue and whole wafer self-alignment based upon self-assembled monolayers

    NASA Astrophysics Data System (ADS)

    Emanuel, Ako; Walker, Ernest; Hallen, Hans

    2008-10-01

    New methodologies for fabrication of multilevel packaging, particularly for RF signal analysis, are investigated. A new method for ``gluing'' silicon wafers together with a Self Assembled Monolayers (SAMs) based nanoglue are discussed, as are methods to enable its use with nonconforming wafers. Results of bond strength measurements as a function of temperature and process will be presented. Surface area bonded is characterized by infrared (IR) imaging. We will also present a method of inducing self-alignment between whole silicon wafers with micrometer precision. This represents a qualitative departure from alignment of millimeter-sized object as has been previously demonstrated. Self-alignment is induced by creating hydrophilic and hydrophobic regions on the wafers and using capillary forces of water in these regions to force the wafers to align with little to no outside influence. Results are characterized by IR imaging. Physical ideas that enable the whole-wafer alignment such as flow channels, elimination of secondary minima, large central capture areas and small edge features are discussed. The possibility of aligning with the nanoglue materials as the alignment drivers is discussed.

  11. Time-varying wetting behavior on copper wafer treated by wet-etching

    NASA Astrophysics Data System (ADS)

    Tu, Sheng-Hung; Wu, Chuan-Chang; Wu, Hsing-Chen; Cheng, Shao-Liang; Sheng, Yu-Jane; Tsao, Heng-Kwong

    2015-06-01

    The wet cleaning process in semiconductor fabrication often involves the immersion of the copper wafer into etching solutions and thereby its surface properties are significantly altered. The wetting behavior of a copper film deposited on silicon wafer is investigated after a short dip in various etching solutions. The etchants include glacial acetic acid and dilute solutions of nitric acid, hydrofluoric acid, and tetramethylammonium hydroxide. It was found that in most cases a thin oxide layer still remains on the surface of as-received Cu wafers when they are subject to etching treatments. However, a pure Cu wafer can be obtained by the glacial acetic acid treatment and its water contact angle (CA) is about 45°. As the pure Cu wafer is placed in the ambient condition, the oxide thickness grows rapidly to the range of 10-20 Å within 3 h and the CA on the hydrophilic surface also rises. In the vacuum, it is surprising to find that the CA and surface roughness of the pure Cu wafer can grow significantly. These interesting results may be attributed to the rearrangement of surface Cu atoms to reduce the surface free energy.

  12. A wafer mapping technique for residual stress in surface micromachined films

    NASA Astrophysics Data System (ADS)

    Schiavone, G.; Murray, J.; Smith, S.; Desmulliez, M. P. Y.; Mount, A. R.; Walton, A. J.

    2016-09-01

    The design of MEMS devices employing movable structures is crucially dependant on the mechanical behaviour of the deposited materials. It is therefore important to be able to fully characterize the micromachined films and predict with confidence the mechanical properties of patterned structures. This paper presents a characterization technique that enables the residual stress in MEMS films to be mapped at the wafer level by using microstructures released by surface micromachining. These dedicated MEMS test structures and the associated measurement techniques are used to extract localized information on the strain and Young’s modulus of the film under investigation. The residual stress is then determined by numerically coupling this data with a finite element analysis of the structure. This paper illustrates the measurement routine and demonstrates it with a case study using electrochemically deposited alloys of nickel and iron, particularly prone to develop high levels of residual stress. The results show that the technique enables wafer mapping of film non-uniformities and identifies wafer-to-wafer differences. A comparison between the results obtained from the mapping technique and conventional wafer bow measurements highlights the benefits of using a procedure tailored to films that are non-uniform, patterned and surface-micromachined, as opposed to simple standard stress extraction methods. The presented technique reveals detailed information that is generally unexplored when using conventional stress extraction methods such as wafer bow measurements.

  13. Mechanical wafer engineering for semitransparent polycrystalline silicon solar cells

    NASA Astrophysics Data System (ADS)

    Willeke, G.; Fath, P.

    1994-03-01

    A concept for the realization of semitransparent bifacially active highly efficient and light weight crystalline silicon solar cells is presented. The concept is based on the preparation of perpendicular V-grooves in silicon blanks by mechanical abrasion using a dicing saw and beveled blades. Holes of variable diameter are formed automatically in the processing step, which provide a connection between the passivated phosphorus doped front and back side emitters. A maximum bulk-emitter distance of ˜30 μm has been realized in 200 μm thick structures which should result in highly efficient solar cell devices even in small grain low quality polycrystalline material. The partial transparency of the presented solar cell structure opens the way for new applications (crystalline Si photovoltaic windows, etc.). The feasibility of the mechanical grooving process has been demonstrated on Wacker SILSO cast silicon. Double-side V-grooved structures (distance between grooves 90 and 140 μm, bevel angle 35°) with hole diameters in the range 10-70 μm, corresponding to a transmittance of up to 30% in the visible, have been prepared with excellent uniformity and mechanical stability over a large area (5×5 cm2). An average total reflectance in the range 500-1000 nm of Rav=0.9% has been measured on a structure with a geometrical hole fraction of 1.7% after growth of a 1170 Å thick layer of thermal oxide. This SILSO structure had an effective silicon thickness of 120 μm, whereas the absorptance spectrum near the band edge was similar to a 5.5 mm thick nongrooved silicon wafer, indicating the excellent light trapping obtained.

  14. NXE:3100 full wafer imaging performance and budget verification

    NASA Astrophysics Data System (ADS)

    van Setten, Eelco; van Ingen Schenau, Koen; O'Mahony, Mark; Hollink, Thijs; Wittebrood, Friso; Davydova, Natalia; Eurlings, Mark; Feenstra, Kees; Finders, Jo; Dusa, Mircea; Young, Stuart

    2012-02-01

    With the introduction of the NXE:3100 NA=0.25 exposure system a big step has been made to get EUV lithography ready for High Volume Manufacturing. Over the last year, 6 exposure systems have been shipped to various customers around the world, active in Logic, DRAM, MPU and Flash memory, covering all major segments in the semi-conductor industry. The integration and qualification of these systems have provided a great learning, identifying the benefits of EUV over ArF immersion and the critical parameters of the exposure tool and how to operate it. In this paper we will focus specifically on the imaging performance of the NXE:3100 EUV scanner. Having been operational for more than a year a wide range of features were evaluated for lithographic performance across the field and across wafer. CD results of 32nm contact holes, 27nm isolated and dense lines, 27nm two-bar, 22nm dense L/S with Dipole, as well as several device features will be discussed and benchmarked against the current ArF immersion performance. A budget verification will be presented showing CD and contrast budgets for a selection of lithographic features. The contribution of the resist process and the mask will be discussed as well. The litho performance optimization will be highlighted with the 27nm twobar and isolated lines features that are sensitive to the illuminator pupil shape and projection lens aberrations. We will estimate the amount of resist induced contrast loss for 27 and 22nm L/S based on measurements of Exposure Latitude and the contributors from the exposure system. We will further present on the impact of variations in the mask blank and patterned mask on imaging, with several new contributors to take into account compared to traditional transmission masks. Finally, the combined results will be projected to the NXE:3300 NA=0.33 exposure system to give an outlook for its imaging performance capabilities.

  15. Control of Gene Expression in Leptospira spp. by Transcription Activator-Like Effectors Demonstrates a Potential Role for LigA and LigB in Leptospira interrogans Virulence.

    PubMed

    Pappas, Christopher J; Picardeau, Mathieu

    2015-11-01

    Leptospirosis is a zoonotic disease that affects ∼1 million people annually, with a mortality rate of >10%. Currently, there is an absence of effective genetic manipulation tools for targeted mutagenesis in pathogenic leptospires. Transcription activator-like effectors (TALEs) are a recently described group of repressors that modify transcriptional activity in prokaryotic and eukaryotic cells by directly binding to a targeted sequence within the host genome. To determine the applicability of TALEs within Leptospira spp., two TALE constructs were designed. First, a constitutively expressed TALE gene specific for the lacO-like region upstream of bgaL was trans inserted in the saprophyte Leptospira biflexa (the TALEβgal strain). Reverse transcriptase PCR (RT-PCR) analysis and enzymatic assays demonstrated that BgaL was not expressed in the TALEβgal strain. Second, to study the role of LigA and LigB in pathogenesis, a constitutively expressed TALE gene with specificity for the homologous promoter regions of ligA and ligB was cis inserted into the pathogen Leptospira interrogans (TALElig). LigA and LigB expression was studied by using three independent clones: TALElig1, TALElig2, and TALElig3. Immunoblot analysis of osmotically induced TALElig clones demonstrated 2- to 9-fold reductions in the expression levels of LigA and LigB, with the highest reductions being noted for TALElig1 and TALElig2, which were avirulent in vivo and nonrecoverable from animal tissues. This study reconfirms galactosidase activity in the saprophyte and suggests a role for LigA and LigB in pathogenesis. Collectively, this study demonstrates that TALEs are effective at reducing the expression of targeted genes within saprophytic and pathogenic strains of Leptospira spp., providing an additional genetic manipulation tool for this genus. PMID:26341206

  16. LIGA for lobster?

    NASA Astrophysics Data System (ADS)

    Peele, Andrew G.; Irving, Thomas H.; Nugent, Keith A.; Mancini, Derrick C.; Moldovan, Nicolaie A.; Christenson, Todd R.; Petre, Robert; Brumby, Steven P.; Priedhorsky, William C.

    2001-01-01

    The prospect of making a lobster-eye telescope is drawing closer with recent developments in the manufacture of microchannel-plate optics. This would lead to an x-ray all-sky monitor with vastly improved sensitivity and resolution over existing and other planned instruments. We consider a new approach, using deep etch x-ray lithography, to making a lobster-eye lens that offers certain advantages even over microchannel-plate technology.

  17. LIGA FOR LOBSTER?

    SciTech Connect

    Peele, A.G.; Irving, T.H.

    2000-09-01

    The prospect of making a lobster-eye telescope is drawing closer with recent developments in the manufacture of microchannel-plate optics. This would lead to an x-ray all-sky monitor with vastly improved sensitivity and resolution over existing and other planned instruments. We consider a new approach, using deep etch x-ray lithography, to making a lobster-eye lens that offers certain advantages even over microchannel-plate technology.

  18. Process variation monitoring (PVM) by wafer inspection tool as a complementary method to CD-SEM for mapping LER and defect density on production wafers

    NASA Astrophysics Data System (ADS)

    Shabtay, Saar; Blumberg, Yuval; Levi, Shimon; Greenberg, Gadi; Harel, Daniel; Conley, Amiad; Meshulach, Doron; Kan, Kobi; Dolev, Ido; Kumar, Surender; Mendel, Kalia; Goto, Kaori; Yamaguchi, Naoaki; Iriuchijima, Yasuhiro; Nakamura, Shinichi; Nagaoka, Shirou; Sekito, Toshiyuki

    2009-03-01

    As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) constitute a higher percentage of the line-width and hence the need to control these parameters increases. Sources of CDU and LER variations include: scanner auto-focus accuracy and stability, lithography stack thickness and composition variations, exposure variations, etc. These process variations in advanced VLSI manufacturing processes, specifically in memory devices where CDU and LER affect cell-to-cell parametric variations, are well known to significantly impact device performance and die yield. Traditionally, measurements of LER are performed by CD-SEM or Optical Critical Dimension (OCD) metrology tools. Typically, these measurements require a relatively long time and cover only a small fraction of the wafer area. In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and Nikon Corporation®, on the implementation of a complementary method to the CD-SEM and OCD tools, to monitor post litho develop CDU and LER on production wafers. The method, referred to as Process Variation Monitoring (PVM), is based on measuring variations in the light reflected from periodic structures, under optimized illumination and collection conditions, and is demonstrated using Applied Materials DUV brightfield (BF) wafer inspection tool. It will be shown that full polarization control in illumination and collection paths of the wafer inspection tool is critical to enable to set an optimized Process Variation Monitoring recipe.

  19. P/N InP solar cells on Ge wafers

    NASA Technical Reports Server (NTRS)

    Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

    1994-01-01

    Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented

  20. Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule

    SciTech Connect

    Emanuel Sachs Tonio Buonassisi

    2013-01-16

    The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the

  1. High aspect ratio nano-fabrication of photonic crystal structures on glass wafers using chrome as hard mask.

    PubMed

    Hossain, Md Nazmul; Justice, John; Lovera, Pierre; McCarthy, Brendan; O'Riordan, Alan; Corbett, Brian

    2014-09-01

    Wafer-scale nano-fabrication of silicon nitride (Si x N y ) photonic crystal (PhC) structures on glass (quartz) substrates is demonstrated using a thin (30 nm) chromium (Cr) layer as the hard mask for transferring the electron beam lithography (EBL) defined resist patterns. The use of the thin Cr layer not only solves the charging effect during the EBL on the insulating substrate, but also facilitates high aspect ratio PhCs by acting as a hard mask while deep etching into the Si x N y . A very high aspect ratio of 10:1 on a 60 nm wide grating structure has been achieved while preserving the quality of the flat top of the narrow lines. The presented nano-fabrication method provides PhC structures necessary for a high quality optical response. Finally, we fabricated a refractive index based PhC sensor which shows a sensitivity of 185 nm per RIU. PMID:25116111

  2. High aspect ratio nano-fabrication of photonic crystal structures on glass wafers using chrome as hard mask

    NASA Astrophysics Data System (ADS)

    Nazmul Hossain, Md; Justice, John; Lovera, Pierre; McCarthy, Brendan; O'Riordan, Alan; Corbett, Brian

    2014-09-01

    Wafer-scale nano-fabrication of silicon nitride (Si x N y ) photonic crystal (PhC) structures on glass (quartz) substrates is demonstrated using a thin (30 nm) chromium (Cr) layer as the hard mask for transferring the electron beam lithography (EBL) defined resist patterns. The use of the thin Cr layer not only solves the charging effect during the EBL on the insulating substrate, but also facilitates high aspect ratio PhCs by acting as a hard mask while deep etching into the Si x N y . A very high aspect ratio of 10:1 on a 60 nm wide grating structure has been achieved while preserving the quality of the flat top of the narrow lines. The presented nano-fabrication method provides PhC structures necessary for a high quality optical response. Finally, we fabricated a refractive index based PhC sensor which shows a sensitivity of 185 nm per RIU.

  3. Stress diagnostics and crack detection in full-size silicon wafers using resonance ultrasonic vibrations

    NASA Astrophysics Data System (ADS)

    Byelyayev, Anton

    Non-destructive monitoring of residual elastic stress in silicon wafers is a matter of strong concern for modern photovoltaic industry. The excess stress can generate cracks within the crystalline structure, which further may lead to wafer breakage. Cracks diagnostics and reduction in multicrystalline silicon, for example, are ones of the most important issues in photovoltaics now. The industry is intent to improve the yield of solar cells fabrication. There is a number of techniques to measure residual stress in semiconductor materials today. They include Raman spectroscopy, X-ray diffraction and infrared polariscopy. None of these methods are applicable for in-line diagnostics of residual elastic stress in silicon wafers for solar cells. Moreover, the method has to be fast enough to fit in solar cell sequential production line. In photovoltaics, fast in-line quality control has to be performed within two seconds per wafer to match the throughput of the production lines. During this Ph.D. research we developed the resonance ultrasonic vibration (RUV) approach to diagnose residual stress non-destructively in full-size multicrystalline silicon wafers used in solar cell manufacturing. This method is based on excitation of longitudinal resonance ultrasonic vibrations in the material using an external piezoelectric transducer combined with high sensitive ultrasonic probe and data acquisition of the frequency response to make the method suitable for in-line diagnostics during wafer and cell manufacturing. Theoretical and experimental analyses of the vibration mode in single crystal and multicrystalline silicon wafers were used to provide a benchmark reference analysis and validation of the approach. Importantly, we observed a clear trend of increasing resonance frequency of the longitudinal vibration mode with higher average in-plane stress obtained with scanning infrared polariscopy. Using the same experimental approach we assessed a fast crack detection and length

  4. Nondestructive evaluation of large-area PZN-8%PT single crystal wafers for medical ultrasound imaging probe applications.

    PubMed

    Kumar, Francis J; Lim, Leong-Chew; Lim, Siak Piang; Lee, Kwok Hong

    2003-03-01

    A nondestructive quality evaluation and control procedure for large-area, (001)-cut PZN-8%PT wafers is described. The crystals were grown by the flux technique engineered to promote (001) layer growth of the crystals. The wafers were sliced parallel to the (001) layer growth plane. Curie temperature (Tc) variations, measured with matching arrays of dot electrodes (of 5.0 mm in center-to-center spacing), were found to be better than +/- 4.0 degrees C both within wafers and from wafer to wafer. After selective dicing to give final wafers of narrower Tc distributions (e.g., +/- 3.0 degrees C or better), the wafers were coated with complete electrodes and poled at room temperature at 0.7-0.9 kV/mm. Typical overall properties of the poled wafers were: K3T = 5,200 (+/- 10% from wafer to wafer), tan delta < 0.01 (all wafers), and kt = 0.55 (+/- 5%) (all percentage variations are in relative percentages). Then, the distributions of K3S, tan delta, and kt were measured by the array dot electrode technique. The variations in K3S (hence K3T) and kt within individual wafers were found to be within +/- 10% and +/- 5%, respectively. The dielectric loss values, measured at 1 kHz, were consistently low, being < 0.01 throughout the wafers. The kt values determined by the dot electrodes were found to be about 5% smaller than those obtained with the complete electrodes, which can be attributed to an increase in capacitance ratio due to the partial electroding. The k33 values, deduced using the relation K3S approximately (1 - k33(2))K3T, from the mean K3S and overall K3T values, average 0.94 (+/- 2%). The present work shows that the distribution of Tc within wafers can be used as a convenient check for the uniformity in composition and electromechanical properties of PZN-8%PT single crystal wafers. Our results show that, to control deltaK3T and deltakt within individual wafer to < or = 10% and 5%, respectively, the variation in Tc within the wafer should be kept within +/- 3.0 degrees

  5. The role of Gliadel wafers in the treatment of newly diagnosed GBM: a meta-analysis

    PubMed Central

    Xing, Wei-kang; Shao, Chuan; Qi, Zhen-yu; Yang, Chao; Wang, Zhong

    2015-01-01

    Background Standard treatment for high-grade glioma (HGG) includes surgery followed by radiotherapy and/or chemotherapy. Insertion of carmustine wafers into the resection cavity as a treatment for malignant glioma is currently a controversial topic among neurosurgeons. Our meta-analysis focused on whether carmustine wafer treatment could significantly benefit the survival of patients with newly diagnosed glioblastoma multiforme (GBM). Method We searched the PubMed and Web of Science databases without any restrictions on language using the keywords “Gliadel wafers”, “carmustine wafers”, “BCNU wafers”, or “interstitial chemotherapy” in newly diagnosed GBM for the period from January 1990 to March 2015. Randomized controlled trials (RCTs) and cohort studies/clinical trials that compared treatments designed with and without carmustine wafers and which reported overall survival or hazard ratio (HR) or survival curves were included in this study. Moreover, the statistical analysis was conducted by the STATA 12.0 software. Results Six studies including two RCTs and four cohort studies, enrolling a total of 513 patients (223 with and 290 without carmustine wafers), matched the selection criteria. Carmustine wafers showed a strong advantage when pooling all the included studies (HR =0.63, 95% confidence interval (CI) =0.49–0.81; P=0.019). However, the two RCTs did not show a statistical increase in survival in the group with carmustine wafer compared to the group without it (HR =0.51, 95% CI =0.18–1.41; P=0.426), while the cohort studies demonstrated a significant survival increase (HR =0.59, 95% CI =0.44–0.79; P<0.0001). Conclusion Carmustine-impregnated wafers play a significant role in improving survival when used for patients with newly diagnosed GBM. More studies should be designed for newly diagnosed GBM in the future. PMID:26170620

  6. Design and fabrication of a 1-DOF drive mode and 2-DOF sense mode micro-gyroscope using SU-8 based UV-LIGA process

    NASA Astrophysics Data System (ADS)

    Verma, Payal; Juneja, Sucheta; Savelyev, Dmitry A.; Khonina, Svetlana N.; Gopal, Ram

    2016-04-01

    This paper presents design and fabrication of a 1-DOF (degree-of-freedom) drive mode and 2-DOF sense mode micro-gyroscope. It is an inherently robust structure and offers a high sense frequency bandwidth. The proposed design utilizes resonance of the1-DOF drive mode oscillator and employs dynamic amplification concept in sense modes to increase the sensitivity while maintaining robustness. The 2-DOF in the sense direction renders the device immune to process imperfections and environmental effects. The design is simulated using FEA software (CoventorWare®). The device is designed considering process compatibility with SU-8 based UV-LIGA process, which is an economical fabrication technique. The complete fabrication process is presented along with SEM images of the fabricated device. The device has 9 µm thick Nickel as the key structural layer with an overall reduced key structure size of 2.2 mm by 2.1 mm.

  7. Structural Damage Detection with Piezoelectric Wafer Active Sensors

    NASA Astrophysics Data System (ADS)

    Giurgiutiu, Victor

    2011-07-01

    Piezoelectric wafer active sensors (PWAS) are lightweight and inexpensive enablers for a large class of damage detection and structural health monitoring (SHM) applications. This paper starts with a brief review of PWAS physical principles and basic modelling and continues by considering the various ways in which PWAS can be used for damage detection: (a) embedded guided-wave ultrasonics, i.e., pitch-catch, pulse-echo, phased arrays, thickness mode; (b) high-frequency modal sensing, i.e., the electro-mechanical (E/M) impedance method; (c) passive detection, i.e., acoustic emission and impact detection. An example of crack-like damage detection and localization with PWAS phased arrays on a small metallic plate is given. The modelling of PWAS detection of disbond damage in adhesive joints is achieved with the analytical transfer matrix method (TMM). The analytical methods offer the advantage of fast computation which enables parameter studies and carpet plots. A parametric study of the effect of crack size and PWAS location on disbond detection is presented. The power and energy transduction between PWAS and structure is studied analytically with a wave propagation method. Special attention is given to the mechatronics modeling of the complete transduction cycle from electrical excitation into ultrasonic acoustic waves by the piezoelectric effect, the transfer through the structure, and finally reverse piezoelectric transduction to generate the received electric signal. It is found that the combination of PWAS size and wave frequency/wavelength play an important role in identifying transduction maxima and minima that could be exploited to achieve an optimum power-efficient design. The multi-physics finite element method (MP-FEM), which permits fine discretization of damaged regions and complicated structural geometries, is used to study the generation of guided waves in a plate from an electrically excited transmitter PWAS and the capture of these waves as electric

  8. Rinsing of wafers after wet processing: Simulation and experiments

    NASA Astrophysics Data System (ADS)

    Chiang, Chieh-Chun

    In semiconductor manufacturing, a large amount (50 billion gallons for US semiconductor fabrication plants in 2006) of ultrapure water (UPW) is used to rinse wafers after wet chemical processing to remove ionic contaminants on surfaces. Of great concern are the contaminants left in narrow (tens of nm), high-aspect-ratio (5:1 to 20:1) features (trenches, vias, and contact holes). The International Technology Roadmap for Semiconductors (ITRS) stipulates that ionic contaminant levels be reduced to below ˜ 10 10 atoms/cm2. Understanding the bottlenecks in the rinsing process would enable conservation of rinse water usage. A comprehensive process model has been developed on the COMSOL platform to predict the dynamics of rinsing of narrow structures on patterned SiO 2 substrates initially cleaned with NH4OH. The model considers the effect of various mass-transport mechanisms, including convection and diffusion/dispersion, which occur simultaneously with various surface phenomena, such as adsorption and desorption of impurities. The influences of charged species in the bulk and on the surface, and their induced electric field that affect both transport and surface interactions, have been addressed. Modeling results show that the efficacy of rinsing is strongly influenced by the rate of desorption of adsorbed contaminants, mass transfer of contaminants from the mouth of the feature to the bulk liquid, and the trench aspect ratio. Detection of the end point of rinsing is another way to conserve water used for rinsing after wet processing. The applicability of electrochemical impedance spectroscopy (EIS) to monitor rinsing of Si processed in HF with and without copper contaminant was explored. In the first study, the effect of the nature of surface state (flat band, depletion, or accumulation) of silicon on rinsing rate was investigated. The experimental results show that the state of silicon could affect rinsing kinetics through modulation of ion adsorption. In the second

  9. Behavior of piezoelectric wafer active sensor in various media

    NASA Astrophysics Data System (ADS)

    Kamas, Tuncay

    The dissertation addresses structural health monitoring (SHM) techniques using ultrasonic waves generated by piezoelectric wafer active sensors (PWAS) with an emphasis on the development of theoretical models of standing harmonic waves and guided waves. The focal objective of the research is to extend the theoretical study of electro-mechanical coupled PWAS as a resonator/transducer that interacts with standing and traveling waves in various media through electro-mechanical impedance spectroscopy (EMIS) method and guided wave propagation. The analytical models are developed and the coupled field finite element analysis (CF-FEA) models are simulated and verified with experiments. The dissertation is divided into two parts with respect to the developments in EMIS methods and GWP methods. In the first part, analytical and finite element models have been developed for the simulation of PWAS-EMIS in in-plane (longitudinal) and out-of-plane (thickness) mode. Temperature effects on free PWAS-EMIS are also discussed with respect to the in-plane mode. Piezoelectric material degradation on certain electrical and mechanical properties as the temperature increases is simulated by our analytical model for in-plane circular PWAS-EMIS that agrees well with the sets of experiments. Then the thickness mode PWAS-EMIS model was further developed for a PWAS resonator bonded on a plate-like structure. The latter analytical model was to determine the resonance frequencies for the normal mode expansion method through the global matrix method by considering PWAS-substrate and proof mass-PWAS-substrate models. The proof mass concept was adapted to shift the systems resonance frequencies in thickness mode. PWAS in contact with liquid medium on one of its surface has been analytically modeled and simulated the electro-mechanical response of PWAS with various liquids with different material properties such as the density and the viscosity. The second part discusses the guided wave propagation

  10. Comparison of measurement methods for microsystem components: application to microstructures made by the deep x-ray lithography process (x-ray LIGA)

    NASA Astrophysics Data System (ADS)

    Meyer, Pascal; Mäder, Olaf; Saile, Volker; Schulz, Joachim

    2009-08-01

    The LIGA (a German acronym for lithography, electroplating and molding) process using highly parallel x-rays permits the production of a microstructure with still unique characteristics: high aspect ratio, high accuracy, high perpendicularity and lower roughness of the side wall. From a marketing point of view, this qualitative description might suffice to attract users to the technology. Regarding widespread commercialization and standardization of x-ray LIGA products, our goal is to establish a rigorous dimensional metrology for which we need to understand and quantify uncertainty, which is the key to accuracy. We report on our metrological study using a coordinate measurement machine (CMM) equipped with a fibre probe (3D measurements) which will be compared to two versions of lateral top-view measurements (2D/surface measurements): an optical microscope provided with a micrometric table and a CMM with an image processing sensor; these two types of measurement methods being complementary. In fact, microsystem technology requires measurements to be performed with precision and accuracy within the range of 0.1 µm. In this paper, we present an analysis and a discussion of both types of measurement systems. The precision and reproducibility of the CMM (with fibre probe) during a two-year study will be exposed; a calibrated series part is being measured every time the machine is used. In this case, the CMM is used as a comparator. Its accuracy and the calibration of the ball diameter using an etalon (ceramic gage block) will be exposed. Furthermore, by taking into account the results obtained by the measurement system analysis (MSA), we will show the measurement's impact on the process by taking as an example the fabrication of mm gold gears for watch industry; a quantitative description of process reproducibility and of the influence of processing parameters influence will be possible in the future.

  11. Wafer-scale integration and two-level pipelined implementations of systolic arrays

    SciTech Connect

    Kung, H.T.; Lam, M.S.

    1984-08-01

    For problems that have been solved exclusively by systolic arrays with feedback cycles, this paper introduces a new class of systolic algorithms based on a ring architecture. These systolic rings have the property that the throughput degrades gracefully as the number of failed cells in the rings increases. Furthermore, as a byproduct of the ring architecture approach, the authors have derived several new systolic algorithms which require only one-third to one-half of the cells used in previous designs while achieving the same throughput. They have shown that the two-level pipelining problem in systolic arrays are solved by the same techniques used to solve the fault-tolerance problem. An important task left for the future is the development of software to solve both problems automatically.

  12. Room-temperature wafer scale bonding using smoothed Au seal ring surfaces for hermetic sealing

    NASA Astrophysics Data System (ADS)

    Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki

    2016-01-01

    We evaluated room-temperature bonding characteristics of electroplated Au surfaces smoothed by the lift-off and imprint methods. As a result, we found that smoothed surfaces enable strong bonding; on the other hand, electroplated rough surfaces result in very weak bonding. In transmission electron microscopy observations, no delamination was observed at the bonding interface bonded at room temperature using a smooth surface prepared by the lift-off method. Moreover, the hermeticity of the bonding interface prepared using smoothed surfaces was evaluated using diaphragm structures. As a result, we confirmed that good hermetic sealing was achieved using the electroplated Au surface smoothed by the lift-off method.

  13. Wafer-scale growth of large arrays of perovskite microplate crystals for functional electronics and optoelectronics

    PubMed Central

    Wang, Gongming; Li, Dehui; Cheng, Hung-Chieh; Li, Yongjia; Chen, Chih-Yen; Yin, Anxiang; Zhao, Zipeng; Lin, Zhaoyang; Wu, Hao; He, Qiyuan; Ding, Mengning; Liu, Yuan; Huang, Yu; Duan, Xiangfeng

    2015-01-01

    Methylammonium lead iodide perovskite has attracted intensive interest for its diverse optoelectronic applications. However, most studies to date have been limited to bulk thin films that are difficult to implement for integrated device arrays because of their incompatibility with typical lithography processes. We report the first patterned growth of regular arrays of perovskite microplate crystals for functional electronics and optoelectronics. We show that large arrays of lead iodide microplates can be grown from an aqueous solution through a seeded growth process and can be further intercalated with methylammonium iodide to produce perovskite crystals. Structural and optical characterizations demonstrate that the resulting materials display excellent crystalline quality and optical properties. We further show that perovskite crystals can be selectively grown on prepatterned electrode arrays to create independently addressable photodetector arrays and functional field effect transistors. The ability to grow perovskite microplates and to precisely place them at specific locations offers a new material platform for the fundamental investigation of the electronic and optical properties of perovskite materials and opens a pathway for integrated electronic and optoelectronic systems. PMID:26601297

  14. Low-dose performance of wafer-scale CMOS-based X-ray detectors

    NASA Astrophysics Data System (ADS)

    Maes, Willem H.; Peters, Inge M.; Smit, Chiel; Kessener, Yves; Bosiers, Jan

    2015-03-01

    Compared to published amorphous-silicon (TFT) based X-ray detectors, crystalline silicon CMOS-based active-pixel detectors exploit the benefits of low noise, high speed, on-chip integration and featuring offered by CMOS technology. This presentation focuses on the specific advantage of high image quality at very low dose levels. The measurement of very low dose performance parameters like Detective Quantum Efficiency (DQE) and Noise Equivalent Dose (NED) is a challenge by itself. Second-order effects like defect pixel behavior, temporal and quantization noise effects, dose measurement accuracy and limitation of the x-ray source settings will influence the measurements at very low dose conditions. Using an analytical model to predict the low dose behavior of a detector from parameters extracted from shot-noise limited dose levels is presented. These models can also provide input for a simulation environment for optimizing the performance of future detectors. In this paper, models for predicting NED and the DQE at very low dose are compared to measurements on different CMOS detectors. Their validity for different sensor and optical stack combinations as well as for different x-ray beam conditions was validated.

  15. Polymer-confined colloidal monolayer: a reusable soft photomask for rapid wafer-scale nanopatterning.

    PubMed

    Fang, Ming; Lin, Hao; Cheung, Ho-Yuen; Xiu, Fei; Shen, Lifan; Yip, SenPo; Pun, Edwin Yue-Bun; Wong, Chun-Yuen; Ho, Johnny C

    2014-12-10

    We demonstrate the repeated utilization of self-assembled colloidal spheres for rapid nanopattern generations. Highly ordered micro-/nanosphere arrays were interlinked and confined by a soft transparent polymer (polydimethylsiloxane, PDMS), which can be used as light-focusing elements/photomasks for area-selective exposures of photoresist in contact. Because of the stiffness of the colloidal spheres, the photomasks do not encounter feature-deformation problems, enabling reliable production of highly uniform patterns over large areas. The geometrical feature of the patterns, including the size, pitch, and even the shape, can be finely tuned by adjusting the mask design and exposure time. The obtained patterns could be used as deposition or etching mask, allowing easy pattern transfer for various applications. PMID:25375239

  16. Heteroepitaxial growth of wafer scale highly oriented graphene using inductively coupled plasma chemical vapor deposition

    NASA Astrophysics Data System (ADS)

    Gao, Libo; Xu, Hai; Li, Linjun; Yang, Yang; Fu, Qiang; Bao, Xinhe; Loh, Kian Ping

    2016-06-01

    The chemical vapor deposition (CVD) of graphene on Cu has attracted much attention because of its industrial scalability. Herein, we report inductively coupled plasma-assisted CVD of epitaxially grown graphene on (111)-textured Cu film alloyed with a small amount of Ni, where large area high quality graphene film can be grown in less than 5 min at 800 °C, thus affording industrial scalability. The epitaxially grown graphene films on (111)-textured Cu contain grains which are predominantly aligned with the Cu lattice and about 10% of 30°-rotated grains (anti-grains). Such graphene films are exclusively monolayer and possess good electrical conductivity, high carrier mobility, and room temperature quantum Hall effect. Magnetoresistance measurements reveal that the reduction of the grain sizes from 150 nm to 50 nm produce increasing Anderson localization and the appearance of a transport gap. Owing to the presence of grain boundaries in these anti-grains, epitaxially grown graphene films possess n-type characteristics and exhibit ultra-high sensitivity to adsorbates.

  17. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Astrophysics Data System (ADS)

    Larkin, David J.; Powell, J. Anthony

    1992-11-01

    A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  18. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Astrophysics Data System (ADS)

    Larkin, David J.; Powell, J. Anthony

    1994-11-01

    This invention is a method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes of vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  19. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Astrophysics Data System (ADS)

    Powell, J. Anthony

    1991-06-01

    This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  20. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Powell, J. Anthony (Inventor)

    1991-01-01

    This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  1. Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

    NASA Technical Reports Server (NTRS)

    Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

    1992-01-01

    A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

  2. Correlation between reticle- and wafer-CD difference of multiple 28nm reticle-sites

    NASA Astrophysics Data System (ADS)

    Ning, Guoxiang; Richter, Frank; Thamm, Thomas; Ackmann, Paul; Staples, Marc; Weisbuch, Francois; Kurth, Karin; Schenker, Joerg; Leschok, Andre; GN, Fang Hong

    2012-11-01

    Reticle critical dimension uniformity (CDU) is an important criterion for the qualification of mask layer processes. Normally, the smaller the three sigma value of reticle CDU is, the better is the reticle CDU performance. For qualification of mask processes, the mask layers to be qualified should have a comparable reticle CDU compared to the process of record (POR) mask layers. Because the reticle critical dimension (CD) measurement is based on algorithms like "middle side lobe measurement", evaluation of the reticle CD-values can not reflect aspects like the sidewall angle of the reticle and variation in corner rounding which may be critical for 45nm technology nodes (and below). All involved tools and processes contribute to the wafer intra-field CDU (scanner, track, reticle, metrology). Normally, the reticle contribution to the wafer CDU should be as small as possible. In order to reduce the process contributions to the wafer intra-field CDU during the mask qualification process, the same toolset (exposure tool, metrology tool) should be applied as for the POR. Out of the results of these investigations the correlation between wafer measurement to target (MTT) and reticle MTT can be obtained in order to accurately qualify the CDU performance of the mask processes. We will demonstrate the correlation between reticle MTT and wafer MTT by use of multiple mask processes and alternative mask blank materials. We will investigate the results of four process-layers looking at advanced binary maskblank material from two different suppliers (moreover the results of a 2X-via layer as an example for a phase-shift maskblank is discussed). Objective of this article is to demonstrate the distribution between reticle MTT and wafer MTT as a qualification criterion for mask processes. The correlation between wafer CD-difference and reticle CD-difference of these mask processes are demonstrated by having performed investigations of dense features of different 28nmtechnology

  3. An aluminum-germanium eutectic structure for silicon wafer bonding technology

    NASA Astrophysics Data System (ADS)

    Perez-Quintana, I.; Ottaviani, G.; Tonini, R.; Felisari, L.; Garavaglia, M.; Oggioni, L.; Morin, D.

    2005-08-01

    An aluminum-germanium eutectic bonding technology has been used to uniformly bond two silicon wafers for MEMS packaging at temperatures as low as 450 °C, well below the aluminum-silicon eutectic temperature (577 °C). A device silicon wafer has been put in contact with a cap wafer where an aluminum film covered by a germanium film has been thermally evaporated. The annealing has been performed in a vacuum furnace under uniaxial pressure variable from 1.8 up to 30 kbar. The samples have been analyzed with various analytical techniques. 4He+ MeV Rutherford Backscattering Spectrometry (RBS) has been used to measure the thicknesses of the deposited films and to follow the aluminum-germanium intermixing, Scanning Acoustic Microscope (SAM) to control the uniformity of the bonding, Scanning Electron Microscope (SEM) associated with electron induced X-ray fluorescence to analyze composition, morphology and elements distribution in the film between the two bonded wafers. The temperatures for the annealing were selected above and below the Ge-Al the eutectic temperature. At temperatures below the eutectic no-bonding has been obtained for any applied pressure. Above the eutectic bonding occurs. The formation of a liquid film is mandatory to obtain a reproducible and robust bonding. The pressure is necessary to improve the contacts between the two wafers; its role in the metallurgy of the bonding needs to be explored.

  4. Minimizing wafer defectivity during high-temperature baking of organic films in 193nm lithography

    NASA Astrophysics Data System (ADS)

    Randall, Mai; Longstaff, Christopher; Ueda, Kenichi; Nicholson, Jim; Winter, Thomas

    2006-03-01

    Demands for continued defect reduction in 300mm IC manufacturing is driving process engineers to examine all aspects of the apply process for improvement. Process engineers, and their respective tool sets, are required to process films at temperatures above the boiling point of the casting solvents. This can potentially lead to the sublimation of the film chemical components. The current methods used to minimize wafer defectivity due to bake residues include frequent cleaning of bake plate modules and surrounding equipment, process optimization, and hardware improvements until more robust chemistries are available. IBM has evaluated the Tokyo Electron CLEAN TRACK TM ACT TM 12 high exhaust high temperature hotplate (HHP) lid to minimize wafer level contamination due to the outgasing of a bottom anti-reflective coating (BARC) films during the high temperature bake process. Goal was to minimize airborne contamination (particles in free space), reduce hotplate contamination build up, and ultimately reduce defects on the wafer. This evaluation was performed on a 193nm BARC material. Evaluation data included visual hardware inspections, airborne particle counting, relative thickness build up measurements on hotplate lids, wafer level defect measurements, and electrical open fail rate. Film coat thickness mean and uniformity were also checked to compare the high exhaust HHP with the standard HHP lid. Chemical analysis of the HHP module residue was performed to identify the source material. The work will quantify potential cost savings achieved by reducing added wafer defects during processing and extending PM frequency for equipment cleaning.

  5. Gated Silicon Drift Detector Fabricated from a Low-Cost Silicon Wafer

    PubMed Central

    Matsuura, Hideharu; Sakurai, Shungo; Oda, Yuya; Fukushima, Shinya; Ishikawa, Shohei; Takeshita, Akinobu; Hidaka, Atsuki

    2015-01-01

    Inexpensive high-resolution silicon (Si) X-ray detectors are required for on-site surveys of traces of hazardous elements in food and soil by measuring the energies and counts of X-ray fluorescence photons radially emitted from these elements. Gated silicon drift detectors (GSDDs) are much cheaper to fabricate than commercial silicon drift detectors (SDDs). However, previous GSDDs were fabricated from 10-kΩ·cm Si wafers, which are more expensive than 2-kΩ·cm Si wafers used in commercial SDDs. To fabricate cheaper portable X-ray fluorescence instruments, we investigate GSDDs formed from 2-kΩ·cm Si wafers. The thicknesses of commercial SDDs are up to 0.5 mm, which can detect photons with energies up to 27 keV, whereas we describe GSDDs that can detect photons with energies of up to 35 keV. We simulate the electric potential distributions in GSDDs with Si thicknesses of 0.5 and 1 mm at a single high reverse bias. GSDDs with one gate pattern using any resistivity Si wafer can work well for changing the reverse bias that is inversely proportional to the resistivity of the Si wafer. PMID:26007742

  6. Lateral Scanning Linnik Interferometry for Large Field of View and Fast Scanning: Wafer Bump Inspection

    NASA Astrophysics Data System (ADS)

    Kim, Min Y.; Veluvolu, Kalyana C.; Lee, Soon-Geul

    2011-07-01

    Wafer-level packaging is currently the major trend in semiconductor packaging for miniaturization and high-density integration. To ensure the package reliability, the wafer and substrate bumps utilized as connection junctions need to be in-line inspected as regards their top-height distribution, coplanarity, and volume uniformity. This article proposes a lateral scanning interferometric system for wafer bump shape inspection in three dimensions with a large field of view and fast inspection speed based on an optomechatronic system design. For multiple-peak interferogram from wafer bumps around a transparent film layer, two-step information extraction algorithms are suggested, including top surface profile and under-layer surface profile detection algorithms. The multiple-peak interferogram is acquired with variations of lateral position of the reference mirror by a piezoelectric transducer (PZT). A series of experiments is performed for representative wafer samples with solder and gold bumps, and the effectiveness of the proposed inspection system is verified from the test results.

  7. Engineering Controlled Spalling in (100)-Oriented GaAs for Wafer Reuse

    SciTech Connect

    Sweet, Cassi A.; McNeely, Joshua E.; Gorman, Brian; Young, David L.; Ptak, Aaron J.; Packard, Corinne E.

    2015-06-14

    Controlled spalling offers a way to cleave thin, single-crystal films or devices from wafers, particularly if the fracture planes in the material are oriented parallel to the wafer surface. Unfortunately, misalignment between the favored fracture planes and the wafer surface preferred for photovoltaic growth in (100)-oriented GaAs produces a highly faceted surface when subject to controlled spalling. This highly faceted cleavage surface is problematic in several ways: (1) it can result in large variations of spall depth due to unstable crack propagation; (2) it may introduce defects into the device zone or underlying substrate; and (3) it consumes many microns of material outside of the device zone. We present the ways in which we have engineered controlled spalling for (100)-oriented GaAs to minimize these effects. We expand the operational window for controlled spalling to avoid spontaneous spalling, find no evidence of dislocation activity in the spalled film or the parent wafer, and reduce facet height and facet height irregularity. Resolving these issues provides a viable path forward for reducing III-V device cost through the controlled spalling of (100)-oriented GaAs devices and subsequent wafer reuse when these processes are combined with a high-throughput growth method such as Hydride Vapor Phase Epitaxy.

  8. Microwave ECR plasma electron flood for low pressure wafer charge neutralization

    NASA Astrophysics Data System (ADS)

    Vanderberg, Bo; Nakatsugawa, Tomoya; Divergilio, William

    2012-11-01

    Modern ion implanters typically use dc arc discharge Plasma Electron Floods (PEFs) to neutralize wafer charge. The arc discharge requires using at least some refractory metal hardware, e.g. a thermionically emitting filament, which can be undesirable in applications where no metallic contamination is critical. rf discharge PEFs have been proposed to mitigate contamination risks but the gas flows required can result in high process chamber pressures. Axcelis has developed a microwave electron cyclotron resonance (ECR) PEF to provide refractory metals contamination-free wafer neutralization with low gas flow requirement. Our PEF uses a custom, reentrant cusp magnet field providing ECR and superior electron confinement. Stable PEF operation with extraction slits sized for 300 mm wafers can be attained at Xe gas flows lower than 0.2 sccm. Electron extraction currents can be as high as 20 mA at absorbed microwave powers < 70 W. On Axcelis' new medium current implanter, plasma generation has proven robust against pressure transients caused by, for example, photoresist outgassing by high power ion beams. Charge monitor and floating potential measurements along the wafer surface corroborate adequate wafer charge neutralization for low energy, high current ion beams.

  9. Automated defect review of the wafer bevel with a defect review scanning electron microscope

    NASA Astrophysics Data System (ADS)

    McGarvey, Steve; Kanezawa, Masakazu

    2009-03-01

    One of the few remaining bastions of non-regulated Integrated Circuit defectivity is the wafer bevel. Recent internal Integrated Circuit Manufacturing studies have suggested that the edge bevel may be responsible for as much as a two to three percent yield loss during a defect excursion on the manufacturing line and a one to two percent yield loss during ongoing wafer manufacturing. A new generation of defect inspection equipment has been introduced to the Research and Development, Integrated Circuit, MEM's and Si wafer manufacturing markets that has imparted the ability for the end equipment user to detect defects located on the bevel of the wafer. The inherent weakness of the current batch of wafer bevel inspection equipment is the lack of automatic discrete defect classification data into multiple, significant classification bins and the lack of discrete elemental analysis data. Root cause analysis is based on minimal discrete defect analysis as a surrogate for a statistically valid sampling of defects from the bevel. This paper provides a study of the methods employed with a Hitachi RS-5500EQEQ Defect Review Scanning Electron Microscope (DRSEM) to automatically capture high resolution/high magnification images and collect elemental analysis on a statistically valid sample of the discrete defects that were located by a bevel inspection system.

  10. Microwave ECR plasma electron flood for low pressure wafer charge neutralization

    SciTech Connect

    Vanderberg, Bo; Nakatsugawa, Tomoya; Divergilio, William

    2012-11-06

    Modern ion implanters typically use dc arc discharge Plasma Electron Floods (PEFs) to neutralize wafer charge. The arc discharge requires using at least some refractory metal hardware, e.g. a thermionically emitting filament, which can be undesirable in applications where no metallic contamination is critical. rf discharge PEFs have been proposed to mitigate contamination risks but the gas flows required can result in high process chamber pressures. Axcelis has developed a microwave electron cyclotron resonance (ECR) PEF to provide refractory metals contamination-free wafer neutralization with low gas flow requirement. Our PEF uses a custom, reentrant cusp magnet field providing ECR and superior electron confinement. Stable PEF operation with extraction slits sized for 300 mm wafers can be attained at Xe gas flows lower than 0.2 sccm. Electron extraction currents can be as high as 20 mA at absorbed microwave powers < 70 W. On Axcelis' new medium current implanter, plasma generation has proven robust against pressure transients caused by, for example, photoresist outgassing by high power ion beams. Charge monitor and floating potential measurements along the wafer surface corroborate adequate wafer charge neutralization for low energy, high current ion beams.

  11. ArF-laser-induced photochemical super mirror-finishing of Si wafer (Abstract Only)

    NASA Astrophysics Data System (ADS)

    Murahara, Masataka M.

    2004-06-01

    Si wafer was polished accurately with ArF laser irradiation in the presence of the hydrofluoric acid water solution. The highest surface accuracy of Si wafer is needed for the Si substrate for using extremely ultra violet (EUV) lithography. Then we tried to polish the SiO2 with hydrofluoric acid water solution, which was photo-oxidized Si wafer surface with active oxygen. The active oxygen was photo-dissociated from water (H2O). The Si wafer surface was pressurized at 50g/cm2 on the fluorocarbon-polishing mat. Next the hydrofluoric acid water solution is infiltrated into the thin gap between the sample and the fluorocarbon. And ArF laser is irradiated through the fluorocarbon turntable. By this irradiation, the Si wafer surface was oxidized and produced SiO2. The moment it is dissolved by HF solution. After the etching, the polishing progresses by the friction with the fluorocarbon. The surface roughness was obtained 3 nm with 30 minute polishing with the ArF laser irradiation (20 mJ/cm2, 100 pps) in 15% HF/H2O ambience.

  12. Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

    NASA Astrophysics Data System (ADS)

    Pa, Pai-Shan

    2010-01-01

    A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

  13. Influence of electrode geometry on the high-field characteristics of photoconductive silicon wafers

    SciTech Connect

    Madangarli, V.P.; Gradinaru, G.; Korony, G.; Sudarshan, T.S.; Loubriel, G.M.; Zutavern, F.J.; Patterson, P.E.

    1994-07-01

    A series of experiment were conducted to study the influence of electrode geometry on the prebreakdown (and breakdown) characteristics of high resistivity ({rho} > 30 k{Omega}-cm), p-type Si wafers under quasi-uniform and non-uniform electric field configurations. In the quasi-uniform field configuration, the 1mm thick Si wafer was mounted between the slots of two plane parallel stainless steel disc electrodes (parallel), while the non-uniform field was obtained by mounting the wafer between two pillar-type electrodes with a hemispherical tip (pillar). The main objective of the above investigation was to verify if the uniform field configuration under a parallel system has a positive influence by reducing the field enhancement at the contact region, as opposed to the definite field enhancement present in the case of the non-uniform pillar system. Also, it was proposed to study the effect of the contact profile on the field distribution over the wafer surface and hence its influence on the high-field performance of the Si wafers.

  14. Wafer bonding technology for new generation vacuum MEMS: challenges and promises

    NASA Astrophysics Data System (ADS)

    Dragoi, V.; Pabo, E.

    2015-05-01

    Various MEMS devices are incorporated into consumer electronic devices. A particular category of MEMS require vacuum packaging by wafer bonding with the need to encapsulate vacuum levels of 10-2 mbar or higher with long time stability. The vacuum requirement is limiting the choice of the wafer bonding process and raises significant challenges to the existing investigation methods (metrology) used for results qualification. From the broad range of wafer bonding processes only few are compatible with vacuum applications: fusion bonding, anodic bonding, glass frit bonding and metal-based bonding. The outgassing from the enclosed surfaces after bonding will affect the vacuum level in the cavity: in some cases, a getter material is used inside the device cavity to compensate for this outgassing. Additionally the selected bonding process must be compatible with the devices on the wafers being bonded. This work reviews the principles of vacuum encapsulation using wafer bonding. Examples showing the suitability of each process for specific applications types will be presented. A significant challenge in vacuum MEMS fabrication is the lack of analytical methods needed for process characterization or reliability testing. A short overview of the most used methods and their limitations will be presented. Specific needs to be addressed will be introduced with examples.

  15. Calibration of Radiation Thermometers in Rapid Thermal Processing Tools Using Si Wafers with Thin-film Thermocouples

    NASA Astrophysics Data System (ADS)

    Kreider, K. G.; Kimes, W. A.; Meyer, C. W.; Ripple, D. C.; Tsai, B. K.; Chen, D. H.; DeWitt, D. P.

    2003-09-01

    Rapid thermal processing (RTP) tools are currently monitored and controlled with lightpipe radiation thermometers (LPRTs) which have been calibrated with thermocouple instrumented wafers. We have developed a thin-film thermocouple wafer that enables more accurate calibration of the LPRTs. The NIST thin-film thermocouple calibration wafer uses Pt/Pd wire thermocouples welded to thin-film Rh/Pt thermocouples to reduce the uncertainty of the wafer temperature measurement in situ. We present the results of testing these thin-film thermocouple calibration wafers in the NIST RTP test bed at temperatures ranging from 650 °C to 830 °C together with a discussion of the materials limitations and capabilities. The difference between the thermocouple junction temperatures and the radiance temperatures indicated by the blackbody-calibrated LPRT can be attributed to the effective emissivity of the wafer, the parameter that accounts for the geometry and radiative properties of the wafer-chamber configuration. An analysis of the uncertainty, u = 1.3 K (k =1), of the wafer surface temperature measurements in the NIST RTP test bed is presented. Confirmation of this value was partially hampered by thermal gradients in the chamber and some problems with the weld pads at high temperature. In addition, we discuss the determination of the Seebeck coefficient of the thin-film thermocouples used on the wafers.

  16. Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

    PubMed

    Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

    2015-11-01

    Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group.

  17. Effect of MeV nitrogen ion implantation on the resistivity transition in Czochralski silicon wafers

    NASA Astrophysics Data System (ADS)

    Moon, Byeong-Sam; Lee, In-Ji; Park, Jea-Gun

    2012-12-01

    We investigated how MeV nitrogen ion implantation affects the resistivity transition in Czochralski (CZ) silicon wafers. After annealing at 800 °C for 20 h and again at 1000 °C for 10 h, the implanted nitrogen atoms accumulated in the projected range (R P ) for ion doses less than 5 × 1014 cm-2 whereas they accumulated at both R P /2 and R P at ion doses above 3 × 1015 cm-2. These results indicate that no resistivity transition was found at nitrogen ion doses less than 5 × 1013 cm-2 whereas n-/p or n+/p resistivity transition was shown at ion doses higher than 5 × 1014 cm-2. Many fewer than 1% of the implanted nitrogen atoms were ionized after the heat treatment. Thus, the resistivity of nitrogen-doped silicon wafers is more than 100 times higher than that of phosphorous-doped silicon wafers.

  18. Radiation thermometry of silicon wafers based on emissivity-invariant condition.

    PubMed

    Iuchi, Tohru; Seo, Tomohiro

    2011-01-20

    An emissivity-invariant condition for a silicon wafer was determined by simulation modeling and it was confirmed experimentally. The p-polarized spectral emissivity at a wavelength of 900 nm and at temperatures over 900 K was constant at 0.83 at an angle of about 55.4° irrespective of large variations in the oxide layer thickness and the resistivity due to the different impurity doping concentrations of the silicon wafer. The expanded uncertainty, U(c) = ku(c) (k = 2), of the temperature measurement is estimated to be 4.9 K. This result is expected to significantly enhance the accuracy of radiometric temperature measurements of silicon wafers in actual manufacturing processes.

  19. Fourier Transform Infrared Spectroscopy of Low-k Dielectric Material on Patterned Wafers

    NASA Astrophysics Data System (ADS)

    Lam, Jeffrey Chorkeung; Tan, Hao; Huang, Maggie Yamin; Zhang, Fan; Sun, Handong; Shen, Zexiang; Mai, Zhihong

    2012-11-01

    With many of research on Fourier transform IR (FTIR) on low-k materials, our experiments extended the FTIR spectroscopy application to characterization and analysis of the low-k dielectric thin film properties on patterned wafers. FTIR spectra on low-k materials were successfully captured under three sampling modes: reflection, attenuated total reflectance (ATR), and mapping mode. ATR mode is more suitable for CHx band than reflection mode due to its higher sensitivity in this range. FTIR spectroscopy signal analysis on mixed structures (metal and low-k dielectric material) on patterned wafers was also investigated with mapping mode. Based on our investigation, FTIR can be used for low-k material studies on patterned wafer.

  20. Synchronous control strategy of wafer and reticle stage of step and scan lithography

    NASA Astrophysics Data System (ADS)

    Li, Lanlan; Hu, Song; Zhao, Lixin; Ma, Ping

    2012-10-01

    For step and scan lithography systems, the synchronization of reticle stage and wafer stage during exposure is one of the most important factors that decides the image quality. In this paper, their principle is analyzed through investigating the structure of step and scan lithography systems. And the coarse and fine laminated model is built. Based on this model, three different kinds of synchronous control structures containing parallel, series and cross-coupled are proposed. Then, the reticle stage is used to compensate the error of the synchronous control system of wafer and reticle stage. Simulation results demonstrate that this control strategy has good synchronization performance, and the synchronous error of wafer stage and reticle stage is less than 0.5nm without disturbance.