Packaged integrated opto-fluidic solution for harmful fluid analysis

NASA Astrophysics Data System (ADS)

Allenet, T.; Bucci, D.; Geoffray, F.; Canto, F.; Couston, L.; Jardinier, E.; Broquin, J.-E.

2016-02-01

Advances in nuclear fuel reprocessing have led to a surging need for novel chemical analysis tools. In this paper, we present a packaged lab-on-chip approach with co-integration of optical and micro-fluidic functions on a glass substrate as a solution. A chip was built and packaged to obtain light/fluid interaction in order for the entire device to make spectral measurements using the photo spectroscopy absorption principle. The interaction between the analyte solution and light takes place at the boundary between a waveguide and a fluid micro-channel thanks to the evanescent part of the waveguide's guided mode that propagates into the fluid. The waveguide was obtained via ion exchange on a glass wafer. The input and the output of the waveguides were pigtailed with standard single mode optical fibers. The micro-scale fluid channel was elaborated with a lithography procedure and hydrofluoric acid wet etching resulting in a 150+/-8 μm deep channel. The channel was designed with fluidic accesses, in order for the chip to be compatible with commercial fluidic interfaces/chip mounts. This allows for analyte fluid in external capillaries to be pumped into the device through micro-pipes, hence resulting in a fully packaged chip. In order to produce this co-integrated structure, two substrates were bonded. A study of direct glass wafer-to-wafer molecular bonding was carried-out to improve detector sturdiness and durability and put forward a bonding protocol with a bonding surface energy of γ>2.0 J.m-2. Detector viability was shown by obtaining optical mode measurements and detecting traces of 1.2 M neodymium (Nd) solute in 12+/-1 μL of 0.01 M and pH 2 nitric acid (HNO3) solvent by obtaining an absorption peak specific to neodymium at 795 nm.

New optoelectronic methodology for nondestructive evaluation of MEMS at the wafer level

NASA Astrophysics Data System (ADS)

Furlong, Cosme; Ferguson, Curtis F.; Melson, Michael J.

2004-02-01

One of the approaches to fabrication of MEMS involves surface micromachining to define dies on single crystal silicon wafers, dicing of the wafers to separate the dies, and electronic packaging of the individual dies. Dicing and packaging of MEMS accounts for a large fraction of the fabrication costs, therefore, nondestructive evaluation at the wafer level, before dicing, can have significant implications on improving production yield and costs. In this paper, advances in development of optoelectronic holography (OEH) techniques for nondestructive, noninvasive, full-field of view evaluation of MEMS at the wafer level are described. With OEH techniques, quantitative measurements of shape and deformation of MEMS, as related to their performance and integrity, are obtained with sub-micrometer spatial resolution and nanometer measuring accuracy. To inspect an entire wafer with OEH methodologies, measurements of overlapping regions of interest (ROI) on a wafer are recorded and adjacent ROIs are stitched together through efficient 3D correlation analysis algorithms. Capabilities of the OEH techniques are illustrated with representative applications, including determination of optimal inspection conditions to minimize inspection time while achieving sufficient levels of accuracy and resolution.

(abstract) Electronic Packaging for Microspacecraft Applications

NASA Technical Reports Server (NTRS)

Wasler, David

1993-01-01

The intent of this presentation is to give a brief look into the future of electronic packaging for microspacecraft applications. Advancements in electronic packaging technology areas have developed to the point where a system engineer's visions, concepts, and requirements for a microspacecraft can now be a reality. These new developments are ideal candidates for microspacecraft applications. These technologies are capable of bringing about major changes in how we design future spacecraft while taking advantage of the benefits due to size, weight, power, performance, reliability , and cost. This presentation will also cover some advantages and limitations of surface mount technology (SMT), multichip modules (MCM), and wafer scale integration (WSI), and what is needed to implement these technologies into microspacecraft.

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

NASA Astrophysics Data System (ADS)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

PubMed

Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

2015-12-16

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

PubMed Central

Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

2015-01-01

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction. PMID:26694407

Optical Forces Near Microfabricated Devices

DTIC Science & Technology

2013-08-01

one beam for two power levels , 50mW and 100mW. 50 µm corresponds to the center of the channel...available MIT MEEP package (32). The computational resolution is 32 grid points per lattice constant. Fig 2.2(a) shows the normalized transmission through...a silicon-on-insulator wafer using standard techniques (33). The lattice constant of the photonic crystal can be scaled to place a given guided

Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress

NASA Astrophysics Data System (ADS)

Chen, Po-Ying; Kung, Heng-Yu; Lai, Yi-Shao; Hsiung Tsai, Ming; Yeh, Wen-Kuan

2008-02-01

In this work, we present a novel approach and method for elucidating the characteristics of wafer-level chip-scale packages (WLCSPs) for electromigration (EM) tests. The die in WLCSP was directly attached to the substrate via a soldered interconnect. The shrinking of the area of the die that is available for power, and the solder bump also shrinks the volume and increases the density of electrons for interconnect efficiency. The bump current density now approaches to 106 A/cm2, at which point the EM becomes a significant reliability issue. As known, the EM failure depends on numerous factors, including the working temperature and the under bump metallization (UBM) thickness. A new interconnection geometry is adopted extensively with moderate success in overcoming larger mismatches between the displacements of components during current and temperature changes. Both environments and testing parameters for WLCSP are increasingly demanded. Although failure mechanisms are considered to have been eliminated or at least made manageable, new package technologies are again challenging its process, integrity and reliability. WLCSP technology was developed to eliminate the need for encapsulation to ensure compatibility with smart-mount technology (SMT). The package has good handing properties but is now facing serious reliability problems. In this work, we investigated the reliability of a WLCSP subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 °C. A very strong correlation exists between the mean time to failure (MTTF) of the WLCSP test vehicle and the mean current density that is carried by a solder joint. A series of current densities were applied to the WLCSP architecture; Black's power law was employed in a failure mode simulation. Additionally, scanning electron microscopy (SEM) was adopted to determine the differences existing between high- and low-current-density failure modes.

A High-Q Resonant Pressure Microsensor with Through-Glass Electrical Interconnections Based on Wafer-Level MEMS Vacuum Packaging

PubMed Central

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-01-01

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in “H” type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than −0.01% F.S/°C in the range of −40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S. PMID:25521385

A high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging.

PubMed

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-12-16

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in "H" type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than -0.01% F.S/°C in the range of -40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S.

Imaging ATUM ultrathin section libraries with WaferMapper: a multi-scale approach to EM reconstruction of neural circuits

PubMed Central

Hayworth, Kenneth J.; Morgan, Josh L.; Schalek, Richard; Berger, Daniel R.; Hildebrand, David G. C.; Lichtman, Jeff W.

2014-01-01

The automated tape-collecting ultramicrotome (ATUM) makes it possible to collect large numbers of ultrathin sections quickly—the equivalent of a petabyte of high resolution images each day. However, even high throughput image acquisition strategies generate images far more slowly (at present ~1 terabyte per day). We therefore developed WaferMapper, a software package that takes a multi-resolution approach to mapping and imaging select regions within a library of ultrathin sections. This automated method selects and directs imaging of corresponding regions within each section of an ultrathin section library (UTSL) that may contain many thousands of sections. Using WaferMapper, it is possible to map thousands of tissue sections at low resolution and target multiple points of interest for high resolution imaging based on anatomical landmarks. The program can also be used to expand previously imaged regions, acquire data under different imaging conditions, or re-image after additional tissue treatments. PMID:25018701

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Application of Au-Sn eutectic bonding in hermetic radio-frequency microelectromechanical system wafer level packaging

NASA Astrophysics Data System (ADS)

Wang, Qian; Choa, Sung-Hoon; Kim, Woonbae; Hwang, Junsik; Ham, Sukjin; Moon, Changyoul

2006-03-01

Development of packaging is one of the critical issues toward realizing commercialization of radio-frequency-microelectromechanical system (RF-MEMS) devices. The RF-MEMS package should be designed to have small size, hermetic protection, good RF performance, and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low-temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at temperatures below 300°C is used. Au-Sn multilayer metallization with a square loop of 70 µm in width is performed. The electrical feed-through is achieved by the vertical through-hole via filling with electroplated Cu. The size of the MEMS package is 1 mm × 1 mm × 700 µm. The shear strength and hermeticity of the package satisfies the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.

Wafer-level hermetic vacuum packaging by bonding with a copper-tin thin film sealing ring

NASA Astrophysics Data System (ADS)

Akashi, Teruhisa; Funabashi, Hirofumi; Takagi, Hideki; Omura, Yoshiteru; Hata, Yoshiyuki

2018-04-01

A wafer-level hermetic vacuum packaging technology intended for use with MEMS devices was developed based on a copper-tin (CuSn) thin film sealing ring. To allow hermetic packaging, the shear strength of the CuSn thin film bond was improved by optimizing the pretreatment conditions. As a result, an average shear strength of 72.3 MPa was obtained and a cavity that had been hermetically sealed using wafer-level packaging (WLP) maintained its vacuum for 1.84 years. The total pressures in the cavities and the partial pressures of residual gases were directly determined with an ultra-low outgassing residual gas analyzer (RGA) system. Hermeticity was evaluated based on helium leak rates, which were calculated from helium pressures determined with the RGA system. The resulting data showed that a vacuum cavity following 1.84 years storage had a total pressure of 83.1 Pa, contained argon as the main residual gas and exhibited a helium leak rate as low as 1.67  ×  10-17 Pa · m3 s-1, corresponding to an air leak rate of 6.19  ×  10-18 Pa · m3 s-1. The RGA data demonstrate that WLP using a CuSn thin film sealing ring permits ultra-high hermeticity in conjunction with long-term vacuum packaging that is applicable to MEMS devices.

Scaling of Fiber Laser Systems Based on Novel Components and High Power Capable Packaging and Joining Technologies

DTIC Science & Technology

2010-09-01

l ri Laser Splicing / Welding r li i / l i Contact Bonding t t i Wafer Level Bonding Mineralic, Fusion . Anodic, Eutectic, Glass-frit, liquid...28-29 September 2010 SET-171 Mid-IR Fiber Laser Workshop partly sponsored by Tapering and splicing device as well as process control developed...Components Laser based splicing and tapering Multimode fiber (ø720µm) with spliced end cap (ø1500µm) © Fraunhofer IOF 28-29 September 2010 SET-171 Mid-IR

Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell#

PubMed Central

Poghossian, Arshak; Schumacher, Kerstin; Kloock, Joachim P.; Rosenkranz, Christian; Schultze, Joachim W.; Müller-Veggian, Mattea; Schöning, Michael J.

2006-01-01

A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor) is realised by means of integration of a specifically designed capillary electrochemical micro-droplet cell into a commercial wafer prober-station. The developed system allows the identification and selection of “good” ISFETs at the earliest stage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. The developed system is also feasible for wafer-level characterisation of ISFETs in terms of sensitivity, hysteresis and response time. Additionally, the system might be also utilised for wafer-level testing of further electrochemical sensors.

Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

NASA Astrophysics Data System (ADS)

Aggarwal, Ankur

With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is developed to address the IC packaging requirements beyond the ITRS projections and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. Nano-structured interconnects provides the ability to assemble the packaged parts on the system board without the use of underfill materials and to enable advanced analog/digital testing, reliability testing, and burn-in at wafer level. This thesis investigates the electrical and mechanical performance of nanostructured interconnections through modeling and test vehicle fabrication. The analytical models evaluate the performance improvements over solder and compliant interconnections. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.

Fabricating a Microcomputer on a Single Silicon Wafer

NASA Technical Reports Server (NTRS)

Evanchuk, V. L.

1983-01-01

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

3D interconnect metrology in CMS/ITRI

NASA Astrophysics Data System (ADS)

Ku, Y. S.; Shyu, D. M.; Hsu, W. T.; Chang, P. Y.; Chen, Y. C.; Pang, H. L.

2011-05-01

Semiconductor device packaging technology is rapidly advancing, in response to the demand for thinner and smaller electronic devices. Three-dimensional chip/wafer stacking that uses through-silicon vias (TSV) is a key technical focus area, and the continuous development of this novel technology has created a need for non-contact characterization. Many of these challenges are novel to the industry due to the relatively large variety of via sizes and density, and new processes such as wafer thinning and stacked wafer bonding. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at EOL/ITRI. While there is a variety of metrology and inspection applications for 3D interconnect processing, the main topics covered here are via CD/depth measurement, thinned wafer inspection and wafer warpage measurement.

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

NASA Astrophysics Data System (ADS)

Mieda, Eiko; Maeda, Tatsuro; Miyata, Noriyuki; Yasuda, Tetsuji; Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki; Aoki, Takeshi; Yamamoto, Taketsugu; Ichikawa, Osamu; Osada, Takenori; Hata, Masahiko; Ogawa, Arito; Kikuchi, Toshiyuki; Kunii, Yasuo

2015-03-01

We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

A Fully Integrated Quartz MEMS VHF TCXO.

PubMed

Kubena, Randall L; Stratton, Frederic P; Nguyen, Hung D; Kirby, Deborah J; Chang, David T; Joyce, Richard J; Yong, Yook-Kong; Garstecki, Jeffrey F; Cross, Matthew D; Seman, S E

2018-06-01

We report on a 32-MHz quartz temperature compensated crystal oscillator (TCXO) fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate, thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ±0.2 parts per million over temperature using on-chip third-order compensation circuitry. The TCXO operates at low power of 2.5 mW and can be thinned to as part of the wafer-level eutectic encapsulation. Full integration with large state-of-the-art CMOS wafers is possible using carrier wafer techniques.

LTCC interconnects in microsystems

NASA Astrophysics Data System (ADS)

Rusu, Cristina; Persson, Katrin; Ottosson, Britta; Billger, Dag

2006-06-01

Different microelectromechanical system (MEMS) packaging strategies towards high packaging density of MEMS devices and lower expenditure exist both in the market and in research. For example, electrical interconnections and low stress wafer level packaging are essential for improving device performance. Hybrid integration of low temperature co-fired ceramics (LTCC) with Si can be a way for an easier packaging system with integrated electrical interconnection, and as well towards lower costs. Our research on LTCC-Si integration is reported in this paper.

A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging.

PubMed

Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

2015-09-21

This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

PubMed Central

Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

2015-01-01

This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%. PMID:26402679

Nonlinear conductivity in silicon nitride

NASA Astrophysics Data System (ADS)

Tuncer, Enis

2017-08-01

To better comprehend electrical silicon-package interaction in high voltage applications requires full characterization of the electrical properties of dielectric materials employed in wafer and package level design. Not only the packaging but wafer level dielectrics, i.e. passivation layers, would experience high electric fields generated by the voltage applied pads. In addition the interface between the passivation layer and a mold compound might develop space charge because of the mismatch in electrical properties of the materials. In this contribution electrical properties of a thin silicon nitride (Si3N4) dielectric is reported as a function of temperature and electric field. The measured values later analyzed using different temperature dependent exponential expressions and found that the Mott variable range hopping conduction model was successful to express the data. A full temperature/electric field dependency of conductivity is generated. It was found that the conduction in Si3N4 could be expressed like a field ionization or Fowler-Nordheim mechanism.

Packaging of MEMS/MOEMS and nanodevices: reliability, testing, and characterization aspects

NASA Astrophysics Data System (ADS)

Tekin, Tolga; Ngo, Ha-Duong; Wittler, Olaf; Bouhlal, Bouchaib; Lang, Klaus-Dieter

2011-02-01

The last decade witnessed an explosive growth in research and development efforts devoted to MEMS devices and packaging. The successfully developed MEMS devices are, for example inkjet, pressure sensors, silicon microphones, accelerometers, gyroscopes, MOEMS, micro fuel cells and emerging MEMS. For the next decade, MEMS/MOEMS and nanodevice based products will penetrate into IT, telecommunications, automotive, defense, life sciences, medical and implantable applications. Forecasts say the MEMS market to be $14 billion by 2012. The packaging cost of MEMS/MOEMS products in general is about 70 percent. Unlike today's electronics IC packaging, their packaging are custom-built and difficult due to the moving structural elements. In order for the moving elements of a MEMS device to move effectively in a well-controlled atmosphere, hermetic sealing of the MEMS device in a cap is necessary. For some MEMS devices, such as resonators and gyroscopes, vacuum packaging is required. Usually, the cap is processed at the wafer level, and thus MEMS packaging is truly a wafer level packaging. In terms of MEMS/MOEMS and nanodevice packaging, there are still many critical issues need to be addressed due to the increasing integration density supported by 3D heterogeneous integration of multi-physic components/layers consisting of photonics, electronics, rf, plasmonics, and wireless. The infrastructure of MEMS/MOEMS and nanodevices and their packaging is not well established yet. Generic packaging platform technologies are not available. Some of critical issues have been studied intensively in the last years. In this paper we will discuss about processes, reliability, testing and characterization of MEMS/MOEMS and nanodevice packaging.

MEMS for Practical Applications

NASA Astrophysics Data System (ADS)

Esashi, Masayoshi

Silicon MEMS as electrostatically levitated rotational gyroscopes and 2D optical scanners, and wafer level packaged devices as integrated capacitive pressure sensors and MEMS switches are described. MEMS which use non-silicon materials as LTCC with electrical feedthrough, SiC and LiNbO3 for probe cards for wafer-level burn-in test, molds for glass press molding and SAW wireless passive sensors respectively are also described.

Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

NASA Astrophysics Data System (ADS)

Sokolovskij, R.; Liu, P.; van Zeijl, H. W.; Mimoun, B.; Zhang, G. Q.

2015-05-01

Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies.

Alternative Packaging for Back-Illuminated Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2009-01-01

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

High-Q Wafer Level Package Based on Modified Tri-Layer Anodic Bonding and High Performance Getter and Its Evaluation for Micro Resonant Pressure Sensor.

PubMed

Wang, Liying; Du, Xiaohui; Wang, Lingyun; Xu, Zhanhao; Zhang, Chenying; Gu, Dandan

2017-03-16

In order to achieve and maintain a high quality factor (high-Q) for the micro resonant pressure sensor, this paper presents a new wafer level package by adopting cross-layer anodic bonding technique of the glass/silicon/silica (GSS) stackable structure and integrated Ti getter. A double-layer structure similar to a silicon-on-insulator (SOI) wafer is formed after the resonant layer and the pressure-sensitive layer are bonded by silicon direct bonding (SDB). In order to form good bonding quality between the pressure-sensitive layer and the glass cap layer, the cross-layer anodic bonding technique is proposed for vacuum package by sputtering Aluminum (Al) on the combination wafer of the pressure-sensitive layer and the resonant layer to achieve electrical interconnection. The model and the bonding effect of this technique are discussed. In addition, in order to enhance the performance of titanium (Ti) getter, the prepared and activation parameters of Ti getter under different sputtering conditions are optimized and discussed. Based on the optimized results, the Ti getter (thickness of 300 nm to 500 nm) is also deposited on the inside of the glass groove by magnetron sputtering to maintain stable quality factor (Q). The Q test of the built testing system shows that the number of resonators with a Q value of more than 10,000 accounts for more than 73% of the total. With an interval of 1.5 years, the Q value of the samples remains almost constant. It proves the proposed cross-layer anodic bonding and getter technique can realize high-Q resonant structure for long-term stable operation.

11.72-sq cm Active-Area Wafer Interconnected PiN Diode Pulsed at 64 kA Dissipates 382 J and Exhibits an Action of 1.7 MA(sup 2)-s

DTIC Science & Technology

2012-01-30

calculated action exceeded 1.7 MA2 -s. Preliminary efforts on high voltage diode interconnection have produced quarter wafer interconnected PiN...was packaged in a “hockey-puck” configuration and pulsed to 64 kA, dissipating 382 J with a calculated action exceeding 1.7 MA2 -s. II. FULL...epitaxial layers are utilized. 11.72-cm2 Active-area Wafer Interconnected PiN Diode pulsed at 64 kA dissipates 382 J and exhibits an action of 1.7 MA2 -s

Qualification and Reliability for MEMS and IC Packages

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

2004-01-01

Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface

Wafer-Level Hermetic Package by Low-Temperature Cu/Sn TLP Bonding with Optimized Sn Thickness

NASA Astrophysics Data System (ADS)

Wu, Zijian; Cai, Jian; Wang, Qian; Wang, Junqiang; Wang, Dejun

2017-10-01

In this paper, a wafer-level package with hermetic sealing by low-temperature Cu/Sn transient liquid phase (TLP) bonding for a micro-electromechanical system was introduced. A Cu bump with a Sn cap and sealing ring were fabricated simultaneously by electroplating. The model of Cu/Sn TLP bonding was established and the thicknesses of Cu and Sn were optimized after a series of bonding experiments. Cu/Sn wafer-level bonding was undertaken at 260°C for 30 min under a vacuum condition. An average shear strength of 50.36 MPa and a fine leak rate of 1.9 × 10-8 atm cc/s were achieved. Scanning electron microscope photos of the Cu/Sn/Cu interlayers were presented, and energy dispersive x-ray analysis was conducted simultaneously. The results showed that the Sn was completely consumed to form the stable intermetallic compound Cu3Sn. An aging test of 200 h at 200°C was conducted to test the performance of the hermetic sealing, while the results of shear strength, fine leak rate and bonding interface were also set out.

The Imaging Properties of a Silicon Wafer X-Ray Telescope

NASA Technical Reports Server (NTRS)

Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

1994-01-01

Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

Wafer-level radiometric performance testing of uncooled microbolometer arrays

NASA Astrophysics Data System (ADS)

Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

2014-03-01

A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

High voltage photo-switch package module having encapsulation with profiled metallized concavities

DOEpatents

Sullivan, James S; Sanders, David M; Hawkins, Steven A; Sampayan, Stephen A

2015-05-05

A photo-conductive switch package module having a photo-conductive substrate or wafer with opposing electrode-interface surfaces metalized with first metallic layers formed thereon, and encapsulated with a dielectric encapsulation material such as for example epoxy. The first metallic layers are exposed through the encapsulation via encapsulation concavities which have a known contour profile, such as a Rogowski edge profile. Second metallic layers are then formed to line the concavities and come in contact with the first metal layer, to form profiled and metalized encapsulation concavities which mitigate enhancement points at the edges of electrodes matingly seated in the concavities. One or more optical waveguides may also be bonded to the substrate for coupling light into the photo-conductive wafer, with the encapsulation also encapsulating the waveguides.

Output blue light evaluation for phosphor based smart white LED wafer level packages.

PubMed

Kolahdouz, Zahra; Rostamian, Ali; Kolahdouz, Mohammadreza; Ma, Teng; van Zeijl, Henk; Zhang, Kouchi

2016-02-22

This study presents a blue light detector for evaluating the output light of phosphor based white LED package. It is composed of a silicon stripe-shaped photodiode designed and implemented in a 2 μm BiCMOS process which can be used for wafer level integration of different passive and active devices all in just 5 lithography steps. The final device shows a high selectivity to blue light. The maximum responsivity at 480 nm is matched with the target blue LED illumination. The designed structure have better responsivity compared to simple photodiode structure due to reducing the effect of dead layer formation close to the surface because of implantation. It has also a two-fold increase in the responsivity and quantum efficiency compared to previously similar published sensors.

Maskless wafer-level microfabrication of optical penetrating neural arrays out of soda-lime glass: Utah Optrode Array.

PubMed

Boutte, Ronald W; Blair, Steve

2016-12-01

Borrowing from the wafer-level fabrication techniques of the Utah Electrode Array, an optical array capable of delivering light for neural optogenetic studies is presented in this paper: the Utah Optrode Array. Utah Optrode Arrays are micromachined out of sheet soda-lime-silica glass using standard backend processes of the semiconductor and microelectronics packaging industries such as precision diamond grinding and wet etching. 9 × 9 arrays with 1100μ m × 100μ m optrodes and a 500μ m back-plane are repeatably reproduced on 2i n wafers 169 arrays at a time. This paper describes the steps and some of the common errors of optrode fabrication.

MEMS for vibration energy harvesting

NASA Astrophysics Data System (ADS)

Li, Lin; Zhang, Yangjian; San, Haisheng; Guo, Yinbiao; Chen, Xuyuan

2008-03-01

In this paper, a capacitive vibration-to-electrical energy harvester was designed. An integrated process flow for fabricating the designed capacitive harvester is presented. For overcoming the disadvantage of depending on external power source in capacitive energy harvester, two parallel electrodes with different work functions are used as the two electrodes of the capacitor to generate a build-in voltage for initially charging the capacitor. The device is a sandwich structure of silicon layer in two glass layers with area of about 1 cm2. The silicon structure is fabricated by using silicon-on-insulator (SOI) wafer. The glass wafers are anodic bonded on to both sides of the SOI wafer to create a vacuum sealed package.

Micro/nano electro mechanical systems for practical applications

NASA Astrophysics Data System (ADS)

Esashi, Masayoshi

2009-09-01

Silicon MEMS as electrostatically levitated rotational gyroscope, 2D optical scanner and wafer level packaged devices as integrated capacitive pressure sensor and MEMS switch are described. MEMS which use non-silicon materials as diamond, PZT, conductive polymer, CNT (carbon nano tube), LTCC with electrical feedthrough, SiC (silicon carbide) and LiNbO3 for multi-probe data storage, multi-column electron beam lithography system, probe card for wafer-level burn-in test, mould for glass press moulding and SAW wireless passive sensor respectively are also described.

First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

NASA Technical Reports Server (NTRS)

Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.;

Warpage Measurement of Thin Wafers by Reflectometry

NASA Astrophysics Data System (ADS)

Ng, Chi Seng; Asundi, Anand Krishna

To cope with advances in the electronic and portable devices, electronic packaging industries have employed thinner and larger wafers to produce thinner packages/ electronic devices. As the thickness of the wafer decrease (below 250um), there is an increased tendency for it to warp. Large stresses are induced during manufacturing processes, particularly during backside metal deposition. The wafers bend due to these stresses. Warpage results from the residual stress will affect subsequent manufacturing processes. For example, warpage due to this residual stresses lead to crack dies during singulation process which will severely reorient the residual stress distributions, thus, weakening the mechanical and electrical properties of the singulated die. It is impossible to completely prevent the residual stress induced on thin wafers during the manufacturing processes. Monitoring of curvature/flatness is thus necessary to ensure reliability of device and its uses. A simple whole-field curvature measurement system using a novel computer aided phase shift reflection grating method has been developed and this project aims to take it to the next step for residual stress and full field surface shape measurement. The system was developed from our earlier works on Computer Aided Moiré Methods and Novel Techniques in Reflection Moiré, Experimental Mechanics (1994) in which novel structured light approach was shown for surface slope and curvature measurement. This method uses similar technology but coupled with a novel phase shift system to accurately measure slope and curvature. In this study, slope of the surface were obtain using the versatility of computer aided reflection grating method to manipulate and generate gratings in two orthogonal directions. The curvature and stress can be evaluated by performing a single order differentiation on slope data.

Die singulation method and package formed thereby

DOEpatents

Anderson, Robert C [Tucson, AZ; Shul, Randy J [Albuquerque, NM; Clews, Peggy J [Tijeras, NM; Baker, Michael S [Albuquerque, NM; De Boer, Maarten P [Albuquerque, NM

2012-08-07

A method is disclosed for singulating die from a substrate having a sacrificial layer and one or more device layers, with a retainer being formed in the device layer(s) and anchored to the substrate. Deep Reactive Ion Etching (DRIE) etching of a trench through the substrate from the bottom side defines a shape for each die. A handle wafer is then attached to the bottom side of the substrate, and the sacrificial layer is etched to singulate the die and to form a frame from the retainer and the substrate. The frame and handle wafer, which retain the singulated die in place, can be attached together with a clamp or a clip and to form a package for the singulated die. One or more stops can be formed from the device layer(s) to limit a sliding motion of the singulated die.

Quantitative phase measurement for wafer-level optics

NASA Astrophysics Data System (ADS)

Qu, Weijuan; Wen, Yongfu; Wang, Zhaomin; Yang, Fang; Huang, Lei; Zuo, Chao

2015-07-01

Wafer-level-optics now is widely used in smart phone camera, mobile video conferencing or in medical equipment that require tiny cameras. Extracting quantitative phase information has received increased interest in order to quantify the quality of manufactured wafer-level-optics, detect defective devices before packaging, and provide feedback for manufacturing process control, all at the wafer-level for high-throughput microfabrication. We demonstrate two phase imaging methods, digital holographic microscopy (DHM) and Transport-of-Intensity Equation (TIE) to measure the phase of the wafer-level lenses. DHM is a laser-based interferometric method based on interference of two wavefronts. It can perform a phase measurement in a single shot. While a minimum of two measurements of the spatial intensity of the optical wave in closely spaced planes perpendicular to the direction of propagation are needed to do the direct phase retrieval by solving a second-order differential equation, i.e., with a non-iterative deterministic algorithm from intensity measurements using the Transport-of-Intensity Equation (TIE). But TIE is a non-interferometric method, thus can be applied to partial-coherence light. We demonstrated the capability and disability for the two phase measurement methods for wafer-level optics inspection.

Wafer scale oblique angle plasma etching

DOEpatents

Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

2017-05-23

Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

Wafer-scale growth of highly textured piezoelectric thin films by pulsed laser deposition for micro-scale sensors and actuators

NASA Astrophysics Data System (ADS)

Nguyen, M. D.; Tiggelaar, R.; Aukes, T.; Rijnders, G.; Roelof, G.

2017-11-01

Piezoelectric lead-zirconate-titanate (PZT) thin films were deposited on 4-inch (111)Pt/Ti/SiO2/Si(001) wafers using large-area pulsed laser deposition (PLD). This study was focused on the homogeneity in film thickness, microstructure, ferroelectric and piezoelectric properties of PZT thin films. The results indicated that the highly textured (001)-oriented PZT thin films with wafer-scale thickness homogeneity (990 nm ± 0.8%) were obtained. The films were fabricated into piezoelectric cantilevers through a MEMS microfabrication process. The measured longitudinal piezoelectric coefficient (d 33f = 210 pm/V ± 1.6%) and piezoelectric transverse coefficient (e 31f = -18.8 C/m2 ± 2.8%) were high and homogeneity across wafers. The high piezoelectric properties on Si wafers will extend industrial application of PZT thin films and further development of piezoMEMS.

Conformal Thin Film Packaging for SiC Sensor Circuits in Harsh Environments

NASA Technical Reports Server (NTRS)

Scardelletti, Maximilian C.; Karnick, David A.; Ponchak, George E.; Zorman, Christian A.

2011-01-01

In this investigation sputtered silicon carbide annealed at 300 C for one hour is used as a conformal thin film package. A RF magnetron sputterer was used to deposit 500 nm silicon carbide films on gold metal structures on alumina wafers. To determine the reliability and resistance to immersion in harsh environments, samples were submerged in gold etchant for 24 hours, in BOE for 24 hours, and in an O2 plasma etch for one hour. The adhesion strength of the thin film was measured by a pull test before and after the chemical immersion, which indicated that the film has an adhesion strength better than 10(exp 8) N/m2; this is similar to the adhesion of the gold layer to the alumina wafer. MIM capacitors are used to determine the dielectric constant, which is dependent on the SiC anneal temperature. Finally, to demonstrate that the SiC, conformal, thin film may be used to package RF circuits and sensors, an LC resonator circuit was fabricated and tested with and without the conformal SiC thin film packaging. The results indicate that the SiC coating adds no appreciable degradation to the circuits RF performance. Index Terms Sputter, silicon carbide, MIM capacitors, LC resonators, gold etchants, BOE, O2 plasma

Wafer-level Cu-Sn micro-joints with high mechanical strength and low Sn overflow

NASA Astrophysics Data System (ADS)

Duan, Ani; Luu, Thi-Thuy; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2015-09-01

In this paper, we report wafer-level bonding using solid-liquid inter-diffusion (SLID) processes for fabricating micro-joints Cu-Sn at low temperature (270 °C). The evolution of multilayer Cu/Sn to micro-joint alloys has been characterized by optical microscopy and mechanical die-shear testing. The Cu-Sn joints with line width from 80 to 200 μm prove to be reliable packaging materials for bonding vacuum micro-cavities with controllable Sn overflow, as well as high mechanical strength (>70 MPa). A thermodynamic model has been performed to further understand the formation of Cu-Sn intermetallic alloys. There are two important findings for this work: 1) Using a two-step temperature profile may significantly reduce the amount of Sn overflow; 2) for packaging, a bond frame width greater than 80 μm will result in high yield.

High voltage photo switch package module

DOEpatents

Sullivan, James S; Sanders, David M; Hawkins, Steven A; Sampayan, Stephen E

2014-02-18

A photo-conductive switch package module having a photo-conductive substrate or wafer with opposing electrode-interface surfaces, and at least one light-input surface. First metallic layers are formed on the electrode-interface surfaces, and one or more optical waveguides having input and output ends are bonded to the substrate so that the output end of each waveguide is bonded to a corresponding one of the light-input surfaces of the photo-conductive substrate. This forms a waveguide-substrate interface for coupling light into the photo-conductive wafer. A dielectric material such as epoxy is then used to encapsulate the photo-conductive substrate and optical waveguide so that only the metallic layers and the input end of the optical waveguide are exposed. Second metallic layers are then formed on the first metallic layers so that the waveguide-substrate interface is positioned under the second metallic layers.

An ultra-compact processor module based on the R3000

NASA Astrophysics Data System (ADS)

Mullenhoff, D. J.; Kaschmitter, J. L.; Lyke, J. C.; Forman, G. A.

1992-08-01

Viable high density packaging is of critical importance for future military systems, particularly space borne systems which require minimum weight and size and high mechanical integrity. A leading, emerging technology for high density packaging is multi-chip modules (MCM). During the 1980's, a number of different MCM technologies have emerged. In support of Strategic Defense Initiative Organization (SDIO) programs, Lawrence Livermore National Laboratory (LLNL) has developed, utilized, and evaluated several different MCM technologies. Prior LLNL efforts include modules developed in 1986, using hybrid wafer scale packaging, which are still operational in an Air Force satellite mission. More recent efforts have included very high density cache memory modules, developed using laser pantography. As part of the demonstration effort, LLNL and Phillips Laboratory began collaborating in 1990 in the Phase 3 Multi-Chip Module (MCM) technology demonstration project. The goal of this program was to demonstrate the feasibility of General Electric's (GE) High Density Interconnect (HDI) MCM technology. The design chosen for this demonstration was the processor core for a MIPS R3000 based reduced instruction set computer (RISC), which has been described previously. It consists of the R3000 microprocessor, R3010 floating point coprocessor and 128 Kbytes of cache memory.

Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

PubMed

Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

2011-04-21

A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

Modified Atmosphere Packaging and Its Feasibility for Military Feeding Systems

DTIC Science & Technology

1994-12-01

must be taken in all food processing . There are special precautions for NAP foods because a MAP food will not be sterilized and contamination or...Food Engineering. October: 62-63. 3 Rice, J., 1989. Modified Atmosphere Packaging. Food Processing . March: 60-76. 4 Coulon, M., and P. Louis, 1989...Prepared Foods. May:131. 9 Rice, J., 1989. Gas-Emitting Wafers: A Cost Effective NAP Approach. Food Processing . September:42. 10 Rice, J., 1991

Advanced uncooled sensor product development

NASA Astrophysics Data System (ADS)

Kennedy, A.; Masini, P.; Lamb, M.; Hamers, J.; Kocian, T.; Gordon, E.; Parrish, W.; Williams, R.; LeBeau, T.

2015-06-01

The partnership between RVS, Seek Thermal and Freescale Semiconductor continues on the path to bring the latest technology and innovation to both military and commercial customers. The partnership has matured the 17μm pixel for volume production on the Thermal Weapon Sight (TWS) program in efforts to bring advanced production capability to produce a low cost, high performance product. The partnership has developed the 12μm pixel and has demonstrated performance across a family of detector sizes ranging from formats as small as 206 x 156 to full high definition formats. Detector pixel sensitivities have been achieved using the RVS double level advanced pixel structure. Transition of the packaging of microbolometers from a traditional die level package to a wafer level package (WLP) in a high volume commercial environment is complete. Innovations in wafer fabrication techniques have been incorporated into this product line to assist in the high yield required for volume production. The WLP seal yield is currently > 95%. Simulated package vacuum lives >> 20 years have been demonstrated through accelerated life testing where the package has been shown to have no degradation after 2,500 hours at 150°C. Additionally the rugged assembly has shown no degradation after mechanical shock and vibration and thermal shock testing. The transition to production effort was successfully completed in 2014 and the WLP design has been integrated into multiple new production products including the TWS and the innovative Seek Thermal commercial product that interfaces directly to an iPhone or android device.

Thick resist for MEMS processing

NASA Astrophysics Data System (ADS)

Brown, Joe; Hamel, Clifford

2001-11-01

The need for technical innovation is always present in today's economy. Microfabrication methods have evolved in support of the demand for smaller and faster integrated circuits with price performance improvements always in the scope of the manufacturing design engineer. The dispersion of processing technology spans well beyond IC fabrication today with batch fabrication and wafer scale processing lending advantages to MEMES applications from biotechnology to consumer electronics from oil exploration to aerospace. Today the demand for innovative processing techniques that enable technology is apparent where only a few years ago appeared too costly or not reliable. In high volume applications where yield and cost improvements are measured in fractions of a percent it is imperative to have process technologies that produce consistent results. Only a few years ago thick resist coatings were limited to thickness less than 20 microns. Factors such as uniformity, edge bead and multiple coatings made high volume production impossible. New developments in photoresist formulation combined with advanced coating equipment techniques that closely controls process parameters have enable thick photoresist coatings of 70 microns with acceptable uniformity and edge bead in one pass. Packaging of microelectronic and micromechanical devices is often a significant cost factor and a reliability issue for high volume low cost production. Technologies such as flip- chip assembly provide a solution for cost and reliability improvements over wire bond techniques. The processing for such technology demands dimensional control and presents a significant cost savings if it were compatible with mainstream technologies. Thick photoresist layers, with good sidewall control would allow wafer-bumping technologies to penetrate the barriers to yield and production where costs for technology are the overriding issue. Single pass processing is paramount to the manufacturability of packaging technology. Uniformity and edge bead control defined the success of process implementation. Today advanced packaging solutions are created with thick photoresist coatings. The techniques and results will be presented.

Mechanical Design and Development of TES Bolometer Detector Arrays for the Advanced ACTPol Experiment

NASA Technical Reports Server (NTRS)

Ward, Jonathan T.; Austermann, Jason; Beall, James A.; Choi, Steve K.; Crowley, Kevin T.; Devlin, Mark J.; Duff, Shannon M.; Gallardo, Patricio M.; Henderson, Shawn W.; Ho, Shuay-Pwu Patty;

Mechanical designs and development of TES bolometer detector arrays for the Advanced ACTPol experiment

NASA Astrophysics Data System (ADS)

Ward, Jonathan T.; Austermann, Jason; Beall, James A.; Choi, Steve K.; Crowley, Kevin T.; Devlin, Mark J.; Duff, Shannon M.; Gallardo, Patricio A.; Henderson, Shawn W.; Ho, Shuay-Pwu Patty; Hilton, Gene; Hubmayr, Johannes; Khavari, Niloufar; Klein, Jeffrey; Koopman, Brian J.; Li, Dale; McMahon, Jeffrey; Mumby, Grace; Nati, Federico; Niemack, Michael D.; Page, Lyman A.; Salatino, Maria; Schillaci, Alessandro; Schmitt, Benjamin L.; Simon, Sara M.; Staggs, Suzanne T.; Thornton, Robert; Ullom, Joel N.; Vavagiakis, Eve M.; Wollack, Edward J.

2016-07-01

The next generation Advanced ACTPol (AdvACT) experiment is currently underway and will consist of four Transition Edge Sensor (TES) bolometer arrays, with three operating together, totaling 5800 detectors on the sky. Building on experience gained with the ACTPol detector arrays, AdvACT will utilize various new technologies, including 150 mm detector wafers equipped with multichroic pixels, allowing for a more densely packed focal plane. Each set of detectors includes a feedhorn array of stacked silicon wafers which form a spline profile leading to each pixel. This is then followed by a waveguide interface plate, detector wafer, back short cavity plate, and backshort cap. Each array is housed in a custom designed structure manufactured from high purity copper and then gold plated. In addition to the detector array assembly, the array package also encloses cryogenic readout electronics. We present the full mechanical design of the AdvACT high frequency (HF) detector array package along with a detailed look at the detector array stack assemblies. This experiment will also make use of extensive hardware and software previously developed for ACT, which will be modified to incorporate the new AdvACT instruments. Therefore, we discuss the integration of all AdvACT arrays with pre-existing ACTPol infrastructure.

Vertical and lateral heterogeneous integration

NASA Astrophysics Data System (ADS)

Geske, Jon; Okuno, Yae L.; Bowers, John E.; Jayaraman, Vijay

2001-09-01

A technique for achieving large-scale monolithic integration of lattice-mismatched materials in the vertical direction and the lateral integration of dissimilar lattice-matched structures has been developed. The technique uses a single nonplanar direct-wafer-bond step to transform vertically integrated epitaxial structures into lateral epitaxial variation across the surface of a wafer. Nonplanar wafer bonding is demonstrated by integrating four different unstrained multi-quantum-well active regions lattice matched to InP on a GaAs wafer surface. Microscopy is used to verify the quality of the bonded interface, and photoluminescence is used to verify that the bonding process does not degrade the optical quality of the laterally integrated wells. The authors propose this technique as a means to achieve greater levels of wafer-scale integration in optical, electrical, and micromechanical devices.

320 x 240 uncooled IRFPA with pixel wise thin film vacuum packaging

NASA Astrophysics Data System (ADS)

Yon, J.-J.; Dumont, G.; Rabaud, W.; Becker, S.; Carle, L.; Goudon, V.; Vialle, C.; Hamelin, A.; Arnaud, A.

2012-10-01

Silicon based vacuum packaging is a key enabling technology for achieving affordable uncooled Infrared Focal Plane Arrays (IRFPA) as required by the promising mass market for very low cost IR applications, such as automotive driving assistance, energy loss monitoring in buildings, motion sensors… Among the various approaches studied worldwide, the CEA, LETI is developing a unique technology where each bolometer pixel is sealed under vacuum at the wafer level, using an IR transparent thin film deposition. This technology referred to as PLP (Pixel Level Packaging), leads to an array of hermetic micro-caps each containing a single microbolometer. Since the successful demonstration that the PLP technology, when applied on a single microbolometer pixel, can provide the required vacuum < 10-3 mbar, the authors have pushed forward the development of the technology on fully operational QVGA readout circuits CMOS base wafers (320 x 240 pixels). In this outlook, the article reports on the electro optical performance obtained from this preliminary PLP based QVGA demonstrator. Apart from the response, noise and NETD distributions, the paper also puts emphasis on additional key features such as thermal time constant, image quality, and ageing properties.

New getter configuration at wafer level for assuring long term stability of MEMs

NASA Astrophysics Data System (ADS)

Moraja, Marco; Amiotti, Marco; Kullberg, Richard C.

2003-01-01

The evolution from ceramic packages to wafer to wafer hermetic sealing poses tremendous technical challenges to integrate a proper getter inside the MEMs to assure a long term stability and reliability of the devices. The state of the art solution to integrate a getter inside the MEMs of the last generation consists in patterning the getter material with a specific geometry onto the Si cap wafer. The practical implementation of this solution consists in a 4" or 6" Si wafers with grooves or particular incisures, where the getter material is placed in form of a thick film. The typical thickness of these thick films is in the range of few microns, depending on the gas load to be handled during the lifetime of the device. The structure of the thick getter film is highly porous in order to improve sorption performances, but at the same time there are no loose particles thanks to a proprietary manufacturing method. The getter thick film is composed of a Zr special alloy with a proper composition to optimize the sorption performances. The getter thick film can be placed selectively into grooves without affecting the lateral regions, surrounding the grooves where the hermetic sealing is performed.

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

PubMed

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this detector compared to FPIs. Optical characterization, x-ray contrast measurements and theoretical DQE evaluation suggest that a trade off can be found between the need of a large imaging area and the requirement of a uniform imaging performance, making the DynAMITe large area CMOS APS suitable for a range of bio-medical applications.

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

NASA Astrophysics Data System (ADS)

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Design, processing and testing of LSI arrays: Hybrid microelectronics task

NASA Technical Reports Server (NTRS)

Himmel, R. P.; Stuhlbarg, S. M.; Ravetti, R. G.; Zulueta, P. J.

1979-01-01

Mathematical cost factors were generated for both hybrid microcircuit and printed wiring board packaging methods. A mathematical cost model was created for analysis of microcircuit fabrication costs. The costing factors were refined and reduced to formulae for computerization. Efficient methods were investigated for low cost packaging of LSI devices as a function of density and reliability. Technical problem areas such as wafer bumping, inner/outer leading bonding, testing on tape, and tape processing, were investigated.

Laser wafering for silicon solar.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurfacemore » damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.« less

Wafer level reliability testing: An idea whose time has come

NASA Technical Reports Server (NTRS)

Trapp, O. D.

1987-01-01

Wafer level reliability testing has been nurtured in the DARPA supported workshops, held each autumn since 1982. The seeds planted in 1982 have produced an active crop of very large scale integration manufacturers applying wafer level reliability test methods. Computer Aided Reliability (CAR) is a new seed being nurtured. Users are now being awakened by the huge economic value of the wafer reliability testing technology.

Wafer-scale growth of VO2 thin films using a combinatorial approach

PubMed Central

Zhang, Hai-Tian; Zhang, Lei; Mukherjee, Debangshu; Zheng, Yuan-Xia; Haislmaier, Ryan C.; Alem, Nasim; Engel-Herbert, Roman

2015-01-01

Transition metal oxides offer functional properties beyond conventional semiconductors. Bridging the gap between the fundamental research frontier in oxide electronics and their realization in commercial devices demands a wafer-scale growth approach for high-quality transition metal oxide thin films. Such a method requires excellent control over the transition metal valence state to avoid performance deterioration, which has been proved challenging. Here we present a scalable growth approach that enables a precise valence state control. By creating an oxygen activity gradient across the wafer, a continuous valence state library is established to directly identify the optimal growth condition. Single-crystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitude change in resistivity across the metal-to-insulator transition. It is demonstrated that ‘electronic grade' transition metal oxide films can be realized on a large scale using a combinatorial growth approach, which can be extended to other multivalent oxide systems. PMID:26450653

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

NASA Astrophysics Data System (ADS)

Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

2017-02-01

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (~1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals.

PubMed

Carey, Benjamin J; Ou, Jian Zhen; Clark, Rhiannon M; Berean, Kyle J; Zavabeti, Ali; Chesman, Anthony S R; Russo, Salvy P; Lau, Desmond W M; Xu, Zai-Quan; Bao, Qiaoliang; Kevehei, Omid; Gibson, Brant C; Dickey, Michael D; Kaner, Richard B; Daeneke, Torben; Kalantar-Zadeh, Kourosh

2017-02-17

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes.

Wafer-scale two-dimensional semiconductors from printed oxide skin of liquid metals

PubMed Central

Carey, Benjamin J.; Ou, Jian Zhen; Clark, Rhiannon M.; Berean, Kyle J.; Zavabeti, Ali; Chesman, Anthony S. R.; Russo, Salvy P.; Lau, Desmond W. M.; Xu, Zai-Quan; Bao, Qiaoliang; Kavehei, Omid; Gibson, Brant C.; Dickey, Michael D.; Kaner, Richard B.; Daeneke, Torben; Kalantar-Zadeh, Kourosh

2017-01-01

A variety of deposition methods for two-dimensional crystals have been demonstrated; however, their wafer-scale deposition remains a challenge. Here we introduce a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds by transforming the native interfacial metal oxide layer of low melting point metal precursors (group III and IV) in liquid form. In an oxygen-containing atmosphere, these metals establish an atomically thin oxide layer in a self-limiting reaction. The layer increases the wettability of the liquid metal placed on oxygen-terminated substrates, leaving the thin oxide layer behind. In the case of liquid gallium, the oxide skin attaches exclusively to a substrate and is then sulfurized via a relatively low temperature process. By controlling the surface chemistry of the substrate, we produce large area two-dimensional semiconducting GaS of unit cell thickness (∼1.5 nm). The presented deposition and patterning method offers great commercial potential for wafer-scale processes. PMID:28211538

Silicon photonics: some remaining challenges

NASA Astrophysics Data System (ADS)

Reed, G. T.; Topley, R.; Khokhar, A. Z.; Thompson, D. J.; Stanković, S.; Reynolds, S.; Chen, X.; Soper, N.; Mitchell, C. J.; Hu, Y.; Shen, L.; Martinez-Jimenez, G.; Healy, N.; Mailis, S.; Peacock, A. C.; Nedeljkovic, M.; Gardes, F. Y.; Soler Penades, J.; Alonso-Ramos, C.; Ortega-Monux, A.; Wanguemert-Perez, G.; Molina-Fernandez, I.; Cheben, P.; Mashanovich, G. Z.

2016-03-01

This paper discusses some of the remaining challenges for silicon photonics, and how we at Southampton University have approached some of them. Despite phenomenal advances in the field of Silicon Photonics, there are a number of areas that still require development. For short to medium reach applications, there is a need to improve the power consumption of photonic circuits such that inter-chip, and perhaps intra-chip applications are viable. This means that yet smaller devices are required as well as thermally stable devices, and multiple wavelength channels. In turn this demands smaller, more efficient modulators, athermal circuits, and improved wavelength division multiplexers. The debate continues as to whether on-chip lasers are necessary for all applications, but an efficient low cost laser would benefit many applications. Multi-layer photonics offers the possibility of increasing the complexity and effectiveness of a given area of chip real estate, but it is a demanding challenge. Low cost packaging (in particular, passive alignment of fibre to waveguide), and effective wafer scale testing strategies, are also essential for mass market applications. Whilst solutions to these challenges would enhance most applications, a derivative technology is emerging, that of Mid Infra-Red (MIR) silicon photonics. This field will build on existing developments, but will require key enhancements to facilitate functionality at longer wavelengths. In common with mainstream silicon photonics, significant developments have been made, but there is still much left to do. Here we summarise some of our recent work towards wafer scale testing, passive alignment, multiplexing, and MIR silicon photonics technology.

Composite germanium monochromators - Results for the TriCS single-crystal diffractometer at SINQ

NASA Astrophysics Data System (ADS)

Schefer, J.; Fischer, S.; Böhm, M.; Keller, L.; Horisberger, M.; Medarde, M.; Fischer, P.

Composite germanium monochromators are foremost in application in neutron diffraction due to their good scattering properties, low absorption values and the diamond structure which avoids second-order contamination when using hhk reflections (all odd). Our slices for the monochromator are built from 24 wafers, each 0.4 mm thick. The alignment of the wafers within the final composite wafer package has been improved by adding tin for the soldering process with a sputtering method instead of foils. Nine slices, each 12.5 mm high, are mounted on separate miniature goniometer heads to the focusing monochromator. The focusing angle is controlled by only one motor/digitizer by using a sophisticated mechanism. Turning the monochromator by 9° around overlineω allow access of the 311 (primary) and 511 (secondary) reflection. We also show the importance of permanent quality control with neutrons. The monochromator will be used on the single-crystal diffractometer TriCS at SINQ.

SEMICONDUCTOR TECHNOLOGY: Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology

NASA Astrophysics Data System (ADS)

Yuhan, Cao; Le, Luo

2009-08-01

A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu6Sn5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 × 10-9 atm cc/s are possible, meeting the demands of MIL-STD-883E.

Low temperature wafer-level bonding for hermetic packaging of 3D microsystems

NASA Astrophysics Data System (ADS)

Tan, C. S.; Fan, J.; Lim, D. F.; Chong, G. Y.; Li, K. H.

2011-07-01

Metallic copper-copper (Cu-Cu) thermo-compression bonding, oxide-oxide (SiO2-SiO2) fusion bonding and silicon-silicon (Si-Si) direct bonding are investigated for potential application as hermetic seal in 3D microsystem packaging. Cavities are etched to a volume of 1.4 × 10-3 cm3 in accordance with the MIL-STD-883E standard prescribed for microelectronics packaging. In the case of metal bonding, a clean Cu layer with a thickness of 300 nm and a Ti barrier layer with an underlying thickness of 50 nm are used. The wafer pair is bonded at 300 °C under the application of a bonding force of 5500 N for 1 h. On the other hand, Si-Si bonding and SiO2-SiO2 bonding are initiated at room ambient after surface activation, followed by annealing in inert ambient at 300 °C for 1 h. The bonded cavities are stored in a helium bomb chamber and the leak rate is measured with a mass spectrometer. An excellent helium leak rate below 5 × 10-9 atm cm3 s-1 is detected for all cases and this is at least ten times better than the reject limit.

Back-illuminated CCD imager adapted for contrast transfer function measurements thereon

NASA Technical Reports Server (NTRS)

Levine, Peter A. (Inventor)

1987-01-01

Stripe patterns of varying spatial frequency, formed in the top-metalization of a back-illuminated solid-state imager, facilitate on-line measurement of contrast transfer function during wafer-probe testing. The imager may be packaged to allow front-illumination during in-the-field testing after its manufacture.

Process Development for the Fabrication of Spheroidal Microdevice Packages Utilizing MEMS Technologies

DTIC Science & Technology

2014-03-27

in a thin conductive layer, the wafer surface can be made into the cathode while using a stainless steel plate as an anode. Bath temperature, voltage...beakers with polytetrafluoroethylene (PTFE) tools while under a fume hood, as HF is known to attack glass and polystyrene [62]. Additionally

Silicon Hybrid Wafer Scale Integration Interconnect Evaluation

DTIC Science & Technology

1989-12-01

perform Wafer Scale Integration on a routine basis is being vigorously pursued by a number of interests in military, academic , and commercial sectors...A iliciosi rip1 St -110 illic. (;11ptai / W. -a ;,tcd Ihat Ilesc hybhrid futl liods separiltely soI lie llixiiiul’upw~v~ ielts andl ~il (otii’ie thli

Protection of microelectronic devices during packaging

DOEpatents

Peterson, Kenneth A.; Conley, William R.

2002-01-01

The present invention relates to a method of protecting a microelectronic device during device packaging, including the steps of applying a water-insoluble, protective coating to a sensitive area on the device; performing at least one packaging step; and then substantially removing the protective coating, preferably by dry plasma etching. The sensitive area can include a released MEMS element. The microelectronic device can be disposed on a wafer. The protective coating can be a vacuum vapor-deposited parylene polymer, silicon nitride, metal (e.g. aluminum or tungsten), a vapor deposited organic material, cynoacrylate, a carbon film, a self-assembled monolayered material, perfluoropolyether, hexamethyldisilazane, or perfluorodecanoic carboxylic acid, silicon dioxide, silicate glass, or combinations thereof. The present invention also relates to a method of packaging a microelectronic device, including: providing a microelectronic device having a sensitive area; applying a water-insoluble, protective coating to the sensitive area; providing a package; attaching the device to the package; electrically interconnecting the device to the package; and substantially removing the protective coating from the sensitive area.

Temporary coatings for protection of microelectronic devices during packaging

DOEpatents

Peterson, Kenneth A.; Conley, William R.

2005-01-18

The present invention relates to a method of protecting a microelectronic device during device packaging, including the steps of applying a water-insoluble, temporary protective coating to a sensitive area on the device; performing at least one packaging step; and then substantially removing the protective coating, preferably by dry plasma etching. The sensitive area can include a released MEMS element. The microelectronic device can be disposed on a wafer. The protective coating can be a vacuum vapor-deposited parylene polymer, silicon nitride, metal (e.g. aluminum or tungsten), a vapor deposited organic material, cynoacrylate, a carbon film, a self-assembled monolayered material, perfluoropolyether, hexamethyldisilazane, or perfluorodecanoic carboxylic acid, silicon dioxide, silicate glass, or combinations thereof. The present invention also relates to a method of packaging a microelectronic device, including: providing a microelectronic device having a sensitive area; applying a water-insoluble, protective coating to the sensitive area; providing a package; attaching the device to the package; electrically interconnecting the device to the package; and substantially removing the protective coating from the sensitive area.

SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

NASA Astrophysics Data System (ADS)

Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

2016-10-01

Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and yield. Soft stamps, usually based on silicone rubber, behave fundamentally different compared to rigid stamps on the macro-, micro- and nanometer level. The main limitation of traditional silicones is that they are too soft to support sub-micron features against surface tension based stamp deformation and collapse [4] and handling a soft stamp to achieve accurate feature placement on wafer scales to allow overlay alignment with sub-100nm overlay accuracy.

Single-Crystal Sapphire Optical Fiber Sensor Instrumentation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pickrell, Gary; Scott, Brian; Wang, Anbo

2013-12-31

This report summarizes technical progress on the program “Single-Crystal Sapphire Optical Fiber Sensor Instrumentation,” funded by the National Energy Technology Laboratory of the U.S. Department of Energy, and performed by the Center for Photonics Technology of the Bradley Department of Electrical and Computer Engineering at Virginia Tech. This project was completed in three phases, each with a separate focus. Phase I of the program, from October 1999 to April 2002, was devoted to development of sensing schema for use in high temperature, harsh environments. Different sensing designs were proposed and tested in the laboratory. Phase II of the program, frommore » April 2002 to April 2009, focused on bringing the sensor technologies, which had already been successfully demonstrated in the laboratory, to a level where the sensors could be deployed in harsh industrial environments and eventually become commercially viable through a series of field tests. Also, a new sensing scheme was developed and tested with numerous advantages over all previous ones in Phase II. Phase III of the program, September 2009 to December 2013, focused on development of the new sensing scheme for field testing in conjunction with materials engineering of the improved sensor packaging lifetimes. In Phase I, three different sensing principles were studied: sapphire air-gap extrinsic Fabry-Perot sensors; intensity-based polarimetric sensors; and broadband polarimetric sensors. Black body radiation tests and corrosion tests were also performed in this phase. The outcome of the first phase of this program was the selection of broadband polarimetric differential interferometry (BPDI) for further prototype instrumentation development. This approach is based on the measurement of the optical path difference (OPD) between two orthogonally polarized light beams in a single-crystal sapphire disk. At the beginning of Phase II, in June 2004, the BPDI sensor was tested at the Wabash River coal gasifier facility in Terre Haute, Indiana. Due to business conditions at industrial partner and several logistical problems, this field test was not successful. An alternative high-temperature sensing system using sapphire wafer-based extrinsic Fabry-Perot interferometry was then developed as a significant improvement over the BPDI solution. From June 2006 to June 2008, three consecutive field tests were performed with the new sapphire wafer sensors at the TECO coal gasifier in Tampa, Florida. One of the sensors survived in the industrial coal gasifier for 7 months, over which time the existing thermocouples were replaced twice. The outcome of these TECO field tests suggests that the sapphire wafer sensor has very good potential to be commercialized. However packaging and sensor protection issues need additional development. During Phase III, several major improvements in the design and fabrication process of the sensor have been achieved through experiments and theoretical analysis. Studies on the property of the key components in the sensor head, including the sapphire fiber and sapphire wafer, were also conducted, for a better understanding of the sensor behavior. A final design based on all knowledge and experience has been developed, free of any issues encountered during the entire research. Sensors with this design performed well as expected in lab long-term tests, and were deployed in the sensing probe of the final coal-gasifier field test. Sensor packaging and protection was improved through materials engineering through testing of packaging designs in two blank probe packaging tests at Eastman Chemical in Kingsport, TN. Performance analysis of the blank probe packaging resulted in improve package designs culminating in a 3rd generation probe packaging utilized for the full field test of the sapphire optical sensor and materials designed sensor packaging.« less

Wafer-size free-standing single-crystalline graphene device arrays

NASA Astrophysics Data System (ADS)

Li, Peng; Jing, Gaoshan; Zhang, Bo; Sando, Shota; Cui, Tianhong

2014-08-01

We report an approach of wafer-scale addressable single-crystalline graphene (SCG) arrays growth by using pre-patterned seeds to control the nucleation. The growth mechanism and superb properties of SCG were studied. Large array of free-standing SCG devices were realized. Characterization of SCG as nano switches shows excellent performance with life time (>22 000 times) two orders longer than that of other graphene nano switches reported so far. This work not only shows the possibility of producing wafer-scale high quality SCG device arrays but also explores the superb performance of SCG as nano devices.

Computational Modeling in Plasma Processing for 300 mm Wafers

NASA Technical Reports Server (NTRS)

Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

1997-01-01

Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

11.72 sq cm SiC Wafer-scale Interconnected 64 kA PiN Diode

DTIC Science & Technology

2012-01-30

drop of 10.3 V. The dissipated energy was 382 J and the calculated action exceeded 1.7 MA2 -s. Preliminary development of high voltage interconnection...scale diode action (surge current integral), a key reliability parameter, exceeded 1.7 MA2 -s. Figure 6: The wafer-scale interconnected diode...scale diode was 382 J and the calculated action exceeded 1.7 MA2 -sec. High voltage operation of PiN diodes, thyristors, and other semiconductor

Impact of front-of-pack nutrition information and label design on children's choice of two snack foods: Comparison of warnings and the traffic-light system.

PubMed

Arrúa, Alejandra; Curutchet, María Rosa; Rey, Natalia; Barreto, Patricia; Golovchenko, Nadya; Sellanes, Andrea; Velazco, Guillermo; Winokur, Medy; Giménez, Ana; Ares, Gastón

2017-09-01

Research on the relative influence of package features on children's perception of food products is still necessary to aid policy design and development. The aim of the present work was to evaluate the relative influence of two front-of-pack (FOP) nutrition labelling schemes, the traffic light system and Chilean warning system, and label design on children's choice of two popular snack foods in Uruguay, wafer cookies and orange juice. A total of 442 children in grades 4 to 6 from 12 primary schools in Montevideo (Uruguay) participated in the study. They were asked to complete a choice-conjoint task with wafer cookies and orange juice labels, varying in label design and the inclusion of FOP nutrition information. Half of the children completed the task with labels featuring the traffic-light system (n = 217) and the other half with labels featuring the Chilean warning system (n = 225). Children's choices of wafer cookies and juice labels was significantly influenced by both label design and FOP nutritional labels. The relative impact of FOP nutritional labelling on children's choices was higher for the warning system compared to the traffic-light system. Results from the present work stress the need to regulate the design of packages and the inclusion of nutrient claims, and provide preliminary evidence of the potential of warnings to discourage children's choice of unhealthful products. Copyright © 2017 Elsevier Ltd. All rights reserved.

Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

NASA Astrophysics Data System (ADS)

Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

2005-01-01

Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

NASA Astrophysics Data System (ADS)

Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

2004-12-01

Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

Non-Destructive Damping Measurement for Wafer-Level Packaged Microelectromechanical System (MEMS) Acceleration Switches

DTIC Science & Technology

2014-09-01

Micromechanics and Microengineering . 2005;15:176–184. 10. Mohite SS, Kesari H, Sonti VR, Pratap R. Analytical solutions for the stiffness and damping...coefficients of squeeze films in MEMS devices with perforated back plates. Journal of Micromechanics and Microengineering . 2005;15:2083–2092. 11. Younis MI

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

NASA Astrophysics Data System (ADS)

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Single-mode glass waveguide technology for optical interchip communication on board level

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning

2012-01-01

The large bandwidth demand in long-distance telecom networks lead to single-mode fiber interconnects as result of low dispersion, low loss and dense wavelength multiplexing possibilities. In contrast, multi-mode interconnects are suitable for much shorter lengths up to 300 meters and are promising for optical links between racks and on board level. Active optical cables based on multi-mode fiber links are at the market and research in multi-mode waveguide integration on board level is still going on. Compared to multi-mode, a single-mode waveguide has much more integration potential because of core diameters of around 20% of a multi-mode waveguide by a much larger bandwidth. But light coupling in single-mode waveguides is much more challenging because of lower coupling tolerances. Together with the silicon photonics technology, a single-mode waveguide technology on board-level will be the straight forward development goal for chip-to-chip optical interconnects integration. Such a hybrid packaging platform providing 3D optical single-mode links bridges the gap between novel photonic integrated circuits and the glass fiber based long-distance telecom networks. Following we introduce our 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip interconnects. This novel packaging approach merges micro-system packaging and glass integrated optics. It consists of a thin glass substrate with planar integrated singlemode waveguide circuits, optical mirrors and lenses providing an integration platform for photonic IC assembly and optical fiber interconnect. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties. That makes it perfect for microsystem packaging. The paper presents recent results in single-mode waveguide technology on wafer level and waveguide characterization. Furthermore the integration in a hybrid packaging process and design issues are discussed.

Scalable Manufacturing of Solderable and Stretchable Physiologic Sensing Systems.

PubMed

Kim, Yun-Soung; Lu, Jesse; Shih, Benjamin; Gharibans, Armen; Zou, Zhanan; Matsuno, Kristen; Aguilera, Roman; Han, Yoonjae; Meek, Ann; Xiao, Jianliang; Tolley, Michael T; Coleman, Todd P

2017-10-01

Methods for microfabrication of solderable and stretchable sensing systems (S4s) and a scaled production of adhesive-integrated active S4s for health monitoring are presented. S4s' excellent solderability is achieved by the sputter-deposited nickel-vanadium and gold pad metal layers and copper interconnection. The donor substrate, which is modified with "PI islands" to become selectively adhesive for the S4s, allows the heterogeneous devices to be integrated with large-area adhesives for packaging. The feasibility for S4-based health monitoring is demonstrated by developing an S4 integrated with a strain gauge and an onboard optical indication circuit. Owing to S4s' compatibility with the standard printed circuit board assembly processes, a variety of commercially available surface mount chip components, such as the wafer level chip scale packages, chip resistors, and light-emitting diodes, can be reflow-soldered onto S4s without modifications, demonstrating the versatile and modular nature of S4s. Tegaderm-integrated S4 respiration sensors are tested for robustness for cyclic deformation, maximum stretchability, durability, and biocompatibility for multiday wear time. The results of the tests and demonstration of the respiration sensing indicate that the adhesive-integrated S4s can provide end users a way for unobtrusive health monitoring. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Wafer-level vacuum packaged resonant micro-scanning mirrors for compact laser projection displays

NASA Astrophysics Data System (ADS)

Hofmann, Ulrich; Oldsen, Marten; Quenzer, Hans-Joachim; Janes, Joachim; Heller, Martin; Weiss, Manfred; Fakas, Georgios; Ratzmann, Lars; Marchetti, Eleonora; D'Ascoli, Francesco; Melani, Massimiliano; Bacciarelli, Luca; Volpi, Emilio; Battini, Francesco; Mostardini, Luca; Sechi, Francesco; De Marinis, Marco; Wagner, Bernd

2008-02-01

Scanning laser projection using resonant actuated MEMS scanning mirrors is expected to overcome the current limitation of small display size of mobile devices like cell phones, digital cameras and PDAs. Recent progress in the development of compact modulated RGB laser sources enables to set up very small laser projection systems that become attractive not only for consumer products but also for automotive applications like head-up and dash-board displays. Within the last years continuous progress was made in increasing MEMS scanner performance. However, only little is reported on how mass-produceability of these devices and stable functionality even under harsh environmental conditions can be guaranteed. Automotive application requires stable MEMS scanner operation over a wide temperature range from -40° to +85°Celsius. Therefore, hermetic packaging of electrostatically actuated MEMS scanning mirrors becomes essential to protect the sensitive device against particle contamination and condensing moisture. This paper reports on design, fabrication and test of a resonant actuated two-dimensional micro scanning mirror that is hermetically sealed on wafer level. With resonant frequencies of 30kHz and 1kHz, an achievable Theta-D-product of 13mm.deg and low dynamic deformation <20nm RMS it targets Lissajous projection with SVGA-resolution. Inevitable reflexes at the vacuum package surface can be seperated from the projection field by permanent inclination of the micromirror.

Graphene-Si heterogeneous nanotechnology

NASA Astrophysics Data System (ADS)

Akinwande, Deji; Tao, Li

2013-05-01

It is widely envisioned that graphene, an atomic sheet of carbon that has generated very broad interest has the largest prospects for flexible smart systems and for integrated graphene-silicon (G-Si) heterogeneous very large-scale integrated (VLSI) nanoelectronics. In this work, we focus on the latter and elucidate the research progress that has been achieved for integration of graphene with Si-CMOS including: wafer-scale graphene growth by chemical vapor deposition on Cu/SiO2/Si substrates, wafer-scale graphene transfer that afforded the fabrication of over 10,000 devices, wafer-scalable mitigation strategies to restore graphene's device characteristics via fluoropolymer interaction, and demonstrations of graphene integrated with commercial Si- CMOS chips for hybrid nanoelectronics and sensors. Metrology at the wafer-scale has led to the development of custom Raman processing software (GRISP) now available on the nanohub portal. The metrology reveals that graphene grown on 4-in substrates have monolayer quality comparable to exfoliated flakes. At room temperature, the high-performance passivated graphene devices on SiO2/Si can afford average mobilities 3000cm2/V-s and gate modulation that exceeds an order of magnitude. The latest growth research has yielded graphene with high mobilities greater than 10,000cm2/V-s on oxidized silicon. Further progress requires track compatible graphene-Si integration via wafer bonding in order to translate graphene research from basic to applied research in commercial R and D laboratories to ultimately yield a viable nanotechnology.

Fabrication of wafer-scale nanopatterned sapphire substrate through phase separation lithography

NASA Astrophysics Data System (ADS)

Guo, Xu; Ni, Mengyang; Zhuang, Zhe; Dai, Jiangping; Wu, Feixiang; Cui, Yushuang; Yuan, Changsheng; Ge, Haixiong; Chen, Yanfeng

2016-04-01

A phase separation lithography (PSL) based on polymer blend provides an extremely simple, low-cost, and high-throughput way to fabricate wafer-scale disordered nanopatterns. This method was introduced to fabricate nanopatterned sapphire substrates (NPSSs) for GaN-based light-emitting diodes (LEDs). The PSL process only involved in spin-coating of polystyrene (PS)/polyethylene glycol (PEG) polymer blend on sapphire substrate and followed by a development with deionized water to remove PEG moiety. The PS nanoporous network was facilely obtained, and the structural parameters could be effectively tuned by controlling the PS/PEG weight ratio of the spin-coating solution. 2-in. wafer-scale NPSSs were conveniently achieved through the PS nanoporous network in combination with traditional nanofabrication methods, such as O2 reactive ion etching (RIE), e-beam evaporation deposition, liftoff, and chlorine-based RIE. In order to investigate the performance of such NPSSs, typical blue LEDs with emission wavelengths of ~450 nm were grown on the NPSS and a flat sapphire substrate (FSS) by metal-organic chemical vapor deposition, respectively. The integral photoluminescence (PL) intensity of the NPSS LED was enhanced by 32.3 % compared to that of the FSS-LED. The low relative standard deviation of 4.7 % for PL mappings of NPSS LED indicated the high uniformity of PL data across the whole 2-in. wafer. Extremely simple, low cost, and high throughput of the process and the ability to fabricate at the wafer scale make PSL a potential method for production of nanopatterned sapphire substrates.

Thinning of PLZT ceramic wafers for sensor integration

NASA Astrophysics Data System (ADS)

Jin, Na; Liu, Weiguo

2010-08-01

Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

Mechanical Designs and Developement of Advanced ACT: A Transfomative Upgrade to the ACTPol Receiver on the Atacama Cosmology Telescope.

NASA Astrophysics Data System (ADS)

Ward, Jonathan; Advanced ACT Collaboration, NASA Space Technology Research Fellowship

2017-06-01

The Atacama Cosmology Telescope is a six-meter diameter telescope located at 17,000 feet (5,200 meters) on Cerro Toco in the Andes Mountains of northern Chile. The next generation Advanced ACT (AdvACT) experiment is currently underway and will consist of three multichroic TES bolometer arrays operating together, totaling 5800 detectors on the sky. Each array will be sensitive to two frequency bands: a high frequency (HF) array at 150 and 230 GHz, two middle frequency (MF) arrays at 90 and 150 GHz, and a low frequency (LF) array at 28 and 41 GHz. The AdACT detector arrays will feature a revamped design when compared to ACTPol, including a transition to 150mm wafers equipped with multichroic pixels, allowing for a more densely packed focal plane. Each set of detectors consists of a feedhorn array of stacked silicon wafers which form a corrugated profile leading to each pixel. This is then followed by a four-piece detector stack assembly of silicon wafers which includes a waveguide interface plate, detector wafer, backshort cavity plate, and backshort cap. Each array is housed in a custom designed structure manufactured out of gold-plated, high purity copper. In addition to the detector array assembly, the array package also encloses the majority of our readout electronics. We present the full mechanical design of the AdvACT HF and MF detector array packages along with a detailed look at the detector array assemblies. We also highlight the use of continuously rotating warm half-wave plates (HWPs) at the front of the AdvACT receiver. We review the design of the rotation system and also early pipeline data analysis results. This experiment will also make use of extensive hardware and software previously developed for ACT, which will be modified to incorporate the new AdvACT instruments. Therefore, we discuss the integration of all AdvACT instruments with pre-existing ACTPol infrastructure.

193nm high power lasers for the wide bandgap material processing

NASA Astrophysics Data System (ADS)

Fujimoto, Junichi; Kobayashi, Masakazu; Kakizaki, Koji; Oizumi, Hiroaki; Mimura, Toshio; Matsunaga, Takashi; Mizoguchi, Hakaru

2017-02-01

Recently infrared laser has faced resolution limit of finer micromachining requirement on especially semiconductor packaging like Fan-Out Wafer Level Package (FO-WLP) and Through Glass Via hole (TGV) which are hard to process with less defect. In this study, we investigated ablation rate with deep ultra violet excimer laser to explore its possibilities of micromachining on organic and glass interposers. These results were observed with a laser microscopy and Scanning Electron Microscope (SEM). As the ablation rates of both materials were quite affordable value, excimer laser is expected to be put in practical use for mass production.

MEMS packaging: state of the art and future trends

NASA Astrophysics Data System (ADS)

Bossche, Andre; Cotofana, Carmen V. B.; Mollinger, Jeff R.

1998-07-01

Now that the technology for Integrated sensor and MEMS devices has become sufficiently mature to allow mass production, it is expected that the prices of bare chips will drop dramatically. This means that the package prices will become a limiting factor in market penetration, unless low cost packaging solutions become available. This paper will discuss the developments in packaging technology. Both single-chip and multi-chip packaging solutions will be addressed. It first starts with a discussion on the different requirements that have to be met; both from a device point of view (open access paths to the environment, vacuum cavities, etc.) and from the application point of view (e.g. environmental hostility). Subsequently current technologies are judged on their applicability for MEMS and sensor packaging and a forecast is given for future trends. It is expected that the large majority of sensing devices will be applied in relative friendly environments for which plastic packages would suffice. Therefore, on the short term an important role is foreseen for recently developed plastic packaging techniques such as precision molding and precision dispensing. Just like in standard electronic packaging, complete wafer level packaging methods for sensing devices still have a long way to go before they can compete with the highly optimized and automated plastic packaging processes.

Wafer integrated micro-scale concentrating photovoltaics

NASA Astrophysics Data System (ADS)

Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

2017-09-01

Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

Wafer-scale synthesis of monolayer and few-layer MoS2 via thermal vapor sulfurization

NASA Astrophysics Data System (ADS)

Robertson, John; Liu, Xue; Yue, Chunlei; Escarra, Matthew; Wei, Jiang

2017-12-01

Monolayer molybdenum disulfide (MoS2) is an atomically thin, direct bandgap semiconductor crystal potentially capable of miniaturizing optoelectronic devices to an atomic scale. However, the development of 2D MoS2-based optoelectronic devices depends upon the existence of a high optical quality and large-area monolayer MoS2 synthesis technique. To address this need, we present a thermal vapor sulfurization (TVS) technique that uses powder MoS2 as a sulfur vapor source. The technique reduces and stabilizes the flow of sulfur vapor, enabling monolayer wafer-scale MoS2 growth. MoS2 thickness is also controlled with great precision; we demonstrate the ability to synthesize MoS2 sheets between 1 and 4 layers thick, while also showing the ability to create films with average thickness intermediate between integer layer numbers. The films exhibit wafer-scale coverage and uniformity, with electrical quality varying depending on the final thickness of the grown MoS2. The direct bandgap of grown monolayer MoS2 is analyzed using internal and external photoluminescence quantum efficiency. The photoluminescence quantum efficiency is shown to be competitive with untreated exfoliated MoS2 monolayer crystals. The ability to consistently grow wafer-scale monolayer MoS2 with high optical quality makes this technique a valuable tool for the development of 2D optoelectronic devices such as photovoltaics, detectors, and light emitters.

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Liangyu, Chen; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

NASA Technical Reports Server (NTRS)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Control wafer bow of InGaP on 200 mm Si by strain engineering

NASA Astrophysics Data System (ADS)

Wang, Bing; Bao, Shuyu; Made, Riko I.; Lee, Kwang Hong; Wang, Cong; Eng Kian Lee, Kenneth; Fitzgerald, Eugene A.; Michel, Jurgen

2017-12-01

When epitaxially growing III-V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III-V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III-V semiconductors on large size Si substrates.

Resolving critical dimension drift over time in plasma etching through virtual metrology based wafer-to-wafer control

NASA Astrophysics Data System (ADS)

Lee, Ho Ki; Baek, Kye Hyun; Shin, Kyoungsub

2017-06-01

As semiconductor devices are scaled down to sub-20 nm, process window of plasma etching gets extremely small so that process drift or shift becomes more significant. This study addresses one of typical process drift issues caused by consumable parts erosion over time and provides feasible solution by using virtual metrology (VM) based wafer-to-wafer control. Since erosion of a shower head has center-to-edge area dependency, critical dimensions (CDs) at the wafer center and edge area get reversed over time. That CD trend is successfully estimated on a wafer-to-wafer basis by a partial least square (PLS) model which combines variables from optical emission spectroscopy (OES), VI-probe and equipment state gauges. R 2 of the PLS model reaches 0.89 and its prediction performance is confirmed in a mass production line. As a result, the model can be exploited as a VM for wafer-to-wafer control. With the VM, advanced process control (APC) strategy is implemented to solve the CD drift. Three σ of CD across wafer is improved from the range (1.3-2.9 nm) to the range (0.79-1.7 nm). Hopefully, results introduced in this paper will contribute to accelerating implementation of VM based APC strategy in semiconductor industry.

Lithographic chip identification: meeting the failure analysis challenge

NASA Astrophysics Data System (ADS)

Perkins, Lynn; Riddell, Kevin G.; Flack, Warren W.

1992-06-01

This paper describes a novel method using stepper photolithography to uniquely identify individual chips for permanent traceability. A commercially available 1X stepper is used to mark chips with an identifier or `serial number' which can be encoded with relevant information for the integrated circuit manufacturer. The permanent identification of individual chips can improve current methods of quality control, failure analysis, and inventory control. The need for this technology is escalating as manufacturers seek to provide six sigma quality control for their products and trace fabrication problems to their source. This need is especially acute for parts that fail after packaging and are returned to the manufacturer for analysis. Using this novel approach, failure analysis data can be tied back to a particular batch, wafer, or even a position within a wafer. Process control can be enhanced by identifying the root cause of chip failures. Chip identification also addresses manufacturers concerns with increasing incidences of chip theft. Since chips currently carry no identification other than the manufacturer's name and part number, recovery efforts are hampered by the inability to determine the sales history of a specific packaged chip. A definitive identifier or serial number for each chip would address this concern. The results of chip identification (patent pending) are easily viewed through a low power microscope. Batch number, wafer number, exposure step, and chip location within the exposure step can be recorded, as can dates and other items of interest. An explanation of the chip identification procedure and processing requirements are described. Experimental testing and results are presented, and potential applications are discussed.

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer

PubMed Central

Yu, Yang; Fong, Patrick W. K.; Wang, Shifeng; Surya, Charles

2016-01-01

High quality wafer-scale free-standing WS2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS2, which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm2 at −1 V which shows superior performances compared to the directly grown WS2/GaN heterojunctions. PMID:27897210

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer.

PubMed

Yu, Yang; Fong, Patrick W K; Wang, Shifeng; Surya, Charles

2016-11-29

High quality wafer-scale free-standing WS 2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS 2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS 2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS 2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS 2 , which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS 2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm 2 at -1 V which shows superior performances compared to the directly grown WS 2 /GaN heterojunctions.

Growth of 1.5 micron gallium indium nitrogen arsenic antimonide vertical cavity surface emitting lasers by molecular beam epitaxy

NASA Astrophysics Data System (ADS)

Wistey, Mark Allan

Fiber optics has revolutionized long distance communication and long haul networks, allowing unimaginable data speeds and noise-free telephone calls around the world for mere pennies per hour at the trunk level. But the high speeds of optical fiber generally do not extend to individual workstations or to the home, in large part because it has been difficult and expensive to produce lasers which emitted light at wavelengths which could take advantage of optical fiber. One of the most promising solutions to this problem is the development of a new class of semiconductors known as dilute nitrides. Dilute nitrides such as GaInNAs can be grown directly on gallium arsenide, which allows well-established processing techniques. More important, gallium arsenide allows the growth of vertical-cavity surface-emitting lasers (VCSELs), which can be grown in dense, 2D arrays on each wafer, providing tremendous economies of scale for manufacturing, testing, and packaging. Unfortunately, GaInNAs lasers have suffered from what has been dubbed the "nitrogen penalty," with high thresholds and low efficiency as the fraction of nitrogen in the semiconductor was increased. This thesis describes the steps taken to identify and essentially eliminate the nitrogen penalty. Protecting the wafer surface from plasma ignition, using an arsenic cap, greatly improved material quality. Using a Langmuir probe, we further found that the nitrogen plasma source produced a large number of ions which damaged the wafer during growth. The ions were dramatically reduced using deflection plates. Low voltage deflection plates were found to be preferable to high voltages, and simulations showed low voltages to be adequate for ion removal. The long wavelengths from dilute nitrides can be partly explained by wafer damage during growth. As a result of these studies, we demonstrated the first CW, room temperature lasers at wavelengths beyond 1.5mum on gallium arsenide, and the first GaInNAs(Sb) VCSELs beyond 1.31mum: 1.46mum. These techniques offer the promise of inexpensive, high speed fiber networking.

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

NASA Astrophysics Data System (ADS)

Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

2013-03-01

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

1366 Project Silicon: Reclaiming US Silicon PV Leadership

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling ofmore » 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the crucial development step between the original research effort in Lexington and the GW factory scheduled to be online before the end of the decade. At the conclusion of the project, it is clear that the Direct Wafer™ technology will have a dramatic impact on the entire silicon photovoltaic supply chain by effectively doubling existing silicon capacity (by reducing silicon usage by 50%) and reducing supply chain capital costs by 35%. The technology, when fully-scaled in the US, will also lead to significant job growth, with the eventual creation of 1,000 jobs in Western New York.« less

Large scale integration of graphene transistors for potential applications in the back end of the line

NASA Astrophysics Data System (ADS)

Smith, A. D.; Vaziri, S.; Rodriguez, S.; Östling, M.; Lemme, M. C.

2015-06-01

A chip to wafer scale, CMOS compatible method of graphene device fabrication has been established, which can be integrated into the back end of the line (BEOL) of conventional semiconductor process flows. In this paper, we present experimental results of graphene field effect transistors (GFETs) which were fabricated using this wafer scalable method. The carrier mobilities in these transistors reach up to several hundred cm2 V-1 s-1. Further, these devices exhibit current saturation regions similar to graphene devices fabricated using mechanical exfoliation. The overall performance of the GFETs can not yet compete with record values reported for devices based on mechanically exfoliated material. Nevertheless, this large scale approach is an important step towards reliability and variability studies as well as optimization of device aspects such as electrical contacts and dielectric interfaces with statistically relevant numbers of devices. It is also an important milestone towards introducing graphene into wafer scale process lines.

Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining.

PubMed

Sano, Yasuhisa; Yamamura, Kazuya; Mimura, Hidekazu; Yamauchi, Kazuto; Mori, Yuzo

2007-08-01

Metal-oxide semiconductor field-effect transistors fabricated on a silicon-on-insulator (SOI) wafer operate faster and at a lower power than those fabricated on a bulk silicon wafer. Scaling down, which improves their performances, demands thinner SOI wafers. In this article, improvement on the thinning of SOI wafers by numerically controlled plasma chemical vaporization machining (PCVM) is described. PCVM is a gas-phase chemical etching method in which reactive species generated in atmospheric-pressure plasma are used. Some factors affecting uniformity are investigated and methods for improvements are presented. As a result of thinning a commercial 8 in. SOI wafer, the initial SOI layer thickness of 97.5+/-4.7 nm was successfully thinned and made uniform at 7.5+/-1.5 nm.

Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments.

PubMed

Bomer, Johan G; Prokofyev, Alexander V; van den Berg, Albert; Le Gac, Séverine

2014-12-07

We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the microchannels, and alignment precision. Experiments on lipid bilayers with electrophysiological recordings using a model pore-forming polypeptide are demonstrated.

Modular packaging concept for MEMS and MOEMS

NASA Astrophysics Data System (ADS)

Stenchly, Vanessa; Reinert, Wolfgang; Quenzer, Hans-Joachim

2017-11-01

Wherever technical systems detect objects in their environment or interact with people, optical devices may play an important role. Light can be relatively easily produced and spatially and temporally modulated. Laser can project sharp images over long distances or cut materials in short distances. Depending on the wavelength an invisible scanning in near infrared for gesture recognition is possible as well as a projection of brilliant colour images. For several years, the Fraunhofer ISIT develops Opto-Packaging processes based on the viscous reshaping of glass wafers: First, hermetically sealed laser micro-mirror scanners WLP with inclined windows deflect in the central light reflex of the window out of the image area. Second, housing with lateral light exit permits hermetic sealing of edge-emitting lasers for highest reliability and durability. Such systems are currently experiencing an extremely high interest of the industry in all segments, from consumer to automotive through to materials processing. Our modular Opto-Packaging platform enables fast product developments. Housing for opto mechanical MEMS devices are equipped with inclined windows to minimize distortion, stray light and reflection losses. The hot viscous glass forming technology is also applied to functionalized substrate wafers which possess areas with high heat dissipation in addition to thermally insulating areas. Electrical contacts may be realized with metal filled vias or TGV (Through Glass Vias). The modular system reduces the development times for new, miniaturized optical systems so that manufacturers can focus on the essentials in their development, namely their product functionalities.

Emission factors of air toxics from semiconductor manufacturing in Korea.

PubMed

Eom, Yun-Sung; Hong, Ji-Hyung; Lee, Suk-Jo; Lee, Eun-Jung; Cha, Jun-Seok; Lee, Dae-Gyun; Bang, Sun-Ae

2006-11-01

The development of local, accurate emission factors is very important for the estimation of reliable national emissions and air quality management. For that, this study is performed for pollutants released to the atmosphere with source-specific emission tests from the semiconductor manufacturing industry. The semiconductor manufacturing industry is one of the major sources of air toxics or hazardous air pollutants (HAPs); thus, understanding the emission characteristics of the emission source is a very important factor in the development of a control strategy. However, in Korea, there is a general lack of information available on air emissions from the semiconductor industry. The major emission sources of air toxics examined from the semiconductor manufacturing industry were wet chemical stations, coating applications, gaseous operations, photolithography, and miscellaneous devices in the wafer fabrication and semiconductor packaging processes. In this study, analyses of emission characteristics, and the estimations of emission data and factors for air toxics, such as acids, bases, heavy metals, and volatile organic compounds from the semiconductor manufacturing process have been performed. The concentration of hydrogen chloride from the packaging process was the highest among all of the processes. In addition, the emission factor of total volatile organic compounds (TVOCs) for the packaging process was higher than that of the wafer fabrication process. Emission factors estimated in this study were compared with those of Taiwan for evaluation, and they were found to be of similar level in the case of TVOCs and fluorine compounds.

Total internal reflection-evanescent coupler for fiber-to-waveguide integration of planar optoelectric devices.

PubMed

Lu, Zhaolin; Prather, Dennis W

2004-08-01

We present a method for parallel coupling from a single-mode fiber, or fiber ribbon, into a silicon-on-insulator waveguide for integration with silicon optoelectronic circuits. The coupler incorporates the advantages of the vertically tapered waveguides and prism couplers, yet offers the flexibility of planar integration. The coupler can be fabricated by use of either wafer polishing technology or gray-scale photolithography. When optimal coupling is achieved in our experimental setup, the coupler can be packaged by epoxy bonding to form a fiber-waveguide parallel coupler or connector. Two-dimensional electromagnetic calculation predicts a coupling efficiency of 77% (- 1.14-dB insertion loss) for a silicon-to-silicon coupler with a uniform tunnel layer. The coupling efficiency is experimentally achieved to be 46% (-3.4-dB insertion loss), excluding the loss in silicon and the reflections from the input surface and the output facet.

Design Study of Wafer Seals for Future Hypersonic Vehicles

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2005-01-01

Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

NASA Technical Reports Server (NTRS)

Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.;

Cu Pillar Low Temperature Bonding and Interconnection Technology of for 3D RF Microsystem

NASA Astrophysics Data System (ADS)

Shi, G. X.; Qian, K. Q.; Huang, M.; Yu, Y. W.; Zhu, J.

2018-03-01

In this paper 3D interconnects technologies used Cu pillars are discussed with respect to RF microsystem. While 2.5D Si interposer and 3D packaging seem to rely to cu pillars for the coming years, RF microsystem used the heterogeneous chip such as GaAs integration with Si interposers should be at low temperature. The pillars were constituted by Cu (2 micron) -Ni (2 micron) -Cu (3 micron) -Sn (1 micron) multilayer metal and total height is 8 micron on the front-side of the wafer by using electroplating. The wafer backside Cu pillar is obtained by temporary bonding, thinning and silicon surface etching. The RF interposers are stacked by Cu-Sn eutectic bonding at 260 °C. Analyzed the reliability of different pillar bonding structure.

Heterogeneous integration based on low-temperature bonding for advanced optoelectronic devices

NASA Astrophysics Data System (ADS)

Higurashi, Eiji

2018-04-01

Heterogeneous integration is an attractive approach to manufacturing future optoelectronic devices. Recent progress in low-temperature bonding techniques such as plasma activation bonding (PAB) and surface-activated bonding (SAB) enables a new approach to integrating dissimilar materials for a wide range of photonics applications. In this paper, low-temperature direct bonding and intermediate layer bonding techniques are focused, and their state-of-the-art applications in optoelectronic devices are reviewed. First, we describe the room-temperature direct bonding of Ge/Ge and Ge/Si wafers for photodetectors and of GaAs/SiC wafers for high-power semiconductor lasers. Then, we describe low-temperature intermediate layer bonding using Au and lead-free Sn-3.0Ag-0.5Cu solders for optical sensors and MEMS packaging.

Wafer-Scale Integration of Systolic Arrays,

DTIC Science & Technology

1985-10-01

hus wtha rbaiith hig robabili, e aubrbe orutysta mostck b(e)adstotoefwsi the cenofther cnnel thati are connted to (g.The kery ato the alevel of t...problems considered heretofore in this paper also have an interpretation in a purely graph theoretic model. Suppose we are given a two-dimensional...graphs," Magyar 7Td. Akad. Math . Kut. Int. Kozl, Vol. 5, 1960, pp. 17-61. [6] D. Fussell and P. Varman, "Fault-tolerant wafer-scale architectures for

Silicon Wafer Advanced Packaging (SWAP). Multichip Module (MCM) Foundry Study. Version 2

DTIC Science & Technology

1991-04-08

Next Layer Dielectric Spacing - Additional Metal Thickness Impact on Dielectric Uniformity/Adhiesion. The first step in .!Ie EPerimental design would be... design CAM - computer aided manufacturing CAE - computer aided engineering CALCE - computer aided life cycle engineering center CARMA - computer aided...expansion 5 j- CVD - chemical vapor deposition J . ..- j DA - design automation J , DEC - Digital Equipment Corporation --- DFT - design for testability

Low-cost far infrared bolometer camera for automotive use

NASA Astrophysics Data System (ADS)

Vieider, Christian; Wissmar, Stanley; Ericsson, Per; Halldin, Urban; Niklaus, Frank; Stemme, Göran; Källhammer, Jan-Erik; Pettersson, Håkan; Eriksson, Dick; Jakobsen, Henrik; Kvisterøy, Terje; Franks, John; VanNylen, Jan; Vercammen, Hans; VanHulsel, Annick

2007-04-01

A new low-cost long-wavelength infrared bolometer camera system is under development. It is designed for use with an automatic vision algorithm system as a sensor to detect vulnerable road users in traffic. Looking 15 m in front of the vehicle it can in case of an unavoidable impact activate a brake assist system or other deployable protection system. To achieve our cost target below €100 for the sensor system we evaluate the required performance and can reduce the sensitivity to 150 mK and pixel resolution to 80 x 30. We address all the main cost drivers as sensor size and production yield along with vacuum packaging, optical components and large volume manufacturing technologies. The detector array is based on a new type of high performance thermistor material. Very thin Si/SiGe single crystal multi-layers are grown epitaxially. Due to the resulting valence barriers a high temperature coefficient of resistance is achieved (3.3%/K). Simultaneously, the high quality crystalline material provides very low 1/f-noise characteristics and uniform material properties. The thermistor material is transferred from the original substrate wafer to the read-out circuit using adhesive wafer bonding and subsequent thinning. Bolometer arrays can then be fabricated using industry standard MEMS process and materials. The inherently good detector performance allows us to reduce the vacuum requirement and we can implement wafer level vacuum packaging technology used in established automotive sensor fabrication. The optical design is reduced to a single lens camera. We develop a low cost molding process using a novel chalcogenide glass (GASIR®3) and integrate anti-reflective and anti-erosion properties using diamond like carbon coating.

Cost-effective method of manufacturing a 3D MEMS optical switch

NASA Astrophysics Data System (ADS)

Carr, Emily; Zhang, Ping; Keebaugh, Doug; Chau, Kelvin

2009-02-01

growth of data and video transport networks. All-optical switching eliminates the need for optical-electrical conversion offering the ability to switch optical signals transparently: independent of data rates, formats and wavelength. It also provides network operators much needed automation capabilities to create, monitor and protect optical light paths. To further accelerate the market penetration, it is necessary to identify a path to reduce the manufacturing cost significantly as well as enhance the overall system performance, uniformity and reliability. Currently, most MEMS optical switches are assembled through die level flip-chip bonding with either epoxies or solder bumps. This is due to the alignment accuracy requirements of the switch assembly, defect matching of individual die, and cost of the individual components. In this paper, a wafer level assembly approach is reported based on silicon fusion bonding which aims to reduce the packaging time, defect count and cost through volume production. This approach is successfully demonstrated by the integration of two 6-inch wafers: a mirror array wafer and a "snap-guard" wafer, which provides a mechanical structure on top of the micromirror to prevent electrostatic snap-down. The direct silicon-to-silicon bond eliminates the CTEmismatch and stress issues caused by non-silicon bonding agents. Results from a completed integrated switch assembly will be presented, which demonstrates the reliability and uniformity of some key parameters of this MEMS optical switch.

Integrated otpical monitoring of MEMS for closed-loop control

NASA Astrophysics Data System (ADS)

Dawson, Jeremy M.; Wang, Limin; McCormick, W. B.; Rittenhouse, S. A.; Famouri, Parviz F.; Hornak, Lawrence A.

2003-01-01

Robust control and failure assessment of MEMS employed in physically demanding, mission critical applications will allow for higher degrees of quality assurance in MEMS operation. Device fault detection and closed-loop control require detailed knowledge of the operational states of MEMS over the lifetime of the device, obtained by a means decoupled from the system. Preliminary through-wafer optical monitoring research efforts have shown that through-wafer optical probing is suitable for characterizing and monitoring the behavior of MEMS, and can be implemented in an integrated optical monitoring package for continuous in-situ device monitoring. This presentation will discuss research undertaken to establish integrated optical device metrology for closed-loop control of a MUMPS fabricated lateral harmonic oscillator. Successful linear closed-loop control results using a through-wafer optical microprobe position feedback signal will be presented. A theoretical optical output field intensity study of grating structures, fabricated on the shuttle of the resonator, was performed to improve the position resolution of the optical microprobe position signal. Through-wafer microprobe signals providing a positional resolution of 2 μm using grating structures will be shown, along with initial binary Fresnel diffractive optical microelement design layout, process development, and testing results. Progress in the design, fabrication, and test of integrated optical elements for multiple microprobe signal delivery and recovery will be discussed, as well as simulation of device system model parameter changes for failure assessment.

Wafer-scale pixelated detector system

DOEpatents

Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

2017-10-17

A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

Neural Implants, Packaging for Biocompatible Implants, and Improving Fabricated Capacitors

NASA Astrophysics Data System (ADS)

Agger, Elizabeth Rose

We have completed the circuit design and packaging procedure for an NIH-funded neural implant, called a MOTE (Microscale Optoelectronically Transduced Electrode). Neural recording implants for mice have greatly advanced neuroscience, but they are often damaging and limited in their recording location. This project will result in free-floating implants that cause less damage, provide rapid electronic recording, and increase range of recording across the cortex. A low-power silicon IC containing amplification and digitization sub-circuits is powered by a dual-function gallium arsenide photovoltaic and LED. Through thin film deposition, photolithography, and chemical and physical etching, the Molnar Group and the McEuen Group (Applied and Engineering Physics department) will package the IC and LED into a biocompatible implant approximately 100microm3. The IC and LED are complete and we have begun refining this packaging procedure in the Cornell NanoScale Science & Technology Facility. ICs with 3D time-resolved imaging capabilities can image microorganisms and other biological samples given proper packaging. A portable, flat, easily manufactured package would enable scientists to place biological samples on slides directly above the Molnar group's imaging chip. We have developed a packaging procedure using laser cutting, photolithography, epoxies, and metal deposition. Using a flip-chip method, we verified the process by aligning and adhering a sample chip to a holder wafer. In the CNF, we have worked on a long-term metal-insulator-metal (MIM) capacitor characterization project. Former Fellow and continuing CNF user Kwame Amponsah developed the original procedure for the capacitor fabrication, and another former fellow, Jonilyn Longenecker, revised the procedure and began the arduous process of characterization. MIM caps are useful to clean room users as testing devices to verify electronic characteristics of their active circuitry. This project's objective is to determine differences in current-voltage (IV) and capacitor-voltage (CV) relationships across variations in capacitor size and dielectric type. This effort requires an approximately 20-step process repeated for two-to-six varieties (dependent on temperature and thermal versus plasma options) of the following dielectrics: HfO2, SiO2, Al2O3, TaOx, and TiO2.

Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

PubMed

Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

2014-01-09

Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

Chelant Enhanced Solution Processing for Wafer Scale Synthesis of Transition Metal Dichalcogenide Thin Films.

PubMed

Ionescu, Robert; Campbell, Brennan; Wu, Ryan; Aytan, Ece; Patalano, Andrew; Ruiz, Isaac; Howell, Stephen W; McDonald, Anthony E; Beechem, Thomas E; Mkhoyan, K Andre; Ozkan, Mihrimah; Ozkan, Cengiz S

2017-07-25

It is of paramount importance to improve the control over large area growth of high quality molybdenum disulfide (MoS 2 ) and other types of 2D dichalcogenides. Such atomically thin materials have great potential for use in electronics, and are thought to make possible the first real applications of spintronics. Here in, a facile and reproducible method of producing wafer scale atomically thin MoS 2 layers has been developed using the incorporation of a chelating agent in a common organic solvent, dimethyl sulfoxide (DMSO). Previously, solution processing of a MoS 2 precursor, ammonium tetrathiomolybdate ((NH 4 ) 2 MoS 4 ), and subsequent thermolysis was used to produce large area MoS 2 layers. Our work here shows that the use of ethylenediaminetetraacetic acid (EDTA) in DMSO exerts superior control over wafer coverage and film thickness, and the results demonstrate that the chelating action and dispersing effect of EDTA is critical in growing uniform films. Raman spectroscopy, photoluminescence (PL), x-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectroscopy (FTIR), atomic force microscopy (AFM) and high-resolution scanning transmission electron microscopy (HR-STEM) indicate the formation of homogenous few layer MoS 2 films at the wafer scale, resulting from the novel chelant-in-solution method.

Thin glass based packaging and photonic single-mode waveguide integration by ion-exchange technology on board and module level

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Lang, Günter; Schröder, Henning

2011-01-01

The proposed novel packaging approach merges micro-system packaging and glass integrated optics. It provides 3D optical single-mode intra system links to bridge the gap between novel photonic integrated circuits and the glass fibers for inter system interconnects. We introduce our hybrid 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip links. Optical mirrors and lenses provide optical mode matching for photonic IC assemblies and optical fiber interconnects. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties as reviewed in the paper. That makes it perfect for micro-system packaging. The adopted planar waveguide process based on ion-exchange technology is capable for high-volume manufacturing. This ion-exchange process and the optical propagation are described in detail for thin glass substrates. An extensive characterization of all basic circuit elements like straight and curved waveguides, couplers and crosses proves the low attenuation of the optical circuit elements.

Wafer-scale plasmonic and photonic crystal sensors

NASA Astrophysics Data System (ADS)

George, M. C.; Liu, J.-N.; Farhang, A.; Williamson, B.; Black, M.; Wangensteen, T.; Fraser, J.; Petrova, R.; Cunningham, B. T.

2015-08-01

200 mm diameter wafer-scale fabrication, metrology, and optical modeling results are reviewed for surface plasmon resonance (SPR) sensors based on 2-D metallic nano-dome and nano-hole arrays (NHA's) as well as 1-D photonic crystal sensors based on a leaky-waveguide mode resonance effect, with potential applications in label free sensing, surface enhanced Raman spectroscopy (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). Potential markets include micro-arrays for medical diagnostics, forensic testing, environmental monitoring, and food safety. 1-D and 2-D nanostructures were fabricated on glass, fused silica, and silicon wafers using optical lithography and semiconductor processing techniques. Wafer-scale optical metrology results are compared to FDTD modeling and presented along with application-based performance results, including label-free plasmonic and photonic crystal sensing of both surface binding kinetics and bulk refractive index changes. In addition, SEFS and SERS results are presented for 1-D photonic crystal and 2-D metallic nano-array structures. Normal incidence transmittance results for a 550 nm pitch NHA showed good bulk refractive index sensitivity, however an intensity-based design with 665 nm pitch was chosen for use as a compact, label-free sensor at both 650 and 632.8 nm wavelengths. The optimized NHA sensor gives an SPR shift of about 480 nm per refractive index unit when detecting a series of 0-40% glucose solutions, but according to modeling shows about 10 times greater surface sensitivity when operating at 532 nm. Narrow-band photonic crystal resonance sensors showed quality factors over 200, with reasonable wafer-uniformity in terms of both resonance position and peak height.

Thermal Hysteresis of MEMS Packaged Capacitive Pressure Sensor (CPS) Based 3C-SiC

NASA Astrophysics Data System (ADS)

Marsi, N.; Majlis, B. Y.; Mohd-Yasin, F.; Hamzah, A. A.; Mohd Rus, A. Z.

2016-11-01

Presented herein are the effects of thermal hysteresis analyses of the MEMS packaged capacitive pressure sensor (CPS). The MEMS CPS was employed on Si-on-3C-SiC wafer that was performed using the hot wall low-pressure chemical vapour deposition (LPCVD) reactors at the Queensland Micro and Nanotechnology Center (QMNC), Griffith University and fabricated using the bulk-micromachining process. The MEMS CPS was operated at an extreme temperature up to 500°C and high external pressure at 5.0 MPa. The thermal hysteresis phenomenon that causes the deflection, strain and stress on the 3C-SiC diaphragm spontaneously influence the MEMS CPS performances. The differences of temperature, hysteresis, and repeatability test were presented to demonstrate the functionality of the MEMS packaged CPS. As expected, the output hysteresis has a low hysteresis (less than 0.05%) which has the hardness greater than the traditional silicon. By utilizing this low hysteresis, it was revealed that the MEMS packaged CPS has high repeatability and stability of the sensor.

Wafer-Scale Integration of Graphene-based Electronic, Optoelectronic and Electroacoustic Devices

PubMed Central

Tian, He; Yang, Yi; Xie, Dan; Cui, Ya-Long; Mi, Wen-Tian; Zhang, Yuegang; Ren, Tian-Ling

2014-01-01

In virtue of its superior properties, the graphene-based device has enormous potential to be a supplement or an alternative to the conventional silicon-based device in varies applications. However, the functionality of the graphene devices is still limited due to the restriction of the high cost, the low efficiency and the low quality of the graphene growth and patterning techniques. We proposed a simple one-step laser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane transistors, photodetectors, and loudspeakers. The in-plane graphene transistors have a large on/off ratio up to 5.34. And the graphene photodetector arrays were achieved with photo responsivity as high as 0.32 A/W. The graphene loudspeakers realize wide-band sound generation from 1 to 50 kHz. These results demonstrated that the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based electronic, optoelectronic and electroacoustic devices. PMID:24398542

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP's standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

Precision depth measurement of through silicon vias (TSVs) on 3D semiconductor packaging process.

PubMed

Jin, Jonghan; Kim, Jae Wan; Kang, Chu-Shik; Kim, Jong-Ahn; Lee, Sunghun

2012-02-27

We have proposed and demonstrated a novel method to measure depths of through silicon vias (TSVs) at high speed. TSVs are fine and deep holes fabricated in silicon wafers for 3D semiconductors; they are used for electrical connections between vertically stacked wafers. Because the high-aspect ratio hole of the TSV makes it difficult for light to reach the bottom surface, conventional optical methods using visible lights cannot determine the depth value. By adopting an optical comb of a femtosecond pulse laser in the infra-red range as a light source, the depths of TSVs having aspect ratio of about 7 were measured. This measurement was done at high speed based on spectral resolved interferometry. The proposed method is expected to be an alternative method for depth inspection of TSVs.

Hollow Microtube Resonators via Silicon Self-Assembly toward Subattogram Mass Sensing Applications.

PubMed

Kim, Joohyun; Song, Jungki; Kim, Kwangseok; Kim, Seokbeom; Song, Jihwan; Kim, Namsu; Khan, M Faheem; Zhang, Linan; Sader, John E; Park, Keunhan; Kim, Dongchoul; Thundat, Thomas; Lee, Jungchul

2016-03-09

Fluidic resonators with integrated microchannels (hollow resonators) are attractive for mass, density, and volume measurements of single micro/nanoparticles and cells, yet their widespread use is limited by the complexity of their fabrication. Here we report a simple and cost-effective approach for fabricating hollow microtube resonators. A prestructured silicon wafer is annealed at high temperature under a controlled atmosphere to form self-assembled buried cavities. The interiors of these cavities are oxidized to produce thin oxide tubes, following which the surrounding silicon material is selectively etched away to suspend the oxide tubes. This simple three-step process easily produces hollow microtube resonators. We report another innovation in the capping glass wafer where we integrate fluidic access channels and getter materials along with residual gas suction channels. Combined together, only five photolithographic steps and one bonding step are required to fabricate vacuum-packaged hollow microtube resonators that exhibit quality factors as high as ∼ 13,000. We take one step further to explore additionally attractive features including the ability to tune the device responsivity, changing the resonator material, and scaling down the resonator size. The resonator wall thickness of ∼ 120 nm and the channel hydraulic diameter of ∼ 60 nm are demonstrated solely by conventional microfabrication approaches. The unique characteristics of this new fabrication process facilitate the widespread use of hollow microtube resonators, their translation between diverse research fields, and the production of commercially viable devices.

Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage.

PubMed

Rack, Alexander; Scheel, Mario; Danilewsky, Andreas N

2016-03-01

Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1-2 ms followed by jumps faster than 2-6 m s(-1), leading to a macroscopically observed average velocity of 0.028-0.055 m s(-1). The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound.

Electron-Beam Deposition of Superconducting Molybdenum Thin Films for the Development of Mo/Au TES X-Ray Microcalorimeter

NASA Technical Reports Server (NTRS)

Finkbeiner, Fred Michael; Adams, Joseph S.; Bandler, Simon R.; Betancour-Martinez, Gabriele L.; Brown, Ari David; Chang, Meng-Ping; Chervenak, James A.; Chiao, Meng P.; Datesman, Aaron; Eckart, Megan E.;

Electrical Characterization of 4H-SiC JFET Wafer: DC Parameter Variations for Extreme Temperature IC Design

NASA Technical Reports Server (NTRS)

Neudeck, Philip G.; Chen, Liangyu; Spry, David J.; Beheim, Glenn M.; Chang, Carl W.

2014-01-01

This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA's on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 degC. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 degC to 500 degC.

Wavelength tunable MEMS VCSELs for OCT imaging

NASA Astrophysics Data System (ADS)

Sahoo, Hitesh Kumar; Ansbæk, Thor; Ottaviano, Luisa; Semenova, Elizaveta; Hansen, Ole; Yvind, Kresten

2018-02-01

MEMS VCSELs are one of the most promising swept source (SS) lasers for optical coherence tomography (OCT) and one of the best candidates for future integration with endoscopes, surgical probes and achieving an integrated OCT system. However, the current MEMS-based SS are processed on the III-V wafers, which are small, expensive and challenging to work with. Furthermore, the actuating part, i.e., the MEMS, is on the top of the structure which causes a strong dependence on packaging to decrease its sensitivity to the operating environment. This work addresses these design drawbacks and proposes a novel design framework. The proposed device uses a high contrast grating mirror on a Si MEMS stage as the bottom mirror, all of which is defined in an SOI wafer. The SOI wafer is then bonded to an InP III-V wafer with the desired active layers, thereby sealing the MEMS. Finally, the top mirror, a dielectric DBR (7 pairs of TiO2 - SiO2), is deposited on top. The new device is based on a silicon substrate with MEMS defined on a silicon membrane in an enclosed cavity. Thus the device is much more robust than the existing MEMS VCSELs. This design also enables either a two-way actuation on the MEMS or a smaller optical cavity (pull-away design), i.e., wider FSR (Free Spectral Range) to increase the wavelength sweep. Fabrication of the proposed device is outlined and the results of device characterization are reported.

Reliability Analysis/Assessment of Advanced Technologies

DTIC Science & Technology

1990-05-01

34, Reliability Physics 1980 , IEEE, p. 165. 25. RADC-TR-83-244. 26. Towner, Janet M., et. al., "Aluminum Electromigration Under Pulsed D.C. Conditions...Duvvury, Redwine, Kitagawa, Haas, Chuang, Beydler, Hyslop , "Impact of Hot Carriers On DRAM circuits", 1987 IEEE/IRPS. 58. Cahoon, Thornewell, Tsai...et. a]., "Substrate for Large Silicon Chip and Full Wafer Packaging", Semiconductor International, pp. 149-156, April 1980 . 5. T.E. Lewis and D.L

Evaluation of a cyanoacrylate dressing to manage peristomal skin alterations under ostomy skin barrier wafers.

PubMed

Milne, Catherine T; Saucier, Darlene; Trevellini, Chenel; Smith, Juliet

2011-01-01

Peristomal skin alterations under ostomy barrier wafers are a commonly reported problem. While a number of interventions to manage this issue have been reported, the use of a topically applied cyanoacrylate has received little attention. This case series describes the use of a topical cyanoacrylate for the management of peristomal skin alterations in persons living with an ostomy. Using a convenience sample, the topical cyanoacrylate dressing was applied to 11 patients with peristomal skin disruption under ostomy wafers in acute care and outpatient settings. The causes of barrier function interruption were also addressed to enhance outcomes. Patients were assessed for wound discomfort using a Likert Scale, time to healing, and number of appliance changes. Patient satisfaction was also examined. Average reported discomfort levels were 9.5 out of 10 at the initial peristomal irritation assessment visit decreased to 3.5 at the first wafer change and were absent by the second wafer change. Wafers had increasing wear time between changes in both settings with acute care patients responding faster. Epidermal resurfacing occurred within 10.2 days in outpatients and within 7 days in acute care patients. Because of the skin sealant action of this dressing, immediate adherence of the wafer was reported at all pouch changes.

High-throughput automatic defect review for 300mm blank wafers with atomic force microscope

NASA Astrophysics Data System (ADS)

Zandiatashbar, Ardavan; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

2015-03-01

While feature size in lithography process continuously becomes smaller, defect sizes on blank wafers become more comparable to device sizes. Defects with nm-scale characteristic size could be misclassified by automated optical inspection (AOI) and require post-processing for proper classification. Atomic force microscope (AFM) is known to provide high lateral and the highest vertical resolution by mechanical probing among all techniques. However, its low throughput and tip life in addition to the laborious efforts for finding the defects have been the major limitations of this technique. In this paper we introduce automatic defect review (ADR) AFM as a post-inspection metrology tool for defect study and classification for 300 mm blank wafers and to overcome the limitations stated above. The ADR AFM provides high throughput, high resolution, and non-destructive means for obtaining 3D information for nm-scale defect review and classification.

Wafer-scale epitaxial graphene on SiC for sensing applications

NASA Astrophysics Data System (ADS)

Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

2015-12-01

The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

Nanogranular soft magnetic material and on-package integrated inductors

NASA Astrophysics Data System (ADS)

Li, Liangliang

2007-12-01

Integrated inductors used in electronic circuits are mainly spiral-shaped aluminum devices fabricated on Si chip. They have several disadvantages---large silicon area consumption, high DC resistance and high cost. An attractive approach to address these issues is directly integrating inductors into package substrates, which provide plenty of usage area, low resistance and low cost. The goals of this dissertation are designing and fabricating magnetic and air-core inductors with characteristic low resistance and high quality factor on package substrates. The research work includes three parts which are summarized below. First, the CoFeHfO nanogranular magnetic material developed on Si wafers and package substrates by pulsed DC reactive sputtering were investigated. On Si wafers, the optimized CoFeHfO film has soft magnetic properties. On printed circuit board (PCB) substrates, these magnetic properties degrade due to the rough surface. Surface planarization such as chemical-mechanical polishing can be applied on PCB substrates to reduce the surface roughness and hence improve these properties. Second, on-package inductors with small resistances and high quality factors were designed, fabricated, measured and analyzed. Air-core and magnetic inductors (20 design variations) were built on 8-inch PCB substrates. The DC resistances of these inductors are less than 12 mO, one of the lowest values ever reported. The maximum quality factors can be as large as ˜80 at around 1 GHz for the air-core inductors and ˜25 at 200 MHz for the magnetic inductors. Third, inductor simulation was carried out to study the effects of magnetic materials on the properties of inductors using the Ansoft HFSS software package. The measurement data for the permeability spectra of the CoFeHfO film and the tensor nature of the permeability were taken into account in the simulation. The simulation results matched the experimental data for the inductances, resistances and quality factors. This established an accurate method for modeling high-frequency magnetic devices. Using this method, an inductor with a closed magnetic core was studied by varying the geometry of the core and copper coil. It has been found that the inductance of this inductor depends strongly on whether the permeability of the magnetic core is isotropic or anisotropic.

Evaluation of four inch diameter VGF-Ge substrates used for manufacturing multi-junction solar cell

NASA Astrophysics Data System (ADS)

Kewei, Cao; Tong, Liu; Jingming, Liu; Hui, Xie; Dongyan, Tao; Youwen, Zhao; Zhiyuan, Dong; Feng, Hui

2016-06-01

Low dislocation density Ge wafers grown by a vertical gradient freeze (VGF) method used for the fabrication of multi-junction photovoltaic cells (MJC) have been studied by a whole wafer scale measurement of the lattice parameter, X-ray rocking curves, etch pit density (EPD), impurities concentration, minority carrier lifetime and residual stress. Impurity content in the VGF-Ge wafers, including that of B, is quite low although B2O3 encapsulation is used in the growth process. An obvious difference exists across the whole wafer regarding the distribution of etch pit density, lattice parameter, full width at half maximum (FWHM) of the X-ray rocking curve and residual stress measured by Raman spectra. These are in contrast to a reference Ge substrate wafer grown by the Cz method. The influence of the VGF-Ge substrate on the performance of the MJC is analyzed and evaluated by a comparison of the statistical results of cell parameters. Project supported by the National Natural Science Foundation of China (No. 61474104).

Flip chip bumping technology—Status and update

NASA Astrophysics Data System (ADS)

Juergen Wolf, M.; Engelmann, Gunter; Dietrich, Lothar; Reichl, Herbert

2006-09-01

Flip chip technology is a key driver for new complex system architectures and high-density packaging, e.g. sensor or pixel devices. Bumped wafers/dice as key elements become very important in terms of general availability at low cost, high yield and quality level. Today, different materials, e.g. Au, Ni, AuSn, SnAg, SnAgCu, SnCu, etc., are used for flip chip interconnects and different bumping approaches are available. Electroplating is the technology of choice for high-yield wafer bumping for small bump sizes and pitches. Lead-free solder bumps require an increase in knowledge in the field of under bump metallization (UBM) and the interaction of bump and substrate metallization, the formation and growth of intermetallic compounds (IMCs) during liquid- and solid-phase reactions. Results of a new bi-layer UBM of Ni-Cu which is especially designed for small-sized lead-free solder bumps will be discussed.

Standard semiconductor packaging for high-reliability low-cost MEMS applications

NASA Astrophysics Data System (ADS)

Harney, Kieran P.

2005-01-01

Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

Standard semiconductor packaging for high-reliability low-cost MEMS applications

NASA Astrophysics Data System (ADS)

Harney, Kieran P.

2004-12-01

Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

Planned development of a 3D computer based on free-space optical interconnects

NASA Astrophysics Data System (ADS)

Neff, John A.; Guarino, David R.

1994-05-01

Free-space optical interconnection has the potential to provide upwards of a million data channels between planes of electronic circuits. This may result in the planar board and backplane structures of today giving away to 3-D stacks of wafers or multi-chip modules interconnected via channels running perpendicular to the processor planes, thereby eliminating much of the packaging overhead. Three-dimensional packaging is very appealing for tightly coupled fine-grained parallel computing where the need for massive numbers of interconnections is severely taxing the capabilities of the planar structures. This paper describes a coordinated effort by four research organizations to demonstrate an operational fine-grained parallel computer that achieves global connectivity through the use of free space optical interconnects.

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

NASA Technical Reports Server (NTRS)

Buehler, M. G. (Inventor)

1985-01-01

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

High-brightness diode pump sources for solid-state and fiber laser pumping across 8xx-9xx nm range

NASA Astrophysics Data System (ADS)

Diamant, Ronen; Berk, Yuri; Cohen, Shalom; Klumel, Genady; Levy, Moshe; Openhaim, Yaki; Peleg, Ophir; Yanson, Dan; Karni, Yoram

2011-06-01

Advanced solid state laser architectures place increasingly demanding requirements on high-brightness, low-cost QCW laser diode pump sources, with custom apertures both for side and end rod pumping configurations. To meet this need, a new series of scalable QCW pump sources at 808nm and 940nm was developed. The stacks, available in multiple output formats, allow for custom aperture filling by varying both the length and quantity of stacked laser bars. For these products, we developed next-generation laser bars based on improved epitaxial wafer designs delivering power densities of 20W/mm of emission aperture. With >200W of peak QCW power available from a full-length 1cm bar, we have demonstrated power scaling to over 2kW in 10-bar stacks with 55% wall plug efficiency. We also present the design and performance of several stack configurations using full-length and reduced-length (mini) bars that demonstrate the versatility of both the bar and packaging designs. We illustrate how the ROBUST HEAD packaging technology developed at SCD is capable of accommodating variable bar length, pitch and quantity for custom rod pumping geometries. The excellent all-around performance of the stacks is supported by reliability data in line with the previously reported 20 Gshot space-grade qualification of SCD's stacks.

Scaleable multi-format QCW pump stacks based on 200W laser diode bars and mini bars at 808nm and 940nm

NASA Astrophysics Data System (ADS)

Berk, Yuri; Karni, Yoram; Klumel, Genady; Openhaim, Yaakov; Cohen, Shalom; Yanson, Dan

2011-03-01

Advanced solid state laser architectures place increasingly demanding requirements on high-brightness, low-cost QCW laser diode pump sources, with custom apertures both for side and end rod pumping configurations. To meet this need, a new series of scaleable pump sources at 808nm and 940nm was developed. The stacks, available in multiple output formats, allow for custom aperture filling by varying both the length and quantity of stacked laser bars. For these products, we developed next-generation laser bars based on improved epitaxial wafer designs delivering power densities of 20W/mm of emission aperture. With >200W of peak QCW power available from a full-length 1cm bar, we have demonstrated power scaling to over 2kW in 10-bar stacks with 55% wall plug efficiency. We also present the design and performance of several stack configurations using full-length and reduced-length (mini) bars that demonstrate the versatility of both the bar and packaging designs. We illustrate how the ROBUST HEAD packaging technology developed at SCD is capable of accommodating variable bar length, pitch and quantity for custom rod pumping geometries. The excellent all-around performance of the stacks is supported by reliability data in line with the previously reported 20 Gshot space-grade qualification of SCD's stacks.

Centimeter-scale MEMS scanning mirrors for high power laser application

NASA Astrophysics Data System (ADS)

Senger, F.; Hofmann, U.; v. Wantoch, T.; Mallas, C.; Janes, J.; Benecke, W.; Herwig, Patrick; Gawlitza, P.; Ortega-Delgado, M.; Grune, C.; Hannweber, J.; Wetzig, A.

2015-02-01

A higher achievable scan speed and the capability to integrate two scan axes in a very compact device are fundamental advantages of MEMS scanning mirrors over conventional galvanometric scanners. There is a growing demand for biaxial high speed scanning systems complementing the rapid progress of high power lasers for enabling the development of new high throughput manufacturing processes. This paper presents concept, design, fabrication and test of biaxial large aperture MEMS scanning mirrors (LAMM) with aperture sizes up to 20 mm for use in high-power laser applications. To keep static and dynamic deformation of the mirror acceptably low all MEMS mirrors exhibit full substrate thickness of 725 μm. The LAMM-scanners are being vacuum packaged on wafer-level based on a stack of 4 wafers. Scanners with aperture sizes up to 12 mm are designed as a 4-DOF-oscillator with amplitude magnification applying electrostatic actuation for driving a motor-frame. As an example a 7-mm-scanner is presented that achieves an optical scan angle of 32 degrees at 3.2 kHz. LAMM-scanners with apertures sizes of 20 mm are designed as passive high-Q-resonators to be externally excited by low-cost electromagnetic or piezoelectric drives. Multi-layer dielectric coatings with a reflectivity higher than 99.9 % have enabled to apply cw-laser power loads of more than 600 W without damaging the MEMS mirror. Finally, a new excitation concept for resonant scanners is presented providing advantageous shaping of intensity profiles of projected laser patterns without modulating the laser. This is of interest in lighting applications such as automotive laser headlights.

Design, Operation, and Modeling of a Vertical APCVD Reactor for Silicon Carbide Film Growth

NASA Technical Reports Server (NTRS)

DeAnna, Russell G.; Fleischman, Aaron J.; Zorman, Christian A.; Mehregany, Mehran

1998-01-01

An atmospheric pressure chemical vapor deposition (APCVD) reactor utilizing a unique vertical geometry which enables 3C-SiC films to be grown on two, 4-inch diameter Si wafers has been constructed. Contrary to expectations, 3C-SiC films grown in this reactor are thickest at the downstream end of the substrates. To better understand the reason for the thickness distribution on the wafers, an axisymmetric finite-element model of the gas flow in the reactor was constructed. The model uses the ANSYS53 Flowtran package and includes compressible and temperature-dependent fluid properties in laminar or turbulent flow. It does not include reaction chemistry or unsteady flow. The ANSYS53 results predict that the cool, inlet fluid falls through the inlet pipe and the warm, diffuser region like a jet. This jet impinges on top of the susceptor and gets diverted to the reactor side walls, where it flows to the bottom of the reactor, turns, and slowly rises along the face of the susceptor. This may explain why the SiC films are thickest at the downstream side of the wafers, as gas containing fresh reactants first passes over this region. Modeling results are presented for both one atmosphere and one half atmosphere reactor pressure.

Fabrication of silicon films from patterned protruded seeds

NASA Astrophysics Data System (ADS)

Zeng, Huang; Zhang, Wei; Li, Jizhou; Wang, Cong; Yang, Hui; Chen, Yigang; Chen, Xiaoyuan; Liu, Dongfang

2017-05-01

Thin, flexible silicon crystals are starting up applications such as light-weighted flexible solar cells, SOI, flexible IC chips, 3D ICs imagers and 3D CMOS imagers on the demand of high performance with low cost. Kerfless wafering technology by direct conversion of source gases into mono-crystalline wafers on reusable substrates is highly cost-effective and feedstock-effective route to cheap wafers with the thickness down to several microns. Here we show a prototype for direct conversion of silicon source gases to wafers by using the substrate with protruded seeds. A reliable and controllable method of wafer-scaled preparation of protruded seed patterns has been developed by filling liquid wax into a rod array as the mask for the selective removal of oxide layer on the rod head. Selectively epitaxial growth is performed on the protruded seeds, and the voidless film is formed by the merging of neighboring seeds through growing. And structured hollows are formed between the grown film and the substrate, which would offer the transferability of the grown film and the reusability of the protruded seeds.

Micro-scale heat-exchangers for Joule-Thomson cooling.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gross, Andrew John

2014-01-01

This project focused on developing a micro-scale counter flow heat exchangers for Joule-Thomson cooling with the potential for both chip and wafer scale integration. This project is differentiated from previous work by focusing on planar, thin film micromachining instead of bulk materials. A process will be developed for fabricating all the devices mentioned above, allowing for highly integrated micro heat exchangers. The use of thin film dielectrics provides thermal isolation, increasing efficiency of the coolers compared to designs based on bulk materials, and it will allow for wafer-scale fabrication and integration. The process is intended to implement a CFHX asmore » part of a Joule-Thomson cooling system for applications with heat loads less than 1mW. This report presents simulation results and investigation of a fabrication process for such devices.« less

Particle detection for patterned wafers of 100nm design rule by evanescent light illumination: analysis of evanescent light scattering using Finite-Difference Time-Domain (FDTD) method

NASA Astrophysics Data System (ADS)

Yoshioka, Toshie; Miyoshi, Takashi; Takaya, Yasuhiro

2005-12-01

To realize high productivity and reliability of the semiconductor, patterned wafers inspection technology to maintain high yield becomes essential in modern semiconductor manufacturing processes. As circuit feature is scaled below 100nm, the conventional imaging and light scattering methods are impossible to apply to the patterned wafers inspection technique, because of diffraction limit and lower S/N ratio. So, we propose a new particle detection method using annular evanescent light illumination. In this method, a converging annular light used as a light source is incident on a micro-hemispherical lens. When the converging angle is larger than critical angle, annular evanescent light is generated under the bottom surface of the hemispherical lens. Evanescent light is localized near by the bottom surface and decays exponentially away from the bottom surface. So, the evanescent light selectively illuminates the particles on the patterned wafer surface, because it can't illuminate the patterned wafer surface. The proposed method evaluates particles on a patterned wafer surface by detecting scattered evanescent light distribution from particles. To analyze the fundamental characteristics of the proposed method, the computer simulation was performed using FDTD method. The simulation results show that the proposed method is effective for detecting 100nm size particle on patterned wafer of 100nm lines and spaces, particularly under the condition that the evanescent light illumination with p-polarization and parallel incident to the line orientation. Finally, the experiment results suggest that 220nm size particle on patterned wafer of about 200nm lines and spaces can be detected.

HED-TIE: A wafer-scale approach for fabricating hybrid electronic devices with trench isolated electrodes

NASA Astrophysics Data System (ADS)

Banerjee, Sreetama; Bülz, Daniel; Solonenko, Dmytro; Reuter, Danny; Deibel, Carsten; Hiller, Karla; Zahn, Dietrich R. T.; Salvan, Georgeta

2017-05-01

Organic-inorganic hybrid electronic devices (HEDs) offer opportunities for functionalities that are not easily obtainable with either organic or inorganic materials individually. In the strive for down-scaling the channel length in planar geometry HEDs, the best results were achieved with electron beam lithography or nanoimprint lithography. Their application on the wafer level is, however, cost intensive and time consuming. Here, we propose trench isolated electrode (TIE) technology as a fast, cost effective, wafer-level approach for the fabrication of planar HEDs with electrode gaps in the range of 100 nm. We demonstrate that the formation of the organic channel can be realized by deposition from solution as well as by the thermal evaporation of organic molecules. To underline one key feature of planar HED-TIEs, namely full accessibility of the active area of the devices by external stimuli such as light, 6,13-bis (triisopropylsilylethynyl) (TIPS)-pentacene/Au HED-TIEs are successfully tested for possible application as hybrid photodetectors in the visible spectral range.

Wafer-scale production of highly uniform two-dimensional MoS2 by metal-organic chemical vapor deposition

NASA Astrophysics Data System (ADS)

Kim, TaeWan; Mun, Jihun; Park, Hyeji; Joung, DaeHwa; Diware, Mangesh; Won, Chegal; Park, Jonghoo; Jeong, Soo-Hwan; Kang, Sang-Woo

2017-05-01

Semiconducting two-dimensional (2D) materials, particularly extremely thin molybdenum disulfide (MoS2) films, are attracting considerable attention from academia and industry owing to their distinctive optical and electrical properties. Here, we present the direct growth of a MoS2 monolayer with unprecedented spatial and structural uniformity across an entire 8 inch SiO2/Si wafer. The influences of growth pressure, ambient gases (Ar, H2), and S/Mo molar flow ratio on the MoS2 layered growth were explored by considering the domain size, nucleation sites, morphology, and impurity incorporation. Monolayer MoS2-based field effect transistors achieve an electron mobility of 0.47 cm2 V-1 s-1 and on/off current ratio of 5.4 × 104. This work demonstrates the potential for reliable wafer-scale production of 2D MoS2 for practical applications in next-generation electronic and optical devices.

Micro-machined resonator oscillator

DOEpatents

Koehler, Dale R.; Sniegowski, Jeffry J.; Bivens, Hugh M.; Wessendorf, Kurt O.

1994-01-01

A micro-miniature resonator-oscillator is disclosed. Due to the miniaturization of the resonator-oscillator, oscillation frequencies of one MHz and higher are utilized. A thickness-mode quartz resonator housed in a micro-machined silicon package and operated as a "telemetered sensor beacon" that is, a digital, self-powered, remote, parameter measuring-transmitter in the FM-band. The resonator design uses trapped energy principles and temperature dependence methodology through crystal orientation control, with operation in the 20-100 MHz range. High volume batch-processing manufacturing is utilized, with package and resonator assembly at the wafer level. Unique design features include squeeze-film damping for robust vibration and shock performance, capacitive coupling through micro-machined diaphragms allowing resonator excitation at the package exterior, circuit integration and extremely small (0.1 in. square) dimensioning. A family of micro-miniature sensor beacons is also disclosed with widespread applications as bio-medical sensors, vehicle status monitors and high-volume animal identification and health sensors. The sensor family allows measurement of temperatures, chemicals, acceleration and pressure. A microphone and clock realization is also available.

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Three Axes MEMS Combined Sensor for Electronic Stability Control System

NASA Astrophysics Data System (ADS)

Jeong, Heewon; Goto, Yasushi; Aono, Takanori; Nakamura, Toshiaki; Hayashi, Masahide

A microelectromechanical systems (MEMS) combined sensor measuring two-axis accelerations and an angular rate (rotation) has been developed for an electronic stability control system of automobiles. With the recent trend to mount the combined sensors in the engine compartment, the operation temperature range increased drastically, with the request of immunity to environmental disturbances such as vibration. In this paper, we report the combined sensor which has a gyroscopic part and two acceleration parts in single die. A deformation-robust MEMS structure has been adopted to achieve stable operation under wide temperature range (-40 to 125°C) in the engine compartment. A package as small as 10 × 19 × 4 mm is achieved by adopting TSV (through silicon via) and WLP (wafer-level package) technologies with enough performance as automotive grade.

A Basic Research for the Development and Evaluation of Novel MEMS Digital Accelerometers

DTIC Science & Technology

2013-02-01

that timing differences as measured by the circuit are linearly dependent on the measured capacitance changes. As such, the circuit’s readout is...error in the electronic measurement to refine the technique. An additional capability of the circuit is the ability to observe the impact of cold...low resistivity on (ɘ.01 Ω-cm) silicon on insulator wafers (SOI). The beams are fabricated in a 0.3 cm by 0.3 cm die which is then packaged and wire

Sensors and Micromachined Devices for the Automotive and New Markets: The Delphi Delco Electronics MEMS Story.

NASA Astrophysics Data System (ADS)

Logsdon, James

2002-03-01

This presentation will provide a brief history of the development of MEMS products and technology, beginning with the manifold absolute pressure sensor in the late seventies through the current variety of Delphi Delco Electronics sensors available today. The technology development of micromachining from uncompensated P plus etch stops to deep reactive ion etching and the technology development of wafer level packaging from electrostatic bonding to glass frit sealing and silicon to silicon direct bonding will be reviewed.

Injectable Ceramic Microcast Silicon Carbonitride (SiCN) Microelectromechanical System (MEMS) for Extreme Temperature Environments with Extension: Micro Packages for Nano-Devices

DTIC Science & Technology

2004-01-01

pyrolyzed to produce the ceramic (SiCN) parts, or they may be retained in the polymeric state and used as high-temperature polymer /glass MEMS devices. Two...structure and the SU8 /wafer is weak due to the Teflon coating. (j) A free standing polymer structure results. The structure is then crosslinked and... polymer . Further efforts are necessary to identify the least damaging rinsing chemicals, that is, chemicals which would not contaminate polymerized

Multi-Step Deep Reactive Ion Etching Fabrication Process for Silicon-Based Terahertz Components

NASA Technical Reports Server (NTRS)

Reck, Theodore (Inventor); Perez, Jose Vicente Siles (Inventor); Lee, Choonsup (Inventor); Cooper, Ken B. (Inventor); Jung-Kubiak, Cecile (Inventor); Mehdi, Imran (Inventor); Chattopadhyay, Goutam (Inventor); Lin, Robert H. (Inventor); Peralta, Alejandro (Inventor)

2016-01-01

A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

Influence of Si wafer thinning processes on (sub)surface defects

NASA Astrophysics Data System (ADS)

Inoue, Fumihiro; Jourdain, Anne; Peng, Lan; Phommahaxay, Alain; De Vos, Joeri; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik; Beyne, Eric; Uedono, Akira

2017-05-01

Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5 μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 μm. For the case of Si thinning towards 5 μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5-2 μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in between grinding and dry etch it is possible to significantly reduce not only the roughness, but also the remaining vacancies at the subsurface. The surface of grinding + CMP + dry etching gives an equivalent mono vacancy result as to that of grinding + CMP. This combination of thinning processes allows development of extremely thin 3D integration devices with minimal roughness and vacancy surface.

Toward the realization of erbium-doped GaN bulk crystals as a gain medium for high energy lasers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sun, Z. Y.; Li, J.; Zhao, W. P.

Er-doped GaN (Er:GaN) is a promising candidate as a gain medium for solid-state high energy lasers (HELs) at the technologically important and eye-safe 1.54 μm wavelength window, as GaN has superior thermal properties over traditional laser gain materials such as Nd:YAG. However, the attainment of wafer-scale Er:GaN bulk or quasi-bulk crystals is a prerequisite to realize the full potential of Er:GaN as a gain medium for HELs. We report the realization of freestanding Er:GaN wafers of 2-in. in diameter with a thickness on the millimeter scale. These freestanding wafers were obtained via growth by hydride vapor phase epitaxy in conjunction withmore » a laser-lift-off process. An Er doping level of 1.4 × 10{sup 20} atoms/cm{sup 3} has been confirmed by secondary ion mass spectrometry measurements. The freestanding Er:GaN wafers exhibit strong photoluminescent emission at 1.54 μm with its emission intensity increasing dramatically with wafer thickness under 980 nm resonant excitation. A low thermal quenching of 10% was measured for the 1.54 μm emission intensity between 10 K and 300 K. This work represents a significant step in providing a practical approach for producing Er:GaN materials with sufficient thicknesses and dimensions to enable the design of gain media in various geometries, allowing for the production of HELs with improved lasing efficiency, atmosphere transmission, and eye-safety.« less

Terahertz Array Receivers with Integrated Antennas

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam; Llombart, Nuria; Lee, Choonsup; Jung, Cecile; Lin, Robert; Cooper, Ken B.; Reck, Theodore; Siles, Jose; Schlecht, Erich; Peralta, Alessandro;

Engineering a nanostructured "super surface" with superhydrophobic and superkilling properties.

PubMed

Hasan, Jafar; Raj, Shammy; Yadav, Lavendra; Chatterjee, Kaushik

2015-05-12

We present a nanostructured "super surface" fabricated using a simple recipe based on deep reactive ion etching of a silicon wafer. The topography of the surface is inspired by the surface topographical features of dragonfly wings. The super surface is comprised of nanopillars 4 μm in height and 220 nm in diameter with random inter-pillar spacing. The surface exhibited superhydrophobicity with a static water contact angle of 154.0° and contact angle hysteresis of 8.3°. Bacterial studies revealed the bactericidal property of the surface against both gram negative ( Escherichia coli ) and gram positive ( Staphylococcus aureus ) strains through mechanical rupture of the cells by the sharp nanopillars. The cell viability on these nanostructured surfaces was nearly six-fold lower than on the unmodified silicon wafer. The nanostructured surface also killed mammalian cells (mouse osteoblasts) through mechanical rupture of the cell membrane. Thus, such nanostructured super surfaces could find applications for designing self-cleaning and anti-bacterial surfaces in diverse applications such as microfluidics, surgical instruments, pipelines and food packaging.

Optical inspection of hidden MEMS structures

NASA Astrophysics Data System (ADS)

Krauter, Johann; Gronle, Marc; Osten, Wolfgang

2017-06-01

Micro-electro-mechanical system's (MEMS) applications have greatly expanded over the recent years, and the MEMS industry has grown almost exponentially. One of the strongest drivers are the automotive and consumer markets. A 100% test is necessary especially in the production of automotive MEMS sensors since they are subject to safety relevant functions. This inspection should be carried out before dicing and packaging since more than 90% of the production costs are incurred during these steps. An electrical test is currently being carried out with each MEMS component. In the case of a malfunction, the defect can not be located on the wafer because the MEMS are no longer optically accessible due to the encapsulation. This paper presents a low coherence interferometer for the topography measurement of MEMS structures located within the wafer stack. Here, a high axial and lateral resolution is necessary to identify defects such as stuck or bent MEMS fingers. First, the boundary conditions for an optical inspection system will be discussed. The setup is then shown with some exemplary measurements.

27 CFR 19.276 - Package scales.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2010-04-01 2010-04-01 false Package scales. 19.276... Package scales. Proprietors shall ensure the accuracy of scales used for weighing packages of spirits through tests conducted at intervals of not more than 6 months or whenever scales are adjusted or repaired...

Single-shot optical recorder with sub-picosecond resolution and scalable record length on a semiconductor wafer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Muir, R.; Heebner, J.

In this study, we demonstrate a novel, single-shot recording technology for transient optical signals. A resolution of 0.4 ps over a record length of 54 ps was demonstrated. Here, a pump pulse crossing through a signal samples a diagonal “slice” of space–time, enabling a camera to record spatially the time content of the signal. Unlike related X (2)-based cross-correlation techniques, here the signal is sampled through optically pumped carriers that modify the refractive index of a silicon wafer. Surrounding the wafer with birefringent retarders enables two time-staggered, orthogonally polarized signal copies to probe the wafer. Recombining the copies at amore » final crossed polarizer destructively interferes with them, except during the brief stagger window, where a differential phase shift is incurred. This enables the integrating response of the rapidly excited but persistent carriers to be optically differentiated. Lastly, this sampling mechanism has several advantages that enable scaling to long record lengths, including making use of large, inexpensive semiconductor wafers, eliminating the need for phase matching, broad insensitivity to the spectral and angular properties of the pump, and overall hardware simplicity.« less

Single-shot optical recorder with sub-picosecond resolution and scalable record length on a semiconductor wafer

DOE PAGES

Muir, R.; Heebner, J.

2017-10-24

In this study, we demonstrate a novel, single-shot recording technology for transient optical signals. A resolution of 0.4 ps over a record length of 54 ps was demonstrated. Here, a pump pulse crossing through a signal samples a diagonal “slice” of space–time, enabling a camera to record spatially the time content of the signal. Unlike related X (2)-based cross-correlation techniques, here the signal is sampled through optically pumped carriers that modify the refractive index of a silicon wafer. Surrounding the wafer with birefringent retarders enables two time-staggered, orthogonally polarized signal copies to probe the wafer. Recombining the copies at amore » final crossed polarizer destructively interferes with them, except during the brief stagger window, where a differential phase shift is incurred. This enables the integrating response of the rapidly excited but persistent carriers to be optically differentiated. Lastly, this sampling mechanism has several advantages that enable scaling to long record lengths, including making use of large, inexpensive semiconductor wafers, eliminating the need for phase matching, broad insensitivity to the spectral and angular properties of the pump, and overall hardware simplicity.« less

"Performance Of A Wafer Stepper With Automatic Intra-Die Registration Correction."

NASA Astrophysics Data System (ADS)

van den Brink, M. A.; Wittekoek, S.; Linders, H. F. D.; van Hout, F. J.; George, R. A.

1987-01-01

An evaluation of a wafer stepper with the new improved Philips/ASM-L phase grating alignment system is reported. It is shown that an accurate alignment system needs an accurate X-Y-0 wafer stage and an accurate reticle Z stage to realize optimum overlay accuracy. This follows from a discussion of the overlay budget and an alignment procedure model. The accurate wafer stage permits high overlay accuracy using global alignment only, thus eliminating the throughput penalty of align-by-field schemes. The accurate reticle Z stage enables an intra-die magnification control with respect to the wafer scale. Various overlay data are reported, which have been measured with the automatic metrology program of the stepper. It is demonstrated that the new dual alignment system (with the external spatial filter) has improved the ability to align to weakly reflecting layers. The results are supported by a Fourier analysis of the alignment signal. Resolution data are given for the PAS 2500 projection lenses, which show that the high overlay accuracy of the system is properly matched with submicron linewidth control. The results of a recently introduced 20mm i-line lens with a numerical aperture of 0.4 (Zeiss 10-78-58) are included.

Contacting graphene in a 200 mm wafer silicon technology environment

NASA Astrophysics Data System (ADS)

Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

2018-06-01

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

Advances in CCD detector technology for x-ray diffraction applications

NASA Astrophysics Data System (ADS)

Thorson, Timothy A.; Durst, Roger D.; Frankel, Dan; Bordwell, Rex L.; Camara, Jose R.; Leon-Guerrero, Edward; Onishi, Steven K.; Pang, Francis; Vu, Paul; Westbrook, Edwin M.

2004-01-01

Phosphor-coupled CCDs are established as one of the most successful technologies for x-ray diffraction. This application demands that the CCD simultaneously achieve both the highest possible sensitivity and high readout speeds. Recently, wafer-scale, back illuminated devices have become available which offer significantly higher quantum efficiency than conventional devices (the Fairchild Imaging CCD 486 BI). However, since back thinning significantly changes the electrical properties of the CCD the high speed operation of wafer-scale, back-illuminated devices is not well understood. Here we describe the operating characteristics (including noise, linearity, full well capacity and CTE) of the back-illuminated CCD 486 at readout speeds up to 4 MHz.

Soft x-ray speckle from rough surfaces

NASA Astrophysics Data System (ADS)

Porter, Matthew Stanton

Dynamic light scattering has been of great use in determining diffusion times for polymer solutions. At the same time, polymer thin films are becoming of increasing importance, especially in the semiconductor industry where they are used as photoresists and interlevel dielectrics. As the dimensions of these devices decrease we will reach a point where lasers will no longer be able to probe the length scales of interest. Current laser wavelengths limit the size of observable diffusion lengths to 180-700 nm. This dissertation will discuss attempts at pushing dynamic fight scattering experiments into the soft x-ray region so that we can examine fluctuations in polymer thin films on the molecular length scale. The dissertation explores the possibility of carrying out a dynamic light scattering experiment in the soft x-ray regime. A detailed account of how to meet the basic requirements for a coherent scattering experiment in the soft x-ray regime win be given. In addition, a complete description of the chamber design will be discussed. We used our custom designed scattering chamber to collect reproducible coherent soft x-ray scattering data from etched silicon wafers and from polystyrene coated silicon wafers. The data from the silicon wafers followed the statistics for a well-developed speckle pattern while the data from the polystyrene films exhibited Poisson statistics. We used the data from both the etched wafers and the polystyrene coated wafers to place a lower limit of ~20 Å on the RMS surface roughness of samples which will produce well defined speckle patterns for the current detector setup. Future experiments which use the criteria set forth in this dissertation have the opportunity to be even more successful than this dissertation project.

Split-mode ultrasonic transducer.

PubMed

Ostrovskii, Igor; Cremaldi, Lucien

2013-08-01

A split-mode ultrasonic transducer is investigated in both theory and experiment. This transducer is a two-dimensional structure of periodically poled domains in a ferroelectric wafer with free surfaces. The acoustic vibrations are excited by a radio frequency electric current applied along the length of the wafer, which allows the basal-plane surfaces to be free of metal coatings and thus ready for further biomedical applications. A specific physical property of this transducer consists of the multiple acousto-electric resonances, which occur due to an acoustic mode split when the acoustic half-wavelength is equal to the domain length. Possible applications include ultrasonic generation and detection at the micro-scale, intravascular sonification and visualization, ultrasound therapy of localized small areas such as the eye, biomedical applications for cell cultures, and traditional nondestructive testing including bones and tissues. A potential use of a non-metallized wafer is a therapeutic application with double action that is both ultrasound itself and an electric field over the wafer. The experimental measurements and theoretical calculations are in good agreement.

Virtual optical interfaces for the transportation industry

NASA Astrophysics Data System (ADS)

Hejmadi, Vic; Kress, Bernard

2010-04-01

We present a novel implementation of virtual optical interfaces for the transportation industry (automotive and avionics). This new implementation includes two functionalities in a single device; projection of a virtual interface and sensing of the position of the fingers on top of the virtual interface. Both functionalities are produced by diffraction of laser light. The device we are developing include both functionalities in a compact package which has no optical elements to align since all of them are pre-aligned on a single glass wafer through optical lithography. The package contains a CMOS sensor which diffractive objective lens is optimized for the projected interface color as well as for the IR finger position sensor based on structured illumination. Two versions are proposed: a version which senses the 2d position of the hand and a version which senses the hand position in 3d.

Slicing of silicon into sheet material. Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project. Third quarterly report, September 20, 1976--December 19, 1976

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holden, S.C.

1976-12-27

The stability of tensioned blades used in multiblade sawing does not seem to be the limitation in cutting with thin blades. So far, 0.010 cm thick blades have been totally unsuccessful. Recently, 0.015 cm blades have proven successful in wafering, offering an 0.005 cm reduction in the silicon used per slice. The failure of thin blades is characterized as a possible result of blade misalignment or from the inherent uncontrollability of the loose abrasive multiblade process. Corrective procedures will be employed in the assembly of packages to eliminate one type of blade misalignment. Two ingots were sliced with the samemore » batch of standard silicon carbide abrasive slurry to determine the useful lifetime of this expendable material. After 250 slices, the cutting efficiency had not degraded. Further tests will be continued to establish the maximum lifetime of both silicon carbide and boron carbide abrasive. Electron microscopy will be employed to evaluate the wear of abrasive particles in the failure of abrasive slurry. The surface damage of silicon wafers has been characterized as predominantly subsurface fracture. Damage with No. 600 SiC is between 10 and 15 microns into the wafer surface. This agrees well with previous investigations of damage from silicon carbide abrasive papers.« less

An all-silicon single-wafer micro-g accelerometer with a combined surface and bulk micromachining process

NASA Technical Reports Server (NTRS)

Yazdi, N.; Najafi, K.

2000-01-01

This paper reports an all-silicon fully symmetrical z-axis micro-g accelerometer that is fabricated on a single-silicon wafer using a combined surface and bulk fabrication process. The microaccelerometer has high device sensitivity, low noise, and low/controllable damping that are the key factors for attaining micro g and sub-micro g resolution in capacitive accelerometers. The microfabrication process produces a large proof mass by using the whole wafer thickness and a large sense capacitance by utilizing a thin sacrificial layer. The sense/feedback electrodes are formed by a deposited 2-3 microns polysilicon film with embedded 25-35 microns-thick vertical stiffeners. These electrodes, while thin, are made very stiff by the thick embedded stiffeners so that force rebalancing of the proof mass becomes possible. The polysilicon electrodes are patterned to create damping holes. The microaccelerometers are batch-fabricated, packaged, and tested successfully. A device with a 2-mm x 1-mm proof mass and a full bridge support has a measured sensitivity of 2 pF/g. The measured sensitivity of a 4-mm x 1-mm accelerometer with a cantilever support is 19.4 pF/g. The calculated noise floor of these devices at atmosphere are 0.23 micro g/sqrt(Hz) and 0.16 micro g/sqrt(Hz), respectively.

A micro-scale plasma spectrometer for space and plasma edge applications (invited)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scime, E. E., E-mail: escime@wvu.edu; Keesee, A. M.; Elliott, D.

2016-11-15

A plasma spectrometer design based on advances in lithography and microchip stacking technologies is described. A series of curved plate energy analyzers, with an integrated collimator, is etched into a silicon wafer. Tests of spectrometer elements, the energy analyzer and collimator, were performed with a 5 keV electron beam. The measured collimator transmission and energy selectivity were in good agreement with design targets. A single wafer element could be used as a plasma processing or fusion first wall diagnostic.

High-resolution and Fast-response Fiber-optic Temperature Sensor Using Silicon Fabry-Perot Cavity

DTIC Science & Technology

2015-03-23

silver diaphragm,” Opt. Lett. 37(9), 1505–1507 (2012). 18. I. M. White and X. D. Fan , “On the performance quantification of resonant refractive index...to the response time, the package of a FBG with a copper tube encapsulation can greatly reduce the response time of the sensor from several seconds...head shown in Fig. 1(b) are described in Fig. 2. The fabrication started with bonding a 200-µm-thick double-side-polished silicon wafer on top of

A new fabrication technique for back-to-back varactor diodes

NASA Technical Reports Server (NTRS)

Smith, R. Peter; Choudhury, Debabani; Martin, Suzanne; Frerking, Margaret A.; Liu, John K.; Grunthaner, Frank A.

1992-01-01

A new varactor diode process has been developed in which much of the processing is done from the back of an extremely thin semiconductor wafer laminated to a low-dielectric substrate. Back-to-back BNN diodes were fabricated with this technique; excellent DC and low-frequency capacitance measurements were obtained. Advantages of the new technique relative to other techniques include greatly reduced frontside wafer damage from exposure to process chemicals, improved capability to integrate devices (e.g. for antenna patterns, transmission lines, or wafer-scale grids), and higher line yield. BNN diodes fabricated with this technique exhibit approximately the expected capacitance-voltage characteristics while showing leakage currents under 10 mA at voltages three times that needed to deplete the varactor. This leakage is many orders of magnitude better than comparable Schottky diodes.

Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

NASA Astrophysics Data System (ADS)

Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

2016-08-01

Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

NASA Technical Reports Server (NTRS)

Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.;

Micro-machined resonator oscillator

DOEpatents

Koehler, D.R.; Sniegowski, J.J.; Bivens, H.M.; Wessendorf, K.O.

1994-08-16

A micro-miniature resonator-oscillator is disclosed. Due to the miniaturization of the resonator-oscillator, oscillation frequencies of one MHz and higher are utilized. A thickness-mode quartz resonator housed in a micro-machined silicon package and operated as a telemetered sensor beacon'' that is, a digital, self-powered, remote, parameter measuring-transmitter in the FM-band. The resonator design uses trapped energy principles and temperature dependence methodology through crystal orientation control, with operation in the 20--100 MHz range. High volume batch-processing manufacturing is utilized, with package and resonator assembly at the wafer level. Unique design features include squeeze-film damping for robust vibration and shock performance, capacitive coupling through micro-machined diaphragms allowing resonator excitation at the package exterior, circuit integration and extremely small (0.1 in. square) dimensioning. A family of micro-miniature sensor beacons is also disclosed with widespread applications as bio-medical sensors, vehicle status monitors and high-volume animal identification and health sensors. The sensor family allows measurement of temperatures, chemicals, acceleration and pressure. A microphone and clock realization is also available. 21 figs.

Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

PubMed Central

Jeong, Seong-Jun; Gu, Yeahyun; Heo, Jinseong; Yang, Jaehyun; Lee, Chang-Seok; Lee, Min-Hyun; Lee, Yunseong; Kim, Hyoungsub; Park, Seongjun; Hwang, Sungwoo

2016-01-01

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer. PMID:26861833

A randomized controlled trial to assess the pain associated with the debond of orthodontic fixed appliances

PubMed Central

Mangnall, Louise A R; Dietrich, Thomas; Scholey, John M

2013-01-01

Objective: To determine patient experience of pain during treatment with fixed orthodontic appliances, expectations of pain during debond and whether biting on a soft acrylic wafer during debond decreases pain experience. Design: Multicentre randomized controlled trial. Setting: Three UK hospital based orthodontic departments: Mid-Staffordshire NHS Foundation Trust, Birmingham Dental Hospital and University Hospital of North Staffordshire. Materials and methods: Ninety patients were randomly allocated to either the control (n = 45) or wafer group (n = 45). A visual analogue scale-based questionnaire was completed pre-debond to determine pain experience during treatment and expectations of pain during debond. The appliances were debonded and those in the wafer group bit on a soft acrylic wafer. A second questionnaire was completed post-debond to assess the pain experienced. Results: Biting on an acrylic wafer significantly reduced the pain experienced when debonding the posterior teeth (P≤0·05). Thirty-nine per cent found the lower anterior teeth the most painful. The expected pain was significantly greater than that actually experienced (P≤0·0001). Greater pain during treatment correlated with increased expectations and increased actually experienced pain (P≤0·0001). Conclusions: Biting on a soft acrylic wafer during debond of the posterior teeth reduces the pain experienced. The lower anterior teeth are the most painful. The pain expected is significantly greater than actually experienced. Patients who had greater pain during treatment expected and experienced greater pain at debond. PMID:24009318

Wafer-Scale and Wrinkle-Free Epitaxial Growth of Single-Orientated Multilayer Hexagonal Boron Nitride on Sapphire.

PubMed

Jang, A-Rang; Hong, Seokmo; Hyun, Chohee; Yoon, Seong In; Kim, Gwangwoo; Jeong, Hu Young; Shin, Tae Joo; Park, Sung O; Wong, Kester; Kwak, Sang Kyu; Park, Noejung; Yu, Kwangnam; Choi, Eunjip; Mishchenko, Artem; Withers, Freddie; Novoselov, Kostya S; Lim, Hyunseob; Shin, Hyeon Suk

2016-05-11

Large-scale growth of high-quality hexagonal boron nitride has been a challenge in two-dimensional-material-based electronics. Herein, we present wafer-scale and wrinkle-free epitaxial growth of multilayer hexagonal boron nitride on a sapphire substrate by using high-temperature and low-pressure chemical vapor deposition. Microscopic and spectroscopic investigations and theoretical calculations reveal that synthesized hexagonal boron nitride has a single rotational orientation with AA' stacking order. A facile method for transferring hexagonal boron nitride onto other target substrates was developed, which provides the opportunity for using hexagonal boron nitride as a substrate in practical electronic circuits. A graphene field effect transistor fabricated on our hexagonal boron nitride sheets shows clear quantum oscillation and highly improved carrier mobility because the ultraflatness of the hexagonal boron nitride surface can reduce the substrate-induced degradation of the carrier mobility of two-dimensional materials.

Getting small: new 10μm pixel pitch cooled infrared products

NASA Astrophysics Data System (ADS)

Reibel, Y.; Pere-Laperne, N.; Augey, T.; Rubaldo, L.; Decaens, G.; Bourqui, M.-L.; Manissadjian, A.; Billon-Lanfrey, D.; Bisotto, S.; Gravrand, O.; Destefanis, G.; Druart, G.; Guerineau, N.

2014-06-01

Recent advances in miniaturization of IR imaging technology have led to a burgeoning market for mini thermalimaging sensors. Seen in this context our development on smaller pixel pitch has opened the door to very compact products. When this competitive advantage is mixed with smaller coolers, thanks to HOT technology, we achieve valuable reductions in size, weight and power of the overall package. In the same time, we are moving towards a global offer based on digital interfaces that provides our customers lower power consumption and simplification on the IR system design process while freeing up more space. Additionally, we are also investigating new wafer level camera solution taking advantage of the progress in micro-optics. This paper discusses recent developments on hot and small pixel pitch technologies as well as efforts made on compact packaging solution developed by SOFRADIR in collaboration with CEA-LETI and ONERA.

Eutectic-based wafer-level-packaging technique for piezoresistive MEMS accelerometers and bond characterization using molecular dynamics simulations

NASA Astrophysics Data System (ADS)

Aono, T.; Kazama, A.; Okada, R.; Iwasaki, T.; Isono, Y.

2018-03-01

We developed a eutectic-based wafer-level-packaging (WLP) technique for piezoresistive micro-electromechanical systems (MEMS) accelerometers on the basis of molecular dynamics analyses and shear tests of WLP accelerometers. The bonding conditions were experimentally and analytically determined to realize a high shear strength without solder material atoms diffusing to adhesion layers. Molecular dynamics (MD) simulations and energy dispersive x-ray (EDX) spectrometry done after the shear tests clarified the eutectic reaction of the solder materials used in this research. Energy relaxation calculations in MD showed that the diffusion of solder material atoms into the adhesive layer was promoted at a higher temperature. Tensile creep MD simulations also suggested that the local potential energy in a solder material model determined the fracture points of the model. These numerical results were supported by the shear tests and EDX analyses for WLP accelerometers. Consequently, a bonding load of 9.8 kN and temperature of 300 °C were found to be rational conditions because the shear strength was sufficient to endure the polishing process after the WLP process and there was little diffusion of solder material atoms to the adhesion layer. Also, eutectic-bonding-based WLP was effective for controlling the attenuation of the accelerometers by determining the thickness of electroplated solder materials that played the role of a cavity between the accelerometers and lids. If the gap distance between the two was less than 6.2 µm, the signal gains for x- and z-axis acceleration were less than 20 dB even at the resonance frequency due to air-damping.

Signal processing techniques for damage detection with piezoelectric wafer active sensors and embedded ultrasonic structural radar

NASA Astrophysics Data System (ADS)

Yu, Lingyu; Bao, Jingjing; Giurgiutiu, Victor

2004-07-01

Embedded ultrasonic structural radar (EUSR) algorithm is developed for using piezoelectric wafer active sensor (PWAS) array to detect defects within a large area of a thin-plate specimen. Signal processing techniques are used to extract the time of flight of the wave packages, and thereby to determine the location of the defects with the EUSR algorithm. In our research, the transient tone-burst wave propagation signals are generated and collected by the embedded PWAS. Then, with signal processing, the frequency contents of the signals and the time of flight of individual frequencies are determined. This paper starts with an introduction of embedded ultrasonic structural radar algorithm. Then we will describe the signal processing methods used to extract the time of flight of the wave packages. The signal processing methods being used include the wavelet denoising, the cross correlation, and Hilbert transform. Though hardware device can provide averaging function to eliminate the noise coming from the signal collection process, wavelet denoising is included to ensure better signal quality for the application in real severe environment. For better recognition of time of flight, cross correlation method is used. Hilbert transform is applied to the signals after cross correlation in order to extract the envelope of the signals. Signal processing and EUSR are both implemented by developing a graphical user-friendly interface program in LabView. We conclude with a description of our vision for applying EUSR signal analysis to structural health monitoring and embedded nondestructive evaluation. To this end, we envisage an automatic damage detection application utilizing embedded PWAS, EUSR, and advanced signal processing.

Switchable static friction of piezoelectric composite—silicon wafer contacts

NASA Astrophysics Data System (ADS)

van den Ende, D. A.; Fischer, H. R.; Groen, W. A.; van der Zwaag, S.

2013-04-01

The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and a silicon wafer counter surface rests solely on the matrix region of the piezocomposite surface. When actuated, the piezoelectric ceramic fibers protrude from the surface and the wafer rests solely on these protrusions. A threefold decrease in engineering static friction coefficient upon actuation of the piezocomposite was observed: from μ* = 1.65 to μ* = 0.50. These experimental results could be linked to the change in contact surface area and roughness using capillary adhesion theory, which relates the adhesive force to the number and size of the contacting asperities for the different surface states.

Wafer-scale aluminum nano-plasmonics

NASA Astrophysics Data System (ADS)

George, Matthew C.; Nielson, Stew; Petrova, Rumyana; Frasier, James; Gardner, Eric

2014-09-01

The design, characterization, and optical modeling of aluminum nano-hole arrays are discussed for potential applications in surface plasmon resonance (SPR) sensing, surface-enhanced Raman scattering (SERS), and surface-enhanced fluorescence spectroscopy (SEFS). In addition, recently-commercialized work on narrow-band, cloaked wire grid polarizers composed of nano-stacked metal and dielectric layers patterned over 200 mm diameter wafers for projection display applications is reviewed. The stacked sub-wavelength nanowire grid results in a narrow-band reduction in reflectance by 1-2 orders of magnitude, which can be tuned throughout the visible spectrum for stray light control.

Survival of epiphytic bacteria from seed stored on the Long Duration Exposure Facility (LDEF)

NASA Technical Reports Server (NTRS)

Schuerger, Andrew C.; Norman, Bret L.; Angelo, Joseph A., Jr.

1991-01-01

This study was designed to determine the survival of microorganisms exposed to the relatively harsh conditions found in low Earth orbit (LEO). Seed of corn, sunflower, canteloupe, zucchini, bean, pea, and pumpkin cultivars were packaged in two 18 x 2.5 cm aluminum tubes; wall thickness for each tube was 1.33 mm. One seed tube was attacked to payload M0006, tray C-2; a second tube was stored at room temperature in a lab on Earth. Five lithium fluoride thermoluminescent dosimetry wafers (TLD-100 wafers) were placed in each aluminum tube. The total mean dosages for flight and ground-control TLD wafers were 210.0 and 0.9 rads, respectively. Seeds were washed for 2 hrs in a phosphate buffered saline solution. Bacteria were isolated by plating samples of the seed-washings onto dilute tryptic soy agar. Pure isolates of morphologically distinct bacteria were obtained by standard microbiological procedures. Bacteria were grouped according to colony-type and preliminary identification was completed using a fatty-acid analysis system. Bacillus spp. were the primary microoganisms that survived on seed during the experiment. Bacterial diversity and relative abundance were similar for the ground flight seed. Bacillus subtilus, B. pumilus, B. licheniformis, B. polymyxa, B. megaterium, and B. pabuli were isolated most frequently. Members of the genera Kurthia, Listeria, Micrococcus, and Arthrobacter were also isolated from flight and ground control seed. Results support the hypothesis that terrestrial microorganisms can survive long periods of time in the relatively harsh LEO environment.

Optoelectronic interconnects for 3D wafer stacks

NASA Astrophysics Data System (ADS)

Ludwig, David E.; Carson, John C.; Lome, Louis S.

1996-01-01

Wafer and chip stacking are envisioned as a means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper provides definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies are discussed.

Optoelectronic interconnects for 3D wafer stacks

NASA Astrophysics Data System (ADS)

Ludwig, David; Carson, John C.; Lome, Louis S.

1996-01-01

Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.

Integrated Arrays on Silicon at Terahertz Frequencies

NASA Technical Reports Server (NTRS)

Chattopadhayay, Goutam; Lee, Choonsup; Jung, Cecil; Lin, Robert; Peralta, Alessandro; Mehdi, Imran; Llombert, Nuria; Thomas, Bertrand

2011-01-01

In this paper we explore various receiver font-end and antenna architecture for use in integrated arrays at terahertz frequencies. Development of wafer-level integrated terahertz receiver front-end by using advanced semiconductor fabrication technologies and use of novel integrated antennas with silicon micromachining are reported. We report novel stacking of micromachined silicon wafers which allows for the 3-dimensional integration of various terahertz receiver components in extremely small packages which easily leads to the development of 2- dimensioanl multi-pixel receiver front-ends in the terahertz frequency range. We also report an integrated micro-lens antenna that goes with the silicon micro-machined front-end. The micro-lens antenna is fed by a waveguide that excites a silicon lens antenna through a leaky-wave or electromagnetic band gap (EBG) resonant cavity. We utilized advanced semiconductor nanofabrication techniques to design, fabricate, and demonstrate a super-compact, low-mass submillimeter-wave heterodyne frontend. When the micro-lens antenna is integrated with the receiver front-end we will be able to assemble integrated heterodyne array receivers for various applications such as multi-pixel high resolution spectrometer and imaging radar at terahertz frequencies.

Silver free III-nitride flip chip light-emitting-diode with wall plug efficiency over 70% utilizing a GaN tunnel junction

NASA Astrophysics Data System (ADS)

Yonkee, B. P.; Young, E. C.; DenBaars, S. P.; Nakamura, S.; Speck, J. S.

2016-11-01

A molecular beam epitaxy regrowth technique was demonstrated on standard industrial patterned sapphire substrate light-emitting diode (LED) epitaxial wafers emitting at 455 nm to form a GaN tunnel junction. By using an HF pretreatment on the wafers before regrowth, a voltage of 3.08 V at 20 A/cm2 was achieved on small area devices. A high extraction package was developed for comparison with flip chip devices which utilize an LED floating in silicone over a BaSO4 coated header and produced a peak external quantum efficiency (EQE) of 78%. A high reflectivity mirror was designed using a seven-layer dielectric coating backed by aluminum which has a calculated angular averaged reflectivity over 98% between 400 and 500 nm. This was utilized to fabricate a flip chip LED which had a peak EQE and wall plug efficiency of 76% and 73%, respectively. This flip chip could increase light extraction over a traditional flip chip LED due to the increased reflectivity of the dielectric based mirror.

Future Development of Dense Ferroelectric Memories for Space Applications

NASA Technical Reports Server (NTRS)

Philpy, Stephen C.; Derbenwick, Gary F.

2001-01-01

The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.

Sidewall patterning—a new wafer-scale method for accurate patterning of vertical silicon structures

NASA Astrophysics Data System (ADS)

Westerik, P. J.; Vijselaar, W. J. C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G. E.

2018-01-01

For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that allows for reproducible sub-micrometer resolution local modification along vertical silicon sidewalls. Instead of optical lithography, this method makes smart use of inclined ion beam etching to selectively etch the top parts of structures, and controlled retraction of a conformal layer to define a hard mask in the vertical direction. The top, bottom or middle part of a structure could be selectively exposed, and it was shown that these exposed regions can, for example, be selectively covered with a catalyst, doped, or structured further.

Addressable test matrix for measuring analog transfer characteristics of test elements used for integrated process control and device evaluation

NASA Technical Reports Server (NTRS)

Buehler, Martin G. (Inventor)

1988-01-01

A set of addressable test structures, each of which uses addressing schemes to access individual elements of the structure in a matrix, is used to test the quality of a wafer before integrated circuits produced thereon are diced, packaged and subjected to final testing. The electrical characteristic of each element is checked and compared to the electrical characteristic of all other like elements in the matrix. The effectiveness of the addressable test matrix is in readily analyzing the electrical characteristics of the test elements and in providing diagnostic information.

Mobil Solar Energy Corporation thin EFG octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-06-01

Mobil Solar Energy Corporation manufactures photovoltaic modules based on its unique Edge-defined Film-fed Growth (EFG) process for producing octagon-shaped hollow polycrystalline silicon tubes. The octagons are cut by lasers into 100 mm x 100 mm wafers which are suitable for solar cell processing. This process avoids slicing, grinding and polishing operations which are wasteful of material and are typical of most other wafer production methods. EFG wafers are fabricated into solar cells and modules using processes that have been specially developed to allow scaling up to high throughput rates. The goals of the Photovoltaic Manufacturing Technology Initiative (PVMaT) program at Mobil Solar were to improve the EFG manufacturing line through technology advances that accelerate cost reduction in production and stimulate market growth for its product. The program was structured into three main tasks: to decrease silicon utilization by lowering wafer thickness from 400 to 200 (mu)m; to enhance laser cutting yields and throughput while improving the wafer strength; and to raise crystal growth productivity and yield. The technical problems faced and the advances made in the Mobil Solar PVMaT program are described. The author concludes with a presentation of the results of a detailed cost model for EFT module production. This model describes the accelerated reductions in manufacturing costs which are already in place and the future benefits anticipated to result from the technical achievements of the PVMaT program.

Fabrication of Fresnel micro lens array in borosilicate glass by F2-laser ablation for glass interposer application

NASA Astrophysics Data System (ADS)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning; Fricke-Begemann, Thomas; Ihlemann, Jürgen

2014-03-01

The future need for more bandwidth forces the development of optical transmission solutions for rack-to-rack, boardto- board and chip-to-chip interconnects. The goals are significant reduction of power consumption, highest density and potential for bandwidth scalability to overcome the limitations of the systems today with mostly copper based interconnects. For system integration the enabling of thin glass as a substrate material for electro-optical components with integrated micro-optics for efficient light coupling to integrated optical waveguides or fibers is becoming important. Our glass based packaging approach merges micro-system packaging and glass integrated optics. This kind of packaging consists of a thin glass substrate with integrated micro lenses providing a platform for photonic component assembly and optical fiber or waveguide interconnection. Thin glass is commercially available in panel and wafer size and characterizes excellent optical and high frequency properties. That makes it perfect for microsystem packaging. A suitable micro lens approach has to be comparable with different commercial glasses and withstand post-processing like soldering. A benefit of using laser ablated Fresnel lenses is the planar integration capability in the substrate for highest integration density. In the paper we introduce our glass based packaging concept and the Fresnel lens design for different scenarios like chip-to-fiber, chip-to-optical-printed-circuit-board coupling. Based on the design the Fresnel lenses were fabricated by using a 157 nm fluorine laser ablation system.

Reward-based learning under hardware constraints-using a RISC processor embedded in a neuromorphic substrate.

PubMed

Friedmann, Simon; Frémaux, Nicolas; Schemmel, Johannes; Gerstner, Wulfram; Meier, Karlheinz

2013-01-01

In this study, we propose and analyze in simulations a new, highly flexible method of implementing synaptic plasticity in a wafer-scale, accelerated neuromorphic hardware system. The study focuses on globally modulated STDP, as a special use-case of this method. Flexibility is achieved by embedding a general-purpose processor dedicated to plasticity into the wafer. To evaluate the suitability of the proposed system, we use a reward modulated STDP rule in a spike train learning task. A single layer of neurons is trained to fire at specific points in time with only the reward as feedback. This model is simulated to measure its performance, i.e., the increase in received reward after learning. Using this performance as baseline, we then simulate the model with various constraints imposed by the proposed implementation and compare the performance. The simulated constraints include discretized synaptic weights, a restricted interface between analog synapses and embedded processor, and mismatch of analog circuits. We find that probabilistic updates can increase the performance of low-resolution weights, a simple interface between analog synapses and processor is sufficient for learning, and performance is insensitive to mismatch. Further, we consider communication latency between wafer and the conventional control computer system that is simulating the environment. This latency increases the delay, with which the reward is sent to the embedded processor. Because of the time continuous operation of the analog synapses, delay can cause a deviation of the updates as compared to the not delayed situation. We find that for highly accelerated systems latency has to be kept to a minimum. This study demonstrates the suitability of the proposed implementation to emulate the selected reward modulated STDP learning rule. It is therefore an ideal candidate for implementation in an upgraded version of the wafer-scale system developed within the BrainScaleS project.

Reward-based learning under hardware constraints—using a RISC processor embedded in a neuromorphic substrate

PubMed Central

Friedmann, Simon; Frémaux, Nicolas; Schemmel, Johannes; Gerstner, Wulfram; Meier, Karlheinz

2013-01-01

In this study, we propose and analyze in simulations a new, highly flexible method of implementing synaptic plasticity in a wafer-scale, accelerated neuromorphic hardware system. The study focuses on globally modulated STDP, as a special use-case of this method. Flexibility is achieved by embedding a general-purpose processor dedicated to plasticity into the wafer. To evaluate the suitability of the proposed system, we use a reward modulated STDP rule in a spike train learning task. A single layer of neurons is trained to fire at specific points in time with only the reward as feedback. This model is simulated to measure its performance, i.e., the increase in received reward after learning. Using this performance as baseline, we then simulate the model with various constraints imposed by the proposed implementation and compare the performance. The simulated constraints include discretized synaptic weights, a restricted interface between analog synapses and embedded processor, and mismatch of analog circuits. We find that probabilistic updates can increase the performance of low-resolution weights, a simple interface between analog synapses and processor is sufficient for learning, and performance is insensitive to mismatch. Further, we consider communication latency between wafer and the conventional control computer system that is simulating the environment. This latency increases the delay, with which the reward is sent to the embedded processor. Because of the time continuous operation of the analog synapses, delay can cause a deviation of the updates as compared to the not delayed situation. We find that for highly accelerated systems latency has to be kept to a minimum. This study demonstrates the suitability of the proposed implementation to emulate the selected reward modulated STDP learning rule. It is therefore an ideal candidate for implementation in an upgraded version of the wafer-scale system developed within the BrainScaleS project. PMID:24065877

Modifications of Fabrication of Vibratory Microgyroscopes

NASA Technical Reports Server (NTRS)

Bae, Sam Y.; Yee, Karl Y.; Wiberg, Dean

2005-01-01

A micromachining process for the fabrication of vibratory microgyroscopes from silicon wafers, and aspects of the microgyroscope design that are inextricably linked with the fabrication process, have been modified in an effort to increase production yields from perspectives of both quantity and quality. Prior to the modifications, the effective production yield of working microgyroscopes was limited to one or less per wafer. The modifications are part of a continuing effort to improve the design and increase production yields to more than 30 working microgyroscopes per wafer. A discussion of pertinent aspects of the unmodified design and the unmodified fabrication process is prerequisite to a meaningful description of the modifications. The design of the microgyroscope package was not conducive to high yield and rapid testing of many microgyroscopes. One of the major impediments to high yield and testing was found to lie in vibration- isolation beams around the four edges of each microgyroscope, which beams were found to be unnecessary for achieving high resonance quality factors (Q values) characterizing the vibrations of petallike cantilevers. The fabrication process included an 8- m-deep plasma etch. The purpose of the etch was to create 8- m vertical gaps, below which were to be placed large gold evaporated electrodes and sensing pads to drive and sense resonant vibrations of the "petals." The process also included a step in which bridges between dies were cut to separate the dies. The etched areas must be kept clean and smooth (free of debris and spikes), because any object close to 8 m high in those areas would stop the vibrations. However, it was found that after the etch, there remained some spikes with heights that were, variously, almost as high or as high as the etch depth. It also was found that the cutting of bridges created silicon debris, some of which lodged in the 8- m gaps and some of which landed on top of the petals. The masses added to the petals by the debris altered resonance frequencies and/or Q values to unacceptable degrees. Hence, the spikes and the debris have been conjectured to cause most of the observed malfunctions of newly fabricated microgyroscopes. Another pertinent aspect of the unmodified design and process was the fabrication of electrodes and the 8- m capacitance gap on a 500- m-thick wafer, and the fabrication of a 3-mm-thick baseplate from another wafer. It was necessary to bond these wafers to each other in an assembly step that was later found to be superfluous in that it could be eliminated by a suitable modification of the design.

System and Method for Fabricating Super Conducting Circuitry on Both Sides of an Ultra-Thin Layer

NASA Technical Reports Server (NTRS)

Brown, Ari D. (Inventor); Mikula, Vilem (Inventor)

2017-01-01

A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.

Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

DOE PAGES

Berman, Diana; Deshmukh, Sanket; Narayanan, Badri; ...

2016-07-04

The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here in this article, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the processmore » can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. Additionally, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.« less

Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berman, Diana; Deshmukh, Sanket; Narayanan, Badri

The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here in this article, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the processmore » can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. Additionally, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu, Jia; Zhang, Ziang; Weng, Zhankun

This paper presents a new method for the generation of cross-scale laser interference patterns and the fabrication of moth-eye structures on silicon. In the method, moth-eye structures were produced on a surface of silicon wafer using direct six-beam laser interference lithography to improve the antireflection performance of the material surface. The periodic dot arrays of the moth-eye structures were formed due to the ablation of the irradiance distribution of interference patterns on the wafer surface. The shape, size, and distribution of the moth-eye structures can be adjusted by controlling the wavelength, incidence angles, and exposure doses in a direct six-beammore » laser interference lithography setup. The theoretical and experimental results have shown that direct six-beam laser interference lithography can provide a way to fabricate cross-scale moth-eye structures for antireflection applications.« less

Advances in process overlay on 300-mm wafers

NASA Astrophysics Data System (ADS)

Staecker, Jens; Arendt, Stefanie; Schumacher, Karl; Mos, Evert C.; van Haren, Richard J. F.; van der Schaar, Maurits; Edart, Remi; Demmerle, Wolfgang; Tolsma, Hoite

2002-07-01

Overlay budgets are getting tighter within 300 mm volume production and as a consequence the process effects on alignment and off-line metrology becomes more important. In a short loop experiment, with cleared reference marks in each image field, the isolated effect of processing was measured with a sub-nanometer accuracy. The examined processes are Shallow Trench Isolation (STI), Tungsten-Chemical Mechanical Processing (W-CMP) and resist spinning. The alignment measurements were done on an ASML TWINSCANT scanner and the off-line metrology measurements on a KLA Tencor. Mark type and mark position dependency of the process effects are analyzed. The mean plus 3 (sigma) of the maximum overlay after correcting batch average wafer parameters is used as an overlay performance indicator (OPI). 3 (sigma) residuals to the wafer-model are used as an indicator of the noise that is added by the process. The results are in agreement with existing knowledge of process effects on 200 mm wafers. The W-CMP process introduces an additional wafer rotation and scaling that is similar for alignment marks and metrology targets. The effects depend on the mark type; in general they get less severe for higher spatial frequencies. For a 7th order alignment mark, the OPI measured about 12 nm and the added noise about 12 nm. For the examined metrology targets the OPI is about 20 nm with an added noise of about 90 nm. Two different types of alignment marks were tested in the STI process, i.e., zero layer marks and marks that were exposed together with the STI product. The overlay contribution due to processing on both types of alignment marks is very low (smaller than 5 nm OPI) and independent on mark type. Some flyers are observed fot the zero layer marks. The flyers can be explained by the residues of oxide and nitride that is left behind in the spaces of the alignment marks. Resist spinning is examined on single layer resist and resist with an organic Bottom Anti-Reflective Coating (BARC) underneath. Single layer resist showed scaling on unsegmented marks that disappears using higher diffraction orders and/or mark segmentation. Resist with a planarizing BARC caused additional effects on the wafer edge for measurements with the red laser signal. The effects disappear using the green laser of ATHENAT.

Reducing the substrate dependent scanner leveling effect in low-k1 contact printing

NASA Astrophysics Data System (ADS)

Chang, C. S.; Tseng, C. F.; Huang, C. H.; Yang, Elvis; Yang, T. H.; Chen, K. C.

2015-03-01

As the scaling down of design rule for high-density memory device, the small depth of focus (DoF) budget may be deteriorated by focus leveling errors, which arises in unpredicted reflectivity from multilayer structures on the topographic wafer. The leveling sensors of ASML scanner use near infrared (NIR) range wavelength which can penetrate through most of films using in semiconductor fabrication such as photo-resist, bottom anti reflective coating (BARC) and dielectric materials. Consequently, the reflected light from underlying substructures would disturb leveling sensors from accurate leveling. The different pattern densities and layout characteristics between array and periphery of a memory chip are expected to result in different leveling signals. Furthermore, the process dependent variations between wafer central and edge areas are also considered to yield different leveling performances during wafer exposure. In this study, lower blind contact immunity was observed for peripheral contacts comparing to the array contacts especially around wafer edge region. In order to overcome this problem, a series of investigations have been carried out. The wafer edge leveling optimization through circuit dependent focus edge clearance (CDFEC) option doesn't get improvement. Air gauge improved process leveling (AGILE) function of ASML immersion scanner doesn't show improved result either. The ILD uniformity improvement and step height treatments around wafer edge such as edge exclusion of film deposition and bevel etching are also ineffective to mitigate the blind contact problem of peripheral patterns. Altering the etch hard-mask stack is finally found to be an effective approach to alleviate the issue. For instance, through either containing high temperature deposition advanced patterning film (APF) in the hard-mask or inserting higher opaque film such as amorphous Si in between the hard-mask stack.

Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging

PubMed Central

Lee, Chang-Chun; Tzeng, Tzai-Liang; Huang, Pei-Chen

2015-01-01

A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young’s modulus (E), Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture. PMID:28793495

Wafer-scale controlled exfoliation of metal organic vapor phase epitaxy grown InGaN/GaN multi quantum well structures using low-tack two-dimensional layered h-BN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ayari, Taha; Li, Xin; Voss, Paul L.

Recent advances in epitaxial growth have led to the growth of III-nitride devices on 2D layered h-BN. This advance has the potential for wafer-scale transfer to arbitrary substrates, which could improve the thermal management and would allow III-N devices to be used more flexibly in a broader range of applications. We report wafer scale exfoliation of a metal organic vapor phase epitaxy grown InGaN/GaN Multi Quantum Well (MQW) structure from a 5 nm thick h-BN layer that was grown on a 2-inch sapphire substrate. The weak van der Waals bonds between h-BN atomic layers break easily, allowing the MQW structure tomore » be mechanically lifted off from the sapphire substrate using a commercial adhesive tape. This results in the surface roughness of only 1.14 nm on the separated surface. Structural characterizations performed before and after the lift-off confirm the conservation of structural properties after lift-off. Cathodoluminescence at 454 nm was present before lift-off and 458 nm was present after. Electroluminescence near 450 nm from the lifted-off structure has also been observed. These results show that the high crystalline quality ultrathin h-BN serves as an effective sacrificial layer—it maintains performance, while also reducing the GaN buffer thickness and temperature ramps as compared to a conventional two-step growth method. These results support the use of h-BN as a low-tack sacrificial underlying layer for GaN-based device structures and demonstrate the feasibility of large area lift-off and transfer to any template, which is important for industrial scale production.« less

Mobil Solar Energy Corporation thin EFG octagons. Final subcontract report, 1 April 1992--31 January 1994

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kalejs, J.P.

1994-06-01

Mobil Solar Energy Corporation manufactures photovoltaic modules based on its unique Edge-defined Film-fed Growth (EFG) process for producing octagon-shaped hollow polycrystalline silicon tubes. The octagons are cut by lasers into 100 mm x 100 mm wafers which are suitable for solar cell processing. This process avoids slicing, grinding and polishing operations which are wasteful of material and are typical of most other wafer production methods. EFG wafers are fabricated into solar cells and modules using processes that have been specially developed to allow scaling up to high throughput rates. The goals of the Photovoltaic Manufacturing Technology Initiative (PVMaT) program atmore » Mobil Solar were to improve the EFG manufacturing line through technology advances that accelerate cost reduction in production and stimulate market growth for its product. The program was structured into three main tasks: to decrease silicon utilization by lowering wafer thickness from 400 to 200 {mu}m; to enhance laser cutting yields and throughput while improving the wafer strength; and to raise crystal growth productivity and yield. The technical problems faced and the advances made in the Mobil Solar PVMaT program are described. The author concludes with a presentation of the results of a detailed cost model for EFT module production. This model describes the accelerated reductions in manufacturing costs which are already in place and the future benefits anticipated to result from the technical achievements of the PVMaT program.« less

Packaging of electro-microfluidic devices

DOEpatents

Benavides, Gilbert L.; Galambos, Paul C.; Emerson, John A.; Peterson, Kenneth A.; Giunta, Rachel K.; Zamora, David Lee; Watson, Robert D.

2003-04-15

A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

Packaging of electro-microfluidic devices

DOEpatents

Benavides, Gilbert L.; Galambos, Paul C.; Emerson, John A.; Peterson, Kenneth A.; Giunta, Rachel K.; Watson, Robert D.

2002-01-01

A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

Merging photonics with nanoelectronics (Conference Presentation)

NASA Astrophysics Data System (ADS)

Liehr, Michael

2016-02-01

The recently established American Institute for Manufacturing Photonics (AIM Photonics) is a manufacturing consortium headquartered in New York, with funding from the US Department of Defense (DoD), New York State, and industrial partners to advance the state of the art in the design, manufacture, testing, assembly, and packaging of integrated photonic devices. Dr. Michael Liehr, CEO of AIM Photonics, will describe the technical goals, operational framework, near-term milestones, and opportunities for the broader photonics community. The Institute intends to organize a currently fragmented domestic capability in integrated photonics. AIM Photonics will develop and demonstrate innovative manufacturing technologies for a number of key application sectors for integrated photonics devices. The Institute will furthermore specifically focus on establishing and building out an infrastructure in key areas required to accelerate the further adoption of integrated photonics. Specifically, we will enhance the available hardware development capability to include Si-based Multi-Project Wafer runs, InP-based Photonic Integrated Circuits, first and second level packaging, test and assembly.

HEMT Amplifiers and Equipment for their On-Wafer Testing

NASA Technical Reports Server (NTRS)

Fung, King man; Gaier, Todd; Samoska, Lorene; Deal, William; Radisic, Vesna; Mei, Xiaobing; Lai, Richard

2008-01-01

Power amplifiers comprising InP-based high-electron-mobility transistors (HEMTs) in coplanar-waveguide (CPW) circuits designed for operation at frequencies of hundreds of gigahertz, and a test set for onwafer measurement of their power levels have been developed. These amplifiers utilize an advanced 35-nm HEMT monolithic microwave integrated-circuit (MMIC) technology and have potential utility as local-oscillator drivers and power sources in future submillimeter-wavelength heterodyne receivers and imaging systems. The test set can reduce development time by enabling rapid output power characterization, not only of these and similar amplifiers, but also of other coplanar-waveguide power circuits, without the necessity of packaging the circuits.

Manufacturable Tri-Stack AlSb/InAs HEMT Low-Noise Amplifiers Using Wafer-Level-Packaging Technology for Light-Weight and Ultralow-Power Applications

DTIC Science & Technology

2009-05-01

shown in Fig. 1 was grown by molecular - beam epitaxy (MBE) on 3-inch semi-insulating GaAs substrates. AlGaSb was used as a buffer. AlSb was used as... beam epitaxy for low-power applications,” J. Vac. Sci. Technol. B. 24, pp. 2581-2585, 2006. [12] Y. C. Chou, L. J. Lee, J. M. Yang, M. D. Lange, P...passivation AlGaSb buffer Figure 1: Cross section of an AlSb/InAs HEMT device on a 3-inch GaAs substrate. The interface region between the

Techniques for control of long-term reliability of complex integrated circuits. I - Reliability assurance by test vehicle qualification.

NASA Technical Reports Server (NTRS)

Van Vonno, N. W.

1972-01-01

Development of an alternate approach to the conventional methods of reliability assurance for large-scale integrated circuits. The product treated is a large-scale T squared L array designed for space applications. The concept used is that of qualification of product by evaluation of the basic processing used in fabricating the product, providing an insight into its potential reliability. Test vehicles are described which enable evaluation of device characteristics, surface condition, and various parameters of the two-level metallization system used. Evaluation of these test vehicles is performed on a lot qualification basis, with the lot consisting of one wafer. Assembled test vehicles are evaluated by high temperature stress at 300 C for short time durations. Stressing at these temperatures provides a rapid method of evaluation and permits a go/no go decision to be made on the wafer lot in a timely fashion.

Wafer scale BN on sapphire substrates for improved graphene transport.

PubMed

Vangala, Shivashankar; Siegel, Gene; Prusnick, Timothy; Snure, Michael

2018-06-11

Wafer scale (2") BN grown by metal organic chemical vapor deposition (MOCVD) on sapphire was examined as a weakly interacting dielectric substrate for graphene, demonstrating improved transport properties over conventional sapphire and SiO 2 /Si substrates. Chemical vapor deposition grown graphene was transferred to BN/sapphire substrates for evaluation of more than 30 samples using Raman and Hall effects measurements. A more than 2x increase in Hall mobility and 10x reduction in sheet carrier density was measured for graphene on BN/sapphire compared to sapphire substrates. Through control of the MOCVD process, BN films with roughness ranging from <0.1 nm to >1 nm were grown and used to study the effects of substrate roughness on graphene transport. Arrays of graphene field effect transistors were fabricated on 2" BN/sapphire substrates demonstrating scalability and device performance enhancement.

Infrared spectroscopy of wafer-scale graphene.

PubMed

Yan, Hugen; Xia, Fengnian; Zhu, Wenjuan; Freitag, Marcus; Dimitrakopoulos, Christos; Bol, Ageeth A; Tulevski, George; Avouris, Phaedon

2011-12-27

We report spectroscopy results from the mid- to far-infrared on wafer-scale graphene, grown either epitaxially on silicon carbide or by chemical vapor deposition. The free carrier absorption (Drude peak) is simultaneously obtained with the universal optical conductivity (due to interband transitions) and the wavelength at which Pauli blocking occurs due to band filling. From these, the graphene layer number, doping level, sheet resistivity, carrier mobility, and scattering rate can be inferred. The mid-IR absorption of epitaxial two-layer graphene shows a less pronounced peak at 0.37 ± 0.02 eV compared to that in exfoliated bilayer graphene. In heavily chemically doped single-layer graphene, a record high transmission reduction due to free carriers approaching 40% at 250 μm (40 cm(-1)) is measured in this atomically thin material, supporting the great potential of graphene in far-infrared and terahertz optoelectronics.

Instructions for Plastic Encapsulated Microcircuit(PEM) Selection, Screening and Qualification.

NASA Technical Reports Server (NTRS)

King, Terry; Teverovsky, Alexander; Leidecker, Henning

2002-01-01

The use of Plastic Encapsulated Microcircuits (PEMs) is permitted on NASA Goddard Space Flight Center (GSFC) spaceflight applications, provided each use is thoroughly evaluated for thermal, mechanical, and radiation implications of the specific application and found to meet mission requirements. PEMs shall be selected for their functional advantage and availability, not for cost saving; the steps necessary to ensure reliability usually negate any initial apparent cost advantage. A PEM shall not be substituted for a form, fit and functional equivalent, high reliability, hermetic device in spaceflight applications. Due to the rapid change in wafer-level designs typical of commercial parts and the unknown traceability between packaging lots and wafer lots, lot specific testing is required for PEMs, unless specifically excepted by the Mission Assurance Requirements (MAR) for the project. Lot specific qualification, screening, radiation hardness assurance analysis and/or testing, shall be consistent with the required reliability level as defined in the MAR. Developers proposing to use PEMs shall address the following items in their Performance Assurance Implementation Plan: source selection (manufacturers and distributors), storage conditions for all stages of use, packing, shipping and handling, electrostatic discharge (ESD), screening and qualification testing, derating, radiation hardness assurance, test house selection and control, data collection and retention.

Preliminary design of 1 kW bipolar Ni-MH battery for LEO-satellite application

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cole, J.H.; Reisner, D.E.; Klein, M.G.

1996-12-31

Electro Energy, Inc. (EEI) is developing a bipolar nickel-metal hydride rechargeable battery based upon the use of stackable wafer cells. The key to viable bipolar operation has been this unique modular (unitized) approach. The patented unit wafer-cell construct exploits the chemical and thermal properties of a proprietary electrically conductive plastic film. Characteristic of bipolar batteries, current flows across the cell interfaces-perpendicular to the electrode plane. EEI has recently contracted with NASA Lewis Research Center (LeRC) to develop an optimized design 1 kW flightweight battery, for low-earth-orbit (LEO) satellite applications, over a 4-year period with a deliverable flightweight design package. Themore » contract includes an option for EEI to deliver up to three flight quality batteries in an 18-month follow-on program. NASA LeRC has promulgated that the program steps include the design, fabrication, and evaluation of four evolutionary stages of the final battery design which have been designated Preliminary, Improved, Optimized, and Flightweight Design. Initial results from the Preliminary Stage are presented including a 1 kW battery design, thermal design, parameter study, and component development in subscale bipolar batteries.« less

Method Of Packaging And Assembling Electro-Microfluidic Devices

DOEpatents

Benavides, Gilbert L.; Galambos, Paul C.; Emerson, John A.; Peterson, Kenneth A.; Giunta, Rachel K.; Zamora, David Lee; Watson, Robert D.

2004-11-23

A new architecture for packaging surface micromachined electro-microfluidic devices is presented. This architecture relies on two scales of packaging to bring fluid to the device scale (picoliters) from the macro-scale (microliters). The architecture emulates and utilizes electronics packaging technology. The larger package consists of a circuit board with embedded fluidic channels and standard fluidic connectors (e.g. Fluidic Printed Wiring Board). The embedded channels connect to the smaller package, an Electro-Microfluidic Dual-Inline-Package (EMDIP) that takes fluid to the microfluidic integrated circuit (MIC). The fluidic connection is made to the back of the MIC through Bosch-etched holes that take fluid to surface micromachined channels on the front of the MIC. Electrical connection is made to bond pads on the front of the MIC.

Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

2014-02-01

Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

NASA Astrophysics Data System (ADS)

Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

2014-08-01

We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

Wave-front propagation of rinsing flows on rotating semiconductor wafers

NASA Astrophysics Data System (ADS)

Frostad, John M.; Ylitalo, Andy; Walls, Daniel J.; Mui, David S. L.; Fuller, Gerald G.

2016-11-01

The semiconductor manufacturing industry is migrating to a cleaning technology that involves dispersing cleaning solutions onto a rotating wafer, similar to spin-coating. Advantages include a more continuous overall fabrication process, lower particle level, no cross contamination from the back side of a wafer, and less usage of harsh chemicals for a lower environmental impact. Rapid rotation of the wafer during rinsing can be more effective, but centrifugal forces can pull spiral-like ribbons of liquid radially outward from the advancing wave-front where particles can build up, causing higher instances of device failure at these locations. A better understanding of the rinsing flow is essential for reducing yield losses while taking advantage of the benefits of rotation. In the present work, high-speed video and image processing are used to study the dynamics of the advancing wave-front from an impinging jet on a rotating substrate. The flow-rate and rotation-speed are varied for substrates coated with a thin layer of a second liquid that has a different surface tension than the jet liquid. The difference in surface tension of the two fluids gives rise to Marangoni stresses at the interface that have a significant impact on the rinsing process, despite the extremely short time-scales involved.

A Summary of Lightpipe Radiation Thermometry Research at NIST

PubMed Central

Tsai, Benjamin K.

2006-01-01

During the last 10 years, research in light-pipe radiation thermometry has significantly reduced the uncertainties for temperature measurements in semiconductor processing. The National Institute of Standards and Technology (NIST) has improved the calibration of lightpipe radiation thermometers (LPRTs), the characterization procedures for LPRTs, the in situ calibration of LPRTs using thin-film thermocouple (TFTC) test wafers, and the application of model-based corrections to improve LPRT spectral radiance temperatures. Collaboration with industry on implementing techniques and ideas established at NIST has led to improvements in temperature measurements in semiconductor processing. LPRTs have been successfully calibrated at NIST for rapid thermal processing (RTP) applications using a sodium heat-pipe blackbody between 700 °C and 900 °C with an uncertainty of about 0.3 °C (k = 1) traceable to the International Temperature Scale of 1990. Employing appropriate effective emissivity models, LPRTs have been used to determine the wafer temperature in the NIST RTP Test Bed with an uncertainty of 3.5 °C. Using a TFTC wafer for calibration, the LPRT can measure the wafer temperature in the NIST RTP Test Bed with an uncertainty of 2.3 °C. Collaborations with industry in characterizing and calibrating LPRTs will be summarized, and future directions for LPRT research will be discussed. PMID:27274914

A Summary of Lightpipe Radiation Thermometry Research at NIST.

PubMed

Tsai, Benjamin K

2006-01-01

During the last 10 years, research in light-pipe radiation thermometry has significantly reduced the uncertainties for temperature measurements in semiconductor processing. The National Institute of Standards and Technology (NIST) has improved the calibration of lightpipe radiation thermometers (LPRTs), the characterization procedures for LPRTs, the in situ calibration of LPRTs using thin-film thermocouple (TFTC) test wafers, and the application of model-based corrections to improve LPRT spectral radiance temperatures. Collaboration with industry on implementing techniques and ideas established at NIST has led to improvements in temperature measurements in semiconductor processing. LPRTs have been successfully calibrated at NIST for rapid thermal processing (RTP) applications using a sodium heat-pipe blackbody between 700 °C and 900 °C with an uncertainty of about 0.3 °C (k = 1) traceable to the International Temperature Scale of 1990. Employing appropriate effective emissivity models, LPRTs have been used to determine the wafer temperature in the NIST RTP Test Bed with an uncertainty of 3.5 °C. Using a TFTC wafer for calibration, the LPRT can measure the wafer temperature in the NIST RTP Test Bed with an uncertainty of 2.3 °C. Collaborations with industry in characterizing and calibrating LPRTs will be summarized, and future directions for LPRT research will be discussed.

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

Less strained and more efficient GaN light-emitting diodes with embedded silica hollow nanospheres

PubMed Central

Kim, Jonghak; Woo, Heeje; Joo, Kisu; Tae, Sungwon; Park, Jinsub; Moon, Daeyoung; Park, Sung Hyun; Jang, Junghwan; Cho, Yigil; Park, Jucheol; Yuh, Hwankuk; Lee, Gun-Do; Choi, In-Suk; Nanishi, Yasushi; Han, Heung Nam; Char, Kookheon; Yoon, Euijoon

2013-01-01

Light-emitting diodes (LEDs) become an attractive alternative to conventional light sources due to high efficiency and long lifetime. However, different material properties between GaN and sapphire cause several problems such as high defect density in GaN, serious wafer bowing, particularly in large-area wafers, and poor light extraction of GaN-based LEDs. Here, we suggest a new growth strategy for high efficiency LEDs by incorporating silica hollow nanospheres (S-HNS). In this strategy, S-HNSs were introduced as a monolayer on a sapphire substrate and the subsequent growth of GaN by metalorganic chemical vapor deposition results in improved crystal quality due to nano-scale lateral epitaxial overgrowth. Moreover, well-defined voids embedded at the GaN/sapphire interface help scatter lights effectively for improved light extraction, and reduce wafer bowing due to partial alleviation of compressive stress in GaN. The incorporation of S-HNS into LEDs is thus quite advantageous in achieving high efficiency LEDs for solid-state lighting. PMID:24220259

Iterative algorithms for tridiagonal matrices on a WSI-multiprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gajski, D.D.; Sameh, A.H.; Wisniewski, J.A.

1982-01-01

With the rapid advances in semiconductor technology, the construction of Wafer Scale Integration (WSI)-multiprocessors consisting of a large number of processors is now feasible. We illustrate the implementation of some basic linear algebra algorithms on such multiprocessors.

Within-wafer CD variation induced by wafer shape

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

2016-03-01

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer PEB temperature non-uniformity attributed to wafer warpage is uncorrectable, and the photo-resist profile variation is believed to affect across-wafer etch bias uniformity to some degree.

Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics.

PubMed

Heo, Jinseong; Byun, Kyung-Eun; Lee, Jaeho; Chung, Hyun-Jong; Jeon, Sanghun; Park, Seongjun; Hwang, Sungwoo

2013-01-01

Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.

Three-dimensional micro/nano-scale structure fabricated by combination of non-volatile polymerizable RTIL and FIB irradiation

PubMed Central

Kuwabata, Susumu; Minamimoto, Hiro; Inoue, Kosuke; Imanishi, Akihito; Hosoya, Ken; Uyama, Hiroshi; Torimoto, Tsukasa; Tsuda, Tetsuya; Seki, Shu

2014-01-01

Room-temperature ionic liquid (RTIL) has been widely investigated as a nonvolatile solvent as well as a unique liquid material because of its interesting features, e.g., negligible vapor pressure and high thermal stability. Here we report that a non-volatile polymerizable RTIL is a useful starting material for the fabrication of micro/nano-scale polymer structures with a focused-ion-beam (FIB) system operated under high-vacuum condition. Gallium-ion beam irradiation to the polymerizable 1-allyl-3-ethylimidazolium bis((trifluoromethane)sulfonyl)amide RTIL layer spread on a Si wafer induced a polymerization reaction without difficulty. What is interesting to note is that we have succeeded in provoking the polymerization reaction anywhere on the Si wafer substrate by using FIB irradiation with a raster scanning mode. By this finding, two- and three-dimensional micro/nano-scale polymer structure fabrications were possible at the resolution of 500,000 dpi. Even intricate three-dimensional micro/nano-figures with overhang and hollow moieties could be constructed at the resolution of approximately 100 nm. PMID:24430465

Wafer screening device and methods for wafer screening

DOEpatents

Sopori, Bhushan; Rupnowski, Przemyslaw

2014-07-15

Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

Overlay performance assessment of MAPPER's FLX-1200 (Conference Presentation)

NASA Astrophysics Data System (ADS)

Lattard, Ludovic; Servin, Isabelle; Pradelles, Jonathan; Blancquaert, Yoann; Rademaker, Guido; Pain, Laurent; de Boer, Guido; Brandt, Pieter; Dansberg, Michel; Jager, Remco J. A.; Peijster, Jerry J. M.; Slot, Erwin; Steenbrink, Stijn W. H. K.; Vergeer, Niels; Wieland, Marco

2017-04-01

Mapper Lithography has introduced its first product, the FLX-1200, which is installed at CEA-Leti in Grenoble (France). This is a mask less lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. This FLX platform is initially targeted for 1 wph performance for 28 nm technology nodes, but can also be used for less demanding imaging. The electron source currently integrated is capable of scaling to 10 wph at the same resolution performance, which will be implemented by gradually upgrading the illumination optics. The system has an optical alignment system enabling mix-and-match with optical 193 nm immersion systems using standard NVSM marks. The tool at CEA-Leti is in-line with a Sokudo Duo clean track. Mapper Lithography and CEA-Leti are working in collaboration to develop turnkey solution for specific applications. At previous conferences we have presented imaging results including 28nm node resolution, cross wafer CDu of 2.5nm 3 and a throughput of half a wafer per hour, overhead times included. At this conference we will present results regarding the overlay performance of the FLX-1200. In figure 2 an initial result towards measuring the overlay performance of the FLX-1200 is shown. We have exposed a wafer twice without unloading the wafer in between exposures. In the first exposure half of a dense dot array is exposed. In the second exposure the remainder of the dense dot array is exposed. After development the wafer has been inspected using a CD-SEM at 480 locations distributed over an area of 100mm x 100mm. For each SEM image the shift of the pattern written in the first exposure relative to the pattern written in the second exposure is measured. Cross wafer this shift is 7 nm u+3s in X and 5 nm u+3s in Y. The next step is to evaluate the impact of unloading and loading of the wafer in between exposures. At the conference the latest results will be presented.

Single Layer Broadband Anti-Reflective Coatings for Plastic Substrates Produced by Full Wafer and Roll-to-Roll Step-and-Flash Nano-Imprint Lithography

PubMed Central

Burghoorn, Marieke; Roosen-Melsen, Dorrit; de Riet, Joris; Sabik, Sami; Vroon, Zeger; Yakimets, Iryna; Buskens, Pascal

2013-01-01

Anti-reflective coatings (ARCs) are used to lower the reflection of light on the surface of a substrate. Here, we demonstrate that the two main drawbacks of moth eye-structured ARCs—i.e., the lack of suitable coating materials and a process for large area, high volume applications—can be largely eliminated, paving the way for cost-efficient and large-scale production of durable moth eye-structured ARCs on polymer substrates. We prepared moth eye coatings on polymethylmethacrylate (PMMA) and polycarbonate using wafer-by-wafer step-and-flash nano-imprint lithography (NIL). The reduction in reflection in the visible field achieved with these coatings was 3.5% and 4.0%, respectively. The adhesion of the coating to both substrates was good. The moth eye coating on PMMA demonstrated good performance in three prototypical accelerated ageing tests. The pencil hardness of the moth eye coatings on both substrates was <4B, which is less than required for most applications and needs further optimization. Additionally, we developed a roll-to-roll UV NIL pilot scale process and produced moth eye coatings on polyethylene terephthalate (PET) at line speeds up to two meters per minute. The resulting coatings showed a good replication of the moth eye structures and, consequently, a lowering in reflection of the coated PET of 3.0%. PMID:28788301

Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

PubMed Central

Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

2016-01-01

Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates. PMID:26864968

A low feed-through 3D vacuum packaging technique with silicon vias for RF MEMS resonators

NASA Astrophysics Data System (ADS)

Zhao, Jicong; Yuan, Quan; Kan, Xiao; Yang, Jinling; Yang, Fuhua

2017-01-01

This paper presents a wafer-level three-dimensional (3D) vacuum packaging technique for radio frequency microelectromechanical systems (RF MEMS) resonators. A Sn-rich Au-Sn solder bonding is employed to provide a vacuum encapsulation as well as electrical conductions. Vertical silicon vias are micro-fabricated by glass reflow process. The optimized grounding, via pitch, and all-round shielding effectively reduce feed-through capacitance. Thus the signal-to-background ratios (SBRs) of the transmission signals increase from 17 dB to 20 dB, and the quality factor (Q) values of the packaged resonators go from around 8000 up to more than 9500. The measured average leak rate and shear strength are (2.55  ±  0.9)  ×  10-8 atm-cc s-1 and 42.53  ±  4.19 MPa, respectively. Furthermore, thermal cycling test between  -40 °C and 100 °C and high temperature storage test at 150 °C show that the resonant-frequency drifts are less than  ±7 ppm. In addition, the SBRs and the Q values have no obvious change after the tests. The experimental results demonstrated that the proposed encapsulation technique is well suited for the applications of RF MEMS devices.

Latest improvements in microbolometer thin film packaging: paving the way for low-cost consumer applications

NASA Astrophysics Data System (ADS)

Yon, J. J.; Dumont, G.; Goudon, V.; Becker, S.; Arnaud, A.; Cortial, S.; Tisse, C. L.

2014-06-01

Silicon-based vacuum packaging is a key enabling technology for achieving affordable uncooled Infrared Focal Plane Arrays (IRFPA) required by a promising mass market that shows momentum for some extensive consumer applications, such as automotive driving assistance, smart presence localization and building management. Among the various approaches studied worldwide, CEA, LETI in partnership with ULIS is committed to the development of a unique technology referred to as PLP (Pixel Level Packaging). In this PLP technology, each bolometer pixel is sealed under vacuum using a transparent thin film deposition on wafer. PLP operates as an array of hermetic micro caps above the focal plane, each enclosing a single microbolometer. In continuation of our on-going studies on PLP for regular QVGA IRFPAs, this paper emphasizes on the innate scalability of the technology which was successfully demonstrated through the development of an 80 × 80 pixel IRFPA. The relevance of the technology with regard to the two formats is discussed, considering both performance and cost issues. We show that the suboptimal fill factor inherent to the PLP arrangement is not so critical when considering smaller arrays preferably fitted for consumer applications. The discussion is supported with the electro-optical performance measurements of the PLP-based 80×80 demonstrator.

Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

NASA Astrophysics Data System (ADS)

Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

2018-05-01

Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

Layer-by-layer assembly of two-dimensional materials into wafer-scale heterostructures

NASA Astrophysics Data System (ADS)

Kang, Kibum; Lee, Kan-Heng; Han, Yimo; Gao, Hui; Xie, Saien; Muller, David A.; Park, Jiwoong

2017-10-01

High-performance semiconductor films with vertical compositions that are designed to atomic-scale precision provide the foundation for modern integrated circuitry and novel materials discovery. One approach to realizing such films is sequential layer-by-layer assembly, whereby atomically thin two-dimensional building blocks are vertically stacked, and held together by van der Waals interactions. With this approach, graphene and transition-metal dichalcogenides--which represent one- and three-atom-thick two-dimensional building blocks, respectively--have been used to realize previously inaccessible heterostructures with interesting physical properties. However, no large-scale assembly method exists at present that maintains the intrinsic properties of these two-dimensional building blocks while producing pristine interlayer interfaces, thus limiting the layer-by-layer assembly method to small-scale proof-of-concept demonstrations. Here we report the generation of wafer-scale semiconductor films with a very high level of spatial uniformity and pristine interfaces. The vertical composition and properties of these films are designed at the atomic scale using layer-by-layer assembly of two-dimensional building blocks under vacuum. We fabricate several large-scale, high-quality heterostructure films and devices, including superlattice films with vertical compositions designed layer-by-layer, batch-fabricated tunnel device arrays with resistances that can be tuned over four orders of magnitude, band-engineered heterostructure tunnel diodes, and millimetre-scale ultrathin membranes and windows. The stacked films are detachable, suspendable and compatible with water or plastic surfaces, which will enable their integration with advanced optical and mechanical systems.

Layer-by-layer assembly of two-dimensional materials into wafer-scale heterostructures.

PubMed

Kang, Kibum; Lee, Kan-Heng; Han, Yimo; Gao, Hui; Xie, Saien; Muller, David A; Park, Jiwoong

2017-10-12

High-performance semiconductor films with vertical compositions that are designed to atomic-scale precision provide the foundation for modern integrated circuitry and novel materials discovery. One approach to realizing such films is sequential layer-by-layer assembly, whereby atomically thin two-dimensional building blocks are vertically stacked, and held together by van der Waals interactions. With this approach, graphene and transition-metal dichalcogenides-which represent one- and three-atom-thick two-dimensional building blocks, respectively-have been used to realize previously inaccessible heterostructures with interesting physical properties. However, no large-scale assembly method exists at present that maintains the intrinsic properties of these two-dimensional building blocks while producing pristine interlayer interfaces, thus limiting the layer-by-layer assembly method to small-scale proof-of-concept demonstrations. Here we report the generation of wafer-scale semiconductor films with a very high level of spatial uniformity and pristine interfaces. The vertical composition and properties of these films are designed at the atomic scale using layer-by-layer assembly of two-dimensional building blocks under vacuum. We fabricate several large-scale, high-quality heterostructure films and devices, including superlattice films with vertical compositions designed layer-by-layer, batch-fabricated tunnel device arrays with resistances that can be tuned over four orders of magnitude, band-engineered heterostructure tunnel diodes, and millimetre-scale ultrathin membranes and windows. The stacked films are detachable, suspendable and compatible with water or plastic surfaces, which will enable their integration with advanced optical and mechanical systems.

Effect of wafer geometry on lithography chucking processes

NASA Astrophysics Data System (ADS)

Turner, Kevin T.; Sinha, Jaydeep K.

2015-03-01

Wafer flatness during exposure in lithography tools is critical and is becoming more important as feature sizes in devices shrink. While chucks are used to support and flatten the wafer during exposure, it is essential that wafer geometry be controlled as well. Thickness variations of the wafer and high-frequency wafer shape components can lead to poor flatness of the chucked wafer and ultimately patterning problems, such as defocus errors. The objective of this work is to understand how process-induced wafer geometry, resulting from deposited films with non-uniform stress, can lead to high-frequency wafer shape variations that prevent complete chucking in lithography scanners. In this paper, we discuss both the acceptable limits of wafer shape that permit complete chucking to be achieved, and how non-uniform residual stresses in films, either due to patterning or process non-uniformity, can induce high spatial frequency wafer shape components that prevent chucking. This paper describes mechanics models that relate non-uniform film stress to wafer shape and presents results for two example cases. The models and results can be used as a basis for establishing control strategies for managing process-induced wafer geometry in order to avoid wafer flatness-induced errors in lithography processes.

High throughput wafer defect monitor for integrated metrology applications in photolithography

NASA Astrophysics Data System (ADS)

Rao, Nagaraja; Kinney, Patrick; Gupta, Anand

2008-03-01

The traditional approach to semiconductor wafer inspection is based on the use of stand-alone metrology tools, which while highly sensitive, are large, expensive and slow, requiring inspection to be performed off-line and on a lot sampling basis. Due to the long cycle times and sparse sampling, the current wafer inspection approach is not suited to rapid detection of process excursions that affect yield. The semiconductor industry is gradually moving towards deploying integrated metrology tools for real-time "monitoring" of product wafers during the manufacturing process. Integrated metrology aims to provide end-users with rapid feedback of problems during the manufacturing process, and the benefit of increased yield, and reduced rework and scrap. The approach of monitoring 100% of the wafers being processed requires some trade-off in sensitivity compared to traditional standalone metrology tools, but not by much. This paper describes a compact, low-cost wafer defect monitor suitable for integrated metrology applications and capable of detecting submicron defects on semiconductor wafers at an inspection rate of about 10 seconds per wafer (or 360 wafers per hour). The wafer monitor uses a whole wafer imaging approach to detect defects on both un-patterned and patterned wafers. Laboratory tests with a prototype system have demonstrated sensitivity down to 0.3 µm on un-patterned wafers and down to 1 µm on patterned wafers, at inspection rates of 10 seconds per wafer. An ideal application for this technology is preventing photolithography defects such as "hot spots" by implementing a wafer backside monitoring step prior to exposing wafers in the lithography step.

Overview of several applications of chemical downstream etching (CDE) for IC manufacturing: advantages and drawbacks versus WET processes

NASA Astrophysics Data System (ADS)

de Buttet, Côme; Prevost, Emilie; Campo, Alain; Garnier, Philippe; Zoll, Stephane; Vallier, Laurent; Cunge, Gilles; Maury, Patrick; Massin, Thomas; Chhun, Sonarith

2017-03-01

Today the IC manufacturing faces lots of problematics linked to the continuous down scaling of printed structures. Some of those issues are related to wet processing, which are often used in the IC manufacturing flow for wafer cleaning, material etching and surface preparation. In the current work we summarize the limitations for the next nodes of wet processing such as metallic contaminations, wafer charging, corrosion and pattern collapse. As a replacement, we promoted the isotropic chemical dry etching (CDE) which is supposed to fix all the above drawbacks. Etching steps of SI3N4 layers were evaluated in order to prove the interest of such technique.

Fabrication of 20 nm embedded longitudinal nanochannels transferred from metal nanowire patterns

NASA Technical Reports Server (NTRS)

Choi, D.; Yang, E. H.

2003-01-01

bstract we describe a technique for fabricating nanometer-scale channels embedded by dielectric materials. Longitudinal 'embedded ' nanochannels with an opening size 20 nm x 80 nm have been successfully fabricated on silicon wafer by transferring sacrificial nanowire structures.

Post exposure bake unit equipped with wafer-shape compensation technology

NASA Astrophysics Data System (ADS)

Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

2007-03-01

In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

NASA Technical Reports Server (NTRS)

Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

2015-01-01

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

Solar lens mission concept for interstellar exploration

NASA Astrophysics Data System (ADS)

Brashears, Travis; Lubin, Philip; Turyshev, Slava; Shao, Michael; Zhang, Qicheng

2015-09-01

The long standing approach to space travel has been to incorporate massive on-board electronics, probes and propellants to achieve space exploration. This approach has led to many great achievements in science, but will never help to explore the interstellar medium. Fortunately, a paradigm shift is upon us in how a spacecraft is constructed and propelled. This paper describes a mission concept to get to our Sun's Gravity Lens at 550AU in less than 10 years. It will be done by using DE-STAR, a scalable solar-powered phased-array laser in Earth Orbit, as a directed energy photon drive of low-mass wafersats. [1] [2] [3] [4] [5] With recent technologies a complete mission can be placed on a wafer including, power from an embedded radio nuclear thermal generator (RTG), PV, laser communications, imaging, photon thrusters for attitude control and other sensors. As one example, a futuristic 200 MW laser array consisting of 1 - 10 kw meter scale sub elements with a 100m baseline can propel a 10 gram wafer scale spacecraft with a 3m laser sail to 60AU/Year. Directed energy propulsion of low-mass spacecraft gives us an opportunity to capture images of Alpha Centauri and its planets, detailed imaging of the cosmic microwave background, set up interstellar communications by using gravity lenses around nearby stars to boost signals from interstellar probes, and much more. This system offers a very large range of missions allowing hundreds of wafer scale payload launches per day to reach this cosmological data reservoir. Directed Energy Propulsion is the only current technology that can provide a near-term path to utilize our Sun's Gravity Lens.

George E. Pake Prize: A Few Challenges in the Evolution of Semiconductor Device/Manufacturing Technology

NASA Astrophysics Data System (ADS)

Doering, Robert

In the early 1980s, the semiconductor industry faced the related challenges of ``scaling through the one-micron barrier'' and converting single-level-metal NMOS integrated circuits to multi-level-metal CMOS. Multiple advances in lithography technology and device materials/process integration led the way toward the deep-sub-micron transistors and interconnects that characterize today's electronic chips. In the 1990s, CMOS scaling advanced at an accelerated pace enabled by rapid advances in many aspects of optical lithography. However, the industry also needed to continue the progress in manufacturing on ever-larger silicon wafers to maintain economy-of-scale trends. Simultaneously, the increasing complexity and absolute-precision requirements of manufacturing compounded the necessity for new processes, tools, and control methodologies. This talk presents a personal perspective on some of the approaches that addressed the aforementioned challenges. In particular, early work on integrating silicides, lightly-doped-drain FETs, shallow recessed isolation, and double-level metal will be discussed. In addition, some pioneering efforts in deep-UV lithography and single-wafer processing will be covered. The latter will be mainly based on results from the MMST Program - a 100 M +, 5-year R&D effort, funded by DARPA, the U.S. Air Force, and Texas Instruments, that developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration of sub-3-day cycle time for manufacturing 350-nm CMOS integrated circuits in 1993. This was principally enabled by the development of: (1) 100% single-wafer processing, including rapid-thermal processing (RTP), and (2) computer-integrated-manufacturing (CIM), including real-time, in-situ process control.

Effect of thermal cycling ramp rate on CSP assembly reliability

NASA Technical Reports Server (NTRS)

Ghaffarian, R.

2001-01-01

A JPL-led chip scale package consortium of enterprises recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages for a variety of projects. The experience of the consortium in building more than 150 test vehicle assemblies, single and double sided multilayer PWBs, and the environmental test results has now been published as a chip scale package guidelines document.

Graphene earphones: entertainment for both humans and animals.

PubMed

Tian, He; Li, Cheng; Mohammad, Mohammad Ali; Cui, Ya-Long; Mi, Wen-Tian; Yang, Yi; Xie, Dan; Ren, Tian-Ling

2014-06-24

The human hearing range is from 20 Hz to 20 kHz. However, many animals can hear much higher sound frequencies. Dolphins, especially, have a hearing range up to 300 kHz. To our knowledge, there is no data of a reported wide-band sound frequency earphone to satisfy both humans and animals. Here, we show that graphene earphones, packaged into commercial earphone casings can play sounds ranging from 100 Hz to 50 kHz. By using a one-step laser scribing technology, wafer-scale flexible graphene earphones can be obtained in 25 min. Compared with a normal commercial earphone, the graphene earphone has a wider frequency response (100 Hz to 50 kHz) and a three times lower fluctuation (±10 dB). A nonlinear effect exists in the graphene-generated sound frequency spectrum. This effect could be explained by the DC bias added to the input sine waves which may induce higher harmonics. Our numerical calculations show that the sound frequency emitted by graphene could reach up to 1 MHz. In addition, we have demonstrated that a dog wearing a graphene earphone could also be trained and controlled by 35 kHz sound waves. Our results show that graphene could be widely used to produce earphones for both humans and animals.

RF beam transmission of x-band PAA system utilizing large-area, polymer-based true-time-delay module developed using imprinting and inkjet printing

NASA Astrophysics Data System (ADS)

Pan, Zeyu; Subbaraman, Harish; Zhang, Cheng; Li, Qiaochu; Xu, Xiaochuan; Chen, Xiangning; Zhang, Xingyu; Zou, Yi; Panday, Ashwin; Guo, L. Jay; Chen, Ray T.

2016-02-01

Phased-array antenna (PAA) technology plays a significant role in modern day radar and communication networks. Truetime- delay (TTD) enabled beam steering networks provide several advantages over their electronic counterparts, including squint-free beam steering, low RF loss, immunity to electromagnetic interference (EMI), and large bandwidth control of PAAs. Chip-scale and integrated TTD modules promise a miniaturized, light-weight system; however, the modules are still rigid and they require complex packaging solutions. Moreover, the total achievable time delay is still restricted by the wafer size. In this work, we propose a light-weight and large-area, true-time-delay beamforming network that can be fabricated on light-weight and flexible/rigid surfaces utilizing low-cost "printing" techniques. In order to prove the feasibility of the approach, a 2-bit thermo-optic polymer TTD network is developed using a combination of imprinting and ink-jet printing. RF beam steering of a 1×4 X-band PAA up to 60° is demonstrated. The development of such active components on large area, light-weight, and low-cost substrates promises significant improvement in size, weight, and power (SWaP) requirements over the state-of-the-art.

Evolution of gettering technologies for vacuum tubes to getters for MEMS

NASA Astrophysics Data System (ADS)

Amiotti, M.

2008-05-01

Getter materials are technically proven and industrially accepted practical ways to maintain vacuum inside hermetically sealed tubes or devices to assure high reliability and long lifetime of the operating devices. The most industrially proven vacuum tube is the cathode rays tubes (CRTs), where large surfaces are available for the deposition of an evaporated barium film by a radio frequency inductive heating of a stainless steel container filled with a BaAl4 powder mixed to Ni powder. The evolution of the CRTs manufacturing technologies required also new types of barium getters able to withstand some thermal process in air without any deterioration of the evaporation characteristics. In other vacuum tubes such as traveling waves tubes, the space available for the evaporation of a barium film and the sorption capacity required to assure the vacuum for the lifetime of the devices did not allow the use of the barium film, prompting the development of sintered non evaporable getter pills that can be activated during the manufacturing process or by flowing current through an embedded resistance. The same sintered non evaporable getter pills could find usage also in evacuated parts to thermally isolate the infrared sensors for different final applications. In high energy physics particle accelerators, the getter technology moved from localized vacuum getter pumps or getter strips to a getter coating over the surface of vacuum chambers in order to guarantee a more uniform pumping speed. With the advent of solid state electronics, new challenges faced the getter technology to assure long life to vacuum or inert gas filled hermetical packages containing microelectronic devices, especially in the telecommunication and military applications. A well known problem of GaAs devices with Pd or Pt metalization is the H2 poisoning of the metal gate: to prevent this degradation a two layer getter film has been develop to absorb a large quantity of H2 per unit of getter surface. The development of Micro Electro Mechanical Systems (MEMS) with moving parts in a vacuum environment required the development of a new generation of getter film, few microns thick, that can be selectively patterned onto a silicon or glass wafer (usually 4'' or 8''). This wafer with patterned getter film can be used directly as the cap wafer of a wafer to wafer bonded MEMS structure, assuring long life and reliability to the moving MEMS structure especially in automotive applications where thermal cycles are required for qualification.

Wafer-scale fabrication of polymer-based microdevices via injection molding and photolithographic micropatterning protocols.

PubMed

Lee, Dae-Sik; Yang, Haesik; Chung, Kwang-Hyo; Pyo, Hyeon-Bong

2005-08-15

Because of their broad applications in biomedical analysis, integrated, polymer-based microdevices incorporating micropatterned metallic and insulating layers are significant in contemporary research. In this study, micropatterns for temperature sensing and microelectrode sets for electroanalysis have been implemented on an injection-molded thin polymer membrane by employing conventional semiconductor processing techniques (i.e., standard photolithographic methods). Cyclic olefin copolymer (COC) is chosen as the polymer substrate because of its high chemical and thermal stability. A COC 5-in. wafer (1-mm thickness) is manufactured using an injection molding method, in which polymer membranes (approximately 130 microm thick and 3 mm x 6 mm in area) are implemented simultaneously in order to reduce local thermal mass around micropatterned heaters and temperature sensors. The highly polished surface (approximately 4 nm within 40 microm x 40 microm area) of the fabricated COC wafer as well as its good resistance to typical process chemicals makes it possible to use the standard photolithographic and etching protocols on the COC wafer. Gold micropatterns with a minimum 5-microm line width are fabricated for making microheaters, temperature sensors, and microelectrodes. An insulating layer of aluminum oxide (Al2O3) is prepared at a COC-endurable low temperature (approximately 120 degrees C) by using atomic layer deposition and micropatterning for the electrode contacts. The fabricated microdevice for heating and temperature sensing shows improved performance of thermal isolation, and microelectrodes display good electrochemical performances for electrochemical sensors. Thus, this novel 5-in. wafer-level microfabrication method is a simple and cost-effective protocol to prepare polymer substrate and demonstrates good potential for application to highly integrated and miniaturized biomedical devices.

From Global to Cloud Resolving Scale: Experiments with a Scale- and Aerosol-Aware Physics Package and Impact on Tracer Transport

NASA Astrophysics Data System (ADS)

Grell, G. A.; Freitas, S. R.; Olson, J.; Bela, M.

2017-12-01

We will start by providing a summary of the latest cumulus parameterization modeling efforts at NOAA's Earth System Research Laboratory (ESRL) will be presented on both regional and global scales. The physics package includes a scale-aware parameterization of subgrid cloudiness feedback to radiation (coupled PBL, microphysics, radiation, shallow and congestus type convection), the stochastic Grell-Freitas (GF) scale- and aerosol-aware convective parameterization, and an aerosol aware microphysics package. GF is based on a stochastic approach originally implemented by Grell and Devenyi (2002) and described in more detail in Grell and Freitas (2014, ACP). It was expanded to include PDF's for vertical mass flux, as well as modifications to improve the diurnal cycle. This physics package will be used on different scales, spanning global to cloud resolving, to look at the impact on scalar transport and numerical weather prediction.

Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

PubMed

Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

2012-07-17

Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

Wafer-scale design of lightweight and transparent electronics that wraps around hairs

NASA Astrophysics Data System (ADS)

Salvatore, Giovanni A.; Münzenrieder, Niko; Kinkeldei, Thomas; Petti, Luisa; Zysset, Christoph; Strebel, Ivo; Büthe, Lars; Tröster, Gerhard

2014-01-01

Electronics on very thin substrates have shown remarkable bendability, conformability and lightness, which are important attributes for biological tissues sensing, wearable or implantable devices. Here we propose a wafer-scale process scheme to realize ultra flexible, lightweight and transparent electronics on top of a 1-μm thick parylene film that is released from the carrier substrate after the dissolution in water of a polyvinyl- alcohol layer. The thin substrate ensures extreme flexibility, which is demonstrated by transistors that continue to work when wrapped around human hairs. In parallel, the use of amorphous oxide semiconductor and high-K dielectric enables the realization of analogue amplifiers operating at 12 V and above 1 MHz. Electronics can be transferred on any object, surface and on biological tissues like human skin and plant leaves. We foresee a potential application as smart contact lenses, covered with light, transparent and flexible devices, which could serve to monitor intraocular pressure for glaucoma disease.

Wafer-scale Fabrication of Non-Polar Mesoporous GaN Distributed Bragg Reflectors via Electrochemical Porosification.

PubMed

Zhu, Tongtong; Liu, Yingjun; Ding, Tao; Fu, Wai Yuen; Jarman, John; Ren, Christopher Xiang; Kumar, R Vasant; Oliver, Rachel A

2017-03-27

Distributed Bragg reflectors (DBRs) are essential components for the development of optoelectronic devices. For many device applications, it is highly desirable to achieve not only high reflectivity and low absorption, but also good conductivity to allow effective electrical injection of charges. Here, we demonstrate the wafer-scale fabrication of highly reflective and conductive non-polar gallium nitride (GaN) DBRs, consisting of perfectly lattice-matched non-polar (11-20) GaN and mesoporous GaN layers that are obtained by a facile one-step electrochemical etching method without any extra processing steps. The GaN/mesoporous GaN DBRs exhibit high peak reflectivities (>96%) across the entire visible spectrum and wide spectral stop-band widths (full-width at half-maximum >80 nm), while preserving the material quality and showing good electrical conductivity. Such mesoporous GaN DBRs thus provide a promising and scalable platform for high performance GaN-based optoelectronic, photonic, and quantum photonic devices.

Low-Temperature Wafer-Scale Deposition of Continuous 2D SnS2 Films.

PubMed

Mattinen, Miika; King, Peter J; Khriachtchev, Leonid; Meinander, Kristoffer; Gibbon, James T; Dhanak, Vin R; Räisänen, Jyrki; Ritala, Mikko; Leskelä, Markku

2018-04-19

Semiconducting 2D materials, such as SnS 2 , hold immense potential for many applications ranging from electronics to catalysis. However, deposition of few-layer SnS 2 films has remained a great challenge. Herein, continuous wafer-scale 2D SnS 2 films with accurately controlled thickness (2 to 10 monolayers) are realized by combining a new atomic layer deposition process with low-temperature (250 °C) postdeposition annealing. Uniform coating of large-area and 3D substrates is demonstrated owing to the unique self-limiting growth mechanism of atomic layer deposition. Detailed characterization confirms the 1T-type crystal structure and composition, smoothness, and continuity of the SnS 2 films. A two-stage deposition process is also introduced to improve the texture of the films. Successful deposition of continuous, high-quality SnS 2 films at low temperatures constitutes a crucial step toward various applications of 2D semiconductors. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Evaluation of anti-sticking layers performances for 200mm wafer scale Smart NILTM process through surface and defectivity characterizations

NASA Astrophysics Data System (ADS)

Delachat, F.; Phillipe, J.-C.; Larrey, V.; Fournel, F.; Bos, S.; Teyssèdre, H.; Chevalier, Xavier; Nicolet, Célia; Navarro, Christophe; Cayrefourcq, Ian

2018-03-01

In this work, an evaluation of various ASL processes for 200 mm wafer scale in the HERCULES® NIL equipment platform available at the CEA-Leti through the INSPIRE program is reported. The surface and adherence energies were correlated to the AFM and defectivity results in order to select the most promising ASL process for high resolution etch mask applications. The ASL performances of the selected process were evaluated by multiple working stamp fabrication using unpatterned and patterned masters though defectivity monitoring on optical based-inspection tools. Optical and SEM defect reviews were systematically performed. Multiple working stamps fabrication without degradation of the master defectivity was witnessed. This evaluation enabled to benchmark several ASL solutions based on the grafted technology develop by ARKEMA in order to reduce and optimize the soft stamp defectivity prior to its replication and therefore considerably reduce the final imprint defectivity for the Smart NIL process.

Wafer-scale self-organized InP nanopillars with controlled orientation for photovoltaic devices.

PubMed

Sanatinia, Reza; Berrier, Audrey; Dhaka, Veer; Perros, Alexander P; Huhtio, Teppo; Lipsanen, Harri; Anand, Srinivasan

2015-10-16

A unique wafer-scale self-organization process for generation of InP nanopillars is demonstrated, which is based on maskless ion-beam etching (IBE) of InP developed to obtain the nanopillars, where the height, shape, and orientation of the nanopillars can be varied by controlling the processing parameters. The fabricated InP nanopillars exhibit broadband suppression of the reflectance, 'black InP,' a property useful for solar cells. The realization of a conformal p-n junction for carrier collection, in the fabricated solar cells, is achieved by a metalorganic vapor phase epitaxy (MOVPE) overgrowth step on the fabricated pillars. The conformal overgrowth retains the broadband anti-reflection property of the InP nanopillars, indicating the feasibility of this technology for solar cells. Surface passivation of the formed InP nanopillars using sulfur-oleylamine solution resulted in improved solar-cell characteristics. An open-circuit voltage of 0.71 V and an increase of 0.13 V compared to the unpassivated device were achieved.

Wafer-scale metasurface for total power absorption, local field enhancement and single molecule Raman spectroscopy

PubMed Central

Wang, Dongxing; Zhu, Wenqi; Best, Michael D.; Camden, Jon P.; Crozier, Kenneth B.

2013-01-01

The ability to detect molecules at low concentrations is highly desired for applications that range from basic science to healthcare. Considerable interest also exists for ultrathin materials with high optical absorption, e.g. for microbolometers and thermal emitters. Metal nanostructures present opportunities to achieve both purposes. Metal nanoparticles can generate gigantic field enhancements, sufficient for the Raman spectroscopy of single molecules. Thin layers containing metal nanostructures (“metasurfaces”) can achieve near-total power absorption at visible and near-infrared wavelengths. Thus far, however, both aims (i.e. single molecule Raman and total power absorption) have only been achieved using metal nanostructures produced by techniques (high resolution lithography or colloidal synthesis) that are complex and/or difficult to implement over large areas. Here, we demonstrate a metasurface that achieves the near-perfect absorption of visible-wavelength light and enables the Raman spectroscopy of single molecules. Our metasurface is fabricated using thin film depositions, and is of unprecedented (wafer-scale) extent. PMID:24091825

Periodic dielectric structure for production of photonic band gap and method for fabricating the same

DOEpatents

Ozbay, Ekmel; Tuttle, Gary; Michel, Erick; Ho, Kai-Ming; Biswas, Rana; Chan, Che-Ting; Soukoulis, Costas

1995-01-01

A method for fabricating a periodic dielectric structure which exhibits a photonic band gap. Alignment holes are formed in a wafer of dielectric material having a given crystal orientation. A planar layer of elongate rods is then formed in a section of the wafer. The formation of the rods includes the step of selectively removing the dielectric material of the wafer between the rods. The formation of alignment holes and layers of elongate rods and wafers is then repeated to form a plurality of patterned wafers. A stack of patterned wafers is then formed by rotating each successive wafer with respect to the next-previous wafer, and then placing the successive wafer on the stack. This stacking results in a stack of patterned wafers having a four-layer periodicity exhibiting a photonic band gap.

Hot embossed polyethylene through-hole chips for bead-based microfluidic devices

PubMed Central

Chou, Jie; Du, Nan; Ou, Tina; Floriano, Pierre N.; Christodoulides, Nicolaos; McDevitt, John T.

2013-01-01

Over the past decade, there has been a growth of interest in the translation of microfluidic systems into real-world clinical practice, especially for use in point-of-care or near patient settings. While initial fabrication advances in microfluidics involved mainly the etching of silicon and glass, the economics of scaling of these materials is not amendable for point-of-care usage where single-test applications forces cost considerations to be kept low and throughput high. As such, a materials base more consistent with point-of-care needs is required. In this manuscript, the fabrication of a hot embossed, through-hole low-density polyethylene ensembles derived from an anisotropically etched silicon wafer is discussed. This semi-opaque polymer that can be easily sterilized and recycled provides low background noise for fluorescence measurements and yields more affordable cost than other thermoplastics commonly used for microfluidic applications such as cyclic olefin copolymer (COC). To fabrication through-hole microchips from this alternative material for microfluidics, a fabrication technique that uses a high-temperature, high-pressure resistant mold is described. This aluminum-based epoxy mold, serving as the positive master mold for embossing, is casted over etched arrays of pyramidal pits in a silicon wafer. Methods of surface treatment of the wafer prior to casting and PDMS casting of the epoxy are discussed to preserve the silicon wafer for future use. Changes in the thickness of polyethylene are observed for varying embossing temperatures. The methodology described herein can quickly fabricate 20 disposable, single use chips in less than 30 minutes with the ability to scale up 4x by using multiple molds simultaneously. When coupled as a platform supporting porous bead sensors, as in the recently developed Programmable Bio-Nano-Chip, this bead chip system can achieve limits of detection, for the cardiac biomarker C-reactive protein, of 0.3 ng/mL, thereby demonstrating the approach is compatible with high performance, real-world clinical measurements in the context of point-of-care testing. PMID:23183187

The iMoD display: considerations and challenges in fabricating MOEMS on large area glass substrates

NASA Astrophysics Data System (ADS)

Chui, Clarence; Floyd, Philip D.; Heald, David; Arbuckle, Brian; Lewis, Alan; Kothari, Manish; Cummings, Bill; Palmateer, Lauren; Bos, Jan; Chang, Daniel; Chiang, Jedi; Wang, Li-Ming; Pao, Edmon; Su, Fritz; Huang, Vincent; Lin, Wen-Jian; Tang, Wen-Chung; Yeh, Jia-Jiun; Chan, Chen-Chun; Shu, Fang-Ann; Ju, Yuh-Diing

2007-01-01

QUALCOMM has developed and transferred to manufacturing iMoD displays, a MEMS-based reflective display technology. The iMoD array architecture allows for development at wafer scale, yet easily scales up to enable fabrication on flat-panel display (FPD) lines. In this paper, we will describe the device operation, process flow and fabrication, technology transfer issues, and display performance.

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Towards a uniform and large-scale deposition of MoS2 nanosheets via sulfurization of ultra-thin Mo-based solid films.

PubMed

Vangelista, Silvia; Cinquanta, Eugenio; Martella, Christian; Alia, Mario; Longo, Massimo; Lamperti, Alessio; Mantovan, Roberto; Basset, Francesco Basso; Pezzoli, Fabio; Molle, Alessandro

2016-04-29

Large-scale integration of MoS2 in electronic devices requires the development of reliable and cost-effective deposition processes, leading to uniform MoS2 layers on a wafer scale. Here we report on the detailed study of the heterogeneous vapor-solid reaction between a pre-deposited molybdenum solid film and sulfur vapor, thus resulting in a controlled growth of MoS2 films onto SiO2/Si substrates with a tunable thickness and cm(2)-scale uniformity. Based on Raman spectroscopy and photoluminescence, we show that the degree of crystallinity in the MoS2 layers is dictated by the deposition temperature and thickness. In particular, the MoS2 structural disorder observed at low temperature (<750 °C) and low thickness (two layers) evolves to a more ordered crystalline structure at high temperature (1000 °C) and high thickness (four layers). From an atomic force microscopy investigation prior to and after sulfurization, this parametrical dependence is associated with the inherent granularity of the MoS2 nanosheet that is inherited by the pristine morphology of the pre-deposited Mo film. This work paves the way to a closer control of the synthesis of wafer-scale and atomically thin MoS2, potentially extendable to other transition metal dichalcogenides and hence targeting massive and high-volume production for electronic device manufacturing.

Fluorinion transfer in silver-assisted chemical etching for silicon nanowires arrays

NASA Astrophysics Data System (ADS)

Feng, Tianyu; Xu, Youlong; Zhang, Zhengwei; Mao, Shengchun

2015-08-01

Uniform silicon nanowires arrays (SiNWAs) were fabricated on unpolished rough silicon wafers through KOH pretreatment followed by silver-assisted chemical etching (SACE). Density functional theory (DFT) calculations were used to investigate the function of silver (Ag) at atomic scale in the etching process. Among three adsorption sites of Ag atom on Si(1 0 0) surface, Ag(T4) above the fourth-layer surface Si atoms could transfer fluorinion (F-) to adjacent Si successfully due to its stronger electrostatic attraction force between Ag(T4) and F-, smaller azimuth angle of Fsbnd Ag(T4)sbnd Si, shorter bond length of Fsbnd Si compared with Fsbnd Ag. As F- was transferred to adjacent Si by Ag(T4) one by one, the Si got away from the wafer in the form of SiF4 when it bonded with enough F- while Ag(T4) was still attached onto the Si wafer ready for next transfer. Cyclic voltammetry tests confirmed that Ag can improve the etching rate by transferring F- to Si.

Big data driven cycle time parallel prediction for production planning in wafer manufacturing

NASA Astrophysics Data System (ADS)

Wang, Junliang; Yang, Jungang; Zhang, Jie; Wang, Xiaoxi; Zhang, Wenjun Chris

2018-07-01

Cycle time forecasting (CTF) is one of the most crucial issues for production planning to keep high delivery reliability in semiconductor wafer fabrication systems (SWFS). This paper proposes a novel data-intensive cycle time (CT) prediction system with parallel computing to rapidly forecast the CT of wafer lots with large datasets. First, a density peak based radial basis function network (DP-RBFN) is designed to forecast the CT with the diverse and agglomerative CT data. Second, the network learning method based on a clustering technique is proposed to determine the density peak. Third, a parallel computing approach for network training is proposed in order to speed up the training process with large scaled CT data. Finally, an experiment with respect to SWFS is presented, which demonstrates that the proposed CTF system can not only speed up the training process of the model but also outperform the radial basis function network, the back-propagation-network and multivariate regression methodology based CTF methods in terms of the mean absolute deviation and standard deviation.

Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

NASA Astrophysics Data System (ADS)

Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

2016-02-01

In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

Feature Modeling of HfO2 Atomic Layer Deposition Using HfCl4/H2O

NASA Astrophysics Data System (ADS)

Stout, Phillip J.; Adams, Vance; Ventzek, Peter L. G.

2003-03-01

A Monte Carlo based feature scale model (Papaya) has been applied to atomic layer deposition (ALD) of HfO2 using HfCl_4/H_20. The model includes physical effects of transport to surface, specular and diffusive reflection within feature, adsorption, surface diffusion, deposition and etching. Discussed will be the 3D feature modeling of HfO2 deposition in assorted features (vias and trenches). The effect of feature aspect ratios, pulse times, cycle number, and temperature on film thickness, feature coverage, and film Cl fraction (surface/bulk) will be discussed. Differences between HfO2 ALD on blanket wafers and in features will be highlighted. For instance, the minimum pulse times sufficient for surface reaction saturation on blanket wafers needs to be increased when depositing on features. Also, HCl products created during the HfCl4 and H_20 pulses are more likely to react within a feature than at the field, reducing OH coverage within the feature (vs blanket wafer) thus limiting the maximum coverage attainable for a pulse over a feature.

Nonepitaxial Thin-Film InP for Scalable and Efficient Photocathodes.

PubMed

Hettick, Mark; Zheng, Maxwell; Lin, Yongjing; Sutter-Fella, Carolin M; Ager, Joel W; Javey, Ali

2015-06-18

To date, some of the highest performance photocathodes of a photoelectrochemical (PEC) cell have been shown with single-crystalline p-type InP wafers, exhibiting half-cell solar-to-hydrogen conversion efficiencies of over 14%. However, the high cost of single-crystalline InP wafers may present a challenge for future large-scale industrial deployment. Analogous to solar cells, a thin-film approach could address the cost challenges by utilizing the benefits of the InP material while decreasing the use of expensive materials and processes. Here, we demonstrate this approach, using the newly developed thin-film vapor-liquid-solid (TF-VLS) nonepitaxial growth method combined with an atomic-layer deposition protection process to create thin-film InP photocathodes with large grain size and high performance, in the first reported solar device configuration generated by materials grown with this technique. Current-voltage measurements show a photocurrent (29.4 mA/cm(2)) and onset potential (630 mV) approaching single-crystalline wafers and an overall power conversion efficiency of 11.6%, making TF-VLS InP a promising photocathode for scalable and efficient solar hydrogen generation.

Non-Contact Technique for Determining the Mechanical Stress in thin Films on Wafers by Profiler

NASA Astrophysics Data System (ADS)

Djuzhev, N. A.; Dedkova, A. A.; E Gusev, E.; Makhiboroda, M. A.; Glagolev, P. Y.

2017-04-01

This paper presents an algorithm for analysis of relief for the purpose of calculating mechanical stresses in a selected direction on the plate in the form of software package Matlab. The method allows for the measurement sample in the local area. It provides a visual representation of the data and allows to get stress distribution on wafer surface. Automated analysis process reduces the likelihood of errors researcher. Achieved time saving during processing results. In carrying out several measurements possible drawing card plate to predict yield crystals. According to this technique done in measurement of mechanical stresses of thermal silicon oxide film on a silicon substrate. Analysis of the results showed objectivity and reliability calculations. This method can be used for selecting the optimal parameters of the material deposition conditions. In software of device-technological simulation TCAD defined process time, temperature and oxidation of the operation of the sample environment for receiving the set value of the dielectric film thickness. Calculated thermal stresses are in the system silicon-silicon oxide. There is a good correlation between numerical simulations and analytical calculation. It is shown that the nature of occurrence of mechanical stress is not limited to the difference of thermal expansion coefficients of materials.

A low power, microvalve regulated architecture for drug delivery systems.

PubMed

Evans, Allan Thomas; Park, Jong M; Chiravuri, Srinivas; Gianchandani, Yogesh B

2010-02-01

This paper describes an actively-controlled architecture for drug delivery systems that offers high performance and volume efficiency through the use of micromachined components. The system uses a controlled valve to regulate dosing by throttling flow from a mechanically pressurized reservoir, thereby eliminating the need for a pump. To this end, the valve is fabricated from a glass wafer and silicon-on-insulator wafer for sensor integration. The valve draws a maximum power of 1.68 μW| (averaged over time); with the existing packaging scheme, it has a volume of 2.475 cm3. The reservoirs are assembled by compressing polyethylene terephthalate polymer balloons with metal springs. The metal springs are fabricated from Elgiloy® using photochemical etching. The springs pressurize the contents of 37 mLchambers up to 15 kPa. The system is integrated with batteries and a control circuit board within a 113 cm3 metal casing. This system has been evaluated in different control modes to mimic clinical applications. Bolus deliveries of1.5 mL have been regulated as well as continuous flows of 0.15 mL/day with accuracies of 3.22%. The results suggest that this device can be used in an implant to regulate intrathecal drug delivery

Periodic dielectric structure for production of photonic band gap and method for fabricating the same

DOEpatents

Ozbay, E.; Tuttle, G.; Michel, E.; Ho, K.M.; Biswas, R.; Chan, C.T.; Soukoulis, C.

1995-04-11

A method is disclosed for fabricating a periodic dielectric structure which exhibits a photonic band gap. Alignment holes are formed in a wafer of dielectric material having a given crystal orientation. A planar layer of elongate rods is then formed in a section of the wafer. The formation of the rods includes the step of selectively removing the dielectric material of the wafer between the rods. The formation of alignment holes and layers of elongate rods and wafers is then repeated to form a plurality of patterned wafers. A stack of patterned wafers is then formed by rotating each successive wafer with respect to the next-previous wafer, and then placing the successive wafer on the stack. This stacking results in a stack of patterned wafers having a four-layer periodicity exhibiting a photonic band gap. 42 figures.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, Theodoer F.

1995-01-01

Apparatus for measuring thicknesses of semiconductor wafers, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light.

A compact linear accelerator based on a scalable microelectromechanical-system RF-structure

DOE PAGES

Persaud, A.; Ji, Q.; Feinberg, E.; ...

2017-06-08

Here, a new approach for a compact radio-frequency (RF) accelerator structure is presented. The new accelerator architecture is based on the Multiple Electrostatic Quadrupole Array Linear Accelerator (MEQALAC) structure that was first developed in the 1980s. The MEQALAC utilized RF resonators producing the accelerating fields and providing for higher beam currents through parallel beamlets focused using arrays of electrostatic quadrupoles (ESQs). While the early work obtained ESQs with lateral dimensions on the order of a few centimeters, using a printed circuit board (PCB), we reduce the characteristic dimension to the millimeter regime, while massively scaling up the potential number ofmore » parallel beamlets. Using Microelectromechanical systems scalable fabrication approaches, we are working on further red ucing the characteristic dimension to the sub-millimeter regime. The technology is based on RF-acceleration components and ESQs implemented in the PCB or silicon wafers where each beamlet passes through beam apertures in the wafer. The complete accelerator is then assembled by stacking these wafers. This approach has the potential for fast and inexpensive batch fabrication of the components and flexibility in system design for application specific beam energies and currents. For prototyping the accelerator architecture, the components have been fabricated using the PCB. In this paper, we present proof of concept results of the principal components using the PCB: RF acceleration and ESQ focusing. Finally, ongoing developments on implementing components in silicon and scaling of the accelerator technology to high currents and beam energies are discussed.« less

A compact linear accelerator based on a scalable microelectromechanical-system RF-structure

NASA Astrophysics Data System (ADS)

Persaud, A.; Ji, Q.; Feinberg, E.; Seidl, P. A.; Waldron, W. L.; Schenkel, T.; Lal, A.; Vinayakumar, K. B.; Ardanuc, S.; Hammer, D. A.

2017-06-01

A new approach for a compact radio-frequency (RF) accelerator structure is presented. The new accelerator architecture is based on the Multiple Electrostatic Quadrupole Array Linear Accelerator (MEQALAC) structure that was first developed in the 1980s. The MEQALAC utilized RF resonators producing the accelerating fields and providing for higher beam currents through parallel beamlets focused using arrays of electrostatic quadrupoles (ESQs). While the early work obtained ESQs with lateral dimensions on the order of a few centimeters, using a printed circuit board (PCB), we reduce the characteristic dimension to the millimeter regime, while massively scaling up the potential number of parallel beamlets. Using Microelectromechanical systems scalable fabrication approaches, we are working on further reducing the characteristic dimension to the sub-millimeter regime. The technology is based on RF-acceleration components and ESQs implemented in the PCB or silicon wafers where each beamlet passes through beam apertures in the wafer. The complete accelerator is then assembled by stacking these wafers. This approach has the potential for fast and inexpensive batch fabrication of the components and flexibility in system design for application specific beam energies and currents. For prototyping the accelerator architecture, the components have been fabricated using the PCB. In this paper, we present proof of concept results of the principal components using the PCB: RF acceleration and ESQ focusing. Ongoing developments on implementing components in silicon and scaling of the accelerator technology to high currents and beam energies are discussed.

A compact linear accelerator based on a scalable microelectromechanical-system RF-structure.

PubMed

Persaud, A; Ji, Q; Feinberg, E; Seidl, P A; Waldron, W L; Schenkel, T; Lal, A; Vinayakumar, K B; Ardanuc, S; Hammer, D A

2017-06-01

A new approach for a compact radio-frequency (RF) accelerator structure is presented. The new accelerator architecture is based on the Multiple Electrostatic Quadrupole Array Linear Accelerator (MEQALAC) structure that was first developed in the 1980s. The MEQALAC utilized RF resonators producing the accelerating fields and providing for higher beam currents through parallel beamlets focused using arrays of electrostatic quadrupoles (ESQs). While the early work obtained ESQs with lateral dimensions on the order of a few centimeters, using a printed circuit board (PCB), we reduce the characteristic dimension to the millimeter regime, while massively scaling up the potential number of parallel beamlets. Using Microelectromechanical systems scalable fabrication approaches, we are working on further reducing the characteristic dimension to the sub-millimeter regime. The technology is based on RF-acceleration components and ESQs implemented in the PCB or silicon wafers where each beamlet passes through beam apertures in the wafer. The complete accelerator is then assembled by stacking these wafers. This approach has the potential for fast and inexpensive batch fabrication of the components and flexibility in system design for application specific beam energies and currents. For prototyping the accelerator architecture, the components have been fabricated using the PCB. In this paper, we present proof of concept results of the principal components using the PCB: RF acceleration and ESQ focusing. Ongoing developments on implementing components in silicon and scaling of the accelerator technology to high currents and beam energies are discussed.

Stable wafer-carrier system

DOEpatents

Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

2013-10-22

One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

Atomic mechanism for the growth of wafer-scale single-crystal graphene: theoretical perspective and scanning tunneling microscopy investigations

NASA Astrophysics Data System (ADS)

Niu, Tianchao; Zhang, Jialin; Chen, Wei

2017-12-01

Chemical vapor deposition (CVD) is the most promising approach for producing low-cost, high-quality, and large area graphene. Revealing the graphene growth mechanism at the atomic-scale is of great importance for realizing single crystal graphene (SCG) over wafer scale. Density functional theoretical (DFT) calculations are playing an increasingly important role in revealing the structure of the most stable carbon species, understanding the evolution processes, and disclosing the active sites. Scanning tunneling microscopy (STM) is a powerful surface characterization tool to illustrate the real space distribution and atomic structures of growth intermediates during the CVD process. Combining them together can provide valuable information to improve the atomically controlled growth of SCG. Starting from a basic concept of the substrate effect on realizing SCG, this review covers the progress made in theoretical investigations on various carbon species during graphene growth on different transition metal substrates, in the STM study of the structural intermediates on transition metal surfaces, and in synthesizing graphene nanoribbons with atomic-precise width and edge structure, ending with a perspective on the future development of 2D materials beyond graphene.

Electrically driven monolithic subwavelength plasmonic interconnect circuits

PubMed Central

Liu, Yang; Zhang, Jiasen; Liu, Huaping; Wang, Sheng; Peng, Lian-Mao

2017-01-01

In the post-Moore era, an electrically driven monolithic optoelectronic integrated circuit (OEIC) fabricated from a single material is pursued globally to enable the construction of wafer-scale compact computing systems with powerful processing capabilities and low-power consumption. We report a monolithic plasmonic interconnect circuit (PIC) consisting of a photovoltaic (PV) cascading detector, Au-strip waveguides, and electrically driven surface plasmon polariton (SPP) sources. These components are fabricated from carbon nanotubes (CNTs) via a CMOS (complementary metal-oxide semiconductor)–compatible doping-free technique in the same feature size, which can be reduced to deep-subwavelength scale (~λ/7 to λ/95, λ = 1340 nm) compared with the 14-nm technique node. An OEIC could potentially be configured as a repeater for data transport because of its “photovoltaic” operation mode to transform SPP energy directly into electricity to drive subsequent electronic circuits. Moreover, chip-scale throughput capability has also been demonstrated by fabricating a 20 × 20 PIC array on a 10 mm × 10 mm wafer. Tailoring photonics for monolithic integration with electronics beyond the diffraction limit opens a new era of chip-level nanoscale electronic-photonic systems, introducing a new path to innovate toward much faster, smaller, and cheaper computing frameworks. PMID:29062890

Chemical multisensors with selective encapsulation of ion-selective membranes

NASA Astrophysics Data System (ADS)

Schwager, Felix J.; Bousse, Luc J.; Bowman, Lyn; Meindl, J. D.

Chemical sensors fabricated with simultaneous wafer scale encapsulation of ion selective electrode mambranes are described. The sensors are miniature ion selective electrodes in chambers located on a silicon substrate. These chambers are made by anodically bonding to the silicon a no. 7740 pyrex glass wafer in which cavities were drilled. Pores with dimensions selectable from 50 microns upwards are opened in the roofs of the chambers by drilling with a CO2 laser. Each sensor die contains four cavities which are filled under reduced pressure with liquid membrane material which is subsequently polymerized. The transducers on the cavity floor are Ag/AgCl electrodes. Interconnects between the sensor chambers on each die and bonding pads are made in the silicon substrate.

All silicon electrode photocapacitor for integrated energy storage and conversion.

PubMed

Cohn, Adam P; Erwin, William R; Share, Keith; Oakes, Landon; Westover, Andrew S; Carter, Rachel E; Bardhan, Rizia; Pint, Cary L

2015-04-08

We demonstrate a simple wafer-scale process by which an individual silicon wafer can be processed into a multifunctional platform where one side is adapted to replace platinum and enable triiodide reduction in a dye-sensitized solar cell and the other side provides on-board charge storage as an electrochemical supercapacitor. This builds upon electrochemical fabrication of dual-sided porous silicon and subsequent carbon surface passivation for silicon electrochemical stability. The utilization of this silicon multifunctional platform as a combined energy storage and conversion system yields a total device efficiency of 2.1%, where the high frequency discharge capability of the integrated supercapacitor gives promise for dynamic load-leveling operations to overcome current and voltage fluctuations during solar energy harvesting.

Structured wafer for device processing

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-05-20

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Structured wafer for device processing

DOEpatents

Okandan, Murat; Nielson, Gregory N

2014-11-25

A structured wafer that includes through passages is used for device processing. Each of the through passages extends from or along one surface of the structured wafer and forms a pattern on a top surface area of the structured wafer. The top surface of the structured wafer is bonded to a device layer via a release layer. Devices are processed on the device layer, and are released from the structured wafer using etchant. The through passages within the structured wafer allow the etchant to access the release layer to thereby remove the release layer.

Apparatus and method for measuring the thickness of a semiconductor wafer

DOEpatents

Ciszek, T.F.

1995-03-07

Apparatus for measuring thicknesses of semiconductor wafers is discussed, comprising: housing means for supporting a wafer in a light-tight environment; a light source mounted to the housing at one side of the wafer to emit light of a predetermined wavelength to normally impinge the wafer; a light detector supported at a predetermined distance from a side of the wafer opposite the side on which a light source impinges and adapted to receive light transmitted through the wafer; and means for measuring the transmitted light. 4 figs.

Performance Evaluations of Ceramic Wafer Seals

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

A user's guide to the ssWavelets package

Treesearch

J.H. ​Gove

2017-01-01

ssWavelets is an R package that is meant to be used in conjunction with the sampSurf package (Gove, 2012) to perform wavelet decomposition on the results of a sampling surface simulation. In general, the wavelet filter decomposes the sampSurf simulation results by scale (distance), with each scale corresponding to a different level of the...

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

2018-04-01

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

Porous solid ion exchange wafer for immobilizing biomolecules

DOEpatents

Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

2007-12-11

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

Interferometric thickness calibration of 300 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Quandou; Griesmann, Ulf; Polvani, Robert

2005-12-01

The "Improved Infrared Interferometer" (IR 3) at the National Institute of Standards and Technology (NIST) is a phase-measuring interferometer, operating at a wavelength of 1550 nm, which is being developed for measuring the thickness and thickness variation of low-doped silicon wafers with diameters up to 300 mm. The purpose of the interferometer is to produce calibrated silicon wafers, with a certified measurement uncertainty, which can be used as reference wafers by wafer manufacturers and metrology tool manufacturers. We give an overview of the design of the interferometer and discuss its application to wafer thickness measurements. The conversion of optical thickness, as measured by the interferometer, to the wafer thickness requires knowledge of the refractive index of the material of the wafer. We describe a method for measuring the refractive index which is then used to establish absolute thickness and thickness variation maps for the wafer.

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fong, Theodore E.

2013-05-06

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

Development of microchannel plate x-ray optics

NASA Technical Reports Server (NTRS)

Kaaret, Philip; Chen, Andrew

1994-01-01

The goal of this research program was to develop a novel technique for focusing x-rays based on the optical system of a lobster's eye. A lobster eye employs many closely packed reflecting surfaces arranged within a spherical or cylindrical shell. These optics have two unique properties: they have unlimited fields of view and can be manufactured via replication of identical structures. Because the angular resolution is given by the ratio of the size of the individual optical elements to the focal length, optical elements with sizes on the order of one hundred microns are required to achieve good angular resolution with a compact telescope. We employed anisotropic etching of single crystal silicon wafers for the fabrication of micron-scale optical elements. This technique, commonly referred to as silicon micromachining, is based on silicon fabrication techniques developed by the microelectronics industry. An anisotropic etchant is a chemical which etches certain silicon crystal planes much more rapidly than others. Using wafers in which the slowly etched crystal planes are aligned perpendicularly to the wafer surface, it is possible to etch a pattern completely through a wafer with very little distortion. Our optics consist of rectangular pores etched completely through group of zone axes (110) oriented silicon wafers. The larger surfaces of the pores (the mirror elements) were aligned with the group of zone axes (111) planes of the crystal perpendicular to the wafer surface. We have succeeded in producing silicon lenses with a geometry suitable for 1-d focusing x-ray optics. These lenses have an aspect ratio (40:1) suitable for x-ray reflection and have very good optical surface alignment. We have developed a number of process refinements which improved the quality of the lens geometry and the repeatability of the etch process. A significant progress was made in obtaining good optical surface quality. The RMS roughness was decreased from 110 A for our initial lenses to 30 A in the final lenses. A further factor of three improvement in surface quality is required for the production of efficient x-ray optics. In addition to the silicon fabrication, an x-ray beam line was constructed at Columbia for testing the optics.

Back-illuminated imager and method for making electrical and optical connections to same

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2010-01-01

Methods for bringing or exposing metal pads or traces to the backside of a backside-illuminated imager allow the pads or traces to reside on the illumination side for electrical connection. These methods provide a solution to a key packaging problem for backside thinned imagers. The methods also provide alignment marks for integrating color filters and microlenses to the imager pixels residing on the frontside of the wafer, enabling high performance multispectral and high sensitivity imagers, including those with extremely small pixel pitch. In addition, the methods incorporate a passivation layer for protection of devices against external contamination, and allow interface trap density reduction via thermal annealing. Backside-illuminated imagers with illumination side electrical connections are also disclosed.

Reliable aluminum contact formation by electrostatic bonding

NASA Astrophysics Data System (ADS)

Kárpáti, T.; Pap, A. E.; Radnóczi, Gy; Beke, B.; Bársony, I.; Fürjes, P.

2015-07-01

The paper presents a detailed study of a reliable method developed for aluminum fusion wafer bonding assisted by the electrostatic force evolving during the anodic bonding process. The IC-compatible procedure described allows the parallel formation of electrical and mechanical contacts, facilitating a reliable packaging of electromechanical systems with backside electrical contacts. This fusion bonding method supports the fabrication of complex microelectromechanical systems (MEMS) and micro-opto-electromechanical systems (MOEMS) structures with enhanced temperature stability, which is crucial in mechanical sensor applications such as pressure or force sensors. Due to the applied electrical potential of  -1000 V the Al metal layers are compressed by electrostatic force, and at the bonding temperature of 450 °C intermetallic diffusion causes aluminum ions to migrate between metal layers.

Free-world microelectronic manufacturing equipment

NASA Astrophysics Data System (ADS)

Kilby, J. S.; Arnold, W. H.; Booth, W. T.; Cunningham, J. A.; Hutcheson, J. D.; Owen, R. W.; Runyan, W. R.; McKenney, Barbara L.; McGrain, Moira; Taub, Renee G.

1988-12-01

Equipment is examined and evaluated for the manufacture of microelectronic integrated circuit devices and sources for that equipment within the Free World. Equipment suitable for the following are examined: single-crystal silicon slice manufacturing and processing; required lithographic processes; wafer processing; device packaging; and test of digital integrated circuits. Availability of the equipment is also discussed, now and in the near future. Very adequate equipment for most stages of the integrated circuit manufacturing process is available from several sources, in different countries, although the best and most widely used versions of most manufacturing equipment are made in the United States or Japan. There is also an active market in used equipment, suitable for manufacture of capable integrated circuits with performance somewhat short of the present state of the art.

Advances in photonic MOEMS-MEMS device thinning and polishing

NASA Astrophysics Data System (ADS)

McAneny, James J.; Kennedy, Mark; McGroggan, Tom

2010-02-01

As devices continue to increase in density and complexity, ever more stringent specifications are placed on the wafer scale equipment manufacturers to produce higher quality and higher output. This results in greater investment and more resource being diverted into producing tools and processes which can meet the latest demanding criteria. Substrate materials employed in the fabrication process range from Silicon through InP and include GaAs, InSb and other optical networking or waveguide materials. With this diversity of substrate materials presented, controlling the geometries and surfaces grows progressively more challenging. This article highlights the key parameters which require close monitoring and control in order to produce highly precise wafers as part of the fabrication process. Several as cut and commercially available standard polished wafer materials were used in empirical trials to test tooling options in generating high levels of geometric control over the dimensions while producing high quality surface finishes. Specific attention was given to the measurement and control of: flatness; parallelism/TTV; surface roughness and final target thickness as common specifications required by the industry. By combining the process variables of: plate speed, download pressure, slurry flow rate and concentration, pad type and wafer travel path across the polish pad, the effect of altering these variables was recorded and analysed to realize the optimum process conditions for the materials under test. The results being then used to design improved methods and tooling for the thinning and polishing of photonic materials applied to MOEMS-MEMS device fabrication.

1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10more » billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).« less

Robust wafer identification recognition based on asterisk-shape filter and high-low score comparison method.

PubMed

Hsu, Wei-Chih; Yu, Tsan-Ying; Chen, Kuan-Liang

2009-12-10

Wafer identifications (wafer ID) can be used to identify wafers from each other so that wafer processing can be traced easily. Wafer ID recognition is one of the problems of optical character recognition. The process to recognize wafer IDs is similar to that used in recognizing car license-plate characters. However, due to some unique characteristics, such as the irregular space between two characters and the unsuccessive strokes of wafer ID, it will not get a good result to recognize wafer ID by directly utilizing the approaches used in car license-plate character recognition. Wafer ID scratches are engraved by a laser scribe almost along the following four fixed directions: horizontal, vertical, plus 45 degrees , and minus 45 degrees orientations. The closer to the center line of a wafer ID scratch, the higher the gray level will be. These and other characteristics increase the difficulty to recognize the wafer ID. In this paper a wafer ID recognition scheme based on an asterisk-shape filter and a high-low score comparison method is proposed to cope with the serious influence of uneven luminance and make recognition more efficiently. Our proposed approach consists of some processing stages. Especially in the final recognition stage, a template-matching method combined with stroke analysis is used as a recognizing scheme. This is because wafer IDs are composed of Semiconductor Equipment and Materials International (SEMI) standard Arabic numbers and English alphabets, and thus the template ID images are easy to obtain. Furthermore, compared with the approach that requires prior training, such as a support vector machine, which often needs a large amount of training image samples, no prior training is required for our approach. The testing results show that our proposed scheme can efficiently and correctly segment out and recognize the wafer ID with high performance.

Laser furnace and method for zone refining of semiconductor wafers

NASA Technical Reports Server (NTRS)

Griner, Donald B. (Inventor); zur Burg, Frederick W. (Inventor); Penn, Wayne M. (Inventor)

1988-01-01

A method of zone refining a crystal wafer (116 FIG. 1) comprising the steps of focusing a laser beam to a small spot (120) of selectable size on the surface of the crystal wafer (116) to melt a spot on the crystal wafer, scanning the small laser beam spot back and forth across the surface of the crystal wafer (116) at a constant velocity, and moving the scanning laser beam across a predetermined zone of the surface of the crystal wafer (116) in a direction normal to the laser beam scanning direction and at a selectible velocity to melt and refine the entire crystal wafer (116).

Silicon sample holder for molecular beam epitaxy on pre-fabricated integrated circuits

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Grunthaner, Paula J. (Inventor); Grunthaner, Frank J. (Inventor)

1994-01-01

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

Carbon dioxide capture using resin-wafer electrodeionization

DOEpatents

Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

2015-09-08

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

Control of polysilicon on-film particulates with on-product measurements

NASA Astrophysics Data System (ADS)

Barker, Judith B.; Chain, Elizabeth E.; Plachecki, Vincent E.

1997-08-01

Historically, a number of in-line particle measurements have been performed on separate test wafers included with product wafers during polysilicon processes. By performing film thickness and particulate measurements directly on product wafers, instead, a number of benefits accrue: (1) reduced test wafer usage, (2) reduced test wafer storage requirements, (3) reduced need for equipment to reclaim test wafers, (4) reduced need for direct labor to reclaim test wafers, and (5) reduced engineering 'false alarms' due to incorrectly processed test wafers. Implementation of on-product measurements for the polysilicon diffusion process required a number of changes in both philosophy and methodology. We show the necessary steps to implementation of on-product particle measurements with concern for overall manufacturing efficiency and the need to maintain appropriate control. Particle results from the Tencor 7600 Surfscan are presented.

Highly Transparent Wafer-Scale Synthesis of Crystalline WS2 Nanoparticle Thin Film for Photodetector and Humidity-Sensing Applications.

PubMed

Pawbake, Amit S; Waykar, Ravindra G; Late, Dattatray J; Jadkar, Sandesh R

2016-02-10

In the present investigation, we report a one-step synthesis method of wafer-scale highly crystalline tungsten disulfide (WS2) nanoparticle thin film by using a modified hot wire chemical vapor deposition (HW-CVD) technique. The average size of WS2 nanoparticle is found to be 25-40 nm over an entire 4 in. wafer of quartz substrate. The low-angle XRD data of WS2 nanoparticle shows the highly crystalline nature of sample along with orientation (002) direction. Furthermore, Raman spectroscopy shows two prominent phonon vibration modes of E(1)2g and A1g at ∼356 and ∼420 cm(-1), respectively, indicating high purity of material. The TEM analysis shows good crystalline quality of sample. The synthesized WS2 nanoparticle thin film based device shows good response to humidity and good photosensitivity along with good long-term stability of the device. It was found that the resistance of the films decreases with increasing relative humidity (RH). The maximum humidity sensitivity of 469% along with response time of ∼12 s and recovery time of ∼13 s were observed for the WS2 thin film humidity sensor device. In the case of photodetection, the response time of ∼51 s and recovery time of ∼88 s were observed with sensitivity ∼137% under white light illumination. Our results open up several avenues to grow other transition metal dichalcogenide nanoparticle thin film for large-area nanoelectronics as well as industrial applications.

Electric field directed assembly of high-density microbead arrays†

PubMed Central

Barbee, Kristopher D.; Hsiao, Alexander P.; Heller, Michael J.; Huang, Xiaohua

2010-01-01

We report a method for rapid, electric field directed assembly of high-density protein-conjugated microbead arrays. Photolithography is used to fabricate an array of micron to sub-micron-scale wells in an epoxy-based photoresist on a silicon wafer coated with a thin gold film, which serves as the primary electrode. A thin gasket is used to form a microfluidic chamber between the wafer and a glass coverslip coated with indium-tin oxide, which serves as the counter electrode. Streptavidin-conjugated microbeads suspended in a low conductance buffer are introduced into the chamber and directed into the wells via electrophoresis by applying a series of low voltage electrical pulses across the electrodes. Hundreds of millions of microbeads can be permanently assembled on these arrays in as little as 30 seconds and the process can be monitored in real time using epifluorescence microscopy. The binding of the microbeads to the gold film is robust and occurs through electrochemically induced gold-protein interactions, which allows excess beads to be washed away or recycled. The well and bead sizes are chosen such that only one bead can be captured in each well. Filling efficiencies greater than 99.9% have been demonstrated across wafer-scale arrays with densities as high as 69 million beads per cm2. Potential applications for this technology include the assembly of DNA arrays for high-throughput genome sequencing and antibody arrays for proteomic studies. Following array assembly, this device may also be used to enhance the concentration-dependent processes of various assays through the accelerated transport of molecules using electric fields. PMID:19865735

Photoluminescence Imaging and LBIC Characterization of Defects in mc-Si Solar Cells

NASA Astrophysics Data System (ADS)

Sánchez, L. A.; Moretón, A.; Guada, M.; Rodríguez-Conde, S.; Martínez, O.; González, M. A.; Jiménez, J.

2018-05-01

Today's photovoltaic market is dominated by multicrystalline silicon (mc-Si) based solar cells with around 70% of worldwide production. In order to improve the quality of the Si material, a proper characterization of the electrical activity in mc-Si solar cells is essential. A full-wafer characterization technique such as photoluminescence imaging (PLi) provides a fast inspection of the wafer defects, though at the expense of the spatial resolution. On the other hand, a study of the defects at a microscopic scale can be achieved through the light-beam induced current technique. The combination of these macroscopic and microscopic resolution techniques allows a detailed study of the electrical activity of defects in mc-Si solar cells. In this work, upgraded metallurgical-grade Si solar cells are studied using these two techniques.

Method for synthesis of high quality graphene

DOEpatents

Lanzara, Alessandra [Piedmont, CA; Schmid, Andreas K [Berkeley, CA; Yu, Xiaozhu [Berkeley, CA; Hwang, Choonkyu [Albany, CA; Kohl, Annemarie [Beneditkbeuern, DE; Jozwiak, Chris M [Oakland, CA

2012-03-27

A method is described herein for the providing of high quality graphene layers on silicon carbide wafers in a thermal process. With two wafers facing each other in close proximity, in a first vacuum heating stage, while maintained at a vacuum of around 10.sup.-6 Torr, the wafer temperature is raised to about 1500.degree. C., whereby silicon evaporates from the wafer leaving a carbon rich surface, the evaporated silicon trapped in the gap between the wafers, such that the higher vapor pressure of silicon above each of the wafers suppresses further silicon evaporation. As the temperature of the wafers is raised to about 1530.degree. C. or more, the carbon atoms self assemble themselves into graphene.

Electrochemical method for defect delineation in silicon-on-insulator wafers

DOEpatents

Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

1991-01-01

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

PubMed

Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

2015-11-01

Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. Copyright © 2015 Elsevier B.V. All rights reserved.

Wafer hot spot identification through advanced photomask characterization techniques: part 2

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; Cho, Young; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2017-03-01

Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.

Advancements in n-Type Base Crystalline Silicon Solar Cells and Their Emergence in the Photovoltaic Industry

PubMed Central

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed. PMID:24459433

Advancements in n-type base crystalline silicon solar cells and their emergence in the photovoltaic industry.

PubMed

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

PubMed

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

A hermetic and room-temperature wafer bonding technique based on integrated reactive multilayer systems

NASA Astrophysics Data System (ADS)

Braeuer, J.; Gessner, T.

2014-11-01

This paper focuses on direct deposition and patterning of reactive and nano-scale multilayer films at wafer level. These multilayer structures are called integrated reactive material systems (iRMS). In contrast to the typically used nickel (Ni)/ aluminum (Al) systems, in this work we needed to have our total multilayer film thicknesses smaller than 2.5 µm to reduce stress within the multilayer as well as deposition costs. Thus, we introduced new high energetic iRMS. These films were deposited by using alternating magnetron sputtering from high purity Al- and palladium (Pd)-targets to obtain films with a defined Al:Pd atomic ratio. In this paper, we present the result for reaction characteristics and reaction velocities which were up to 72.5 m s-1 for bond frames with lateral dimensions as low as 20 µm. Furthermore, the feasibility of silicon (Si)-Si, Si-glass as well as Si-ceramic hermetic and metallic wafer bonding at room temperature is presented. We show that by using this bond technology, strong (maximum shear strengths of 235 MPa) and hermetically sealed bond interfaces can be achieved without any additional solder material.

Solar Spectrum Photocatalytic Conversion of CO2 and Water Vapor Into Hydrocarbons Using TiO2 Nanoparticle Membranes

NASA Astrophysics Data System (ADS)

Rani, Sanju; Bao, Ningzhong; Roy, Somnath C.

2014-01-01

A viable option for recycling carbon dioxide is through the sunlight-powered photocatalytic conversion of CO2 and water vapor into hydrocarbon fuels over highly active nanocatalysts. With photocatalytic CO2 reduction sunlight, a renewable energy source as durable as the sun, is used to drive the catalytic reaction with the resultant fuel products compatible with the current hydrocarbon-based energy infrastructure. The use of co-catalyst (Cu, Pt)-sensitized TiO2 nanoparticle wafers in the photocatalytic conversion of CO2 and water vapor to hydrocarbon fuels, with optimal humidity levels and exposure times established. We also attempted to increase product formation by sputtering both co-catalysts on the nanoparticle wafer's surface, with the resulting product rates significantly higher than that of either the Cu or Pt coated samples. When the TiO2 nanoparticle wafers are used in a flow-through membrane implementation we find a significant increase in product rates of formation, including methane, hydrogen, and carbon monoxide. We believe that nanocatalyst-based flow-through membranes are a viable route for achieving large-scale and low cost photocatalytic solar fuel production.

Bio-inspired Fabrication of Complex Hierarchical Structure in Silicon.

PubMed

Gao, Yang; Peng, Zhengchun; Shi, Tielin; Tan, Xianhua; Zhang, Deqin; Huang, Qiang; Zou, Chuanping; Liao, Guanglan

2015-08-01

In this paper, we developed a top-down method to fabricate complex three dimensional silicon structure, which was inspired by the hierarchical micro/nanostructure of the Morpho butterfly scales. The fabrication procedure includes photolithography, metal masking, and both dry and wet etching techniques. First, microscale photoresist grating pattern was formed on the silicon (111) wafer. Trenches with controllable rippled structures on the sidewalls were etched by inductively coupled plasma reactive ion etching Bosch process. Then, Cr film was angled deposited on the bottom of the ripples by electron beam evaporation, followed by anisotropic wet etching of the silicon. The simple fabrication method results in large scale hierarchical structure on a silicon wafer. The fabricated Si structure has multiple layers with uniform thickness of hundreds nanometers. We conducted both light reflection and heat transfer experiments on this structure. They exhibited excellent antireflection performance for polarized ultraviolet, visible and near infrared wavelengths. And the heat flux of the structure was significantly enhanced. As such, we believe that these bio-inspired hierarchical silicon structure will have promising applications in photovoltaics, sensor technology and photonic crystal devices.

Flexible metal-semiconductor-metal device prototype on wafer-scale thick boron nitride layers grown by MOVPE.

PubMed

Li, Xin; Jordan, Matthew B; Ayari, Taha; Sundaram, Suresh; El Gmili, Youssef; Alam, Saiful; Alam, Muhbub; Patriarche, Gilles; Voss, Paul L; Paul Salvestrini, Jean; Ougazzaden, Abdallah

2017-04-11

Practical boron nitride (BN) detector applications will require uniform materials over large surface area and thick BN layers. To report important progress toward these technological requirements, 1~2.5 µm-thick BN layers were grown on 2-inch sapphire substrates by metal-organic vapor phase epitaxy (MOVPE). The structural and optical properties were carefully characterized and discussed. The thick layers exhibited strong band-edge absorption near 215 nm. A highly oriented two-dimensional h-BN structure was formed at the film/sapphire interface, which permitted an effective exfoliation of the thick BN film onto other adhesive supports. And this structure resulted in a metal-semiconductor-metal (MSM) device prototype fabricated on BN membrane delaminating from the substrate. MSM photodiode prototype showed low dark current of 2 nA under 100 V, and 100 ± 20% photoconductivity yield for deep UV light illumination. These wafer-scale MOVPE-grown thick BN layers present great potential for the development of deep UV photodetection applications, and even for flexible (opto-) electronics in the future.

Internal gas and liquid distributor for electrodeionization device

DOEpatents

Lin, YuPo J.; Snyder, Seth W.; Henry, Michael P.; Datta, Saurav

2016-05-17

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The gas and aqueous fluid are introduced into each basic wafer via a porous gas distributor which disperses the gas as micro-sized bubbles laterally throughout the distributor before entering the wafer. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme or inorganic catalyst to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium.

Support apparatus for semiconductor wafer processing

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

2003-06-10

A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

NASA Astrophysics Data System (ADS)

Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

2012-05-01

In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

Low-to-high refractive index contrast transition (RICT) device for low loss polymer-based optical coupling

NASA Astrophysics Data System (ADS)

Calabretta, N.; Cooman, I. A.; Stabile, R.

2018-04-01

We propose for the first time a coupling device concept for passive low-loss optical coupling, which is compatible with the ‘generic’ indium phosphide (InP) multi-project-wafer manufacturing. A low-to-high vertical refractive index contrast transition InP waveguide is designed and tapered down to adiabatically couple light into a top polymer waveguide. The on-chip embedded polymer waveguide is engineered at the chip facets for offering refractive-index and spot-size-matching to silica fiber-arrays. Numerical analysis shows that coupling losses lower than 1.5 dB can be achieved for a TE-polarized light between the InP waveguide and the on-chip embedded polymer waveguide at 1550 nm wavelength. The performance is mainly limited by the difficulty to control single-mode operation. However, coupling losses lower than 1.9 dB can be achieved for a bandwidth as large as 200 nm. Moreover, the foreseen fabrication process steps are indicated, which are compatible with the ‘generic’ InP multi-project-wafer manufacturing. A fabrication error tolerance study is performed, indicating that fabrication errors occur only in 0.25 dB worst case excess losses, as long as high precision lithography is used. The obtained results are promising and may open the route to large port counts and cheap packaging of InP-based photonic integrated chips.

A two layer hermetic-like coating process for on-wafer encapsulation of GaAs MMIC`s

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kaleta, T.; Varmazis, C.; Carney, J.P.

1995-12-31

The authors have developed a low-cost, manufacturable, 2-layer coating process for on-wafer encapsulation of GaAs MMICs. This packaging approach takes advantage of the low dielectric permittivity of polymers such as Benzocyclobutene (BCB) and the sealing properties of ceramics such as SiC to provide both mechanical protection to MMICs during handling and also hermetic-like equivalence to moisture with predictable changes in the electrical performance of the coated MMICs. The effects of coatings on FET parameters, spiral inductors and a two stage X-Band LNA have been investigated. Results on FETs indicate that the internode capacitances Cgs and Cgd exhibited the same incrementalmore » change of 0.035 pF/mm (3 and 25 % increase respectively), while Cds changed by 0.051 pF/mm (27% increase) with very minimal changes in the other FET parameters. The only observed change in spiral inductors was a 112% increase in Cp from 0.006 pF to 0.013 pF. The LNA exhibited a 1 GHz shift in frequency response from 7 to 11 GHz to 6 to 11 GHz with no substantial changes in gain and noise figure. Preliminary reliability investigations on coated devices did not show any failures after 150 hours in autoclave (120C, 100% humidity).« less

Quartz 9-inch size mask blanks for ArF PSM (Phase Shift Mask)

NASA Astrophysics Data System (ADS)

Harashima, Noriyuki; Isozaki, Tatsuya; Kawanishi, Arata; Kanai, Shuichiro; Kageyama, Kagehiro; Iso, Hiroyuki; Chishima, Tatsuya

2017-07-01

Semiconductor technology nodes are steadily miniaturizing. On the other hand, various efforts have been made to reduce costs, mass production lines have shifted from 200 mmφ of Si wafer to 300 mmφ, and technology development of Si wafer 450 mmφ is also in progress. As a photomask, 6-inch size binary Cr mask has been used for many years, but in recent years, the use of 9-inch binary Cr masks for Proximity Lithography Process in automotive applications, MEMS, packages, etc. has increased, and cost reduction has been taken. Since the miniaturization will progress in the above applications in the future, products corresponding to miniaturization are also desired in 9-inch photomasks. The high grade Cr - binary mask blanks used in proximity exposure process, there is a prospect of being able to use it by ULVAC COATING CORPORATION's tireless research. As further demands for miniaturization, KrF and ArF Lithography Process, which are used for steppers and scanners , there are also a demand for 9-inch size Mask Blanks. In ULVAC COATING CORPORATION, we developed a 9 - inch size KrF PSM mask Blanks prototype in 2016 and proposed a new high grade 9 - inch photomask. This time, we have further investigated and developed 9-inch size ArF PSM Mask Blanks corresponding to ArF Lithography Process, so we report it.

MEMS scanner with 2D tilt, piston, and focus motion

NASA Astrophysics Data System (ADS)

Lani, S.; Bayat, D.; Petremand, Y.; Regamey, Y.-J.; Onillon, E.; Pierer, J.; Grossmann, S.

2017-02-01

A MEMS scanner with a high level of motion freedom has been developed. It includes a 2D mechanical tilting capability of +/- 15°, a piston motion of 50μm and a focus/defocus control system of a 2mm diameter mirror. The tilt and piston motion is achieved with an electromagnetic actuation (moving magnet) and the focus control with a deformation of the reflective surface with pneumatic actuation. This required the fabrication of at least one channel on the compliant membrane and a closed cavity below the mirror surface and connected to an external pressure regulator (vacuum to several bars). The fabrication relies on 3 SOI wafers, 2 for forming the compliant membranes and the integrated channel, and 1 to form the cavity mirror. All wafers were then assembled by fusion bonding. Pneumatic actuation for focus control can be achieved from front or back side; function of packaging concept. A reflective coating can be added at the mirror surface depending of the application. The tilt and piston actuation is achieved by electromagnetic actuation for which a magnet is fixed on the moving part of the MEMS device. Finally the MEMS device is mounted on a ceramic PCB, containing the actuation micro-coils. Concept, fabrication, and testing of the devices will be presented. A case study for application in an endoscope with an integrated high power laser and a MEMS steering mechanism will be presented.

Model-Based Infrared Metrology for Advanced Technology Nodes and 300 mm Wafer Processing

NASA Astrophysics Data System (ADS)

Rosenthal, Peter A.; Duran, Carlos; Tower, Josh; Mazurenko, Alex; Mantz, Ulrich; Weidner, Peter; Kasic, Alexander

2005-09-01

The use of infrared spectroscopy for production semiconductor process monitoring has evolved recently from primarily unpatterned, i.e. blanket test wafer measurements in a limited historical application space of blanket epitaxial, BPSG, and FSG layers to new applications involving patterned product wafer measurements, and new measurement capabilities. Over the last several years, the semiconductor industry has adopted a new set of materials associated with copper/low-k interconnects, and new structures incorporating exotic materials including silicon germanium, SOI substrates and high aspect ratio trenches. The new device architectures and more chemically sophisticated materials have raised new process control and metrology challenges that are not addressed by current measurement technology. To address the challenges we have developed a new infrared metrology tool designed for emerging semiconductor production processes, in a package compatible with modern production and R&D environments. The tool incorporates recent advances in reflectance instrumentation including highly accurate signal processing, optimized reflectometry optics, and model-based calibration and analysis algorithms. To meet the production requirements of the modern automated fab, the measurement hardware has been integrated with a fully automated 300 mm platform incorporating front opening unified pod (FOUP) interfaces, automated pattern recognition and high throughput ultra clean robotics. The tool employs a suite of automated dispersion-model analysis algorithms capable of extracting a variety of layer properties from measured spectra. The new tool provides excellent measurement precision, tool matching, and a platform for deploying many new production and development applications. In this paper we will explore the use of model based infrared analysis as a tool for characterizing novel bottle capacitor structures employed in high density dynamic random access memory (DRAM) chips. We will explore the capability of the tool for characterizing multiple geometric parameters associated with the manufacturing process that are important to the yield and performance of advanced bottle DRAM devices.

A Z-Axis Quartz Cross-Fork Micromachined Gyroscope Based on Shear Stress Detection

PubMed Central

Xie, Liqiang; Wu, Xuezhong; Li, Shengyi; Wang, Haoxu; Su, Jianbin; Dong, Peitao

2010-01-01

Here we propose a novel quartz micromachined gyroscope. The sensor has a simple cross-fork structure in the x-y plane of quartz crystal. Shear stress rather than normal stress is utilized to sense Coriolis’ force generated by the input angular rate signal. Compared to traditional quartz gyroscopes, which have two separate sense electrodes on each sidewall, there is only one electrode on each sidewall of the sense beam. As a result, the fabrication of the electrodes is simplified and the structure can be easily miniaturized. In order to increase sensitivity, a pair of proof masses is attached to the ends of the drive beam, and the sense beam has a tapered design. The structure is etched from a z-cut quartz wafer and the electrodes are realized by direct evaporation using the aperture mask method. The drive mode frequency of the prototype is 13.38 kHz, and the quality factor is approximately 1,000 in air. Therefore, the gyroscope can work properly without a vacuum package. The measurement ability of the shear stress detection design scheme is validated by the Coriolis’ force test. The performance of the sensor is characterized on a precision rate table using a specially designed readout circuit. The experimentally obtained scale factor is 1.45 mV/°/s and the nonlinearity is 3.6% in range of ±200 °/s. PMID:22294887

Hot embossed polyethylene through-hole chips for bead-based microfluidic devices.

PubMed

Chou, Jie; Du, Nan; Ou, Tina; Floriano, Pierre N; Christodoulides, Nicolaos; McDevitt, John T

2013-04-15

Over the past decade, there has been a growth of interest in the translation of microfluidic systems into real-world clinical practice, especially for use in point-of-care or near patient settings. While initial fabrication advances in microfluidics involved mainly the etching of silicon and glass, the economics of scaling of these materials is not amendable for point-of-care usage where single-test applications force cost considerations to be kept low and throughput high. As such, materials base more consistent with point-of-care needs is required. In this manuscript, the fabrication of a hot embossed, through-hole low-density polyethylene ensembles derived from an anisotropically etched silicon wafer is discussed. This semi-opaque polymer that can be easily sterilized and recycled provides low background noise for fluorescence measurements and yields more affordable cost than other thermoplastics commonly used for microfluidic applications such as cyclic olefin copolymer (COC). To fabrication through-hole microchips from this alternative material for microfluidics, a fabrication technique that uses a high-temperature, high-pressure resistant mold is described. This aluminum-based epoxy mold, serving as the positive master mold for embossing, is casted over etched arrays of pyramidal pits in a silicon wafer. Methods of surface treatment of the wafer prior to casting and PDMS casting of the epoxy are discussed to preserve the silicon wafer for future use. Changes in the thickness of polyethylene are observed for varying embossing temperatures. The methodology described herein can quickly fabricate 20 disposable, single use chips in less than 30 min with the ability to scale up 4 times by using multiple molds simultaneously. When coupled as a platform supporting porous bead sensors, as in the recently developed Programmable Bio-Nano-Chip, this bead chip system can achieve limits of detection, for the cardiac biomarker C-reactive protein, of 0.3 ng/mL, thereby demonstrating that the approach is compatible with high performance, real-world clinical measurements in the context of point-of-care testing. Copyright © 2012 Elsevier B.V. All rights reserved.

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, G.S.

1998-12-15

Particulate contamination removal from wafers is disclosed using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer`s position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates. 4 figs.

Micro-miniature gas chromatograph column disposed in silicon wafers

DOEpatents

Yu, Conrad M.

2000-01-01

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Advances in LEDs for automotive applications

NASA Astrophysics Data System (ADS)

Bhardwaj, Jy; Peddada, Rao; Spinger, Benno

2016-03-01

High power LEDs were introduced in automotive headlights in 2006-2007, for example as full LED headlights in the Audi R8 or low beam in Lexus. Since then, LED headlighting has become established in premium and volume automotive segments and beginning to enable new compact form factors such as distributed low beam and new functions such as adaptive driving beam. New generations of highly versatile high power LEDs are emerging to meet these application needs. In this paper, we will detail ongoing advances in LED technology that enable revolutionary styling, performance and adaptive control in automotive headlights. As the standards which govern the necessary lumens on the road are well established, increasing luminance enables not only more design freedom but also headlight cost reduction with space and weight saving through more compact optics. Adaptive headlighting is based on LED pixelation and requires high contrast, high luminance, smaller LEDs with high-packing density for pixelated Matrix Lighting sources. Matrix applications require an extremely tight tolerance on not only the X, Y placement accuracy, but also on the Z height of the LEDs given the precision optics used to image the LEDs onto the road. A new generation of chip scale packaged (CSP) LEDs based on Wafer Level Packaging (WLP) have been developed to meet these needs, offering a form factor less than 20% increase over the LED emitter surface footprint. These miniature LEDs are surface mount devices compatible with automated tools for L2 board direct attach (without the need for an interposer or L1 substrate), meeting the high position accuracy as well as the optical and thermal performance. To illustrate the versatility of the CSP LEDs, we will show the results of, firstly, a reflector-based distributed low beam using multiple individual cavities each with only 20mm height and secondly 3x4 to 3x28 Matrix arrays for adaptive full beam. Also a few key trends in rear lighting and impact on LED light source technology are discussed.

ILT based defect simulation of inspection images accurately predicts mask defect printability on wafer

NASA Astrophysics Data System (ADS)

Deep, Prakash; Paninjath, Sankaranarayanan; Pereira, Mark; Buck, Peter

2016-05-01

At advanced technology nodes mask complexity has been increased because of large-scale use of resolution enhancement technologies (RET) which includes Optical Proximity Correction (OPC), Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO). The number of defects detected during inspection of such mask increased drastically and differentiation of critical and non-critical defects are more challenging, complex and time consuming. Because of significant defectivity of EUVL masks and non-availability of actinic inspection, it is important and also challenging to predict the criticality of defects for printability on wafer. This is one of the significant barriers for the adoption of EUVL for semiconductor manufacturing. Techniques to decide criticality of defects from images captured using non actinic inspection images is desired till actinic inspection is not available. High resolution inspection of photomask images detects many defects which are used for process and mask qualification. Repairing all defects is not practical and probably not required, however it's imperative to know which defects are severe enough to impact wafer before repair. Additionally, wafer printability check is always desired after repairing a defect. AIMSTM review is the industry standard for this, however doing AIMSTM review for all defects is expensive and very time consuming. Fast, accurate and an economical mechanism is desired which can predict defect printability on wafer accurately and quickly from images captured using high resolution inspection machine. Predicting defect printability from such images is challenging due to the fact that the high resolution images do not correlate with actual mask contours. The challenge is increased due to use of different optical condition during inspection other than actual scanner condition, and defects found in such images do not have correlation with actual impact on wafer. Our automated defect simulation tool predicts printability of defects at wafer level and automates the process of defect dispositioning from images captured using high resolution inspection machine. It first eliminates false defects due to registration, focus errors, image capture errors and random noise caused during inspection. For the remaining real defects, actual mask-like contours are generated using the Calibre® ILT solution [1][2], which is enhanced to predict the actual mask contours from high resolution defect images. It enables accurate prediction of defect contours, which is not possible from images captured using inspection machine because some information is already lost due to optical effects. Calibre's simulation engine is used to generate images at wafer level using scanner optical conditions and mask-like contours as input. The tool then analyses simulated images and predicts defect printability. It automatically calculates maximum CD variation and decides which defects are severe to affect patterns on wafer. In this paper, we assess the printability of defects for the mask of advanced technology nodes. In particular, we will compare the recovered mask contours with contours extracted from SEM image of the mask and compare simulation results with AIMSTM for a variety of defects and patterns. The results of printability assessment and the accuracy of comparison are presented in this paper. We also suggest how this method can be extended to predict printability of defects identified on EUV photomasks.

Parachute Dynamics Investigations Using a Sensor Package Airdropped from a Small-Scale Airplane

NASA Technical Reports Server (NTRS)

Dooley, Jessica; Lorenz, Ralph D.

2005-01-01

We explore the utility of various sensors by recovering parachute-probe dynamics information from a package released from a small-scale, remote-controlled airplane. The airdrops aid in the development of datasets for the exploration of planetary probe trajectory recovery algorithms, supplementing data collected from instrumented, full-scale tests and computer models.

Effect of Various Packaging Methods on Small-Scale Hanwoo (Korean Native Cattle) during Refrigerated Storage

PubMed Central

Yu, Hwan Hee; Song, Myung Wook; Kim, Tae-Kyung; Choi, Yun-Sang; Cho, Gyu Yong; Lee, Na-Kyoung; Paik, Hyun-Dong

2018-01-01

Abstract The objective of this study was to investigate comparison of physicochemical, microbiological, and sensory characteristics of Hanwoo eye of round by various packaging methods [wrapped packaging (WP), modified atmosphere packaging (MAP), vacuum packaging (VP) with three different vacuum films, and vacuum skin packaging (VSP)] at a small scale. Packaged Hanwoo beef samples were stored in refrigerated conditions (4±1°C) for 28 days. Packaged beef was sampled on days 0, 7, 14, 21, and 28. Physicochemical [pH, surface color, thiobarbituric acid reactive substances (TBARS), and volatile basic nitrogen (VBN) values], microbiological, and sensory analysis of packaged beef samples were performed. VP and VSP samples showed low TBARS and VBN values, and pH and surface color did not change substantially during the 28-day period. For VSP, total viable bacteria, psychrotrophic bacteria, lactic acid bacteria, and coliform counts were lower than those for other packaging systems. Salmonella spp. and Escherichia coli O157:H7 were not detected in any packaged beef samples. A sensory analysis showed that the scores for appearance, flavor, color, and overall acceptability did not change significantly until day 7. In total, VSP was effective with respect to significantly higher a* values, physicochemical stability, and microbial safety in Hanwoo packaging (p<0.05). PMID:29805283

X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

NASA Technical Reports Server (NTRS)

Park, Yeonjoon (Inventor); Kim, Hyun Jung (Inventor); Skuza, Jonathan R. (Inventor); Lee, Kunik (Inventor); Choi, Sang Hyouk (Inventor); King, Glen C. (Inventor)

2017-01-01

An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

Dissolution of Oxygen Precipitate Nuclei in n-Type CZ-Si Wafers to Improve Their Material Quality: Experimental Results

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, Bhushan; Basnyat, Prakash; Devayajanam, Srinivas

2017-01-01

We present experimental results which show that oxygen-related precipitate nuclei (OPN) present in p-doped, n-type, Czochralski wafers can be dissolved using a flash-annealing process, yielding very high quality wafers for high-efficiency solar cells. Flash annealing consists of heating a wafer in an optical furnace to temperature between 1150 and 1250 degrees C for a short time. This process produces a large increase in the minority carrier lifetime (MCLT) and homogenizes each wafer. We have tested wafers from different axial locations of two ingots. All wafers reach nearly the same high value of MCLT. The OPN dissolution is confirmed by oxygenmore » analysis using Fourier transform infrared spectra and injection-level dependence of MCLT.« less

Wafer edge overlay control solution for N7 and beyond

NASA Astrophysics Data System (ADS)

van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

2018-03-01

Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

Noncontact sheet resistance measurement technique for wafer inspection

NASA Astrophysics Data System (ADS)

Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

1995-12-01

A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

The fastclime Package for Linear Programming and Large-Scale Precision Matrix Estimation in R.

PubMed

Pang, Haotian; Liu, Han; Vanderbei, Robert

2014-02-01

We develop an R package fastclime for solving a family of regularized linear programming (LP) problems. Our package efficiently implements the parametric simplex algorithm, which provides a scalable and sophisticated tool for solving large-scale linear programs. As an illustrative example, one use of our LP solver is to implement an important sparse precision matrix estimation method called CLIME (Constrained L 1 Minimization Estimator). Compared with existing packages for this problem such as clime and flare, our package has three advantages: (1) it efficiently calculates the full piecewise-linear regularization path; (2) it provides an accurate dual certificate as stopping criterion; (3) it is completely coded in C and is highly portable. This package is designed to be useful to statisticians and machine learning researchers for solving a wide range of problems.

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

PubMed

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-05-13

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

An SU-8 liquid cell for surface acoustic wave biosensors

NASA Astrophysics Data System (ADS)

Francis, Laurent A.; Friedt, Jean-Michel; Bartic, Carmen; Campitelli, Andrew

2004-08-01

One significant challenge facing biosensor development is packaging. For surface acoustic wave based biosensors, packaging influences the general sensing performance. The acoustic wave is generated and received thanks to interdigital transducers and the separation between the transducers defines the sensing area. Liquids used in biosensing experiments lead to an attenuation of the acoustic signal while in contact with the transducers. We have developed a liquid cell based on photodefinable epoxy SU-8 that prevents the presence of liquid on the transducers, has a small disturbance effect on the propagation of the acoustic wave, does not interfere with the biochemical sensing event, and leads to an integrated sensor system with reproducible properties. The liquid cell is achieved in two steps. In a first step, the SU-8 is precisely patterned around the transducers to define 120 μm thick walls. In a second step and after the dicing of the sensors, a glass capping is placed manually and glued on top of the SU-8 walls. This design approach is an improvement compared to the more classical solution consisting of a pre-molded cell that must be pressed against the device in order to avoid leaks, with negative consequences on the reproducibility of the experimental results. We demonstrate the effectiveness of our approach by protein adsorption monitoring. The packaging materials do not interfere with the biomolecules and have a high chemical resistance. For future developments, wafer level bonding of the quartz capping onto the SU-8 walls is envisioned.

A CWDM photoreceiver module for 10 Gb/s x 4ch interconnection based on a vertical-illumination-type Ge-on-Si photodetectors and a silica-based AWG

NASA Astrophysics Data System (ADS)

Jang, Ki-Seok; Joo, Jiho; Kim, Taeyong; Kim, Sanghoon; Oh, Jin Hyuk; Kim, In Gyoo; Kim, Sun Ae; Kim, Gyungock

2015-03-01

We report a 40 Gb/s photoreceiver based on vertical-illumination type Ge-on-Si photodetectors and a silica-based AWG demultiplexer by employing 4-channel CWDM. The 60um-diameter Ge-on-Si photodetector arrays, grown on a bulk silicon wafer by RPCVD and fabricated with CMOS-compatible process, have ~0.9 A/W responsivity with 13 GHz bandwidth at λ ~ 1330nm. Ge-on-Si photodetector arrays are hybrid-integrated with TIA/LAs and directly-coupled to the AWG. The low-cost FPCB-package based photoreceiver module shows 10.3 Gb/s × 4-channel interconnection with -11 ~ -12.2 dBm sensitivity at a BER = 10-12.

Temperature Dependent Electrical Properties of PZT Wafer

NASA Astrophysics Data System (ADS)

Basu, T.; Sen, S.; Seal, A.; Sen, A.

2016-04-01

The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

Wafer hot spot identification through advanced photomask characterization techniques

NASA Astrophysics Data System (ADS)

Choi, Yohan; Green, Michael; McMurran, Jeff; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

2016-10-01

As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that the classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced characterization methods in order to optimize the mask process to meet the wafer lithographer's needs. These advanced characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled wafer performance.

Epitaxial thinning process

NASA Technical Reports Server (NTRS)

Siegel, C. M. (Inventor)

1984-01-01

A method is described for thinning an epitaxial layer of a wafer that is to be used in producing diodes having a specified breakdown voltage and which also facilitates the thinning process. Current is passed through the epitaxial layer, by connecting a current source between the substrate of the wafer and an electrolyte in which the wafer is immersed. When the wafer is initially immersed, the voltage across the wafer initially drops and then rises at a steep rate. When light is applied to the wafer the voltage drops, and when the light is interrupted the voltage rises again. These changes in voltage, each indicate the breakdown voltage of a Schottky diode that could be prepared from the wafer at that time. The epitaxial layer is thinned by continuing to apply current through the wafer while it is immersed and light is applied, to form an oxide film and when the oxide film is thick the wafer can then be cleaned of oxide and the testing and thinning continued. Uninterrupted thinning can be achieved by first forming an oxide film, and then using an electrolyte that dissolves the oxide about as fast as it is being formed, to limit the thickness of the oxide layer.

Thermal cycling test results of CSP and RF assemblies

NASA Technical Reports Server (NTRS)

Ghaffarian, R.; Nelson, G.; Cooper, M.; Lam, D.; Strudler, S.; Umdekar, A.; Selk, K.; Bjorndahl, B.; Duprey, R.

2000-01-01

A JPL-led chip scale package (CSP) Consortium of enterprises, composed of representing agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.

Thin layer composite unimorph ferroelectric driver and sensor

NASA Technical Reports Server (NTRS)

Hellbaum, Richard F. (Inventor); Bryant, Robert G. (Inventor); Fox, Robert L. (Inventor); Jalink, Jr., Antony (Inventor); Rohrbach, Wayne W. (Inventor); Simpson, Joycelyn O. (Inventor)

2004-01-01

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled, causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

Thin Layer Composite Unimorph Ferroelectric Driver and Sensor

NASA Technical Reports Server (NTRS)

Helbaum, Richard F. (Inventor); Bryant, Robert G. (Inventor); Fox, Robert L. (Inventor); Jalink, Antony, Jr. (Inventor); Rohrbach, Wayne W. (Inventor); Simpson, Joycelyn O. (Inventor)

1995-01-01

A method for forming ferroelectric wafers is provided. A prestress layer is placed on the desired mold. A ferroelectric wafer is placed on top of the prestress layer. The layers are heated and then cooled, causing the ferroelectric wafer to become prestressed. The prestress layer may include reinforcing material and the ferroelectric wafer may include electrodes or electrode layers may be placed on either side of the ferroelectric layer. Wafers produced using this method have greatly improved output motion.

Chemical effect on diffusion in intermetallic compounds

NASA Astrophysics Data System (ADS)

Chen, Yi-Ting

With the trend of big data and the Internet of things, we live in a world full of personal electronic devices and small electronic devices. In order to make the devices more powerful, advanced electronic packaging such as wafer level packaging or 3D IC packaging play an important role. Furthermore, ?-bumps, which connect silicon dies together with dimension less than 10 ?m, are crucial parts in advanced packaging. Owing to the dimension of ?-bumps, they transform into intermetallic compound from tin based solder after the liquid state bonding process. Moreover, many new reliability issues will occur in electronic packaging when the bonding materials change; in this case, we no longer have tin based solder joint, instead, we have intermetallic compound ?-bumps. Most of the potential reliability issues in intermetallic compounds are caused by the chemical reactions driven by atomic diffusion in the material; thus, to know the diffusivities of atoms inside a material is significant and can help us to further analyze the reliability issues. However, we are lacking these kinds of data in intermetallic compound because there are some problems if used traditional Darken's analysis. Therefore, we considered Wagner diffusivity in our system to solve the problems and applied the concept of chemical effect on diffusion by taking the advantage that large amount of energy will release when compounds formed. Moreover, by inventing the holes markers made by Focus ion beam (FIB), we can conduct the diffusion experiment and obtain the tracer diffusivities of atoms inside the intermetallic compound. We applied the technique on Ni3Sn4 and Cu3Sn, which are two of the most common materials in electronic packaging, and the tracer diffusivities are measured under several different temperatures; moreover, microstructure of the intermetallic compounds are investigated to ensure the diffusion environment. Additionally, the detail diffusion mechanism was also discussed in aspect of diffusion activation enthalpy and diffusion pre-factor by using lattice structure simulation. Last but not the least, X-ray photoelectron spectroscopy and First principal calculation simulation were used to observe the electron binding energies in the intermetallic compound and illustrate the partial covalent bonding behavior in the intermetallic compounds.

Soft X-ray multilayers produced by sputtering and molecular beam epitaxy (MBE) - Substrate and interfacial roughness

NASA Astrophysics Data System (ADS)

Kearney, Patrick A.; Slaughter, J. M.; Powers, K. D.; Falco, Charles M.

1988-01-01

Roughness measurements were made on uncoated silicon wafers and float glass using a WYKO TOPO-3D phase shifting interferometry, and the results are reported. The wafers are found to be slightly smoother than the flat glass. The effects of different cleaning methods and of the deposition of silicon 'buffer layers' on substrate roughness are examined. An acid cleaning method is described which gives more consistent results than detergent cleaning. Healing of the roughness due to sputtered silicon buffer layers was not observed on the length scale probed by the WYKO. Sputtered multilayers are characterized using both the WYKO interferometer and low-angle X-ray diffraction in order to yield information about the roughness of the top surface and of the multilayer interfaces. Preliminary results on film growth using molecular beam epitaxy are also presented.

Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication.

PubMed

Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

2017-02-01

In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80-100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

High-throughput preparation of complex multi-scale patterns from block copolymer/homopolymer blend films

NASA Astrophysics Data System (ADS)

Park, Hyungmin; Kim, Jae-Up; Park, Soojin

2012-02-01

A simple, straightforward process for fabricating multi-scale micro- and nanostructured patterns from polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP)/poly(methyl methacrylate) (PMMA) homopolymer in a preferential solvent for PS and PMMA is demonstrated. When the PS-b-P2VP/PMMA blend films were spin-coated onto a silicon wafer, PS-b-P2VP micellar arrays consisting of a PS corona and a P2VP core were formed, while the PMMA macrodomains were isolated, due to the macrophase separation caused by the incompatibility between block copolymer micelles and PMMA homopolymer during the spin-coating process. With an increase of PMMA composition, the size of PMMA macrodomains increased. Moreover, the P2VP blocks have a strong interaction with a native oxide of the surface of the silicon wafer, so that the P2VP wetting layer was first formed during spin-coating, and PS nanoclusters were observed on the PMMA macrodomains beneath. Whereas when a silicon surface was modified with a PS brush layer, the PS nanoclusters underlying PMMA domains were not formed. The multi-scale patterns prepared from copolymer micelle/homopolymer blend films are used as templates for the fabrication of gold nanoparticle arrays by incorporating the gold precursor into the P2VP chains. The combination of nanostructures prepared from block copolymer micellar arrays and macrostructures induced by incompatibility between the copolymer and the homopolymer leads to the formation of complex, multi-scale surface patterns by a simple casting process.A simple, straightforward process for fabricating multi-scale micro- and nanostructured patterns from polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP)/poly(methyl methacrylate) (PMMA) homopolymer in a preferential solvent for PS and PMMA is demonstrated. When the PS-b-P2VP/PMMA blend films were spin-coated onto a silicon wafer, PS-b-P2VP micellar arrays consisting of a PS corona and a P2VP core were formed, while the PMMA macrodomains were isolated, due to the macrophase separation caused by the incompatibility between block copolymer micelles and PMMA homopolymer during the spin-coating process. With an increase of PMMA composition, the size of PMMA macrodomains increased. Moreover, the P2VP blocks have a strong interaction with a native oxide of the surface of the silicon wafer, so that the P2VP wetting layer was first formed during spin-coating, and PS nanoclusters were observed on the PMMA macrodomains beneath. Whereas when a silicon surface was modified with a PS brush layer, the PS nanoclusters underlying PMMA domains were not formed. The multi-scale patterns prepared from copolymer micelle/homopolymer blend films are used as templates for the fabrication of gold nanoparticle arrays by incorporating the gold precursor into the P2VP chains. The combination of nanostructures prepared from block copolymer micellar arrays and macrostructures induced by incompatibility between the copolymer and the homopolymer leads to the formation of complex, multi-scale surface patterns by a simple casting process. Electronic supplementary information (ESI) available: AFM images of PS-b-P2VP/PMMA blend films and cross-sectional line scans. See DOI: 10.1039/c2nr11792d

Consequences of atomic layer etching on wafer scale uniformity in inductively coupled plasmas

NASA Astrophysics Data System (ADS)

Huard, Chad M.; Lanham, Steven J.; Kushner, Mark J.

2018-04-01

Atomic layer etching (ALE) typically divides the etching process into two self-limited reactions. One reaction passivates a single layer of material while the second preferentially removes the passivated layer. As such, under ideal conditions the wafer scale uniformity of ALE should be independent of the uniformity of the reactant fluxes onto the wafers, provided all surface reactions are saturated. The passivation and etch steps should individually asymptotically saturate after a characteristic fluence of reactants has been delivered to each site. In this paper, results from a computational investigation are discussed regarding the uniformity of ALE of Si in Cl2 containing inductively coupled plasmas when the reactant fluxes are both non-uniform and non-ideal. In the parameter space investigated for inductively coupled plasmas, the local etch rate for continuous processing was proportional to the ion flux. When operated with saturated conditions (that is, both ALE steps are allowed to self-terminate), the ALE process is less sensitive to non-uniformities in the incoming ion flux than continuous etching. Operating ALE in a sub-saturation regime resulted in less uniform etching. It was also found that ALE processing with saturated steps requires a larger total ion fluence than continuous etching to achieve the same etch depth. This condition may result in increased resist erosion and/or damage to stopping layers using ALE. While these results demonstrate that ALE provides increased etch depth uniformity, they do not show an improved critical dimension uniformity in all cases. These possible limitations to ALE processing, as well as increased processing time, will be part of the process optimization that includes the benefits of atomic resolution and improved uniformity.

Optic probe for semiconductor characterization

DOEpatents

Sopori, Bhushan L [Denver, CO; Hambarian, Artak [Yerevan, AM

2008-09-02

Described herein is an optical probe (120) for use in characterizing surface defects in wafers, such as semiconductor wafers. The optical probe (120) detects laser light reflected from the surface (124) of the wafer (106) within various ranges of angles. Characteristics of defects in the surface (124) of the wafer (106) are determined based on the amount of reflected laser light detected in each of the ranges of angles. Additionally, a wafer characterization system (100) is described that includes the described optical probe (120).

Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Zaunbracher, K.

2011-07-01

Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finishedmore » cell performance.« less

An Update on Structural Seal Development at NASA GRC

NASA Technical Reports Server (NTRS)

Dunlap, Pat; Steinetz, Bruce; Finkbeiner, Josh; DeMange, Jeff; Taylor, Shawn; Daniels, Chris; Oswald, Jay

2006-01-01

A viewgraph presentation describing advanced structural seal development for NASA exploration is shown. The topics include: 1) GRC Structural Seals Team Research Areas; 2) Research Areas & Objective; 3) Wafer Seal Geometry/Flow Investigations; 4) Wafer Seal Installation DOE Study; 5) Results of Wafer Seal Installation DOE Study; 6) Wafer Geometry Study: Thickness Variations; 7) Wafer Geometry Study: Full-Size vs. Half-Size Wafers; 8) Spring Tube Seal Development; 9) Resiliency Improvement for Rene 41 Spring Tube; 10) Spring Tube Seals: Go-Forward Plan; 11) High Temperature Seal Preloader Development: TZM Canted Coil Spring; 12) TZM Canted Coil Spring Development; 13) Arc Jet Test Rig Development; and 14) Arc Jet Test Rig Status.

EPE analysis of sub-N10 BEoL flow with and without fully self-aligned via using Coventor SEMulator3D

NASA Astrophysics Data System (ADS)

Franke, Joern-Holger; Gallagher, Matt; Murdoch, Gayle; Halder, Sandip; Juncker, Aurelie; Clark, William

2017-03-01

During the last few decades, the semiconductor industry has been able to scale device performance up while driving costs down. What started off as simple geometrical scaling, driven mostly by advances in lithography, has recently been accompanied by advances in processing techniques and in device architectures. The trend to combine efforts using process technology and lithography is expected to intensify, as further scaling becomes ever more difficult. One promising component of future nodes are "scaling boosters", i.e. processing techniques that enable further scaling. An indispensable component in developing these ever more complex processing techniques is semiconductor process modeling software. Visualization of complex 3D structures in SEMulator3D, along with budget analysis on film thicknesses, CD and etch budgets, allow process integrators to compare flows before any physical wafers are run. Hundreds of "virtual" wafers allow comparison of different processing approaches, along with EUV or DUV patterning options for defined layers and different overlay schemes. This "virtual fabrication" technology produces massively parallel process variation studies that would be highly time-consuming or expensive in experiment. Here, we focus on one particular scaling booster, the fully self-aligned via (FSAV). We compare metal-via-metal (mevia-me) chains with self-aligned and fully-self-aligned via's using a calibrated model for imec's N7 BEoL flow. To model overall variability, 3D Monte Carlo modeling of as many variability sources as possible is critical. We use Coventor SEMulator3D to extract minimum me-me distances and contact areas and show how fully self-aligned vias allow a better me-via distance control and tighter via-me contact area variability compared with the standard self-aligned via (SAV) approach.

Strong emission of terahertz radiation from nanostructured Ge surfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kang, Chul; Maeng, Inhee; Kee, Chul-Sik, E-mail: cskee@gist.ac.kr

2015-06-29

Indirect band gap semiconductors are not efficient emitters of terahertz radiation. Here, we report strong emission of terahertz radiation from germanium wafers with nanostructured surfaces. The amplitude of THz radiation from an array of nano-bullets (nano-cones) is more than five (three) times larger than that from a bare-Ge wafer. The power of the terahertz radiation from a Ge wafer with an array of nano-bullets is comparable to that from n-GaAs wafers, which have been widely used as a terahertz source. We find that the THz radiation from Ge wafers with the nano-bullets is even more powerful than that from n-GaAsmore » for frequencies below 0.6 THz. Our results suggest that introducing properly designed nanostructures on indirect band gap semiconductor wafers is a simple and cheap method to improve the terahertz emission efficiency of the wafers significantly.« less

Method for nanomachining high aspect ratio structures

DOEpatents

Yun, Wenbing; Spence, John; Padmore, Howard A.; MacDowell, Alastair A.; Howells, Malcolm R.

2004-11-09

A nanomachining method for producing high-aspect ratio precise nanostructures. The method begins by irradiating a wafer with an energetic charged-particle beam. Next, a layer of patterning material is deposited on one side of the wafer and a layer of etch stop or metal plating base is coated on the other side of the wafer. A desired pattern is generated in the patterning material on the top surface of the irradiated wafer using conventional electron-beam lithography techniques. Lastly, the wafer is placed in an appropriate chemical solution that produces a directional etch of the wafer only in the area from which the resist has been removed by the patterning process. The high mechanical strength of the wafer materials compared to the organic resists used in conventional lithography techniques with allows the transfer of the precise patterns into structures with aspect ratios much larger than those previously achievable.

Evaluation of the Technical Feasibility and Effective Cost of Various Wafer Thicknesses for the Manufacture of Solar Cells

NASA Technical Reports Server (NTRS)

1979-01-01

Fourteen wafering characterization runs were completed on a wire saw. Wafer thickness/taper uniformity was excellent. Several alternations and design adjustments were made, facilitating saw operation. A wafering characterization cycle was initiated, and is close to completion. A cell characterization cycle was initiated.

Evaluation of the technical feasibility and effective cost of various wafer thicknesses for the manufacture of solar cells

NASA Technical Reports Server (NTRS)

1978-01-01

Three wafering demonstration runs were completed on the Yasunaga wire saw. Wafer thickness/taper uniformity is excellent. Many small problems were encountered with Yasunaga accessories, slowing the effort. A wafer characterization cycle was defined and will be initiated during the next period.

Intrinsic Gettering in Nitrogen-Doped and Hydrogen-Annealed Czochralski-Grown Silicon Wafers

NASA Astrophysics Data System (ADS)

Goto, Hiroyuki; Pan, Lian-Sheng; Tanaka, Masafumi; Kashima, Kazuhiko

2001-06-01

The properties of nitrogen-doped and hydrogen-annealed Czochralski-grown silicon (NHA-CZ-Si) wafers were investigated in this study. The quality of the subsurface was investigated by monitoring the generation lifetime of minority carriers, as measured by the capacitance-time measurements of a metal oxide silicon capacitor (MOS C-t). The intrinsic gettering (IG) ability was investigated by determining the nickel concentration on the surface and in the subsurface as measured by graphite furnace atomic absorption spectrometry (GFAAS) after the wafer was deliberately contaminated with nickel. From the results obtained, the generation lifetimes of these NHA-CZ-Si wafers were determined to be almost the same as, or a little longer than those of epitaxial wafers, and the IG ability was proportional to the total volume of oxygen precipitates [i.e., bulk micro defects (BMDs)], which was influenced by the oxygen and nitrogen concentrations in the wafers. Therefore, it is suggested that the subsurface of the NHA-CZ-Si wafers is of good quality and the IG capacity is controllable by the nitrogen and oxygen concentrations in the wafers.

Silicon direct bonding approach to high voltage power device (insulated gate bipolar transistors)

NASA Astrophysics Data System (ADS)

Cha, Giho; Kim, Youngchul; Jang, Hyungwoo; Kang, Hyunsoon; Song, Changsub

2001-10-01

Silicon direct bonding technique was successfully applied for the fabrication of high voltage IGBT (Insulated Gate Bipolar Transistor). In this work, 5 inch, p-type CZ wafer for handle wafer and n-type FZ wafer for device wafer were used and bonding the two wafers was performed at reduced pressure (1mmTorr) using a modified vacuum bonding machine. Since the breakdown voltage in high voltage device has been determined by the remained thickness of device layer, grinding and CMP steps should be carefully designed in order to acquire better uniformity of device layer. In order to obtain the higher removal rate and the final better uniformity of device layer, the harmony of the two processes must be considered. We found that the concave type of grinding profile and the optimal thickness of ground wafer was able to reduce the process time of CMP step and also to enhance the final thickness uniformity of device layer up to +/- 1%. Finally, when compared epitaxy layer with SDB wafer, the SDB wafer was found to be more favorable in terms of cost and electrical characteristics.

Arrangement, Dopant Source, And Method For Making Solar Cells

DOEpatents

Rohatgi, Ajeet; Krygowski, Thomas W.

1999-10-26

Disclosed is an arrangement, dopant source and method used in the fabrication of photocells that minimize handling of cell wafers and involve a single furnace step. First, dopant sources are created by depositing selected dopants onto both surfaces of source wafers. The concentration of dopant that is placed on the surface is relatively low so that the sources are starved sources. These sources are stacked with photocell wafers in alternating orientation in a furnace. Next, the temperature is raised and thermal diffusion takes place whereby the dopant leaves the source wafers and becomes diffused in a cell wafer creating the junctions necessary for photocells to operate. The concentration of dopant diffused into a single side of the cell wafer is proportional to the concentration placed on the respective dopant source facing the side of the cell wafer. Then, in the same thermal cycle, a layer of oxide is created by introducing oxygen into the furnace environment after sufficient diffusion has taken place. Finally, the cell wafers receive an anti-reflective coating and electrical contacts for the purpose of gathering electrical charge.

Edge printability: techniques used to evaluate and improve extreme wafer edge printability

NASA Astrophysics Data System (ADS)

Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

2004-05-01

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

Green Packaging Management of Logistics Enterprises

NASA Astrophysics Data System (ADS)

Zhang, Guirong; Zhao, Zongjian

From the connotation of green logistics management, we discuss the principles of green packaging, and from the two levels of government and enterprises, we put forward a specific management strategy. The management of green packaging can be directly and indirectly promoted by laws, regulations, taxation, institutional and other measures. The government can also promote new investment to the development of green packaging materials, and establish specialized institutions to identify new packaging materials, standardization of packaging must also be accomplished through the power of the government. Business units of large scale through the packaging and container-based to reduce the use of packaging materials, develop and use green packaging materials and easy recycling packaging materials for proper packaging.

Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

PubMed

Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

2017-10-01

Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

Particulate contamination removal from wafers using plasmas and mechanical agitation

DOEpatents

Selwyn, Gary S.

1998-01-01

Particulate contamination removal from wafers using plasmas and mechanical agitation. The present invention includes the use of plasmas with mechanical agitation for removing particulate matter from the surface of a wafer. The apparatus hereof comprises a mechanical activator, at least one conducting contact pin for transferring the vibration from the activator to the wafer, clamp fingers that maintain the wafer's position, and means for generating a plasma in the vicinity of the surface of the wafer, all parts of the cleaning apparatus except the mechanical activator and part of the contact pin being contained inside the processing chamber. By exposing a wafer to a plasma and providing motion thereto in a direction perpendicular to its surface, the bonding between the particulate matter and the surface may be overcome. Once free of the wafer surface, the particulates become charged by electrons from the plasma and are drawn into the plasma by attractive forces which keep them from redepositing. The introduction of a flowing gas through the plasma sweeps the particulates away from the wafer and out of the plasma. The entire surface is cleaned during one cleaning step. The use of an rf plasma to accomplish the particulate removal was found to remove more than 90% of the particulates.

Automatic cassette to cassette radiant impulse processor

NASA Astrophysics Data System (ADS)

Sheets, Ronald E.

1985-01-01

Single wafer rapid annealing using high temperature isothermal processing has become increasingly popular in recent years. In addition to annealing, this process is also being investigated for suicide formation, passivation, glass reflow and alloying. Regardless of the application, there is a strong necessity to automate in order to maintain process control, repeatability, cleanliness and throughput. These requirements have been carefully addressed during the design and development of the Model 180 Radiant Impulse Processor which is a totally automatic cassette to cassette wafer processing system. Process control and repeatability are maintained by a closed loop optical pyrometer system which maintains the wafer at the programmed temperature-time conditions. Programmed recipes containing up to 10 steps may be easily entered on the computer keyboard or loaded in from a recipe library stored on a standard 5 {1}/{4″} floppy disk. Cold wall heating chamber construction, controlled environment (N 2, A, forming gas) and quartz wafer carriers prevent contamination of the wafer during high temperature processing. Throughputs of 150-240 wafers per hour are achieved by quickly heating the wafer to temperature (450-1400°C) in 3-6 s with a high intensity, uniform (± 1%) radiant flux of 100 {W}/{cm 2}, parallel wafer handling system and a wafer cool down stage.

Critical dimension control using ultrashort laser for improving wafer critical dimension uniformity

NASA Astrophysics Data System (ADS)

Avizemer, Dan; Sharoni, Ofir; Oshemkov, Sergey; Cohen, Avi; Dayan, Asaf; Khurana, Ranjan; Kewley, Dave

2015-07-01

Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE 6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension-scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.

Chip Scale Package Integrity Assessment by Isothermal Aging

NASA Technical Reports Server (NTRS)

Ghaffarian, Reza

1998-01-01

Many aspects of chip scale package (CSP) technology, with focus on assembly reliability characteristics, are being investigated by the JPL-led consortia. Three types of test vehicles were considered for evaluation and currently two configurations have been built to optimize attachment processes. These test vehicles use numerous package types. To understand potential failure mechanisms of the packages, particularly solder ball attachment, the grid CSPs were subjected to environmental exposure. Package I/Os ranged from 40 to nearly 300. This paper presents both as assembled, up to 1, 000 hours of isothermal aging shear test results and photo micrographs, and tensile test results before and after 1,500 cycles in the range of -30/100 C for CSPs. Results will be compared to BGAs with the same the same isothermal aging environmental exposures.

Tip/tilt-compensated through-focus scanning optical microscopy

NASA Astrophysics Data System (ADS)

Lee, Jun Ho; Park, Jun Hyung; Jeong, Dohwan; Shin, Eun Ji; Park, Chris

2016-11-01

Through-Focus Optical Microscopy (TSOM), with nanometer scale lateral and vertical sensitivity matching those of scanning electron microscopy, has been demonstrated to be utilized for 3D inspection and metrology. There have been sensitivity and instability issues in acquiring through-focus images because TSOM 3D information is indirectly extracted by differentiating a target TSOM image from reference TSOM images. This paper first reports on the optical axis instability that occurs during the scanning process of TSOM when implemented in an existing patterned wafer inspection tool by moving the wafer plane; this is followed by quantitative confirmation of the optical/mechanical instability using a new TSOM tool on an optical bench with a Shack-Hartmann wavefront sensor and a tip/tilt sensor. Then, this paper proposes two tip/tilt compensated TSOM optical acquisition methods that can be applied with adaptive optics. The first method simply adopts a tip/tilt mirror with a quad cell in a simple closed loop, while the second method adopts a highorder deformable mirror with a Shack-Hartmann sensor. The second method is able to correct high-order residual aberrations as well as to perform through-focus scanning without z-axis movement, while the first method is easier to implement in pre-existing wafer inspection systems with only minor modification.

Design Considerations in Capacitively Coupled Plasmas

NASA Astrophysics Data System (ADS)

Song, Sang-Heon; Ventzek, Peter; Ranjan, Alok

2015-11-01

Microelectronics industry has driven transistor feature size scaling from 10-6 m to 10-9 m during the past 50 years, which is often referred to as Moore's law. It cannot be overstated that today's information technology would not have been so successful without plasma material processing. One of the major plasma sources for the microelectronics fabrication is capacitively coupled plasmas (CCPs). The CCP reactor has been intensively studied and developed for the deposition and etching of different films on the silicon wafer. As the feature size gets to around 10 nm, the requirement for the process uniformity is less than 1-2 nm across the wafer (300 mm). In order to achieve the desired uniformity, the hardware design should be as precise as possible before the fine tuning of process condition is applied to make it even better. In doing this procedure, the computer simulation can save a significant amount of resources such as time and money which are critical in the semiconductor business. In this presentation, we compare plasma properties using a 2-dimensional plasma hydrodynamics model for different kinds of design factors that can affect the plasma uniformity. The parameters studied in this presentation include chamber accessing port, pumping port, focus ring around wafer substrate, and the geometry of electrodes of CCP.

Defect printability for high-exposure dose advanced packaging applications

NASA Astrophysics Data System (ADS)

Mikles, Max; Flack, Warren; Nguyen, Ha-Ai; Schurz, Dan

2003-12-01

Pellicles are used in semiconductor lithography to minimize printable defects and reduce reticle cleaning frequency. However, there are a growing number of microlithography applications, such as advanced packaging and nanotechnology, where it is not clear that pellicles always offer a significant benefit. These applications have relatively large critical dimensions and require ultra thick photoresists with extremely high exposure doses. Given that the lithography is performed in Class 100 cleanroom conditions, it is possible that the risk of defects from contamination is sufficiently low that pellicles would not be required on certain process layer reticles. The elimination of the pellicle requirement would provide a cost reduction by saving the original pellicle cost and eliminating future pellicle replacement and repair costs. This study examines the imaging potential of defects with reticle patterns and processes typical for gold-bump and solder-bump advanced packaging lithography. The test reticle consists of 30 to 90 μm octagonal contact patterns representative of advanced packaging reticles. Programmed defects are added that represent the range of particle sizes (3 to 30 μm) normally protected by the pellicle and that are typical of advanced packaging lithography cleanrooms. The reticle is exposed using an Ultratech Saturn Spectrum 300e2 1X stepper on wafers coated with a variety of ultra thick (30 to 100 μm) positive and negative-acting photoresists commonly used in advanced packaging. The experimental results show that in many cases smaller particles continue to be yield issues for the feature size and density typical of advanced packaging processes. For the two negative photoresists studied it appears that a pellicle is not required for protection from defects smaller than 10 to 15 μm depending on the photoresist thickness. Thus the decision on pellicle usage for these materials would need to be made based on the device fabrication process and the cleanliness of a fabrication facility. For the two positive photoresists studied it appears that a pellicle is required to protect from defects down to 3 μm defects depending on the photoresist thickness. This suggests that a pellicle should always be used for these materials. Since a typical fabrication facility would use both positive and negative photoresists it may be advantageous to use pellicles on all reticles simply to avoid confusion. The cost savings of not using a pellicle could easily be outweighed by the yield benefits of using one.

Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

NASA Astrophysics Data System (ADS)

Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

2018-03-01

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up to 7KW. The wafer surface is coated with Yttrium oxide film which allows Silicon Etch chemistry. At Fab-8, we carried investigations in 14 nm FEOL critical etch process which has direct impact on yield, using SensorArray EtchTemp-SE wafer, we measured ESC temperature profile across multiple chambers, for both plasma on and plasma off, promising results achieved on chamber temperature signature identification, guideline for chamber to chamber matching improvement. Correlation between wafer mean temperature and determining criticality-process parameters of recess depth and CD is observed. Furthermore, detail zonal temperature/profile correlation is investigated to identify individual correlation in each chuck zone, and provided unique process knobs corresponding to each chunk. Meanwhile, passive ESC Chuck DOE was done to modulate wafer temperature at different zones, and Sensor Array wafer measurements verified temperature responding well with the ESC set point. Correlation R2 = 0.9979 for outer ring and R2 = 0.9981 for Mid Outer ring is observed, as shown in . Experiments planning to modulate edge zone ESC temperature to tune profile within-wafer uniformity and prove gain in edge yield enhancement and to improve edge yield is underway.

Dry etch method for texturing silicon and device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gershon, Talia S.; Haight, Richard A.; Kim, Jeehwan

2017-07-25

A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.

Patterned wafer geometry grouping for improved overlay control

NASA Astrophysics Data System (ADS)

Lee, Honggoo; Han, Sangjun; Woo, Jaeson; Park, Junbeom; Song, Changrock; Anis, Fatima; Vukkadala, Pradeep; Jeon, Sanghuck; Choi, DongSub; Huang, Kevin; Heo, Hoyoung; Smith, Mark D.; Robinson, John C.

2017-03-01

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

Methane production using resin-wafer electrodeionization

DOEpatents

Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

2014-03-25

The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

Reticle variation influence on manufacturing line and wafer device performance

NASA Astrophysics Data System (ADS)

Nistler, John L.; Spurlock, Kyle

1994-01-01

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

Advanced plasma etch technologies for nanopatterning

NASA Astrophysics Data System (ADS)

Wise, Rich

2013-10-01

Advances in patterning techniques have enabled the extension of immersion lithography from 65/45 nm through 14/10 nm device technologies. A key to this increase in patterning capability has been innovation in the subsequent dry plasma etch processing steps. Multiple exposure techniques, such as litho-etch-litho-etch, sidewall image transfer, line/cut mask, and self-aligned structures, have been implemented to solution required device scaling. Advances in dry plasma etch process control across wafer uniformity and etch selectivity to both masking materials have enabled adoption of vertical devices and thin film scaling for increased device performance at a given pitch. Plasma etch processes, such as trilayer etches, aggressive critical dimension shrink techniques, and the extension of resist trim processes, have increased the attainable device dimensions at a given imaging capability. Precise control of the plasma etch parameters affecting across-design variation, defectivity, profile stability within wafer, within lot, and across tools has been successfully implemented to provide manufacturable patterning technology solutions. IBM has addressed these patterning challenges through an integrated total patterning solutions team to provide seamless and synergistic patterning processes to device and integration internal customers. We will discuss these challenges and the innovative plasma etch solutions pioneered by IBM and our alliance partners.

Advanced plasma etch technologies for nanopatterning

NASA Astrophysics Data System (ADS)

Wise, Rich

2012-03-01

Advances in patterning techniques have enabled the extension of immersion lithography from 65/45nm through 14/10nm device technologies. A key to this increase in patterning capability has been innovation in the subsequent dry plasma etch processing steps. Multiple exposure techniques such as litho-etch-litho-etch, sidewall image transfer, line/cut mask and self-aligned structures have been implemented to solution required device scaling. Advances in dry plasma etch process control, across wafer uniformity and etch selectivity to both masking materials and have enabled adoption of vertical devices and thin film scaling for increased device performance at a given pitch. Plasma etch processes such as trilayer etches, aggressive CD shrink techniques, and the extension of resist trim processes have increased the attainable device dimensions at a given imaging capability. Precise control of the plasma etch parameters affecting across design variation, defectivity, profile stability within wafer, within lot, and across tools have been successfully implemented to provide manufacturable patterning technology solutions. IBM has addressed these patterning challenges through an integrated Total Patterning Solutions team to provide seamless and synergistic patterning processes to device and integration internal customers. This paper will discuss these challenges and the innovative plasma etch solutions pioneered by IBM and our alliance partners.

Molecular transport through nanoporous silicon nitride membranes produced from self-assembling block copolymers.

PubMed

Montagne, Franck; Blondiaux, Nicolas; Bojko, Alexandre; Pugin, Raphaël

2012-09-28

To achieve fast and selective molecular filtration, membrane materials must ideally exhibit a thin porous skin and a high density of pores with a narrow size distribution. Here, we report the fabrication of nanoporous silicon nitride membranes (NSiMs) at the full wafer scale using a versatile process combining block copolymer (BCP) self-assembly and conventional photolithography/etching techniques. In our method, self-assembled BCP micelles are used as templates for creating sub-100 nm nanopores in a thin low-stress silicon nitride layer, which is then released from the underlying silicon wafer by etching. The process yields 100 nm thick free-standing NSiMs of various lateral dimensions (up to a few mm(2)). We show that the membranes exhibit a high pore density, while still retaining excellent mechanical strength. Permeation experiments reveal that the molecular transport rate across NSiMs is up to 16-fold faster than that of commercial polymeric membranes. Moreover, using dextran molecules of various molecular weights, we also demonstrate that size-based separation can be achieved with a very good selectivity. These new silicon nanosieves offer a relevant technological alternative to commercially available ultra- and microfiltration membranes for conducting high resolution biomolecular separations at small scales.

Microfabrication of microsystem-enabled photovoltaic (MEPV) cells

NASA Astrophysics Data System (ADS)

Nielson, Gregory N.; Okandan, Murat; Cruz-Campa, Jose L.; Resnick, Paul J.; Wanlass, Mark W.; Clews, Peggy J.; Pluym, Tammy C.; Sanchez, Carlos A.; Gupta, Vipin P.

2011-02-01

Microsystem-Enabled Photovoltaic (MEPV) cells allow solar PV systems to take advantage of scaling benefits that occur as solar cells are reduced in size. We have developed MEPV cells that are 5 to 20 microns thick and down to 250 microns across. We have developed and demonstrated crystalline silicon (c-Si) cells with solar conversion efficiencies of 14.9%, and gallium arsenide (GaAs) cells with a conversion efficiency of 11.36%. In pursuing this work, we have identified over twenty scaling benefits that reduce PV system cost, improve performance, or allow new functionality. To create these cells, we have combined microfabrication techniques from various microsystem technologies. We have focused our development efforts on creating a process flow that uses standard equipment and standard wafer thicknesses, allows all high-temperature processing to be performed prior to release, and allows the remaining post-release wafer to be reprocessed and reused. The c-Si cell junctions are created using a backside point-contact PV cell process. The GaAs cells have an epitaxially grown junction. Despite the horizontal junction, these cells also are backside contacted. We provide recent developments and details for all steps of the process including junction creation, surface passivation, metallization, and release.

Large area nanoimprint by substrate conformal imprint lithography (SCIL)

NASA Astrophysics Data System (ADS)

Verschuuren, Marc A.; Megens, Mischa; Ni, Yongfeng; van Sprang, Hans; Polman, Albert

2017-06-01

Releasing the potential of advanced material properties by controlled structuring materials on sub-100-nm length scales for applications such as integrated circuits, nano-photonics, (bio-)sensors, lasers, optical security, etc. requires new technology to fabricate nano-patterns on large areas (from cm2 to 200 mm up to display sizes) in a cost-effective manner. Conventional high-end optical lithography such as stepper/scanners is highly capital intensive and not flexible towards substrate types. Nanoimprint has had the potential for over 20 years to bring a cost-effective, flexible method for large area nano-patterning. Over the last 3-4 years, nanoimprint has made great progress towards volume production. The main accelerator has been the switch from rigid- to wafer-scale soft stamps and tool improvements for step and repeat patterning. In this paper, we discuss substrate conformal imprint lithography (SCIL), which combines nanometer resolution, low patterns distortion, and overlay alignment, traditionally reserved for rigid stamps, with the flexibility and robustness of soft stamps. This was made possible by a combination of a new soft stamp material, an inorganic resist, combined with an innovative imprint method. Finally, a volume production solution will be presented, which can pattern up to 60 wafers per hour.

Maskless EUV lithography: an already difficult technology made even more complicated?

NASA Astrophysics Data System (ADS)

Chen, Yijian

2012-03-01

In this paper, we present the research progress made in maskless EUV lithography and discuss the emerging opportunities for this disruptive technology. It will be shown nanomirrors based maskless approach is one path to costeffective and defect-free EUV lithography, rather than making it even more complicated. The focus of our work is to optimize the existing vertical comb process and scale down the mirror size from several microns to sub-micron regime. The nanomirror device scaling, system configuration, and design issues will be addressed. We also report our theoretical and simulation study of reflective EUV nanomirror based imaging behavior. Dense line/space patterns are formed with an EUV nanomirror array by assigning a phase shift of π to neighboring nanomirrors. Our simulation results show that phase/intensity imbalance is an inherent characteristic of maskless EUV lithography while it only poses a manageable challenge to CD control and process window. The wafer scan and EUV laser jitter induced image blur phenomenon is discussed and a blurred imaging theory is constructed. This blur effect is found to degrade the image contrast at a level that mainly depends on the wafer scan speed.

Assembly reliability of CSPs with various chiip sizes by accelerated thermal and mechanical cycling test

NASA Technical Reports Server (NTRS)

Ghaffarian, R.

2000-01-01

A JPL-led chip scale package (CSP) Consortium, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.

Characterization of silicon-on-insulator wafers

NASA Astrophysics Data System (ADS)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

NASA Astrophysics Data System (ADS)

Qiusheng, Y.; Senkai, C.; Jisheng, P.

2015-03-01

Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

NASA Astrophysics Data System (ADS)

Matsuoka, Yoichi; Seki, Junichi; Nakayama, Takahiro; Nakagawa, Kazuki; Azuma, Hisanobu; Yamamoto, Kiyohito; Sato, Chiaki; Sakai, Fumio; Takabayashi, Yukio; Aghili, Ali; Mizuno, Makoto; Choi, Jin; Jones, Chris E.

2016-10-01

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. On the mask side, a new replication tool, the FPA-1100 NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control, resolution and image placement accuracy. In this paper we discuss the progress made in both feature resolution and in meeting the image placement specification for replica masks.

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene

DTIC Science & Technology

2014-08-01

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene by Eugene Zakar, Wayne Churaman, Collin Becker, Bernard Rod, Luke...Laboratory Adelphi, MD 20783-1138 ARL-TR-7025 August 2014 Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene...Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6

Optima XE Single Wafer High Energy Ion Implanter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Satoh, Shu; Ferrara, Joseph; Bell, Edward

2008-11-03

The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowingmore » the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.« less

Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

NASA Astrophysics Data System (ADS)

Turner, K. T.; Spearing, S. M.

2002-12-01

Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

A Knowledge Database on Thermal Control in Manufacturing Processes

NASA Astrophysics Data System (ADS)

Hirasawa, Shigeki; Satoh, Isao

A prototype version of a knowledge database on thermal control in manufacturing processes, specifically, molding, semiconductor manufacturing, and micro-scale manufacturing has been developed. The knowledge database has search functions for technical data, evaluated benchmark data, academic papers, and patents. The database also displays trends and future roadmaps for research topics. It has quick-calculation functions for basic design. This paper summarizes present research topics and future research on thermal control in manufacturing engineering to collate the information to the knowledge database. In the molding process, the initial mold and melt temperatures are very important parameters. In addition, thermal control is related to many semiconductor processes, and the main parameter is temperature variation in wafers. Accurate in-situ temperature measurment of wafers is important. And many technologies are being developed to manufacture micro-structures. Accordingly, the knowledge database will help further advance these technologies.

Integrated layout based Monte-Carlo simulation for design arc optimization

NASA Astrophysics Data System (ADS)

Shao, Dongbing; Clevenger, Larry; Zhuang, Lei; Liebmann, Lars; Wong, Robert; Culp, James

2016-03-01

Design rules are created considering a wafer fail mechanism with the relevant design levels under various design cases, and the values are set to cover the worst scenario. Because of the simplification and generalization, design rule hinders, rather than helps, dense device scaling. As an example, SRAM designs always need extensive ground rule waivers. Furthermore, dense design also often involves "design arc", a collection of design rules, the sum of which equals critical pitch defined by technology. In design arc, a single rule change can lead to chain reaction of other rule violations. In this talk we present a methodology using Layout Based Monte-Carlo Simulation (LBMCS) with integrated multiple ground rule checks. We apply this methodology on SRAM word line contact, and the result is a layout that has balanced wafer fail risks based on Process Assumptions (PAs). This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533

Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

PubMed Central

Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

2017-01-01

In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80–100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes. PMID:28145513

Homogeneous transparent conductive ZnO:Ga by ALD for large LED wafers

NASA Astrophysics Data System (ADS)

Szabó, Zoltán; Baji, Zsófia; Basa, Péter; Czigány, Zsolt; Bársony, István; Wang, Hsin-Ying; Volk, János

2016-08-01

Highly conductive and uniform Ga doped ZnO (GZO) films were prepared by atomic layer deposition (ALD) as transparent conductive layers for InGaN/GaN LEDs. The optimal Ga doping concentration was found to be 3 at%. Even for 4" wafers, the TCO layer shows excellent homogeneity of film resistivity (0.8 %) according to Eddy current and spectroscopic ellipsometry mapping. This makes ALD a favourable technique over concurrent methods like MBE and PLD where the up-scaling is problematic. In agreement with previous studies, it was found that by an annealing treatment the quality of the GZO/p-GaN interface can be improved, although it causes the degradation of TCO conductivity. Therefore, a two-step ALD deposition technique was proposed and demonstrated: a "buffer layer" deposited and annealed first was followed by a second deposition step to maintain the high conductivity of the top layer.

Quasi-optical antenna-mixer-array design for terahertz frequencies

NASA Technical Reports Server (NTRS)

Guo, Yong; Potter, Kent A.; Rutledge, David B.

1992-01-01

A new quasi-optical antenna-mixer-array design for terahertz frequencies is presented. In the design, antenna and mixer are combined into an entity, based on the technology in which millimeter-wave horn antenna arrays have been fabricated in silicon wafers. It consists of a set of forward- and backward-looking horns made with a set of silicon wafers. The front side is used to receive incoming signal, and the back side is used to feed local oscillator signal. Intermediate frequency is led out from the side of the array. Signal received by the horn array is picked up by antenna probes suspended on thin silicon-oxynitride membranes inside the horns. Mixer diodes will be located on the membranes inside the horns. Modeling of such an antenna-mixer-array design is done on a scaled model at microwave frequencies. The impedance matching, RF and LO isolation, and patterns of the array have been tested and analyzed.

Laser annealing of ion implanted CZ silicon for solar cell junction formation

NASA Technical Reports Server (NTRS)

Katzeff, J. S.

1981-01-01

The merits of large spot size pulsed laser annealing of phosphorus implanted, Czochralski grown silicon for function formation of solar cells are evaluated. The feasibility and requirements are also determined to scale-up a laser system to anneal 7.62 cm diameter wafers at a rate of one wafer/second. Results show that laser annealing yields active, defect-free, shallow junction devices. Functional cells with AM 1 conversion efficiencies up to 15.4% for 2 x 2 cm and 2 x 4 cm sizes were attained. For larger cells, 7.62 cm dia., conversion efficiencies ranged up to 14.5%. Experiments showed that texture etched surfaces are not compatible with pulsed laser annealing due to the surface melting caused by the laser energy. When compared with furnace annealed cells, the laser annealed cells generally exhibited conversion efficiencies which were equal to or better than those furnace annealed. In addition, laser annealing has greater throughput potential.

Contactless measurement of electrical conductivity of semiconductor wafers using the reflection of millimeter waves

NASA Astrophysics Data System (ADS)

Ju, Yang; Inoue, Kojiro; Saka, Masumi; Abe, Hiroyuki

2002-11-01

We present a method for quantitative measurement of electrical conductivity of semiconductor wafers in a contactless fashion by using millimeter waves. A focusing sensor was developed to focus a 110 GHz millimeter wave beam on the surface of a silicon wafer. The amplitude and the phase of the reflection coefficient of the millimeter wave signal were measured by which electrical conductivity of the wafer was determined quantitatively, independent of the permittivity and thickness of the wafers. The conductivity obtained by this method agrees well with that measured by the conventional four-point-probe method.

Localized heating and bonding technique for MEMS packaging

NASA Astrophysics Data System (ADS)

Cheng, Yu-Ting

Localized heating and bonding techniques have been developed for hermetic and vacuum packaging of MEMS devices, including silicon-to-glass fusion, silicon-gold eutectic, and silicon-to-glass bonding using PSG, indium, aluminum, and aluminum/silicon alloy as the intermediate layer. Line shaped phosphorus-doped polysilicon or gold films are used as resistive microheaters to provide enough thermal energy for bonding. The bonding processes are conducted in the common environment of room temperature and atmospheric pressure and can achieve bonding strength comparable to the fracture toughness of bulk silicon in less than 10 minutes. About 5 watts of input power is needed for localized bonding which can seal a 500 x 500 mum2 area. The total input power is determined by the thermal properties of bonding materials, including the heat capacity and latent heat. Two important bonding results are obtained: (1) The surface step created by the electrical interconnect line can be planarized by reflowing the metal solder. (2) Small applied pressure, less than 1MPa, for intimate contact reduces mechanical damage to the device substrate. This new class of bonding technology has potential applications for MEMS fabrication and packaging that require low temperature processing at the wafer level, excellent bonding strength and hermetic sealing characteristics. A hermetic package based on localized aluminum/silicon-to-glass bonding has been successfully fabricated. Less than 0.2 MPa contact pressure with 46mA input current for two parallel 3.5mum wide polysilicon on-chip microheaters can create as high as 700°C bonding temperature and achieve a strong and reliable bond in 7.5 minutes. Accelerated testing in an autoclave shows some packages survive more than 450 hours under 3 atm, 100%RH and 128°C. Premature failure has been attributed to some unbonded regions on the failed samples. The bonding yield and reliability have been improved by increasing bonding time and applied pressure. Finally, vacuum encapsulation of folded-beam comb-drive mu-resonators used as pressure monitors has been demonstrated using localized aluminum/silicon-to-glass bonding. With 3.4 watt heating power, ˜0.2MPa applied contact pressure, and 90 minutes wait time before bonding, vacuum encapsulation can be achieved with the same vacuum level as the packaging environment which is about 25 mtorr. Metal coating used as diffusion barrier and a longer wait time before bonding are used to improve the vacuum level of the package. Long-term measurement of the Q of un-annealed vacuum-packaged mu-resonators, illustrates stable operation after 19 weeks.

High Volume Manufacturing and Field Stability of MEMS Products

NASA Astrophysics Data System (ADS)

Martin, Jack

Low volume MEMS/NEMS production is practical when an attractive concept is implemented with business, manufacturing, packaging, and test support. Moving beyond this to high volume production adds requirements on design, process control, quality, product stability, market size, market maturity, capital investment, and business systems. In a broad sense, this chapter uses a case study approach: It describes and compares the silicon-based MEMS accelerometers, pressure sensors, image projection systems, and gyroscopes that are in high volume production. Although they serve several markets, these businesses have common characteristics. For example, the manufacturing lines use automated semiconductor equipment and standard material sets to make consistent products in large quantities. Standard, well controlled processes are sometimes modified for a MEMS product. However, novel processes that cannot run with standard equipment and material sets are avoided when possible. This reliance on semiconductor tools, as well as the organizational practices required to manufacture clean, particle-free products partially explains why the MEMS market leaders are integrated circuit manufacturers. There are other factors. MEMS and NEMS are enabling technologies, so it can take several years for high volume applications to develop. Indeed, market size is usually a strong function of price. This becomes a vicious circle, because low price requires low cost - a result that is normally achieved only after a product is in high volume production. During the early years, IC companies reduced cost and financial risk by using existing facilities for low volume MEMS production. As a result, product architectures are partially determined by capabilities developed for previous products. This chapter includes a discussion of MEMS product architecture with particular attention to the impact of electronic integration, packaging, and surfaces. Packaging and testing are critical, because they are significant factors in MEMS product cost. These devices have extremelyhigh surface/volume ratios, so performance and stability may depend on the control of surface characteristics after packaging. Looking into the future, the competitive advantage of IC suppliers will decrease as small companies learn to integrate MEMS/NEMS devices on CMOS foundry wafers. Packaging challenges still remain, because most MEMS/NEMS products must interact with the environment without degrading stability or reliability. Generic packaging solutions are unlikely. However, packaging subcontractors recognize that MEMS/NEMS is a growth opportunity. They will spread the overhead burden of high-capital-cost-facilities by developing flexible processes in order to package several types of moderate volume integrated MEMS/NEMS products on the same equipment.

High Volume Manufacturing and Field Stability of MEMS Products

NASA Astrophysics Data System (ADS)

Martin, Jack

Low volume MEMS/NEMS production is practical when an attractive concept is implemented with business, manufacturing, packaging, and test support. Moving beyond this to high volume production adds requirements on design, process control, quality, product stability, market size, market maturity, capital investment, and business systems. In a broad sense, this chapter uses a case study approach: It describes and compares the silicon-based MEMS accelerometers, pressure sensors, image projection systems, and gyroscopes that are in high volume production. Although they serve several markets, these businesses have common characteristics. For example, the manufacturing lines use automated semiconductor equipment and standard material sets to make consistent products in large quantities. Standard, well controlled processes are sometimes modified for a MEMS product. However, novel processes that cannot run with standard equipment and material sets are avoided when possible. This reliance on semiconductor tools, as well as the organizational practices required to manufacture clean, particle-free products partially explains why the MEMS market leaders are integrated circuit manufacturers. There are other factors. MEMS and NEMS are enabling technologies, so it can take several years for high volume applications to develop. Indeed, market size is usually a strong function of price. This becomes a vicious circle, because low price requires low cost - a result that is normally achieved only after a product is in high volume production. During the early years, IC companies reduced cost and financial risk by using existing facilities for low volume MEMS production. As a result, product architectures are partially determined by capabilities developed for previous products. This chapter includes a discussion of MEMS product architecture with particular attention to the impact of electronic integration, packaging, and surfaces. Packaging and testing are critical, because they are significant factors in MEMS product cost. These devices have extremely high surface/volume ratios, so performance and stability may depend on the control of surface characteristics after packaging. Looking into the future, the competitive advantage of IC suppliers will decrease as small companies learn to integrate MEMS/NEMS devices on CMOS foundry wafers. Packaging challenges still remain, because most MEMS/NEMS products must interact with the environment without degrading stability or reliability. Generic packaging solutions are unlikely. However, packaging subcontractors recognize that MEMS/NEMS is a growth opportunity. They will spread the overhead burden of high-capital-cost-facilities by developing flexible processes in order to package several types of moderate volume integrated MEMS/NEMS products on the same equipment.

Recent Advances of VCSEL Photonics

NASA Astrophysics Data System (ADS)

Koyama, Fumio

2006-12-01

A vertical-cavity surface emitting laser (VCSEL) was invented 30 years ago. A lot of unique features can be expected, such as low-power consumption, wafer-level testing, small packaging capability, and so on. The market of VCSELs has been growing up rapidly in recent years, and they are now key devices in local area networks using multimode optical fibers. Also, long wavelength VCSELs are currently attracting much interest for use in single-mode fiber metropolitan area and wide area network applications. In addition, a VCSEL-based disruptive technology enables various consumer applications such as a laser mouse and laser printers. In this paper, the recent advance of VCSEL photonics will be reviewed, which include the wavelength extension of single-mode VCSELs and their wavelength integration/control. Also, this paper explores the potential and challenges for new functions of VCSELs toward optical signal processing.

Degradation and Its Control of Ultraviolet Avalanche Photodiodes Using PEDOT:PSS/ZnSSe Organic-Inorganic Hybrid Structure

NASA Astrophysics Data System (ADS)

Abe, Tomoki; Uchida, Shigeto; Tanaka, Keita; Fujisawa, Takanobu; Kasada, Hirofumi; Ando, Koshi; Akaiwa, Kazuaki; Ichino, Kunio

2018-05-01

We investigated device degradation in PEDOT:PSS/ZnSSe organic-inorganic hybrid ultraviolet avalanche photodiodes (UV-APDs). ZnSSe/n-GaAs wafers were grown by molecular beam epitaxy, and PEDOT:PSS window layers were formed by inkjet technique. We observed rapid degradation with APD-mode stress (˜ 30 V) in the N2 (4 N) atmosphere, while we observed no marked change in forward bias current stress and photocurrent stress. In the case of a vacuum condition, we observed no detectable degradation in the dark avalanche current with APD-mode stress. Therefore, the degradation in the PEDOT:PSS/ZnSSe interface under the APD-mode stress was caused by the residual water vapor or oxygen in the N2 atmosphere and could be controlled by vacuum packaging.

Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

NASA Astrophysics Data System (ADS)

Syed, Ahmed Rashid

Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by employing broadband quartz rod-transducer assembles). Experimental results, as predicted by prior rigorous simulations, prove that the temperature measurement accuracy obtained through several dynamic runs using the above specified approach, is better than +/-2°C. Furthermore, these results are highly repeatable and independent of wafer treatment conditions, thereby extolling the versatility and immunity of the new method from environmental conditions.

A new approach to measure the temperature in rapid thermal processing

NASA Astrophysics Data System (ADS)

Yan, Jiang

This dissertation has presented the research work about a new method to measure the temperatures for the silicon wafer. The new technology is mainly for the rapid thermal processing (RTP) system. RTP is a promising technology in semiconductor manufacturing especially for the devices with minimum feature size less than 0.5 μm. The technique to measure the temperatures of the silicon wafer accurately is the key factor to apply the RTP technology to more critical processes in the manufacturing. Two methods which are mostly used nowadays, thermocouples and pyrometer, all have the limitation to be applied in the RTP. This is the motivation to study the new method using acoustic waves for the temperature measurement. The test system was designed and built up for the study of the acoustic method. The whole system mainly includes the transducer unit, circuit hardware, control software, the computer, and the chamber. The acoustic wave was generated by the PZT-5H transducer. The wave travels through the quartz rod into the silicon wafer. After traveling a certain distances in the wafer, the acoustic waves could be received by other transducers. By measuring the travel time and with the travel distance, the velocity of the acoustic wave traveling in the silicon wafer can be calculated. Because there is a relationship between the velocity and the temperature: the velocities of the acoustic waves traveling in the silicon wafer decrease as the temperatures of the wafer increase, the temperature of the wafer can be finally obtained. The thermocouples were used to check the measurement accuracy of the acoustic method. The temperature mapping across the 8″ silicon wafer was obtained with four transducer sensor unit. The temperatures of the wafer were measured using acoustic method at both static and dynamic status. The main purpose of the tests is to know the measurement accuracy for the new method. The goal of the research work regarding to the accuracy is <=+/-3°C. The measurement was also done under the different wafer conditions in order to clarify that the acoustic method is independent of the wafer conditions.

Study of providing omnidirectional vibration isolation to entire space shuttle payload packages

NASA Technical Reports Server (NTRS)

Chang, C. S.; Robinson, G. D.; Weber, D. E.

1974-01-01

Techniques to provide omnidirectional vibration isolation for a space shuttle payload package were investigated via a reduced-scale model. Development, design, fabrication, assembly and test evaluation of a 0.125-scale isolation model are described. Final drawings for fabricated mechanical components are identified, and prints of all drawings are included.

CORRELATIONS BETWEEN HOMOLOGUE CONCENTRATIONS OF PCDD/FS AND TOXIC EQUIVALENCY VALUES IN LABORATORY-, PACKAGE BOILER-, AND FIELD-SCALE INCINERATORS

EPA Science Inventory

The toxic equivalency (TEQ) values of polychlorinated dibenzo-p-dioxins and polychlorinated dibenzofurans (PCDD/Fs) are predicted with a model based on the homologue concentrations measured from a laboratory-scale reactor (124 data points), a package boiler (61 data points), and ...

Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

NASA Astrophysics Data System (ADS)

Wang, Shing-Dar; Chen, Ting-Wei

2018-06-01

In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in <1 0 0> direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

Novel Ruggedized Packaging Technology for VCSELs

DTIC Science & Technology

2017-03-01

Novel Ruggedized Packaging Technology for VCSELs Charlie Kuznia ckuznia@ultracomm-inc.com Ultra Communications, Inc. Vista, CA, USA, 92081...n ac hieve l ow-power, E MI-immune links within hi gh-performance m ilitary computing an d sensor systems. Figure 1. Chip-scale-packaging of

Multi-wafer bonding technology for the integration of a micromachined Mirau interferometer

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Lullin, Justine; Froemel, Joerg; Wiemer, Maik; Bargiel, Sylwester; Passilly, Nicolas; Gorecki, Christophe; Gessner, Thomas

2015-02-01

The paper presents the multi-wafer bonding technology as well as the integration of electrical connection to the zscanner wafer of the micromachined array-type Mirau interferometer. A Mirau interferometer, which is a key-component of optical coherence tomography (OCT) microsystem, consists of a microlens doublet, a MOEMS Z-scanner, a focusadjustment spacer and a beam splitter plate. For the integration of this MOEMS device heterogeneous bonding of Si, glass and SOI wafers is necessary. Previously, most of the existing methods for multilayer wafer bonding require annealing at high temperature, i.e., 1100°C. To be compatible with MEMS devices, bonding of different material stacks at temperatures lower than 400°C has also been investigated. However, if more components are involved, it becomes less effective due to the alignment accuracy or degradation of surface quality of the not-bonded side after each bonding operation. The proposed technology focuses on 3D integration of heterogeneous building blocks, where the assembly process is compatible with the materials of each wafer stack and with position accuracy which fits optical requirement. A demonstrator with up to 5 wafers bonded lower than 400°C is presented and bond interfaces are evaluated. To avoid the complexity of through wafer vias, a design which creates electrical connections along vertical direction by mounting a wafer stack on a flip chip PCB is proposed. The approach, which adopts vertically-stacked wafers along with electrical connection functionality, provides not only a space-effective integration of MOEMS device but also a design where the Mirau stack can be further integrated with other components of the OCT microsystem easily.

Radiation-Hardened Wafer Scale Integration

DTIC Science & Technology

1989-10-25

unlimited. LEXINGTON MASSACHUSETTS EXECUTIVE SUMMARY A focal plane processor (FPP) for a large array of LWIR photodetectors on a space platform must...It seems certain that large. scanning LWIR arrays will once again be of interest in the future, though their specifications will differ from those... nonuniformity and defects in the ZMR material, but films of good quality produced by this technique are now available commercially from Kopin Corporation. Such

Wafer-scale Reduced Graphene Oxide Films for Nanomechanical Devices

DTIC Science & Technology

2008-08-01

2008, 2 (3), 463–470. (15) Wang, X.; Zhi, L.; Mullen, K. Nano Lett. 2008, 8 (1), 323–327. (16) Stankovich, S.; Dikin , D. A.; Piner, R. D.; Kohlhaas, K. A...Prud’homme, R. K.; Aksay, I. A.; Car, R. Phys. ReV. Lett. 2006, 96 (17), 176101–4. (18) Dikin , D. A.; Stankovich, S.; Zimney, E. J.; Piner, R. D.; Dommett

A CMOS Compatible, Forming Free TaO x ReRAM

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lohn, A. J.; Stevens, J. E.; Mickel, P. R.

2013-08-31

Resistive random access memory (ReRAM) has become a promising candidate for next-generation high-performance non-volatile memory that operates by electrically tuning resistance states via modulating vacancy concentrations. Here, we demonstrate a wafer-scale process for resistive switching in tantalum oxide that is completely CMOS compatible. The resulting devices are forming-free and with greater than 1x10 5 cycle endurance.

High-throughput preparation of complex multi-scale patterns from block copolymer/homopolymer blend films.

PubMed

Park, Hyungmin; Kim, Jae-Up; Park, Soojin

2012-02-21

A simple, straightforward process for fabricating multi-scale micro- and nanostructured patterns from polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP)/poly(methyl methacrylate) (PMMA) homopolymer in a preferential solvent for PS and PMMA is demonstrated. When the PS-b-P2VP/PMMA blend films were spin-coated onto a silicon wafer, PS-b-P2VP micellar arrays consisting of a PS corona and a P2VP core were formed, while the PMMA macrodomains were isolated, due to the macrophase separation caused by the incompatibility between block copolymer micelles and PMMA homopolymer during the spin-coating process. With an increase of PMMA composition, the size of PMMA macrodomains increased. Moreover, the P2VP blocks have a strong interaction with a native oxide of the surface of the silicon wafer, so that the P2VP wetting layer was first formed during spin-coating, and PS nanoclusters were observed on the PMMA macrodomains beneath. Whereas when a silicon surface was modified with a PS brush layer, the PS nanoclusters underlying PMMA domains were not formed. The multi-scale patterns prepared from copolymer micelle/homopolymer blend films are used as templates for the fabrication of gold nanoparticle arrays by incorporating the gold precursor into the P2VP chains. The combination of nanostructures prepared from block copolymer micellar arrays and macrostructures induced by incompatibility between the copolymer and the homopolymer leads to the formation of complex, multi-scale surface patterns by a simple casting process. This journal is © The Royal Society of Chemistry 2012

Boron diffusion in silicon devices

DOEpatents

Rohatgi, Ajeet; Kim, Dong Seop; Nakayashiki, Kenta; Rounsaville, Brian

2010-09-07

Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat ramp-up associated with a first heating cycle that results in a release of an amount of boron for diffusion into the wafer.

Method and Apparatus for Obtaining a Precision Thickness in Semiconductor and Other Wafers

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2002-01-01

A method and apparatus for processing a wafer comprising a material selected from an electrical semiconducting material and an electrical insulating material is presented. The wafer has opposed generally planar front and rear sides and a peripheral edge, wherein said wafer is pressed against a pad in the presence of a slurry to reduce its thickness. The thickness of the wafer is controlled by first forming a recess such as a dimple on the rear side of the wafer. A first electrical conducting strip extends from a first electrical connection means to the base surface of the recess to the second electrical connector. The first electrical conducting strip overlies the base surface of the recess. There is also a second electrical conductor with an electrical potential source between the first electrical connector and the second electrical connector to form. In combination with the first electrical conducting strip, the second electrical conductor forms a closed electrical circuit, and an electrical current flows through the closed electrical circuit. From the front side of the wafer the initial thickness of the wafer is reduced by lapping until the base surface of the recess is reached. The conductive strip is at least partially removed from the base surface to automatically stop the lapping procedure and thereby achieve the desired thickness.

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

PubMed

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

Fabrication of nano-scale Cu bond pads with seal design in 3D integration applications.

PubMed

Chen, K N; Tsang, C K; Wu, W W; Lee, S H; Lu, J Q

2011-04-01

A method to fabricate nano-scale Cu bond pads for improving bonding quality in 3D integration applications is reported. The effect of Cu bonding quality on inter-level via structural reliability for 3D integration applications is investigated. We developed a Cu nano-scale-height bond pad structure and fabrication process for improved bonding quality by recessing oxides using a combination of SiO2 CMP process and dilute HF wet etching. In addition, in order to achieve improved wafer-level bonding, we introduced a seal design concept that prevents corrosion and provides extra mechanical support. Demonstrations of these concepts and processes provide the feasibility of reliable nano-scale 3D integration applications.

Novel wafer stepper with violet LED light source

NASA Astrophysics Data System (ADS)

Ting, Yung-Chiang; Shy, Shyi-Long

2014-03-01

Novel wafer stepper by using contact or proximity printing will be developed, using violet LED light source to replace Hg Arc. lamp or laser. Mirror, filter and condenser lens for Hg Arc. Lamp or laser and reduction lens for projection printing can be discarded. Reliability and manufacturing cost of wafer stepper can be improved. Exposure result by using IP3600 resist and wafer stepper with violet LED light source (wave-length 360nm to 410 nm) will be obtained. This novel wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist with sub-micron to 100 micron thickness.

Method for wafer edge profile extraction using optical images obtained in edge defect inspection process

NASA Astrophysics Data System (ADS)

Okamoto, Hiroaki; Sakaguchi, Naoshi; Hayano, Fuminori

2010-03-01

It is becoming increasingly important to monitor wafer edge profiles in the immersion lithography era. A Nikon edge defect inspection tool acquires the circumferential optical images of the wafer edge during its inspection process. Nikon's unique illumination system and optics make it possible to then convert the brightness data of the captured images to quantifiable edge profile information. During this process the wafer's outer shape is also calculated. Test results show that even newly shipped bare wafers may not have a constant shape over 360 degree. In some cases repeated deformations with 90 degree pitch are observed.

Reducing the Cost of Solar Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scanlon, B.

2012-04-01

Solar-powered electricity prices could soon approach those of power from coal or natural gas thanks to collaborative research with solar startup Ampulse Corporation at the National Renewable Energy Laboratory. Silicon wafers account for almost half the cost of today's solar photovoltaic panels, so reducing or eliminating wafer costs is essential to bringing prices down. Current crystalline silicon technology converts energy in a highly efficient manner; however, that technology is manufactured with processes that could stand some improvement. The industry needs a method that is less complex, creates less waste and uses less energy. First, half the refined silicon is lostmore » as dust in the wafer-sawing process, driving module costs higher. Wafers are sawn off of large cylindrical ingots, or boules, of silicon. A typical 2-meter boule loses as many as 6,000 potential wafers during sawing. Second, the wafers produced are much thicker than necessary. To efficiently convert sunlight into electricity, the wafers need be only one-tenth the typical thickness. NREL, the Oak Ridge National Laboratory and Ampulse have partnered on an approach to eliminate this waste and dramatically lower the cost of the finished solar panels. By using a chemical vapor deposition process to grow the silicon on inexpensive foil, Ampulse is able to make the solar cells just thick enough to convert most of the solar energy into electricity. No more sawdust - and no more wasting refined silicon materials. NREL developed the technology to grow high-quality silicon and ORNL developed the metal foil that has the correct crystal structure to support that growth. Ampulse is installing a pilot manufacturing line in NREL's Process Development Integration Laboratory, where solar companies can work closely with lab scientists on integrated equipment to answer pressing questions related to their technology development, as well as rapidly overcoming R and D challenges and risk. NREL's program is focused on transformative innovation in the domestic PV industry. With knowledge and expertise acquired from the PDIL pilot production line tools, Ampulse plans to design a full-scale production line to accommodate long rolls of metal foil. The Ampulse process 'goes straight from pure silicon-containing gas to high-quality crystal silicon film,' said Brent Nelson, the operational manager for the Process Development Integration Laboratory. 'The advantage is you can make the wafer just as thin as you need it - 10 microns or less.' Most of today's solar cells are made out of wafer crystalline silicon, though thin-film cells made of more exotic elements such as copper, indium, gallium, arsenic, cadmium, tellurium and others are making a strong push into the market. The advantage of silicon is its abundance, because it is derived from sand. Silicon's disadvantage is that purifying it into wafers suitable for solar cells can be expensive and energy intensive. Manufacturers add carbon and heat to sand to produce metallurgical-grade silicon, which is useful in other industries, but not yet suitable for making solar cells. So this metallurgical-grade silicon is then converted to pure trichlorosilane (SiCl3) or silane (SiH4) gas. Typically, the purified gas is then converted to create a silicon feedstock at 1,000 degrees Celsius. This feedstock is melted at 1,414 C and recrystallized into crystal ingots that are finally sawed into wafers. The Ampulse method differs in that it eliminates the last two steps in the traditional process and works directly with the silane gas growing only the needed silicon right onto a foil substrate. A team of NREL scientists had developed a way to use a process called hot-wire chemical vapor deposition to thicken silicon wafers with near perfect crystal structure. Using a hot tungsten filament much like the one found in an incandescent light bulb, the silane gas molecules are broken apart and deposited onto the wafer using the chemical vapor deposition technique at about 700 C - a much lower temperature than needed to make the wafer. The hot filament decomposes the gas, allowing silicon layers to deposit directly onto the substrate. Armed with this new technique, Branz and Teplin searched for ways to grow the silicon on cheaper materials and still use it for solar cells. They found the ideal synergy when visiting venture capitalists from Battelle Ventures asked them whether they could do anything useful with a breakthrough from Oak Ridge's superconducting wire development group. The new development, called the rolling assisted biaxially textured substrate (RABiTS), was just the opportunity the two scientists had been seeking. If metal foil is to work as a substrate, it must be able to act as a seed crystal so the silicon can grow on it with the correct structure. The RABiTS process forms crystals in the foil that are correctly oriented to receive the silicon atoms and lock them into just the right positions.« less

Aluminum-Scandium: A Material for Semiconductor Packaging

NASA Astrophysics Data System (ADS)

Geissler, Ute; Thomas, Sven; Schneider-Ramelow, Martin; Mukhopadhyay, Biswajit; Lang, Klaus-Dieter

2016-10-01

A well-known aluminum-scandium (Al-Sc) alloy, already used in lightweight sports equipment, is about to be established for use in electronic packaging. One application for Al-Sc alloy is manufacture of bonding wires. The special feature of the alloy is its ability to harden by precipitation. The new bonding wires with electrical conductivity similar to pure Al wires can be processed on common wire bonders for aluminum wedge/wedge (w/w) bonding. The wires exhibit very fine-grained microstructure. Small Al3Sc particles are the main reason for its high strength and prevent recrystallization and grain growth at higher temperatures (>150°C). After the wire-bonding process, the interface is well closed. Reliability investigations by active power cycling demonstrated considerably improved lifetime compared with pure Al heavy wires. Furthermore, the Al-Sc alloy was sputter-deposited onto silicon wafer to test it as chip metallization in copper (Cu) ball/wedge bonding technology. After deposition, the layers exhibited fine-grained columnar structure and small coherent Al3Sc particles with dimensions of a few nanometers. These particles inhibit softening processes such as Al splashing in fine wire bonding processes and increase the thickness of remnant Al under the copper balls to 85% of the initial thickness.

Study of cavity effect in micro-Pirani gauge chamber with improved sensitivity for high vacuum regime

NASA Astrophysics Data System (ADS)

Zhang, Guohe; Lai, Junhua; Kong, Yanmei; Jiao, Binbin; Yun, Shichang; Ye, Yuxin

2018-05-01

Ultra-low pressure application of Pirani gauge needs significant improvement of sensitivity and expansion of measureable low pressure limit. However, the performance of Pirani gauge in high vacuum regime remains critical concerns since gaseous thermal conduction with high percentage is essential requirement. In this work, the heat transfer mechanism of micro-Pirani gauge packaged in a non-hermetic chamber was investigated and analyzed compared with the one before wafer-level packaging. The cavity effect, extremely important for the efficient detection of low pressure, was numerically and experimentally analyzed considering the influence of the pressure, the temperature and the effective heat transfer area in micro-Pirani gauge chamber. The thermal conduction model is validated by experiment data of MEMS Pirani gauges with and without capping. It is found that nature gaseous convection in chamber, determined by the Rayleigh number, should be taken into consideration. The experiment and model calculated results show that thermal resistance increases in the molecule regime, and further increases after capping due to the suppression of gaseous convection. The gaseous thermal conduction accounts for an increasing percentage of thermal conduction at low pressure while little changes at high pressure after capping because of the existence of cavity effect improving the sensitivity of cavity-effect-influenced Pirani gauge for high vacuum regime.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Dorn, D.

2012-06-01

Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect bandmore » images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.« less

In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

PubMed Central

Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

2013-01-01

Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

Ileostomy - changing your pouch

MedlinePlus

... it right away. If you have a pouch system made of 2 pieces (a pouch and a wafer) you ... pouch and barrier or wafer (wafers are part of a 2-piece pouch system). Use a stoma guide with different sizes and ...

From magic to technology: materials integration by wafer bonding

NASA Astrophysics Data System (ADS)

Dragoi, Viorel

2006-02-01

Wafer bonding became in the last decade a very powerful technology for MEMS/MOEMS manufacturing. Being able to offer a solution to overcome some problems of the standard processes used for materials integration (e.g. epitaxy, thin films deposition), wafer bonding is nowadays considered an important item in the MEMS engineer toolbox. Different principles governing the wafer bonding processes will be reviewed in this paper. Various types of applications will be presented as examples.

Noncontacting acoustics-based temperature measurement techniques in rapid thermal processing

NASA Astrophysics Data System (ADS)

Lee, Yong J.; Chou, Ching-Hua; Khuri-Yakub, Butrus T.; Saraswat, Krishna C.

1991-04-01

Temperature measurement of silicon wafers based on the temperature dependence of acoustic waves is studied. The change in the temperature-dependent dispersion relations of the plate modes through the wafer can be exploited to provide a viable temperature monitoring scheme with advantages over both thermocouples and pyrometers. Velocity measurements of acoustic waves through a thin layer of ambient directly above the wafer provides the temperature of the wafer-ambient interface. 1.

Model-based correction for local stress-induced overlay errors

NASA Astrophysics Data System (ADS)

Stobert, Ian; Krishnamurthy, Subramanian; Shi, Hongbo; Stiffler, Scott

2018-03-01

Manufacturing embedded DRAM deep trench capacitors can involve etching very deep holes into silicon wafers1. Due to various design constraints, these holes may not be uniformly distributed across the wafer surface. Some wafer processing steps for these trenches results in stress effects which can distort the silicon wafer in a manner that creates localized alignment issues between the trenches and the structures built above them on the wafer. In this paper, we describe a method to model these localized silicon distortions for complex layouts involving billions of deep trench structures. We describe wafer metrology techniques and data which have been used to verify the stress distortion model accuracy. We also provide a description of how this kind of model can be used to manipulate the polygons in the mask tape out flow to compensate for predicted localized misalignments between design shapes from a deep trench mask and subsequent masks.

Cadmium telluride photovoltaic radiation detector

DOEpatents

Agouridis, D.C.; Fox, R.J.

A dosimetry-type radiation detector is provided which employs a polycrystalline, chlorine-compensated cadmium telluride wafer fabricated to operate as a photovoltaic current generator used as the basic detecting element. A photovoltaic junction is formed in the wafer by painting one face of the cadmium telluride wafer with an n-type semi-conductive material. The opposite face of the wafer is painted with an electrically conductive material to serve as a current collector. The detector is mounted in a hermetically sealed vacuum containment. The detector is operated in a photovoltaic mode (zero bias) while DC coupled to a symmetrical differential current amplifier having a very low input impedance. The amplifier converts the current signal generated by radiation impinging upon the barrier surface face of the wafer to a voltage which is supplied to a voltmeter calibrated to read quantitatively the level of radiation incident upon the detecting wafer.

Noncontact Measurement of Doping Profile for Bare Silicon

NASA Astrophysics Data System (ADS)

Kohno, Motohiro; Matsubara, Hideaki; Okada, Hiroshi; Hirae, Sadao; Sakai, Takamasa

1998-10-01

In this study, we evaluate the doping concentrations of bare silicon wafers by noncontact capacitance voltage (C V) measurements. The metal-air-insulator-semiconductor (MAIS) method enables the measurement of C V characteristics of silicon wafers without oxidation and electrode preparation. This method has the advantage that a doping profile close to the wafer surface can be obtained. In our experiment, epitaxial silicon wafers were used to compare the MAIS method with the conventional MIS method. The experimental results obtained from the two methods showed good agreement. Then, doping profiles of boron-doped Czochralski (CZ) wafers were measured by the MAIS method. The result indicated a significant reduction of the doping concentration near the wafer surface. This observation is attributed to the well-known deactivation of boron with atomic hydrogen which permeated the silicon bulk during the polishing process. This deactivation was recovered by annealing in air at 180°C for 120 min.

The reverse laser drilling of transparent materials

NASA Technical Reports Server (NTRS)

Anthony, T. R.; Lindner, P. A.

1980-01-01

Within a limited range of incident laser-beam intensities, laser drilling of a sapphire wafer initiates on the surface of the wafer where the laser beam exits and proceeds upstream in the laser beam to the surface where the laser beam enters the wafer. This reverse laser drilling is the result of the constructive interference between the laser beam and its reflected component on the exit face of the wafer. Constructive interference occurs only at the exit face of the sapphire wafer because the internally reflected laser beam suffers no phase change there. A model describing reverse laser drilling predicts the ranges of incident laser-beam intensity where no drilling, reverse laser drilling, and forward laser drilling can be expected in various materials. The application of reverse laser drilling in fabricating feed-through conductors in silicon-on-sapphire wafers for a massively parallel processer is described.

Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

NASA Astrophysics Data System (ADS)

Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

2018-04-01

Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

Non-contact defect diagnostics in Cz-Si wafers using resonance ultrasonic vibrations

NASA Astrophysics Data System (ADS)

Belyaev, A.; Kochelap, V. A.; Tarasov, I.; Ostapenko, S.

2001-01-01

A new resonance effect of generation of sub-harmonic acoustic vibrations was applied to characterize defects in as-grown and processed Cz-Si wafers. Ultrasonic vibrations were generated into standard 8″ wafers using an external ultrasonic transducer and their amplitude recorded in a non-contact mode using a scanning acoustic probe. By tuning the frequency, f, of the transducer we observed generation of intense sub-harmonic acoustic mode ("whistle" or w-mode) with f/2 frequency. The characteristics of the w-mode-amplitude dependence, frequency scans, spatial distribution allow a clear distinction versus harmonic vibrations of the same wafer. The origin of sub-harmonic vibrations observed on 8″ Cz-Si wafers is attributed to a parametric resonance of flexural vibrations in thin silicon circular plates. We present evidence that "whistle" effect shows a strong dependence on the wafer's growth and processing history and can be used for quality assurance purposes.

Cadmium telluride photovoltaic radiation detector

DOEpatents

Agouridis, Dimitrios C.; Fox, Richard J.

1981-01-01

A dosimetry-type radiation detector is provided which employs a polycrystalline, chlorine-compensated cadmium telluride wafer fabricated to operate as a photovoltaic current generator used as the basic detecting element. A photovoltaic junction is formed in the wafer by painting one face of the cadmium telluride wafer with an n-type semiconductive material. The opposite face of the wafer is painted with an electrically conductive material to serve as a current collector. The detector is mounted in a hermetically sealed vacuum containment. The detector is operated in a photovoltaic mode (zero bias) while DC coupled to a symmetrical differential current amplifier having a very low input impedance. The amplifier converts the current signal generated by radiation impinging upon the barrier surface face of the wafer to a voltage which is supplied to a voltmeter calibrated to read quantitatively the level of radiation incident upon the detecting wafer.

The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line

NASA Astrophysics Data System (ADS)

Lee, Jeffrey; McGarvey, Steve

2013-04-01

The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the standpoint of the generations of hundreds of SSIS recipes for the global member companies of ISMI, it is simply not economically viable to create all recipes based on PSL based light scattering response curves. This paper will explore the challenges/end results encountered with the PSL based SSIS recipe generation and compare those against the challenges/end results of SSIS recipes generated based strictly upon theoretical Bidirectional reflectance distribution function (BRDF) light scattering modeling. The BRDF modeling will allow for the creation of SSIS recipes without PSL deposition, which is greatly appealing for a multitude of both technical and commercial considerations. This paper will also explore the technical challenges of SSIS recipe generation based strictly upon BRDF modeling.

Joint Communications Support Element: The Voice Heard Round the World

DTIC Science & Technology

2013-01-01

Initial Entry Package ( IEP ), Early Entry Package (EEP), and Joint Mobil- ity Package provide secure and nonsecure voice, video, and data to small mobile...teams operating worldwide. The IEP and EEP can be rapidly scaled to meet force surge require- ments from small dismounted teams up to an advance

The Chip-Scale Atomic Clock - Low-Power Physics Package

DTIC Science & Technology

2004-12-01

36th Annual Precise Time and Time Interval (PTTI) Meeting 339 THE CHIP-SCALE ATOMIC CLOCK – LOW-POWER PHYSICS PACKAGE R. Lutwak ...pdf/documents/ds-x72.pdf [2] R. Lutwak , D. Emmons, W. Riley, and R. M. Garvey, 2003, “The Chip-Scale Atomic Clock – Coherent Population Trapping vs...2002, Reston, Virginia, USA (U.S. Naval Observatory, Washington, D.C.), pp. 539-550. [3] R. Lutwak , D. Emmons, T. English, and W. Riley, 2004

Atomic layer deposition frequency-multiplied Fresnel zone plates for hard x-rays focusing

DOE PAGES

Moldovan, Nicolaie; Divan, Ralu; Zeng, Hongjun; ...

2017-12-01

The design and fabrication of Fresnel zone plates for hard x-ray focusing up to 25 keV photon energies with better than 50 nm imaging half-pitch resolution is reported as performed by forming an ultrananocrystalline diamond (UNCD) scaffold, subsequently coating it with atomic layer deposition (ALD) with an absorber/phase shifting material, followed by back side etching of Si to form a diamond membrane device. The scaffold is formed by chemical vapor-deposited UNCD, electron beam lithography, and deep-reactive ion etching of diamond to desired specifications. The benefits of using diamond are as follows: improved mechanical robustness to prevent collapse of high-aspect-ratio ringmore » structures, a known high-aspect-ratio etch method, excellent radiation hardness, extremely low x-ray absorption, and significantly improved thermal/dimensional stability as compared to alternative materials. Central to the technology is the high-resolution patterning of diamond membranes at wafer scale, which was pushed to 60 nm lines and spaces etched 2.2-mu m-deep, to an aspect ratio of 36:1. The absorber growth was achieved by ALD of Ir, Pt, or W, while wafer-level processing allowed to obtain up to 121 device chips per 4 in. wafer with yields better than 60%. X-ray tests with such zone plates allowed resolving 50 nm lines and spaces, at the limit of the available resolution test structures.« less

Mechanical properties of silicon in subsurface damage layer from nano-grinding studied by atomistic simulation

NASA Astrophysics Data System (ADS)

Zhang, Zhiwei; Chen, Pei; Qin, Fei; An, Tong; Yu, Huiping

2018-05-01

Ultra-thin silicon wafer is highly demanded by semi-conductor industry. During wafer thinning process, the grinding technology will inevitably induce damage to the surface and subsurface of silicon wafer. To understand the mechanism of subsurface damage (SSD) layer formation and mechanical properties of SSD layer, atomistic simulation is the effective tool to perform the study, since the SSD layer is in the scale of nanometer and hardly to be separated from underneath undamaged silicon. This paper is devoted to understand the formation of SSD layer, and the difference between mechanical properties of damaged silicon in SSD layer and ideal silicon. With the atomistic model, the nano-grinding process could be performed between a silicon workpiece and diamond tool under different grinding speed. To reach a thinnest SSD layer, nano-grinding speed will be optimized in the range of 50-400 m/s. Mechanical properties of six damaged silicon workpieces with different depths of cut will be studied. The SSD layer from each workpiece will be isolated, and a quasi-static tensile test is simulated to perform on the isolated SSD layer. The obtained stress-strain curve is an illustration of overall mechanical properties of SSD layer. By comparing the stress-strain curves of damaged silicon and ideal silicon, a degradation of Young's modulus, ultimate tensile strength (UTS), and strain at fracture is observed.

Unveiling the Formation Pathway of Single Crystalline Porous Silicon Nanowires

PubMed Central

Zhong, Xing; Qu, Yongquan; Lin, Yung-Chen; Liao, Lei; Duan, Xiangfeng

2011-01-01

Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H2O2) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H2O2) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and re-nucleate on the sidewalls of nanowires to initiate new etching pathways to produce porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 m2·g−1 to 30 m2·g−1, and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy. PMID:21244020

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moldovan, Nicolaie; Divan, Ralu; Zeng, Hongjun

The design and fabrication of Fresnel zone plates for hard x-ray focusing up to 25 keV photon energies with better than 50 nm imaging half-pitch resolution is reported as performed by forming an ultrananocrystalline diamond (UNCD) scaffold, subsequently coating it with atomic layer deposition (ALD) with an absorber/phase shifting material, followed by back side etching of Si to form a diamond membrane device. The scaffold is formed by chemical vapor-deposited UNCD, electron beam lithography, and deep-reactive ion etching of diamond to desired specifications. The benefits of using diamond are as follows: improved mechanical robustness to prevent collapse of high-aspect-ratio ringmore » structures, a known high-aspect-ratio etch method, excellent radiation hardness, extremely low x-ray absorption, and significantly improved thermal/dimensional stability as compared to alternative materials. Central to the technology is the high-resolution patterning of diamond membranes at wafer scale, which was pushed to 60 nm lines and spaces etched 2.2-mu m-deep, to an aspect ratio of 36:1. The absorber growth was achieved by ALD of Ir, Pt, or W, while wafer-level processing allowed to obtain up to 121 device chips per 4 in. wafer with yields better than 60%. X-ray tests with such zone plates allowed resolving 50 nm lines and spaces, at the limit of the available resolution test structures.« less

Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly

NASA Technical Reports Server (NTRS)

Jhabvala, Murzy; Jhabvala, Christine A.; Ewin, Audrey J.; Hess, Larry A.; Hartmann, Thomas M.; La, Anh T.

2012-01-01

A paper describes the Thermal Infrared Sensor (TIRS), a QWIP-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 microns. The focal plane will contain three 640x512 QWIP arrays mounted on a silicon substrate. The silicon substrate is a custom-fabricated carrier board with a single layer of aluminum interconnects. The general fabrication process starts with a 4-in. (approx.10-cm) diameter silicon wafer. The wafer is oxidized, a single substrate contact is etched, and aluminum is deposited, patterned, and alloyed. This technology development is aimed at incorporating three large-format infrared detecting arrays based on GaAs QWIP technology onto a common focal plane with precision alignment of all three arrays. This focal plane must survive the rigors of flight qualification and operate at a temperature of 43 K (-230 C) for five years while orbiting the Earth. The challenges presented include ensuring thermal compatibility among all the components, designing and building a compact, somewhat modular system and ensuring alignment to very tight levels. The multi-array focal plane integrated onto a single silicon substrate is a new application of both QWIP array development and silicon wafer scale integration. The Invar-based assembly has been tested to ensure thermal reliability.

Detection and characterization of microdefects and microprecipitates in Si wafers by Brewster angle illumination using an optical fiber system

NASA Astrophysics Data System (ADS)

Taijing, Lu; Toyoda, Koichi; Nango, Nobuhito; Ogawa, Tomoya

1991-10-01

Microdefects and microprecipitates were non-destructively detected in bulk and near surface of a Si wafer by Brewster angle illumination using an optical fiber system, because the p-component of the illumination enters completely into the wafer and then makes scattering from the defects while the other s-component reflects on the wafer surface so as to deviate from an objective lens for the detection of the scattering. Some results of observations and discussions will be done here about the scatterers in epitaxially grown Si layers, denuded zones of Si wafers, annealed amorphous SiC films, SIMOX specimens and slip bands in Si crystals.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1991-01-01

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

1992-01-01

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Residual Stress and Fracture of PECVD Thick Oxide Films for Power MEMS Structures and Devices

DTIC Science & Technology

2007-06-01

Residual stress leads to large overall wafer bow, which makes further processing difficult. For example some microfabrication machines , such as chemical...curvature will be measured across the wafer surface in 12 scans, rotating 24 the wafer by 300 between each scan. In situ wafer curvature will be...SiOx. 4.1. Introduction As introduced earlier (Sec.1), in Power MEMS (micro energy- harvesting devices such as micro heat engines and related components

Study of temperature distributions in wafer exposure process

NASA Astrophysics Data System (ADS)

Lin, Zone-Ching; Wu, Wen-Jang

During the exposure process of photolithography, wafer absorbs the exposure energy, which results in rising temperature and the phenomenon of thermal expansion. This phenomenon was often neglected due to its limited effect in the previous generation of process. However, in the new generation of process, it may very likely become a factor to be considered. In this paper, the finite element model for analyzing the transient behavior of the distribution of wafer temperature during exposure was established under the assumption that the wafer was clamped by a vacuum chuck without warpage. The model is capable of simulating the distribution of the wafer temperature under different exposure conditions. The flowchart of analysis begins with the simulation of transient behavior in a single exposure region to the variation of exposure energy, interval of exposure locations and interval of exposure time under continuous exposure to investigate the distribution of wafer temperature. The simulation results indicate that widening the interval of exposure locations has a greater impact in improving the distribution of wafer temperature than extending the interval of exposure time between neighboring image fields. Besides, as long as the distance between the field center locations of two neighboring exposure regions exceeds the straight distance equals to three image fields wide, the interacting thermal effect during wafer exposure can be ignored. The analysis flow proposed in this paper can serve as a supporting reference tool for engineers in planning exposure paths.

Precision of a CAD/CAM-engineered surgical template based on a facebow for orthognathic surgery: an experiment with a rapid prototyping maxillary model.

PubMed

Lee, Jae-Won; Lim, Se-Ho; Kim, Moon-Key; Kang, Sang-Hoon

2015-12-01

We examined the precision of a computer-aided design/computer-aided manufacturing-engineered, manufactured, facebow-based surgical guide template (facebow wafer) by comparing it with a bite splint-type orthognathic computer-aided design/computer-aided manufacturing-engineered surgical guide template (bite wafer). We used 24 rapid prototyping (RP) models of the craniofacial skeleton with maxillary deformities. Twelve RP models each were used for the facebow wafer group and the bite wafer group (experimental group). Experimental maxillary orthognathic surgery was performed on the RP models of both groups. Errors were evaluated through comparisons with surgical simulations. We measured the minimum distances from 3 planes of reference to determine the vertical, lateral, and anteroposterior errors at specific measurement points. The measured errors were compared between experimental groups using a t test. There were significant intergroup differences in the lateral error when we compared the absolute values of the 3-D linear distance, as well as vertical, lateral, and anteroposterior errors between experimental groups. The bite wafer method exhibited little lateral error overall and little error in the anterior tooth region. The facebow wafer method exhibited very little vertical error in the posterior molar region. The clinical precision of the facebow wafer method did not significantly exceed that of the bite wafer method. Copyright © 2015 Elsevier Inc. All rights reserved.

A Comparative Study of Inspection Techniques for Array Packages

NASA Technical Reports Server (NTRS)

Mohammed, Jelila; Green, Christopher

2008-01-01

This viewgraph presentation reviews the inspection techniques for Column Grid Array (CGA) packages. The CGA is a method of chip scale packaging using high temperature solder columns to attach part to board. It is becoming more popular over other techniques (i.e. quad flat pack (QFP) or ball grid array (BGA)). However there are environmental stresses and workmanship challenges that require good inspection techniques for these packages.

A novel patterning control strategy based on real-time fingerprint recognition and adaptive wafer level scanner optimization

NASA Astrophysics Data System (ADS)

Cekli, Hakki Ergun; Nije, Jelle; Ypma, Alexander; Bastani, Vahid; Sonntag, Dag; Niesing, Henk; Zhang, Linmiao; Ullah, Zakir; Subramony, Venky; Somasundaram, Ravin; Susanto, William; Matsunobu, Masazumi; Johnson, Jeff; Tabery, Cyrus; Lin, Chenxi; Zou, Yi

2018-03-01

In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a `fingerprint', on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching <3nm, requiring the allowable budget for process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel `computational process control strategy' which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each wafer and on every layer during the lithography steps. This metrology data will be used to obtain the process fingerprints. Also, the per exposure and per wafer correction potential of the scanners will be utilized for improved patterning control. Additionally, the fingerprint library will provide early detection of excursions for inline root cause analysis and process optimization guidance.

In-situ wafer bowing measurements of GaN grown on Si (111) substrate by reflectivity mapping in metal organic chemical vapor deposition system

NASA Astrophysics Data System (ADS)

Yang, Yi-Bin; Liu, Ming-Gang; Chen, Wei-Jie; Han, Xiao-Biao; Chen, Jie; Lin, Xiu-Qi; Lin, Jia-Li; Luo, Hui; Liao, Qiang; Zang, Wen-Jie; Chen, Yin-Song; Qiu, Yun-Ling; Wu, Zhi-Sheng; Liu, Yang; Zhang, Bai-Jun

2015-09-01

In this work, the wafer bowing during growth can be in-situ measured by a reflectivity mapping method in the 3×2″ Thomas Swan close coupled showerhead metal organic chemical vapor deposition (MOCVD) system. The reflectivity mapping method is usually used to measure the film thickness and growth rate. The wafer bowing caused by stresses (tensile and compressive) during the epitaxial growth leads to a temperature variation at different positions on the wafer, and the lower growth temperature leads to a faster growth rate and vice versa. Therefore, the wafer bowing can be measured by analyzing the discrepancy of growth rates at different positions on the wafer. Furthermore, the wafer bowings were confirmed by the ex-situ wafer bowing measurement. High-resistivity and low-resistivity Si substrates were used for epitaxial growth. In comparison with low-resistivity Si substrate, GaN grown on high-resistivity substrate shows a larger wafer bowing caused by the highly compressive stress introduced by compositionally graded AlGaN buffer layer. This transition of wafer bowing can be clearly in-situ measured by using the reflectivity mapping method. Project supported by the National Natural Science Foundation of China (Grant Nos. 61274039 and 51177175), the National Basic Research Program of China (Grant No. 2011CB301903), the Ph.D. Programs Foundation of Ministry of Education of China (Grant No. 20110171110021), the International Science and Technology Collaboration Program of China (Grant No. 2012DFG52260), the International Science and Technology Collaboration Program of Guangdong Province, China (Grant No. 2013B051000041), the Science and Technology Plan of Guangdong Province, China (Grant No. 2013B010401013), the National High Technology Research and Development Program of China (Grant No. 2014AA032606), and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics, China (Grant No. IOSKL2014KF17).

Modeling Impact-induced Failure of Polysilicon MEMS: A Multi-scale Approach.

PubMed

Mariani, Stefano; Ghisi, Aldo; Corigliano, Alberto; Zerbini, Sarah

2009-01-01

Failure of packaged polysilicon micro-electro-mechanical systems (MEMS) subjected to impacts involves phenomena occurring at several length-scales. In this paper we present a multi-scale finite element approach to properly allow for: (i) the propagation of stress waves inside the package; (ii) the dynamics of the whole MEMS; (iii) the spreading of micro-cracking in the failing part(s) of the sensor. Through Monte Carlo simulations, some effects of polysilicon micro-structure on the failure mode are elucidated.

Bar-Coated Ultrathin Semiconductors from Polymer Blend for One-Step Organic Field-Effect Transistors.

PubMed

Ge, Feng; Liu, Zhen; Lee, Seon Baek; Wang, Xiaohong; Zhang, Guobing; Lu, Hongbo; Cho, Kilwon; Qiu, Longzhen

2018-06-27

One-step deposition of bi-functional semiconductor-dielectric layers for organic field-effect transistors (OFETs) is an effective way to simplify the device fabrication. However, the proposed method has rarely been reported in large-area flexible organic electronics. Herein, we demonstrate wafer-scale OFETs by bar coating the semiconducting and insulating polymer blend solution in one-step. The semiconducting polymer poly(3-hexylthiophene) (P3HT) segregates on top of the blend film, whereas dielectric polymethyl methacrylate (PMMA) acts as the bottom layer, which is achieved by a vertical phase separation structure. The morphology of blend film can be controlled by varying the concentration of P3HT and PMMA solutions. The wafer-scale one-step OFETs, with a continuous ultrathin P3HT film of 2.7 nm, exhibit high electrical reproducibility and uniformity. The one-step OFETs extend to substrate-free arrays that can be attached everywhere on varying substrates. In addition, because of the well-ordered molecular arrangement, the moderate charge transport pathway is formed, which resulted in stable OFETs under various organic solvent vapors and lights of different wavelengths. The results demonstrate that the one-step OFETs have promising potential in the field of large-area organic wearable electronics.

Ultra-dense magnetoresistive mass memory

NASA Technical Reports Server (NTRS)

Daughton, J. M.; Sinclair, R.; Dupuis, T.; Brown, J.

1992-01-01

This report details the progress and accomplishments of Nonvolatile Electronics (NVE), Inc., on the design of the wafer scale MRAM mass memory system during the fifth quarter of the project. NVE has made significant progress this quarter on the one megabit design in several different areas. A test chip, which will verify a working GMR bit with the dimensions required by the 1 Meg chip, has been designed, laid out, and is currently being processed in the NVE labs. This test chip will allow electrical specifications, tolerances, and processing issues to be finalized before construction of the actual chip, thus providing a greater assurance of success of the final 1 Meg design. A model has been developed to accurately simulate the parasitic effects of unselected sense lines. This model gives NVE the ability to perform accurate simulations of the array electronic and test different design concepts. Much of the circuit design for the 1 Meg chip has been completed and simulated and these designs are included. Progress has been made in the wafer scale design area to verify the reliable operation of the 16 K macrocell. This is currently being accomplished with the design and construction of two stand alone test systems which will perform life tests and gather data on reliabiliy and wearout mechanisms for analysis.

Correlation of 150-mm silicon wafer site flatness with stepper performance for deep submicron applications

NASA Astrophysics Data System (ADS)

Huff, Howard R.; Vigil, Joseph C.; Kuyel, Birol; Chan, David Y.; Nguyen, Long P.

1992-06-01

An experimental study was conducted to correlate wafer site flatness SFQD with stepper performance for half-micron lines and spaces. CD measurements were taken on wafers patterned on both GCA pre-production XLS i-line and SVGL Micrascan-90 DUV steppers as well as focus measurements on the Micrascan-90. Wafer site flatness SFQD less than 0.3 micrometers was observed to be a sufficiently small variable in CD non-uniformities for these initial half-micron stepper applications.

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

NASA Technical Reports Server (NTRS)

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

The opportunity and challenge of spin coat based nanoimprint lithography

NASA Astrophysics Data System (ADS)

Jung, Wooyung; Cho, Jungbin; Choi, Eunhyuk; Lim, Yonghyun; Bok, Cheolkyu; Tsuji, Masatoshi; Kobayashi, Kei; Kono, Takuya; Nakasugi, Tetsuro

2017-03-01

Since multi patterning with spacer was introduced in NAND flash memory1, multi patterning with spacer has been a promising solution to overcome the resolution limit. However, the increase in process cost of multi patterning with spacer must be a serious burden to device manufacturers as half pitch of patterns gets smaller.2, 3 Even though Nano Imprint Lithography (NIL) has been considered as one of strong candidates to avoid cost issue of multi patterning with spacer, there are still negative viewpoints; template damage induced from particles between template and wafer, overlay degradation induced from shear force between template and wafer, and throughput loss induced from dispensing and spreading resist droplet. Jet and Flash Imprint Lithography (J-FIL4, 5, 6) has contributed to throughput improvement, but still has these above problems. J-FIL consists of 5 steps; dispense of resist droplets on wafer, imprinting template on wafer, filling the gap between template and wafer with resist, UV curing, and separation of template from wafer. If dispensing resist droplets by inkjet is replaced with coating resist at spin coater, additional progress in NIL can be achieved. Template damage from particle can be suppressed by thick resist which is spin-coated at spin coater and covers most of particles on wafer, shear force between template and wafer can be minimized with thick resist, and finally additional throughput enhancement can be achieved by skipping dispense of resist droplets on wafer. On the other hand, spin-coat-based NIL has side effect such as pattern collapse which comes from high separation energy of resist. It is expected that pattern collapse can be improved by the development of resist with low separation energy.

Interface and facet control during Czochralski growth of (111) InSb crystals for cost reduction and yield improvement of IR focal plane array substrates

NASA Astrophysics Data System (ADS)

Gray, Nathan W.; Perez-Rubio, Victor; Bolke, Joseph G.; Alexander, W. B.

2014-10-01

Focal plane arrays (FPAs) made on InSb wafers are the key cost-driving component in IR imaging systems. The electronic and crystallographic properties of the wafer directly determine the imaging device performance. The "facet effect" describes the non-uniform electronic properties of crystals resulting from anisotropic dopant segregation during bulk growth. When the segregation coefficient of dopant impurities changes notably across the melt/solid interface of a growing crystal the result is non-uniform electronic properties across wafers made from these crystals. The effect is more pronounced in InSb crystals grown on the (111) axis compared with other orientations and crystal systems. FPA devices made on these wafers suffer costly yield hits due to inconsistent device response and performance. Historically, InSb crystal growers have grown approximately 9-19 degree off-axis from the (111) to avoid the facet effect and produced wafers with improved uniformity of electronic properties. It has been shown by researchers in the 1960s that control of the facet effect can produce uniform small diameter crystals. In this paper, we share results employing a process that controls the facet effect when growing large diameter crystals from which 4, 5, and 6" wafers can be manufactured. The process change resulted in an increase in wafers yielded per crystal by several times, all with high crystal quality and uniform electronic properties. Since the crystals are grown on the (111) axis, manufacturing (111) oriented wafers is straightforward with standard semiconductor equipment and processes common to the high-volume silicon wafer industry. These benefits result in significant manufacturing cost savings and increased value to our customers.

Bulk lifetime characterization of corona charged silicon wafers with high resistivity by means of microwave detected photoconductivity

NASA Astrophysics Data System (ADS)

Engst, C. R.; Rommel, M.; Bscheid, C.; Eisele, I.; Kutter, C.

2017-12-01

Minority carrier lifetime (lifetime) measurements are performed on corona-charged silicon wafers by means of Microwave Detected Photoconductivity (MDP). The corona charge is deposited on the front and back sides of oxidized wafers in order to adjust accumulation conditions. Once accumulation is established, interface recombination is suppressed and bulk lifetimes are obtained. Neither contacts nor non-CMOS compatible preparation techniques are required in order to achieve accumulation conditions, which makes the method ideally suited for inline characterization. The novel approach, termed ChargedMDP (CMDP), is used to investigate neutron transmutation doped (NTD) float zone silicon with resistivities ranging from 6.0 to 8.2 kΩ cm. The bulk properties of 150 mm NTD wafers are analyzed in detail by performing measurements of the carrier lifetime and the steady-state photoconductivity at various injection levels. The results are compared with MDP measurements of uncharged wafers as well as to the established charged microwave detected Photoconductance Decay (charge-PCD) method. Besides analyzing whole wafers, CMDP measurements are performed on oxide test-structures on a patterned wafer. Finally, the oxide properties are characterized by means of charge-PCD as well as capacitance-voltage measurements. With CMDP, average bulk lifetimes up to 33.1 ms are measured, whereby significant variations are observed among wafers, which are produced out of the same ingot but oxidized in different furnaces. The observed lifetime variations are assumed to be caused by contaminations, which are introduced during the oxidation process. The results obtained by CMDP were neither accessible by means of conventional MDP measurements of uncharged wafers nor with the established charge-PCD method.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2008-10-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Automated reticle inspection data analysis for wafer fabs

NASA Astrophysics Data System (ADS)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-03-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Semiconductor P-I-N detector

DOEpatents

Sudharsanan, Rengarajan; Karam, Nasser H.

2001-01-01

A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

Reliable bonding using indium-based solders

NASA Astrophysics Data System (ADS)

Cheong, Jongpil; Goyal, Abhijat; Tadigadapa, Srinivas; Rahn, Christopher

2004-01-01

Low temperature bonding techniques with high bond strengths and reliability are required for the fabrication and packaging of MEMS devices. Indium and indium-tin based bonding processes are explored for the fabrication of a flextensional MEMS actuator, which requires the integration of lead zirconate titanate (PZT) substrate with a silicon micromachined structure at low temperatures. The developed technique can be used either for wafer or chip level bonding. The lithographic steps used for the patterning and delineation of the seed layer limit the resolution of this technique. Using this technique, reliable bonds were achieved at a temperature of 200°C. The bonds yielded an average tensile strength of 5.41 MPa and 7.38 MPa for samples using indium and indium-tin alloy solders as the intermediate bonding layers respectively. The bonds (with line width of 100 microns) showed hermetic sealing capability of better than 10-11 mbar-l/s when tested using a commercial helium leak tester.

Reliable bonding using indium-based solders

NASA Astrophysics Data System (ADS)

Cheong, Jongpil; Goyal, Abhijat; Tadigadapa, Srinivas; Rahn, Christopher

2003-12-01

Low temperature bonding techniques with high bond strengths and reliability are required for the fabrication and packaging of MEMS devices. Indium and indium-tin based bonding processes are explored for the fabrication of a flextensional MEMS actuator, which requires the integration of lead zirconate titanate (PZT) substrate with a silicon micromachined structure at low temperatures. The developed technique can be used either for wafer or chip level bonding. The lithographic steps used for the patterning and delineation of the seed layer limit the resolution of this technique. Using this technique, reliable bonds were achieved at a temperature of 200°C. The bonds yielded an average tensile strength of 5.41 MPa and 7.38 MPa for samples using indium and indium-tin alloy solders as the intermediate bonding layers respectively. The bonds (with line width of 100 microns) showed hermetic sealing capability of better than 10-11 mbar-l/s when tested using a commercial helium leak tester.

Fabrication and electrical characterization of partially metallized vias fabricated by inkjet

NASA Astrophysics Data System (ADS)

Khorramdel, B.; Mäntysalo, M.

2016-04-01

Through silicon vias (TSVs), acting as vertical interconnections, play an important role in micro-electro-mechanical systems (MEMS) 3D wafer level packaging. Today, taking advantage of nanoparticle inks, inkjet technologies as local filling methods could be used to plate the inside the vias with a conductive material, rather than using a current method, such as chemical vapor deposition or electrolytic growth. This could decrease the processing time, cost and waste material produced. In this work, we have fabricated and demonstrated electrical characterization of TSVs with a top diameter of 85 μm, and partially metallized on their inside walls using silver nanoparticle ink and drop-on-demand inkjet printing. Electrical measurement showed that the resistance of a single via with a void free coverage from top to bottom could be less than 4 Ω, which is still acceptable for MEMS applications.

Ultra-compact 32 × 32 strictly-non-blocking Si-wire optical switch with fan-out LGA interposer.

PubMed

Tanizawa, Ken; Suzuki, Keijiro; Toyama, Munehiro; Ohtsuka, Minoru; Yokoyama, Nobuyuki; Matsumaro, Kazuyuki; Seki, Miyoshi; Koshino, Keiji; Sugaya, Toshio; Suda, Satoshi; Cong, Guangwei; Kimura, Toshio; Ikeda, Kazuhiro; Namiki, Shu; Kawashima, Hitoshi

2015-06-29

We demonstrate a 32 × 32 path-independent-insertion-loss optical path switch that integrates 1024 thermooptic Mach-Zehnder switches and 961 intersections on a small, 11 × 25 mm2 die. The switch is fabricated on a 300-mm-diameter silicon-on-insulator wafer by a complementary metal-oxide semiconductor-compatible process with advanced ArF immersion lithography. For reliable electrical packaging, the switch chip is flip-chip bonded to a ceramic interposer that arranges the electrodes in a 0.5-mm pitch land grid array. The on-chip loss is measured to be 15.8 ± 1.0 dB, and successful switching is demonstrated for digital-coherent 43-Gb/s QPSK signals. The total crosstalk of the switch is estimated to be less than -20 dB at the center wavelength of 1545 nm. The bandwidth narrowing caused by dimensional errors that arise during fabrication is discussed.