ECLSS Sustaining Compatibility Testing on Urine Processor Assembly Nonmetallic Materials for Reformulation of Pretreated Urine Solution

NASA Technical Reports Server (NTRS)

Wingard, C. D.

2015-01-01

On International Space Station (ISS), the Urine Processor Assembly (UPA) converts human urine and flush water into potable water. The urine is acid-pretreated primarily to control microbial growth. In recent years, the sulfuric acid (H2SO4) pretreatment was believed to be largely responsible for producing salt crystals capable of plugging filters in UPA components and significantly reducing the percentage of water recovery from urine. In 2012, ISS management decided to change the acid pretreatment for urine from sulfuric to phosphoric with the goal of eliminating or minimizing formation of salt crystals. In 2013-2014, as part of the qualification of the phosphoric acid (H3PO4) formulation, samples of 12 nonmetallic materials used in UPA components were immersed for up to one year in pretreated urine and brine solutions made with the new H3PO4 formulation. Dynamic mechanical analysis (DMA) was used to measure modulus (stiffness) of the immersed samples compared to virgin control samples. Such compatibility data obtained by DMA for the H3PO4-based solutions were compared to DMA data obtained for the H2SO4-based solutions in 2002-2003.

Installing the ARFTA (Advanced Recycle Filter Tank Assembly)

NASA Image and Video Library

2011-10-10

ISS029-E-021648 (10 Oct. 2011) --- NASA astronaut Mike Fossum, Expedition 29 commander, installs the Advanced Recycle Filter Tank Assembly (ARFTA) at the Urine Processor Assembly / Water Recovery System (UPA WRS) in the Destiny laboratory of the International Space Station.

Selection of a Brine Processor Technology for NASA Manned Missions

NASA Technical Reports Server (NTRS)

Carter, Donald L.; Gleich, Andrew F.

2016-01-01

The current ISS Water Recovery System (WRS) reclaims water from crew urine, humidity condensate, and Sabatier product water. Urine is initially processed by the Urine Processor Assembly (UPA) which recovers 75% of the urine as distillate. The remainder of the water is present in the waste brine which is currently disposed of as trash on ISS. For future missions this additional water must be reclaimed due to the significant resupply penalty for missions beyond Low Earth Orbit (LEO). NASA has pursued various technology development programs for a brine processor in the past several years. This effort has culminated in a technology down-select to identify the optimum technology for future manned missions. The technology selection is based on various criteria, including mass, power, reliability, maintainability, and safety. Beginning in 2016 the selected technology will be transitioned to a flight hardware program for demonstration on ISS. This paper summarizes the technology selection process, the competing technologies, and the rationale for the technology selected for future manned missions.

Status of the Regenerative ECLSS Water Recovery System

NASA Technical Reports Server (NTRS)

Carter, Donald Layne

2009-01-01

NASA has completed the delivery of the regenerative Water Recovery System (WRS) for the International Space Station (ISS). The major assemblies included in this system are the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the final effort to deliver the hardware to the Kennedy Space Center for launch on STS-126, the on-orbit status as of April 2009, and describes some of the technical challenges encountered and lessons learned over the past year.

Compatibility Testing of Polymeric Materials for the Urine Processor Assembly (UPA) of International Space Station (ISS)

NASA Technical Reports Server (NTRS)

Wingard, Charles D.

2003-01-01

In the International Space Station (ISS), astronauts will convert urine into potable water with the Urine Processor Assembly (UPA) by a distillation process. The urine is pre-treated, containing flush water and stabilizers. About 2.5% solids in the urine are concentrated up to 16% brine through distillation. Dynamic mechanical analysis (DMA) in the stress relaxation mode was primarily used to test 15 polymeric UPA materials for compatibility with the pre-treated and brine solutions. There were concerns that chromium trioxide (CrO3), a stabilizer not in the original pre-treat formulation for similar compatibility testing in 2000, could have an adverse effect on these polymers. DMA testing is partially complete for polymeric material samples immersed in the two solutions at room temperature for as long as 200 days. By comparing each material (conditioned and virgin), the stress relaxation modulus (E) was determined for short-term use and predicted for as long as a 10-year use in space. Such a delta E showed a decrease of as much as 79% for a Nylon material, but an increase as much as 454% for a polysulfone material, with increasing immersion time.

Compatibility Testing of Non-Metallic Materials for the Urine Processor Assembly (UPA) of International Space Station (ISS)

NASA Technical Reports Server (NTRS)

Wingard, Charles Doug; Munafo, Paul M. (Technical Monitor)

2001-01-01

In the International Space Station (ISS), astronauts will convert urine into potable water with the Urine Processor Assembly (UPA). The urine is distilled, with the concentrated form containing about 15% brine solids, and the dilute form as a blend of pre-treated urine/wastewater. Eighteen candidate non-metallic materials for use with the UPA were tested in 2000 for compatibility with the concentrated and dilute urine solutions for continuous times of at least 30 days, and at conditions of 0.5 psia pressure and 100 F, to simulate the working UPA environment. A primary screening test for each material (virgin and conditioned) was dynamic mechanical analysis (DMA) in the stress relaxation mode, with the test data used to predict material performance for a 10-year use in space. Data showed that most of the candidate materials passed the compatibility testing, although a few significant changes in stress relaxation modulus were observed.

Updated Performance Evaluation of the ISS Water Processor Multifiltration Beds

NASA Technical Reports Server (NTRS)

Bowman, Elizabeth M.; Carter, Layne; Carpenter, Joyce; Orozco, Nicole; Weir, Natalee; Wilson, Mark

2014-01-01

The ISS Water Processor Assembly (WPA) produces potable water from a waste stream containing humidity condensate and urine distillate. The primary treatment process is achieved in the Multifiltration Beds, which include adsorbent media and ion exchange resin for the removal of dissolved organic and inorganic contaminants. Two Multifiltration Beds (MF Beds) were replaced on ISS in July 2010 after initial indication of inorganic breakthrough of the first bed and an increasing Total Organic Carbon (TOC) trend in the product water. The first bed was sampled and analyzed Sept 2011 through March 2012. The second MF Bed was sampled and analyzed June 2012 through August 2012. The water resident in the both beds was analyzed for various parameters to evaluate adsorbent loading, performance of the ion exchange resin, microbial activity, and generation of leachates from the ion exchange resin. Portions of the adsorbent media and ion exchange resin were sampled and subsequently desorbed to identify the primary contaminants removed at various points in the bed in addition to microbial analysis. Analysis of the second bed will be compared to results from the first bed to provide a comprehensive overview of how the Multifiltration Beds function on orbit. New data from the second bed supplements the analysis of the first bed (previously reported) and gives a more complete picture of breakthrough compounds, resin breakdown products, microbial activity, and difficult to remove compounds. The results of these investigations and implications to the operation of the WPA on ISS are documented in this paper.

Status of ISS Water Management and Recovery

NASA Technical Reports Server (NTRS)

Carter, Layne; Wilson, Laura Labuda; Orozco, Nicole

2012-01-01

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment, and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of May 2011, and describes the technical challenges encountered and lessons learned over the past year.

Status of ISS Water Management and Recovery

NASA Technical Reports Server (NTRS)

Carter, Layne; Pruitt, Jennifer; Brown, Christopher A.; Bazley, Jesse; Gazda, Daniel; Schaezler, Ryan; Bankers, Lyndsey

2016-01-01

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of May 2016 and describes the technical challenges encountered and lessons learned over the past year.

Status of ISS Water Management and Recovery

NASA Technical Reports Server (NTRS)

Carter, Layne; Brown, Christopher; Orozco, Nicole

2014-01-01

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment, and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of June 2013, and describes the technical challenges encountered and lessons learned over the past year.

Status of ISS Water Management and Recovery

NASA Technical Reports Server (NTRS)

Carter, Layne; Tobias, Barry; Orozco, Nicole

2012-01-01

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment, and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of June 2012, and describes the technical challenges encountered and lessons learned over the past year.

Status of ISS Water Management and Recovery

NASA Technical Reports Server (NTRS)

Carter, Layne; Takada, Kevin; Gazda, Daniel; Brown, Christopher; Bazley, Jesse; Schaezler, Ryan; Bankers, Lyndsey

2017-01-01

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of June 2017 and describes the technical challenges encountered and lessons learned over the past year.

Status of ISS Water Management and Recovery

NASA Technical Reports Server (NTRS)

Carter, Layne; Pruitt, Jennifer; Brown, Christopher A.; Schaezler, Ryan; Bankers, Lyndsey

2015-01-01

Water management on ISS is responsible for the provision of water to the crew for drinking water, food preparation, and hygiene, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. This paper summarizes water management activities on the ISS US Segment, and provides a status of the performance and issues related to the operation of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA). This paper summarizes the on-orbit status as of May 2015 and describes the technical challenges encountered and lessons learned over the past two years.

Ion Exchange Technology Development in Support of the Urine Processor Assembly

NASA Technical Reports Server (NTRS)

Mitchell, Julie; Broyan, James; Pickering, Karen

2013-01-01

The urine processor assembly (UPA) on the International Space Station (ISS) recovers water from urine via a vacuum distillation process. The distillation occurs in a rotating distillation assembly (DA) where the urine is heated and subjected to sub-ambient pressure. As water is removed, the original organics, salts, and minerals in the urine become more concentrated and result in urine brine. Eventually, water removal will concentrate the urine brine to super saturation of individual constituents, and precipitation occurs. Under typical UPA DA operating conditions, calcium sulfate or gypsum is the first chemical to precipitate in substantial quantity. During preflight testing with ground urine, the UPA achieved 85% water recovery without precipitation. However, on ISS, it is possible that crewmember urine can be significantly more concentrated relative to urine from ground donors. As a result, gypsum precipitated in the DA when operating at water recovery rates at or near 85%, causing the failure and subsequent re14 NASA Tech Briefs, September 2013 placement of the DA. Later investigations have demonstrated that an excess of calcium and sulfate will cause precipitation at water recovery rates greater than 70%. The source of the excess calcium is likely physiological in nature, via crewmembers' bone loss, while the excess sulfate is primarily due to the sulfuric acid component of the urine pretreatment. To prevent gypsum precipitation in the UPA, the Precipitation Prevention Project (PPP) team has focused on removing the calcium ion from pretreated urine, using ion exchange resins as calcium removal agents. The selectivity and effectiveness of ion exchange resins are determined by such factors as the mobility of the liquid phase through the polymer matrix, the density of functional groups, type of functional groups bound to the matrix, and the chemical characteristics of the liquid phase (pH, oxidation potential, and ionic strength). Previous experience with ion

Upgrades to the ISS Water Recovery System

NASA Technical Reports Server (NTRS)

Kayatin, Matthew J.; Carter, Donald L.; Schunk, Richard G.; Pruitt, Jennifer M.

2016-01-01

The International Space Station Water Recovery System (WRS) is comprised of the Water Processor Assembly (WPA) and the Urine Processor Assembly (UPA). The WRS produces potable water from a combination of crew urine (first processed through the UPA), crew latent, and Sabatier product water. Though the WRS has performed well since operations began in November 2008, several modifications have been identified to improve the overall system performance. These modifications can reduce resupply and improve overall system reliability, which is beneficial for the ongoing ISS mission as well as for future NASA manned missions. The following paper details efforts to reduce the resupply mass of the WPA Multifiltration Bed, develop improved catalyst for the WPA Catalytic Reactor, evaluate optimum operation of UPA through parametric testing, and improve reliability of the UPA fluids pump and Distillation Assembly.

Contaminant Permeation in the Ionomer-Membrane Water Processor (IWP) System

NASA Technical Reports Server (NTRS)

Kelsey, Laura K.; Finger, Barry W.; Pasadilla, Patrick; Perry, Jay

2016-01-01

The Ionomer-membrane Water Processor (IWP) is a patented membrane-distillation based urine brine water recovery system. The unique properties of the IWP membrane pair limit contaminant permeation from the brine to the recovered water and purge gas. A paper study was conducted to predict volatile trace contaminant permeation in the IWP system. Testing of a large-scale IWP Engineering Development Unit (EDU) with urine brine pretreated with the International Space Station (ISS) pretreatment formulation was then conducted to collect air and water samples for quality analysis. Distillate water quality and purge air GC-MS results are presented and compared to predictions, along with implications for the IWP brine processing system.

Ion Exchange Technology Development in Support of the Urine Processor Assembly Precipitation Prevention Project for the International Space Station

NASA Technical Reports Server (NTRS)

Mitchell, Julie L.; Broyan, James L.; Pickering, Karen D.; Adam, Niklas; Casteel, Michael; Callahan, Michael; Carrier, Chris

2012-01-01

In support of the Urine Processor Assembly Precipitation Prevention Project (UPA PPP), multiple technologies were explored to prevent CaSO4 2H2O (gypsum) precipitation during the on-orbit distillation process. Gypsum precipitation currently limits the water recovery rate onboard the International Space Station (ISS) to 70% versus the planned 85% target water recovery rate. Due to its ability to remove calcium cations in pretreated augmented urine (PTAU), ion exchange was selected as one of the technologies for further development by the PPP team. A total of 13 ion exchange resins were evaluated in various equilibrium and dynamic column tests with solutions of dissolved gypsum, urine ersatz, PTAU, and PTAU brine at 85% water recovery. While initial evaluations indicated that the Purolite SST60 resin had the highest calcium capacity in PTAU (0.30 meq/mL average), later tests showed that the Dowex G26 and Amberlite FPC12H resins had the highest capacity (0.5 meq/mL average). Testing at the Marshall Spaceflight Center (MSFC) integrates the ion exchange technology with a UPA ground article under flight-like pulsed flow conditions with PTAU. To date, no gypsum precipitation has taken place in any of the initial evaluations.

A debugger-interpreter with setup facilities for assembly programs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dolinskii, I.S.; Zisel`man, I.M.; Belotskii, S.L.

1995-11-01

In this paper a software program allowing one to introduce and debug the descriptions of the von Nuemann architecture processors and their assemblers, efficiently debug assembly programs, and investigate the instruction sets of the described processors is considered. For a description of the processor sematics and assembler syntax, a metassembly language is suggested.

Clean Water for Remote Locations

NASA Technical Reports Server (NTRS)

2006-01-01

Marshall Space Flight Center engineers are working on creating the Regenerative Environmental Control and Life Support System, a complex system of devices intended to sustain the astronauts living on the ISS and, in the future, sustain those who are blasting off to the Moon or Mars. The devices make use of the available resources, by turning wastewater from respiration, sweat, and urine into drinkable water. One of the devices that Marshall has been working on is the Water Recovery System (WRS). Marshall has teamed with long-time NASA contractor, Hamilton Sundstrand Space Systems International, Inc., of Windsor Locks, Connecticut. Hamilton Sundstrand, the original designer of the life support devices for the space suits, developed the Water Processor Assembly (WPA). It, along with the Urine Processor Assembly (UPA) developed by Marshall, combines to make up the total system, which is about the size of two refrigerators, and will support up to a six-member crew. The system is currently undergoing final testing and verification. "The Water Processor Assembly can produce up to about 28 gallons of potable recycled water each day," said Bob Bagdigian, Marshall Regenerative Environmental Control and Life Support System project manager. After the new systems are installed, annual delivered water to the ISS should decrease by approximately 15,960 pounds, or about 1,600 gallons.

Upgrades to the ISS Water Recovery System

NASA Technical Reports Server (NTRS)

Pruitt, Jennifer M.; Carter, Layne; Bagdigian, Robert M.; Kayatin, Mattthew J.

2015-01-01

The ISS Water Recovery System (WRS) includes the Water Processor Assembly (WPA) and the Urine Processor Assembly (UPA). The WRS produces potable water from a combination of crew urine (first processed through the UPA), crew latent, and Sabatier product water. The WRS has been operational on ISS since November 2008, producing over 21,000 L of potable water during that time. Though the WRS has performed well during this time, several modifications have been identified to improve the overall system performance. These modifications can reduce resupply and improve overall system reliability, which is beneficial for the ongoing ISS mission as well as for future NASA manned missions. The following paper lists these modifications, how they improve WRS performance, and a status on the ongoing development effort.

Upgrades to the ISS Water Recovery System

NASA Technical Reports Server (NTRS)

Kayatin, Matthew; Takada, Kevin; Carter, Layne

2017-01-01

The ISS Water Recovery System (WRS) includes the Water Processor Assembly (WPA) and the Urine Processor Assembly (UPA). The WRS produces potable water from a combination of crew urine (first processed through the UPA), crew latent, and Sabatier product water. Though the WRS has performed well since operations began in November 2008, several modifications have been identified to improve the overall system performance. These modifications can reduce resupply and improve overall system reliability, which is beneficial for the ongoing ISS mission as well as for future NASA manned missions. The following paper details efforts to improve the WPA through the use of Reverse Osmosis technology to reduce the resupply mass of the WPA Multifiltration Bed and improved catalyst for the WPA Catalytic Reactor to reduce the operational temperature and pressure. For the UPA, this paper discusses progress on various concepts for improving the reliability of the UPA, including the implementation of a more reliable drive belt, improved methods for managing condensate in the stationary bowl of the Distillation Assembly, deleting the Separator Plumbing Assembly, and evaluating upgrades to the UPA vacuum pump.

Ion Exchange Technology Development in Support of the Urine Processor Assembly Precipitation Prevention Project for the International Space Station

NASA Technical Reports Server (NTRS)

Mitchell, Julie L.; Broyan, James L.; Pickering, Karen D.; Adam, Niklas; Casteel, Michael; Callaham, Michael; Carrier, Chris

2011-01-01

In support of the Urine Processor Assembly Precipitation Prevention Project (UPA PPP), multiple technologies were explored to prevent CaSO4 dot 2H2O (gypsum) precipitation during the on-orbit distillation process. Gypsum precipitation currently limits the water recovery rate onboard the International Space Station (ISS) to 70% versus the planned 85% target water recovery rate. Due to its advanced performance in removing calcium cations in pretreated augmented urine (PTAU), ion exchange was selected as one of the technologies for further development by the PPP team. A total of 12 ion exchange resins were evaluated in various equilibrium and dynamic column tests with solutions of dissolved gypsum, urine ersatz, PTAU, and PTAU brine at 85% water recovery. While initial evaluations indicated that the Purolite SST60 resin had the highest calcium capacity in PTAU (0.30 meq/mL average), later tests showed that the Dowex G26 and Amberlite FPC12H resins had the highest capacity (0.5 meq/mL average). Further dynamic column testing proved that G26 performance is +/- 10% of that value at flow rates of 0.45 and 0.79 Lph under continuous flow, and 10.45 Lph under pulsed flow. Testing at the Marshall Spaceflight Center (MSFC) integrates the ion exchange technology with a UPA ground article under flight-like pulsed flow conditions with PTAU. To date, no gypsum precipitation has taken place in any of the initial evaluations.

Preventing Precipitation in the ISS Urine Processor

NASA Technical Reports Server (NTRS)

Muirhead, Dean; Carter, Layne; Williamson, Jill; Chambers, Antja

2017-01-01

The ISS Urine Processor Assembly (UPA) was initially designed to achieve 85% recovery of water from pretreated urine on ISS. Pretreated urine is comprised of crew urine treated with flush water, an oxidant (chromium trioxide), and an inorganic acid (sulfuric acid) to control microbial growth and inhibit precipitation. Unfortunately, initial operation of the UPA on ISS resulted in the precipitation of calcium sulfate at 85% recovery. This occurred because the calcium concentration in the crew urine was elevated in microgravity due to bone loss. The higher calcium concentration precipitated with sulfate from the pretreatment acid, resulting in a failure of the UPA due to the accumulation of solids in the Distillation Assembly. Since this failure, the UPA has been limited to a reduced recovery of water from urine to prevent calcium sulfate from reaching the solubility limit. NASA personnel have worked to identify a solution that would allow the UPA to return to a nominal recovery rate of 85%. This effort has culminated with the development of a pretreatment based on phosphoric acid instead of sulfuric acid. By eliminating the sulfate associated with the pretreatment, the brine can be concentrated to a much higher concentration before calcium sulfate reach the solubility limit. This paper summarizes the development of this pretreatment and the testing performed to verify its implementation on ISS.

Expedition Seven CDR Malenkenko performs IFM on Condensate Water Processor

NASA Image and Video Library

2003-07-03

ISS007-E-09229 (3 July 2003) --- Cosmonaut Yuri I. Malenchenko, Expedition 7 mission commander, performs scheduled in-flight maintenance (IFM) on the condensate water processor (SRV-K2M) by removing and replacing its BKO multifiltration/purification column unit, which has reached its service life limit (450 liters min.). The old unit will be discarded on Progress. The IFM took place in the Zvezda Service Module on the International Space Station (ISS). Malenchenko represents Rosaviakosmos.

Expedition Seven CDR Malenkenko performs IFM on Condensate Water Processor

NASA Image and Video Library

2003-07-03

ISS007-E-09231 (3 July 2003) --- Cosmonaut Yuri I. Malenchenko, Expedition 7 mission commander, performs scheduled in-flight maintenance (IFM) on the condensate water processor (SRV-K2M) by removing and replacing its BKO multifiltration/purification column unit, which has reached its service life limit (450 liters min.). The old unit will be discarded on Progress. The IFM took place in the Zvezda Service Module on the International Space Station (ISS). Malenchenko represents Rosaviakosmos.

High-speed assembly language (80386/80387) programming for laser spectra scan control and data acquisition providing improved resolution water vapor spectroscopy

NASA Technical Reports Server (NTRS)

Allen, Robert J.

1988-01-01

An assembly language program using the Intel 80386 CPU and 80387 math co-processor chips was written to increase the speed of data gathering and processing, and provide control of a scanning CW ring dye laser system. This laser system is used in high resolution (better than 0.001 cm-1) water vapor spectroscopy experiments. Laser beam power is sensed at the input and output of white cells and the output of a Fabry-Perot. The assembly language subroutine is called from Basic, acquires the data and performs various calculations at rates greater than 150 faster than could be performed by the higher level language. The width of output control pulses generated in assembly language are 3 to 4 microsecs as compared to 2 to 3.7 millisecs for those generated in Basic (about 500 to 1000 times faster). Included are a block diagram and brief description of the spectroscopy experiment, a flow diagram of the Basic and assembly language programs, listing of the programs, scope photographs of the computer generated 5-volt pulses used for control and timing analysis, and representative water spectrum curves obtained using these programs.

Status of the International Space Station Regenerative ECLSS Water Recovery and Oxygen Generation Systems

NASA Technical Reports Server (NTRS)

Bagdigian, Robert M.; Cloud, Dale

2005-01-01

NASA is developing three racks containing regenerative water recovery and oxygen generation systems (WRS and OGS) for deployment on the International Space Station (ISS). The major assemblies included in these racks are the Water Processor Assembly (WPA), Urine Processor Assembly (UPA), Oxygen Generation Assembly (OGA), and the Power Supply Module (PSM) supporting the OGA. The WPA and OGA are provided by Hamilton Sundstrand Space Systems International (HSSSI), Inc., while the UPA and PSM are developed in- house by the Marshall Space Flight Center (MSFC). The assemblies have completed the manufacturing phase and are in various stages of testing and integration into the flight racks. This paper summarizes the status as of April 2005 and describes some of the technical challenges encountered and lessons learned over the past year.

Methane Post-Processor Development to Increase Oxygen Recovery beyond State-of-the-Art Carbon Dioxide Reduction Technology

NASA Technical Reports Server (NTRS)

Abney, Morgan; Miller, Lee; Greenwood, Zach; Iannantuono, Michelle; Jones, Kenny

2013-01-01

State-of-the-art life support carbon dioxide (CO2) reduction technology, based on the Sabatier reaction, is theoretically capable of 50% recovery of oxygen from metabolic CO2. This recovery is constrained by the limited availability of reactant hydrogen. Post-processing of the methane byproduct from the Sabatier reactor results in hydrogen recycle and a subsequent increase in oxygen recovery. For this purpose, a Methane Post-Processor Assembly containing three sub-systems has been developed and tested. The assembly includes a Methane Purification Assembly (MePA) to remove residual CO2 and water vapor from the Sabatier product stream, a Plasma Pyrolysis Assembly (PPA) to partially pyrolyze methane into hydrogen and acetylene, and an Acetylene Separation Assembly (ASepA) to purify the hydrogen product for recycle. The results of partially integrated testing of the sub-systems are reported.

Methane Post-Processor Development to Increase Oxygen Recovery beyond State-of-the-Art Carbon Dioxide Reduction Technology

NASA Technical Reports Server (NTRS)

Abney, Morgan B.; Greenwood, Zachary; Miller, Lee A.; Alvarez, Giraldo; Iannantuono, Michelle; Jones, Kenny

2013-01-01

State-of-the-art life support carbon dioxide (CO2) reduction technology, based on the Sabatier reaction, is theoretically capable of 50% recovery of oxygen from metabolic CO2. This recovery is constrained by the limited availability of reactant hydrogen. Post-processing of the methane byproduct from the Sabatier reactor results in hydrogen recycle and a subsequent increase in oxygen recovery. For this purpose, a Methane Post-Processor Assembly containing three sub-systems has been developed and tested. The assembly includes a Methane Purification Assembly (MePA) to remove residual CO2 and water vapor from the Sabatier product stream, a Plasma Pyrolysis Assembly (PPA) to partially pyrolyze methane into hydrogen and acetylene, and an Acetylene Separation Assembly (ASepA) to purify the hydrogen product for recycle. The results of partially integrated testing of the sub-systems are reported

Status of the Node 3 Regenerative Environmental Cpntrol& Life Support System Water Recovery & Oxygen Generation Systems

NASA Technical Reports Server (NTRS)

Carrasquillo, Robyn L.

2003-01-01

NASA s Marshall Space Flight Center is providing three racks containing regenerative water recovery and oxygen generation systems (WRS and OGS) for flight on the lnternational Space Station s (ISS) Node 3 element. The major assemblies included in these racks are the Water Processor Assembly (WPA), Urine Processor Assembly (UPA), Oxygen Generation Assembly (OGA), and the Power Supply Module (PSM) supporting the OGA. The WPA and OGA are provided by Hamilton Sundstrand Space Systems lnternational (HSSSI), while the UPA and PSM are being designed and manufactured in-house by MSFC. The assemblies are currently in the manufacturing and test phase and are to be completed and integrated into flight racks this year. This paper gives an overview of the technologies and system designs, technical challenges encountered and solved, and the current status.

Experimental testing of the noise-canceling processor.

PubMed

Collins, Michael D; Baer, Ralph N; Simpson, Harry J

2011-09-01

Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

System and method for controlling a combustor assembly

DOEpatents

York, William David; Ziminsky, Willy Steve; Johnson, Thomas Edward; Stevenson, Christian Xavier

2013-03-05

A system and method for controlling a combustor assembly are disclosed. The system includes a combustor assembly. The combustor assembly includes a combustor and a fuel nozzle assembly. The combustor includes a casing. The fuel nozzle assembly is positioned at least partially within the casing and includes a fuel nozzle. The fuel nozzle assembly further defines a head end. The system further includes a viewing device configured for capturing an image of at least a portion of the head end, and a processor communicatively coupled to the viewing device, the processor configured to compare the image to a standard image for the head end.

Integral Fast Reactor fuel pin processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Levinskas, D.

1993-01-01

This report discusses the pin processor which receives metal alloy pins cast from recycled Integral Fast Reactor (IFR) fuel and prepares them for assembly into new IFR fuel elements. Either full length as-cast or precut pins are fed to the machine from a magazine, cut if necessary, and measured for length, weight, diameter and deviation from straightness. Accepted pins are loaded into cladding jackets located in a magazine, while rejects and cutting scraps are separated into trays. The magazines, trays, and the individual modules that perform the different machine functions are assembled and removed using remote manipulators and master-slaves.

Integral Fast Reactor fuel pin processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Levinskas, D.

1993-03-01

This report discusses the pin processor which receives metal alloy pins cast from recycled Integral Fast Reactor (IFR) fuel and prepares them for assembly into new IFR fuel elements. Either full length as-cast or precut pins are fed to the machine from a magazine, cut if necessary, and measured for length, weight, diameter and deviation from straightness. Accepted pins are loaded into cladding jackets located in a magazine, while rejects and cutting scraps are separated into trays. The magazines, trays, and the individual modules that perform the different machine functions are assembled and removed using remote manipulators and master-slaves.

Integrated Advanced Microwave Sounding Unit-A(AMSU-A). Engineering Test Report: METSAT A1 Signal Processor, (P/N 1331670-2, S /N F05)

NASA Technical Reports Server (NTRS)

Lund, D.

1998-01-01

This report presents a description of the tests performed, and the test data, for the AI METSAT Signal Processor Assembly P/N 1331670-2, S/N F05. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

Integrated Advanced Microwave Sounding Unit-A (AMSU-A). Engineering Test Report: METSAT A1 Signal Processor (P/N 1331670-2, S/N F03)

NASA Technical Reports Server (NTRS)

Lund, D.

1998-01-01

This report presents a description of tests performed, and the test data, for the A1 METSAT Signal Processor Assembly PN: 1331679-2, S/N F03. This assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

A VME-based software trigger system using UNIX processors

NASA Astrophysics Data System (ADS)

Atmur, Robert; Connor, David F.; Molzon, William

1997-02-01

We have constructed a distributed computing platform with eight processors to assemble and filter data from digitization crates. The filtered data were transported to a tape-writing UNIX computer via ethernet. Each processor ran a UNIX operating system and was installed in its own VME crate. Each VME crate contained dual-port memories which interfaced with the digitizers. Using standard hardware and software (VME and UNIX) allows us to select from a wide variety of non-proprietary products and makes upgrades simpler, if they are necessary.

Upgrades to the International Space Station Water Recovery System

NASA Technical Reports Server (NTRS)

Kayatin, Matthew J.; Pruitt, Jennifer M.; Nur, Mononita; Takada, Kevin C.; Carter, Layne

2017-01-01

The International Space Station (ISS) Water Recovery System (WRS) includes the Water Processor Assembly (WPA) and the Urine Processor Assembly (UPA). The WRS produces potable water from a combination of crew urine (first processed through the UPA), crew latent, and Sabatier product water. Though the WRS has performed well since operations began in November 2008, several modifications have been identified to improve the overall system performance. These modifications aim to reduce resupply and improve overall system reliability, which is beneficial for the ongoing ISS mission as well as for future NASA manned missions. The following paper details efforts to improve the WPA through the use of reverse osmosis membrane technology to reduce the resupply mass of the WPA Multi-filtration Bed and improved catalyst for the WPA Catalytic Reactor to reduce the operational temperature and pressure. For the UPA, this paper discusses progress on various concepts for improving the reliability of the system, including the implementation of a more reliable drive belt, improved methods for managing condensate in the stationary bowl of the Distillation Assembly, and evaluating upgrades to the UPA vacuum pump.

Estimating water flow through a hillslope using the massively parallel processor

NASA Technical Reports Server (NTRS)

Devaney, Judy E.; Camillo, P. J.; Gurney, R. J.

1988-01-01

A new two-dimensional model of water flow in a hillslope has been implemented on the Massively Parallel Processor at the Goddard Space Flight Center. Flow in the soil both in the saturated and unsaturated zones, evaporation and overland flow are all modelled, and the rainfall rates are allowed to vary spatially. Previous models of this type had always been very limited computationally. This model takes less than a minute to model all the components of the hillslope water flow for a day. The model can now be used in sensitivity studies to specify which measurements should be taken and how accurate they should be to describe such flows for environmental studies.

Integrated Advanced Microwave Sounding Unit-A (AMSU-A). Engineering Test Report: METSAT A1 Signal Processor (P/N: 1331670-2, S/N: F04)

NASA Technical Reports Server (NTRS)

Lund, D.

1998-01-01

This report presents a description of the tests performed, and the test data, for the A1 METSAT Signal Processor Assembly PN: 1331679-2, S/N F04. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

Electrical Prototype Power Processor for the 30-cm Mercury electric propulsion engine

NASA Technical Reports Server (NTRS)

Biess, J. J.; Frye, R. J.

1978-01-01

An Electrical Prototpye Power Processor has been designed to the latest electrical and performance requirements for a flight-type 30-cm ion engine and includes all the necessary power, command, telemetry and control interfaces for a typical electric propulsion subsystem. The power processor was configured into seven separate mechanical modules that would allow subassembly fabrication, test and integration into a complete power processor unit assembly. The conceptual mechanical packaging of the electrical prototype power processor unit demonstrated the relative location of power, high voltage and control electronic components to minimize electrical interactions and to provide adequate thermal control in a vacuum environment. Thermal control was accomplished with a heat pipe simulator attached to the base of the modules.

Regenerative (Regen) ECLSS Operations Water Balance

NASA Technical Reports Server (NTRS)

Tobias, Barry

2010-01-01

In November 2008, the Water Regenerative System racks were launched aboard Space Shuttle flight, STS-126 (ULF2) and installed and activated on the International Space Station (ISS). These racks, consisting of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA), completed the installation of the Regenerative (Regen) ECLSS systems which includes the Oxygen Generator Assembly (OGA) that was launched 2 years prior. With the onset of active water management on the US segment of the ISS, a new operational concept was required, that of "water balance." Even more recently, in 2010 the Sabatier system came online which converts H2 and CO2 into water and methane. The Regen ECLSS systems accept condensation from the atmosphere, urine from crew, and processes that fluid via various means into potable water which is used for crew drinking, building up skip-cycle water inventory, and water for electrolysis to produce oxygen. Specification rates of crew urine output, condensate output, O2 requirements, toilet flush water and drinking needs are well documented and used as a general plan when Regen ECLSS came online. Spec rates are useful in long term planning, however, daily or weekly rates are dependent on a number of variables. The constantly changing rates created a new challenge for the ECLSS flight controllers, who are responsible for operating the ECLSS systems onboard ISS. This paper will review the various inputs to rate changes and inputs to planning events, including but not limited to; crew personnel makeup, Regen ECLSS system operability, vehicle traffic, water containment availability, and Carbon Dioxide Removal Assembly (CDRA) capability. Along with the inputs that change the various rates, the paper will review the different systems, their constraints and finally the operational means by which flight controllers manage this new challenge of "water balance."

Distributed processor allocation for launching applications in a massively connected processors complex

DOEpatents

Pedretti, Kevin

2008-11-18

A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute processor allocator. The compute processor allocators can share a common database of information pertinent to compute processor allocation. A communication path permits retrieval of information from the database independently of the compute processor allocators.

A microcomputer based frequency-domain processor for laser Doppler anemometry

NASA Technical Reports Server (NTRS)

Horne, W. Clifton; Adair, Desmond

1988-01-01

A prototype multi-channel laser Doppler anemometry (LDA) processor was assembled using a wideband transient recorder and a microcomputer with an array processor for fast Fourier transform (FFT) computations. The prototype instrument was used to acquire, process, and record signals from a three-component wind tunnel LDA system subject to various conditions of noise and flow turbulence. The recorded data was used to evaluate the effectiveness of burst acceptance criteria, processing algorithms, and selection of processing parameters such as record length. The recorded signals were also used to obtain comparative estimates of signal-to-noise ratio between time-domain and frequency-domain signal detection schemes. These comparisons show that the FFT processing scheme allows accurate processing of signals for which the signal-to-noise ratio is 10 to 15 dB less than is practical using counter processors.

Integrated Advanced Microwave Sounding Unit-A (AMSU-A): Engineering Test Report: METSAT A2 Signal Processor (P/N 1331120-2, S/N F03) S/N 107

NASA Technical Reports Server (NTRS)

1998-01-01

This report presents a description of the tests performed, and the test data, for the A2 METSAT Signal Processor Assembly PN: 1331120-2, S/N F03. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure."

Integrated Advanced Microwave Sounding Unit-A (AMSU-A): Engineering Test Report, METSAT A2 Signal Processor (P/N 1331120-2, S/N F04) S/N 108

NASA Technical Reports Server (NTRS)

1998-01-01

This report presents a description of the tests performed, and the test data, for the A2 METSAT Signal Processor Assembly PN: 1331120-2, S/N F04. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure."

International Space Station Water Balance Operations

NASA Technical Reports Server (NTRS)

Tobias, Barry; Garr, John D., II; Erne, Meghan

2011-01-01

In November 2008, the Water Regenerative System racks were launched aboard Space Shuttle flight, STS-126 (ULF2) and installed and activated on the International Space Station (ISS). These racks, consisting of the Water Processor Assembly (WPA) and Urine Processor Assembly (UPA), completed the installation of the Regenerative (Regen) Environmental Control and Life Support Systems (ECLSS), which includes the Oxygen Generation Assembly (OGA) that was launched 2 years prior. With the onset of active water management on the US segment of the ISS, a new operational concept was required, that of water balance . In November of 2010, the Sabatier system, which converts H2 and CO2 into water and methane, was brought on line. The Regen ECLSS systems accept condensation from the atmosphere, urine from crew, and processes that fluid via various means into potable water, which is used for crew drinking, building up skip-cycle water inventory, and water for electrolysis to produce oxygen. Specification (spec) rates of crew urine output, condensate output, O2 requirements, toilet flush water, and drinking needs are well documented and used as the best guess planning rates when Regen ECLSS came online. Spec rates are useful in long term planning, however, daily or weekly rates are dependent upon a number of variables. The constantly changing rates created a new challenge for the ECLSS flight controllers, who are responsible for operating the ECLSS systems onboard ISS from Mission Control in Houston. This paper reviews the various inputs to water planning, rate changes, and dynamic events, including but not limited to: crew personnel makeup, Regen ECLSS system operability, vehicle traffic, water storage availability, and Carbon Dioxide Removal Assembly (CDRA), Sabatier, and OGA capability. Along with the inputs that change the various rates, the paper will review the different systems, their constraints, and finally the operational challenges and means by which flight controllers

Measure Guideline: Water Management at Tub and Shower Assemblies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dickson, B.

2011-12-01

Due to the high concentrations of water and the consequential risk of water damage to the home's structure a comprehensive water management system is imperative to protect the building assemblies underlying the finish surround of tub and shower areas. This guide shows how to install fundamental waterproofing strategies to prevent water related issues at shower and tub areas. When conducting a total gut rehab of a structure or constructing a new home, best practice installation and detailing for effective waterproofing are critically important at bathtub and shower assemblies. Water management issues in a structure may go unrecognized for long periods,more » so that when they are finally observed, the damage from long-term water exposure is extensive. A gut rehab is often undertaken when a home has experienced a natural disaster or when the homeowners are interested in converting an old, high-energy-use building into a high-quality, efficient structure that meets or exceeds one of the national energy standards, such as ENERGY STAR or LEED for homes. During a gut rehab, bath areas need to be replaced with diligent attention to detail. Employing effective water management practices in the installation and detailing of tub and shower assemblies will minimize or eliminate water issues within the building cavities and on the finished surfaces. A residential tub-and-shower surround or shower-stall assembly is designed to handle a high volume of water - 2.5 gallons per minute, with multiple baths occurring during a typical day. Transitions between dissimilar materials and connections between multiple planes must be installed with care to avoid creating a pathway for water to enter the building assemblies. Due to the high volume of water and the consequential risk of water damage to the home's structure, a comprehensive water management system is imperative to protect the building assemblies underlying the finish surround of tub and shower areas. At each stage of

CWSA (Condensate Water Separator Assembly)

NASA Image and Video Library

2009-05-14

ISS019-E-016029 (14 May 2009) --- Japan Aerospace Exploration Agency (JAXA) astronaut Koichi Wakata, Expedition 19/20 flight engineer, performs in-flight maintenance on the Condensate Water Separator Assembly (CWSA) in the Columbus laboratory of the International Space Station.

Advanced On-Board Processor (AOP). [for future spacecraft applications

NASA Technical Reports Server (NTRS)

1973-01-01

Advanced On-board Processor the (AOP) uses large scale integration throughout and is the most advanced space qualified computer of its class in existence today. It was designed to satisfy most spacecraft requirements which are anticipated over the next several years. The AOP design utilizes custom metallized multigate arrays (CMMA) which have been designed specifically for this computer. This approach provides the most efficient use of circuits, reduces volume, weight, assembly costs and provides for a significant increase in reliability by the significant reduction in conventional circuit interconnections. The required 69 CMMA packages are assembled on a single multilayer printed circuit board which together with associated connectors constitutes the complete AOP. This approach also reduces conventional interconnections thus further reducing weight, volume and assembly costs.

FPGA wavelet processor design using language for instruction-set architectures (LISA)

NASA Astrophysics Data System (ADS)

Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

2007-04-01

The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.

Use of DSC and DMA Techniques to Help Investigate a Material Anomaly for PTFE Used in Processing a Piston Cup for the Urine Processor Assembly (UPA) on International Space Station (ISS)

NASA Technical Reports Server (NTRS)

Wingard, Doug

2010-01-01

Human urine and flush water are eventually converted into drinking water with the Urine Processor Assembly (UPA) aboard the International Space Station (ISS). This conversion is made possible through the Distillation Assembly (DA) of the UPA. One component of the DA is a molded circular piston cup made of virgin polytetrafluoroethylene (PTFE). The piston cup is assembled to a titanium component using eight fasteners and washers. Molded PTFE produced for spare piston cups in the first quarter of 2010 was different in appearance and texture, and softer than material molded for previous cups. For the suspect newer PTFE material, cup fasteners were tightened to only one-half the required torque value, yet the washers embedded almost halfway into the material. The molded PTFE used in the DA piston cup should be Type II, based on AMS 3667D and ASTM D4894 specifications. The properties of molded PTFE are considerably different between Type I and II materials. Engineers working with the DA thought that if Type I PTFE was molded by mistake instead of Type II material, that could have resulted in the anomalous material properties. Typically, the vendor molds flat sheet PTFE from the same material lot used to mold the piston cups, and tensile testing as part of quality control should verify that the PTFE is Type II material. However, for this discrepant lot of material, such tensile data was not available. Differential scanning calorimetry (DSC) and dynamic mechanical analysis (DMA) were two of the testing techniques used at the NASA/Marshall Space Flight Center (MSFC) to investigate the anomaly for the PTFE material. Other techniques used on PTFE specimens were: Shore D hardness testing, tensile testing on dog bone specimens and a qualitative estimation of porosity by optical and scanning electron microscopy.

Self-assembly of water-soluble nanocrystals

DOEpatents

Fan, Hongyou [Albuquerque, NM; Brinker, C Jeffrey [Albuquerque, NM; Lopez, Gabriel P [Albuquerque, NM

2012-01-10

A method for forming an ordered array of nanocrystals where a hydrophobic precursor solution with a hydrophobic core material in an organic solvent is added to a solution of a surfactant in water, followed by removal of a least a portion of the organic solvent to form a micellar solution of nanocrystals. A precursor co-assembling material, generally water-soluble, that can co-assemble with individual micelles formed in the micellar solution of nanocrystals can be added to this micellar solution under specified reaction conditions (for example, pH conditions) to form an ordered-array mesophase material. For example, basic conditions are used to precipitate an ordered nanocrystal/silica array material in bulk form and acidic conditions are used to form an ordered nanocrystal/silica array material as a thin film.

Compact propane fuel processor for auxiliary power unit application

NASA Astrophysics Data System (ADS)

Dokupil, M.; Spitta, C.; Mathiak, J.; Beckhaus, P.; Heinzel, A.

With focus on mobile applications a fuel cell auxiliary power unit (APU) using liquefied petroleum gas (LPG) is currently being developed at the Centre for Fuel Cell Technology (Zentrum für BrennstoffzellenTechnik, ZBT gGmbH). The system is consisting of an integrated compact and lightweight fuel processor and a low temperature PEM fuel cell for an electric power output of 300 W. This article is presenting the current status of development of the fuel processor which is designed for a nominal hydrogen output of 1 k Wth,H2 within a load range from 50 to 120%. A modular setup was chosen defining a reformer/burner module and a CO-purification module. Based on the performance specifications, thermodynamic simulations, benchmarking and selection of catalysts the modules have been developed and characterised simultaneously and then assembled to the complete fuel processor. Automated operation results in a cold startup time of about 25 min for nominal load and carbon monoxide output concentrations below 50 ppm for steady state and dynamic operation. Also fast transient response of the fuel processor at load changes with low fluctuations of the reformate gas composition have been achieved. Beside the development of the main reactors the transfer of the fuel processor to an autonomous system is of major concern. Hence, concepts for packaging have been developed resulting in a volume of 7 l and a weight of 3 kg. Further a selection of peripheral components has been tested and evaluated regarding to the substitution of the laboratory equipment.

6. SAWTOOTH WINDOW RANKS ABOVE ASSEMBLY LINES, WATER TOWER, AND ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

6. SAWTOOTH WINDOW RANKS ABOVE ASSEMBLY LINES, WATER TOWER, AND SECOND FLOOR WAREHOUSE STRUCTURE. VIEW TO SOUTH-SOUTHEAST. - Ford Motor Company Long Beach Assembly Plant, Assembly Building, 700 Henry Ford Avenue, Long Beach, Los Angeles County, CA

A parallel algorithm for generation and assembly of finite element stiffness and mass matrices

NASA Technical Reports Server (NTRS)

Storaasli, O. O.; Carmona, E. A.; Nguyen, D. T.; Baddourah, M. A.

1991-01-01

A new algorithm is proposed for parallel generation and assembly of the finite element stiffness and mass matrices. The proposed assembly algorithm is based on a node-by-node approach rather than the more conventional element-by-element approach. The new algorithm's generality and computation speed-up when using multiple processors are demonstrated for several practical applications on multi-processor Cray Y-MP and Cray 2 supercomputers.

Challenges with Operating a Water Recovery System (WRS) in the Microgravity Environment of the International Space Station (ISS)

NASA Technical Reports Server (NTRS)

Carter, Donald Layne

2017-01-01

The ISS WRS produces potable water from crew urine, crew latent, and Sabatier product water. This system has been operational on ISS since November 2008, producing over 30,000 L of water during that time. The WRS includes a Urine Processor Assembly (UPA) to produce a distillate from the crew urine. This distillate is combined with the crew latent and Sabatier product water and further processed by the Water Processor Assembly (WPA) to the potable water. The UPA and WPA use technologies commonly used on ISS for water purification, including filtration, distillation, adsorption, ion exchange, and catalytic oxidation. The primary challenge with the design and operation of the WRS has been with implementing these technologies in microgravity. The absence of gravity has created unique issues that impact the constituency of the waste streams, alter two-phase fluid dynamics, and increases the impact of particulates on system performance. NASA personnel continue to pursue upgrades to the existing design to improve reliability while also addressing their viability for missions beyond ISS.

Self-assembly of chlorophenols in water

PubMed Central

Rogalska, Ewa; Rogalski, Marek; Gulik-Krzywicki, Tadeusz; Gulik, Annette; Chipot, Christophe

1999-01-01

In saturated solutions of some di- and trichlorophenols, structures with complex morphologies, consisting of thin, transparent sheets often coiling into helices and ultimately twisting into filaments, were observed under the optical microscope. Freeze-fracture electron microscopy, x-ray diffraction, phase diagrams, and molecular modeling were performed to elucidate the observed phenomena. Here, we present evidence that the chlorophenols studied, when interacting with water, self-assemble into bilayers. The fact that some chlorophenols form the same supramolecular structures as those described previously for structurally nonrelated surfactants sheds light on the mechanisms of self-assembly. PMID:10359753

Stream Processors

NASA Astrophysics Data System (ADS)

Erez, Mattan; Dally, William J.

Stream processors, like other multi core architectures partition their functional units and storage into multiple processing elements. In contrast to typical architectures, which contain symmetric general-purpose cores and a cache hierarchy, stream processors have a significantly leaner design. Stream processors are specifically designed for the stream execution model, in which applications have large amounts of explicit parallel computation, structured and predictable control, and memory accesses that can be performed at a coarse granularity. Applications in the streaming model are expressed in a gather-compute-scatter form, yielding programs with explicit control over transferring data to and from on-chip memory. Relying on these characteristics, which are common to many media processing and scientific computing applications, stream architectures redefine the boundary between software and hardware responsibilities with software bearing much of the complexity required to manage concurrency, locality, and latency tolerance. Thus, stream processors have minimal control consisting of fetching medium- and coarse-grained instructions and executing them directly on the many ALUs. Moreover, the on-chip storage hierarchy of stream processors is under explicit software control, as is all communication, eliminating the need for complex reactive hardware mechanisms.

Array processor architecture

NASA Technical Reports Server (NTRS)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1983-01-01

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

A self-sustained, complete and miniaturized methanol fuel processor for proton exchange membrane fuel cell

NASA Astrophysics Data System (ADS)

Yang, Mei; Jiao, Fengjun; Li, Shulian; Li, Hengqiang; Chen, Guangwen

2015-08-01

A self-sustained, complete and miniaturized methanol fuel processor has been developed based on modular integration and microreactor technology. The fuel processor is comprised of one methanol oxidative reformer, one methanol combustor and one two-stage CO preferential oxidation unit. Microchannel heat exchanger is employed to recover heat from hot stream, miniaturize system size and thus achieve high energy utilization efficiency. By optimized thermal management and proper operation parameter control, the fuel processor can start up in 10 min at room temperature without external heating. A self-sustained state is achieved with H2 production rate of 0.99 Nm3 h-1 and extremely low CO content below 25 ppm. This amount of H2 is sufficient to supply a 1 kWe proton exchange membrane fuel cell. The corresponding thermal efficiency of whole processor is higher than 86%. The size and weight of the assembled reactors integrated with microchannel heat exchangers are 1.4 L and 5.3 kg, respectively, demonstrating a very compact construction of the fuel processor.

Green Secure Processors: Towards Power-Efficient Secure Processor Design

NASA Astrophysics Data System (ADS)

Chhabra, Siddhartha; Solihin, Yan

With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

Results of the Alternative Water Processor Test, A Novel Technology for Exploration Wastewater Remediation

NASA Technical Reports Server (NTRS)

Meyer, Caitlin E.; Pensinger, Stuart; Adam, Niklas; Pickering, Karen D.; Barta, Daniel; Shull, Sarah A.; Vega, Leticia M.; Lange, Kevin; Christenson, Dylan; Jackson, W. Andrew

2016-01-01

Biologically-based water recovery systems are a regenerative, low energy alternative to physiochemical processes to reclaim water from wastewater. This report summarizes the results of the Alternative Water Processor (AWP) Integrated Test, conducted from June 2013 until April 2014. The system was comprised of four (4) membrane aerated bioreactors (MABRs) to remove carbon and nitrogen from an exploration mission wastewater and a coupled forward and reverse osmosis system to remove large organic and inorganic salts from the biological system effluent. The system exceeded the overall objectives of the test by recovering 90% of the influent wastewater processed into a near potable state and a 64% reduction of consumables from the current state of the art water recovery system on the International Space Station (ISS). However, the biological system fell short of its test goals, failing to remove 75% and 90% of the influent ammonium and organic carbon, respectively. Despite not meeting its test goals, the BWP demonstrated the feasibility of an attached-growth biological system for simultaneous nitrification and denitrification, an innovative, volume- and consumable-saving design that does not require toxic pretreatment.

Heat pump water heater and storage tank assembly

DOEpatents

Dieckmann, John T.; Nowicki, Brian J.; Teagan, W. Peter; Zogg, Robert

1999-09-07

A water heater and storage tank assembly comprises a housing defining a chamber, an inlet for admitting cold water to the chamber, and an outlet for permitting flow of hot water from the chamber. A compressor is mounted on the housing and is removed from the chamber. A condenser comprises a tube adapted to receive refrigerant from the compressor, and winding around the chamber to impart heat to water in the chamber. An evaporator is mounted on the housing and removed from the chamber, the evaporator being adapted to receive refrigerant from the condenser and to discharge refrigerant to conduits in communication with the compressor. An electric resistance element extends into the chamber, and a thermostat is disposed in the chamber and is operative to sense water temperature and to actuate the resistance element upon the water temperature dropping to a selected level. The assembly includes a first connection at an external end of the inlet, a second connection at an external end of the outlet, and a third connection for connecting the resistance element, compressor and evaporator to an electrical power source.

Simulating Synchronous Processors

DTIC Science & Technology

1988-06-01

34f Fvtvru m LABORATORY FOR INMASSACHUSETTSFCOMPUTER SCIENCE TECHNOLOGY MIT/LCS/TM-359 SIMULATING SYNCHRONOUS PROCESSORS Jennifer Lundelius Welch...PROJECT TASK WORK UNIT Arlington, VA 22217 ELEMENT NO. NO. NO ACCESSION NO. 11. TITLE Include Security Classification) Simulating Synchronous Processors...necessary and identify by block number) In this paper we show how a distributed system with synchronous processors and asynchro- nous message delays can

Dormancy and Recovery Testing for Biological Wastewater Processors

NASA Technical Reports Server (NTRS)

Hummerick, Mary F.; Coutts, Janelle L.; Lunn, Griffin M.; Spencer, LaShelle; Khodadad, Christina L.; Birmele, Michele N.; Frances, Someliz; Wheeler, Raymond

2015-01-01

Resource recovery and recycling waste streams to usable water via biological water processors is a plausible component of an integrated water purification system. Biological processing as a pretreatment can reduce the load of organic carbon and nitrogen compounds entering physiochemical systems downstream. Aerated hollow fiber membrane bioreactors, have been proposed and studied for a number of years as an approach for treating wastewater streams for space exploration.

Hybrid Electro-Optic Processor

DTIC Science & Technology

1991-07-01

This report describes the design of a hybrid electro - optic processor to perform adaptive interference cancellation in radar systems. The processor is...modulator is reported. Included is this report is a discussion of the design, partial fabrication in the laboratory, and partial testing of the hybrid electro ... optic processor. A follow on effort is planned to complete the construction and testing of the processor. The work described in this report is the

Evaluation of the Sentinel-3 Hydrologic Altimetry Processor prototypE (SHAPE) methods.

NASA Astrophysics Data System (ADS)

Benveniste, J.; Garcia-Mondéjar, A.; Bercher, N.; Fabry, P. L.; Roca, M.; Varona, E.; Fernandes, J.; Lazaro, C.; Vieira, T.; David, G.; Restano, M.; Ambrózio, A.

2017-12-01

Inland water scenes are highly variable, both in space and time, which leads to a much broader range of radar signatures than ocean surfaces. This applies to both LRM and "SAR" mode (SARM) altimetry. Nevertheless the enhanced along-track resolution of SARM altimeters should help improve the accuracy and precision of inland water height measurements from satellite. The SHAPE project - Sentinel-3 Hydrologic Altimetry Processor prototypE - which is funded by ESA through the Scientific Exploitation of Operational Missions Programme Element (contract number 4000115205/15/I-BG) aims at preparing for the exploitation of Sentinel-3 data over the inland water domain. The SHAPE Processor implements all of the steps necessary to derive rivers and lakes water levels and discharge from Delay-Doppler Altimetry and perform their validation against in situ data. The processor uses FBR CryoSat-2 and L1A Sentinel-3A data as input and also various ancillary data (proc. param., water masks, L2 corrections, etc.), to produce surface water levels. At a later stage, water level data are assimilated into hydrological models to derive river discharge. This poster presents the improvements obtained with the new methods and algorithms over the regions of interest (Amazon and Danube rivers, Vanern and Titicaca lakes).

Virtualization for Cost-Effective Teaching of Assembly Language Programming

ERIC Educational Resources Information Center

Cadenas, José O.; Sherratt, R. Simon; Howlett, Des; Guy, Chris G.; Lundqvist, Karsten O.

2015-01-01

This paper describes a virtual system that emulates an ARM-based processor machine, created to replace a traditional hardware-based system for teaching assembly language. The virtual system proposed here integrates, in a single environment, all the development tools necessary to deliver introductory or advanced courses on modern assembly language…

Environmental Control and Life Support System, Water Recovery System

NASA Technical Reports Server (NTRS)

2000-01-01

The Environmental Control and Life Support System (ECLSS) Group of the Flight Projects Directorate at the Marshall Space Flight Center (MSFC) is responsible for designing and building the life support systems that will provide the crew of the International Space Station (ISS) a comfortable environment in which to live and work. This is a close-up view of ECLSS Water Recovery System (WRS) racks. The MSFC's ECLSS Group overseas much of the development of the hardware that will allow a constant supply of clean water for four to six crewmembers aboard the ISS. The WRS provides clean water through the reclamation of wastewaters, including water obtained from the Space Shuttle's fuel cells, crewmember urine, used shower, handwash and oral hygiene water cabin humidity condensate, and Extravehicular Activity (EVA) wastes. The WRS is comprised of a Urine Processor Assembly (UPA), and a Water Processor Assembly (WPA). The UPA accepts and processes pretreated crewmember urine to allow it to be processed along with other wastewaters in the WPA, which removes free gas, organic, and nonorganic constituents before the water goes through a series of multifiltration beds for further purification. Product water quality is monitored primarily through conductivity measurements. Unacceptable water is sent back through the WPA for reprocessing. Clean water is sent to a storage tank. The water must meet stringent purity standards before consumption by the crew. The UPA provided by the MSFC and the WRA is provided by the prime contractor, Hamilton Sundstrand Space Systems, International (HSSSI) from Cornecticut.

Hybrid Optical Processor

DTIC Science & Technology

1990-08-01

LCTVs) ..................... 17 2.14 JOINT FOURIER TRANSFORM PROCESSOR .................. 18 2.15 HOLOGRAPHIC ASSOCIATIVE MEMORY USING A MICRO ...RADC-TR-90-256 Final Technical Report August1990 AD-A227 163 HYBRID OPTICAL PROCESSOR Dove Electronics, Inc. J.F. Dove, F.T .S. Yu, C. Eldering...ANM SUSUE & FUNDING NUMBERS C - F19628-87-C-0086 HYBRID OPTICAL PROCESSOR PE - 61102F PR - 2305 &AUThNOA TA - J7 J.F. Dove, F.T.S. Yu, C. Eldering WU

Sequence information signal processor

DOEpatents

Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

1999-01-01

An electronic circuit is used to compare two sequences, such as genetic sequences, to determine which alignment of the sequences produces the greatest similarity. The circuit includes a linear array of series-connected processors, each of which stores a single element from one of the sequences and compares that element with each successive element in the other sequence. For each comparison, the processor generates a scoring parameter that indicates which segment ending at those two elements produces the greatest degree of similarity between the sequences. The processor uses the scoring parameter to generate a similar scoring parameter for a comparison between the stored element and the next successive element from the other sequence. The processor also delivers the scoring parameter to the next processor in the array for use in generating a similar scoring parameter for another pair of elements. The electronic circuit determines which processor and alignment of the sequences produce the scoring parameter with the highest value.

Method for fast start of a fuel processor

DOEpatents

Ahluwalia, Rajesh K [Burr Ridge, IL; Ahmed, Shabbir [Naperville, IL; Lee, Sheldon H. D. [Willowbrook, IL

2008-01-29

An improved fuel processor for fuel cells is provided whereby the startup time of the processor is less than sixty seconds and can be as low as 30 seconds, if not less. A rapid startup time is achieved by either igniting or allowing a small mixture of air and fuel to react over and warm up the catalyst of an autothermal reformer (ATR). The ATR then produces combustible gases to be subsequently oxidized on and simultaneously warm up water-gas shift zone catalysts. After normal operating temperature has been achieved, the proportion of air included with the fuel is greatly diminished.

Sentinel-2 Level 2A Prototype Processor: Architecture, Algorithms And First Results

NASA Astrophysics Data System (ADS)

Muller-Wilm, Uwe; Louis, Jerome; Richter, Rudolf; Gascon, Ferran; Niezette, Marc

2013-12-01

Sen2Core is a prototype processor for Sentinel-2 Level 2A product processing and formatting. The processor is developed for and with ESA and performs the tasks of Atmospheric Correction and Scene Classification of Level 1C input data. Level 2A outputs are: Bottom-Of- Atmosphere (BOA) corrected reflectance images, Aerosol Optical Thickness-, Water Vapour-, Scene Classification maps and Quality indicators, including cloud and snow probabilities. The Level 2A Product Formatting performed by the processor follows the specification of the Level 1C User Product.

Multithreading in vector processors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

Hardware multiplier processor

DOEpatents

Pierce, Paul E.

1986-01-01

A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

Hardware multiplier processor

DOEpatents

Pierce, P.E.

A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

Results of the Alternative Water Processor Test, A Novel Technology for Exploration Wastewater Remediation

NASA Technical Reports Server (NTRS)

Vega, Leticia; Meyer, Caitlin

2016-01-01

Biologically-based water recovery systems are a regenerative, low energy alternative to physiochemical processes to reclaim water from wastewater. This paper summarizes the results of the Alternative Water Processor (AWP) test conducted over one year. The AWP recovered 90% of water from four crewmembers using (4) membrane aerated bioreactors (MABRs) to remove carbon and nitrogen from an exploration mission wastewater, including urine, hygiene, laundry and humidity condensate. Downstream, a coupled forward and reverse osmosis system removed large organics and inorganic salts from the biological system effluent. The system exceeded the overall objectives of the test by recovering 90% of the influent wastewater processed and a 29% reduction of consumables from the current state of the art water recovery system on the International Space Station (ISS). However the biological system fell short of its test goals, failing to remove 75% and 90% of the influent ammonium and organic carbon, respectively. Despite not meeting its test goals, the BWP demonstrated the feasibility of an attached-growth biological system for simultaneous nitrification and denitrification, an innovative, volume and consumable-saving design that doesn't require toxic pretreatment. This paper will explain the reasons for this and will discuss steps to optimize each subsystem to increase effluent quality from the MABRs and the FOST to advance the system.

Results of the Alternative Water Processor Test, A Novel Technology for Exploration Wastewater Remediation

NASA Technical Reports Server (NTRS)

Vega, Leticia; Meyer, Caitlin

2015-01-01

Biologically-based water recovery systems are a regenerative, low energy alternative to physiochemical processes to reclaim water from wastewater. This paper summarizes the results of the Alternative Water Processor (AWP) test conducted over one year. The AWP recovered 90% of water from four crewmembers using (4) membrane aerated bioreactors (MABRs) to remove carbon and nitrogen from an exploration mission wastewater, including urine, hygiene, laundry and humidity condensate. Downstream, a coupled forward and reverse osmosis system removed large organics and inorganic salts from the biological system effluent. The system exceeded the overall objectives of the test by recovering 90% of the influent wastewater processed and a 29% reduction of consumables from the current state of the art water recovery system on the International Space Station (ISS). However the biological system fell short of its test goals, failing to remove 75% and 90% of the influent ammonium and organic carbon, respectively. Despite not meeting its test goals, the BWP demonstrated the feasibility of an attachedgrowth biological system for simultaneous nitrification and denitrification, an innovative, volume and consumable-saving design that doesn't require toxic pretreatment. This paper will explain the reasons for this and will discuss steps to optimize each subsystem to increase effluent quality from the MABRs and the FOST to advance the system.

Miniature Fuel Processors for Portable Fuel Cell Power Supplies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holladay, Jamie D.; Jones, Evan O.; Palo, Daniel R.

2003-06-02

Miniature and micro-scale fuel processors are discussed. The enabling technologies for these devices are the novel catalysts and the micro-technology-based designs. The novel catalyst allows for methanol reforming at high gas hourly space velocities of 50,000 hr-1 or higher, while maintaining a carbon monoxide levels at 1% or less. The micro-technology-based designs enable the devices to be extremely compact and lightweight. The miniature fuel processors can nominally provide between 25-50 watts equivalent of hydrogen which is ample for soldier or personal portable power supplies. The integrated processors have a volume less than 50 cm3, a mass less than 150 grams,more » and thermal efficiencies of up to 83%. With reasonable assumptions on fuel cell efficiencies, anode gas and water management, parasitic power loss, etc., the energy density was estimated at 1700 Whr/kg. The miniature processors have been demonstrated with a carbon monoxide clean-up method and a fuel cell stack. The micro-scale fuel processors have been designed to provide up to 0.3 watt equivalent of power with efficiencies over 20%. They have a volume of less than 0.25 cm3 and a mass of less than 1 gram.« less

Array processor architecture connection network

NASA Technical Reports Server (NTRS)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1982-01-01

A connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors. The connection network includes a plurality of switching elements interposed between the processor array and the memory modules array in an Omega networking architecture. Each switching element includes a first and a second processor side port, a first and a second memory module side port, and control logic circuitry for providing data connections between the first and second processor ports and the first and second memory module ports. The control logic circuitry includes strobe logic for examining data arriving at the first and the second processor ports to indicate when the data arriving is requesting data from a requesting processor to a requested memory module. Further, connection circuitry is associated with the strobe logic for examining requesting data arriving at the first and the second processor ports for providing a data connection therefrom to the first and the second memory module ports in response thereto when the data connection so provided does not conflict with a pre-established data connection currently in use.

Processor register error correction management

DOEpatents

Bose, Pradip; Cher, Chen-Yong; Gupta, Meeta S.

2016-12-27

Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

NASA Astrophysics Data System (ADS)

Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

2017-11-01

Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

40 CFR 791.45 - Processors.

Code of Federal Regulations, 2010 CFR

2010-07-01

...) When a test rule or subsequent Federal Register notice pertaining to a test rule expressly obligates processors as well as manufacturers to assume direct testing and data reimbursement responsibilities. (2... processors voluntarily agree to reimburse manufacturers for a portion of test costs. Only those processors...

Nanoscale water condensation on click-functionalized self-assembled monolayers.

PubMed

James, Michael; Ciampi, Simone; Darwish, Tamim A; Hanley, Tracey L; Sylvester, Sven O; Gooding, J Justin

2011-09-06

We have examined the nanoscale adsorption of molecular water under ambient conditions onto a series of well-characterized functionalized surfaces produced by Cu(I)-catalyzed alkyne-azide cycloaddition (CuAAC or "click") reactions on alkyne-terminated self-assembled monolayers on silicon. Water contact angle (CA) measurements reveal a range of macroscopic hydrophilicity that does not correlate with the tendency of these surfaces to adsorb water at the molecular level. X-ray reflectometry has been used to follow the kinetics of water adsorption on these "click"-functionalized surfaces, and also shows that dense continuous molecular water layers are formed over 30 h. For example, a highly hydrophilic surface, functionalized by an oligo(ethylene glycol) moiety (with a CA = 34°) showed 2.9 Å of adsorbed water after 30 h, while the almost hydrophobic underlying alkyne-terminated monolayer (CA = 84°) showed 5.6 Å of adsorbed water over the same period. While this study highlights the capacity of X-ray reflectometry to study the structure of adsorbed water on these surfaces, it should also serve as a warning for those intending to characterize self-assembled monolayers and functionalized surfaces to avoid contamination by even trace amounts of water vapor. Moreover, contact angle measurements alone cannot be relied upon to predict the likely degree of moisture uptake on such surfaces. © 2011 American Chemical Society

Electromagnetic compatibility test report for the tethered satellite data acquisition and control assembly

NASA Astrophysics Data System (ADS)

Hoskins, Douglas; Snead, Robert

1988-05-01

This report details the results of an electromagnetic compatibility test on the SCI Systems Data Acquisition and Control Assembly (DACA). This assembly is an electronic processor which controls the central communication link from the Tethered Satellite System (TSS) to the Space Transportation System Orbiter Space Shuttle.

Controlling water evaporation through self-assembly

PubMed Central

Roger, Kevin; Liebi, Marianne; Heimdal, Jimmy; Pham, Quoc Dat; Sparr, Emma

2016-01-01

Water evaporation concerns all land-living organisms, as ambient air is dryer than their corresponding equilibrium humidity. Contrarily to plants, mammals are covered with a skin that not only hinders evaporation but also maintains its rate at a nearly constant value, independently of air humidity. Here, we show that simple amphiphiles/water systems reproduce this behavior, which suggests a common underlying mechanism originating from responding self-assembly structures. The composition and structure gradients arising from the evaporation process were characterized using optical microscopy, infrared microscopy, and small-angle X-ray scattering. We observed a thin and dry outer phase that responds to changes in air humidity by increasing its thickness as the air becomes dryer, which decreases its permeability to water, thus counterbalancing the increase in the evaporation driving force. This thin and dry outer phase therefore shields the systems from humidity variations. Such a feedback loop achieves a homeostatic regulation of water evaporation. PMID:27573848

Controlling water evaporation through self-assembly.

PubMed

Roger, Kevin; Liebi, Marianne; Heimdal, Jimmy; Pham, Quoc Dat; Sparr, Emma

2016-09-13

Water evaporation concerns all land-living organisms, as ambient air is dryer than their corresponding equilibrium humidity. Contrarily to plants, mammals are covered with a skin that not only hinders evaporation but also maintains its rate at a nearly constant value, independently of air humidity. Here, we show that simple amphiphiles/water systems reproduce this behavior, which suggests a common underlying mechanism originating from responding self-assembly structures. The composition and structure gradients arising from the evaporation process were characterized using optical microscopy, infrared microscopy, and small-angle X-ray scattering. We observed a thin and dry outer phase that responds to changes in air humidity by increasing its thickness as the air becomes dryer, which decreases its permeability to water, thus counterbalancing the increase in the evaporation driving force. This thin and dry outer phase therefore shields the systems from humidity variations. Such a feedback loop achieves a homeostatic regulation of water evaporation.

Water ordering controls the dynamic equilibrium of micelle-fibre formation in self-assembly of peptide amphiphiles.

PubMed

Deshmukh, Sanket A; Solomon, Lee A; Kamath, Ganesh; Fry, H Christopher; Sankaranarayanan, Subramanian K R S

2016-08-24

Understanding the role of water in governing the kinetics of the self-assembly processes of amphiphilic peptides remains elusive. Here, we use a multistage atomistic-coarse-grained approach, complemented by circular dichroism/infrared spectroscopy and dynamic light scattering experiments to highlight the dual nature of water in driving the self-assembly of peptide amphiphiles (PAs). We show computationally that water cage formation and breakage near the hydrophobic groups control the fusion dynamics and aggregation of PAs in the micellar stage. Simulations also suggest that enhanced structural ordering of vicinal water near the hydrophilic amino acids shifts the equilibrium towards the fibre phase and stimulates structure and order during the PA assembly into nanofibres. Experiments validate our simulation findings; the measured infrared O-H bond stretching frequency is reminiscent of an ice-like bond which suggests that the solvated water becomes increasingly ordered with time in the assembled peptide network, thus shedding light on the role of water in a self-assembly process.

Reversible Self-Assembly of Water-Soluble Gold(I) Complexes.

PubMed

Aguiló, Elisabet; Moro, Artur J; Gavara, Raquel; Alfonso, Ignacio; Pérez, Yolanda; Zaccaria, Francesco; Guerra, Célia Fonseca; Malfois, Marc; Baucells, Clara; Ferrer, Montserrat; Lima, João Carlos; Rodríguez, Laura

2018-02-05

The reaction of the gold polymers containing bipyridyl and terpyridyl units, [Au(C≡CC 15 H 10 N 3 )] n and [Au(C≡CC 10 H 7 N 2 )] n , with the water-soluble phosphines 1,3,5-triaza-7-phosphatricyclo[3.3.1.13.7]decane and 3,7-diacetyl-1,3,7-triaza-5-phosphabicyclo[3.3.1]nonane gives rise to the formation of four gold(I) alkynyl complexes that self-assemble in water (H 2 O) and dimethyl sulfoxide (DMSO), through different intermolecular interactions, with an impact on the observed luminescence displayed by the supramolecular assemblies. A detailed analysis carried out by NMR studies performed in different DMSO/deuterated H 2 O mixtures indicates the presence of two different assembly modes in the aggregates: (i) chain assemblies, which are based mainly on aurophilic interactions, and (ii) stacked assemblies, which are based on Au···π and π···π interactions. These different supramolecular environments can also be detected by their intrinsic optical properties (differences in absorption and emission spectra) and are predicted by the changes in the relative binding energy from density functional theory calculations carried out in DMSO and H 2 O. Small-angle X-ray scattering (SAXS) experiments performed in the same mixture of solvents are in agreement with the formation of aggregates in all cases. The aromatic units chosen, bipyridine and terpyridine, allow the use of external stimuli to reversibly change the aggregation state of the supramolecular assemblies. Interaction with the Zn 2+ cation is observed to disassemble the aggregates, while encapsulating agents competing for Zn 2+ complexation revert the process to the aggregation stage, as verified by SAXS and NMR. The adaptive nature of the supramolecular assemblies to the metal-ion content is accompanied by significant changes in the absorption and emission spectra, signaling the aggregation state and also the content on Zn 2+ .

Optical Associative Processors For Visual Perception"

NASA Astrophysics Data System (ADS)

Casasent, David; Telfer, Brian

1988-05-01

We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

Design of an integrated fuel processor for residential PEMFCs applications

NASA Astrophysics Data System (ADS)

Seo, Yu Taek; Seo, Dong Joo; Jeong, Jin Hyeok; Yoon, Wang Lai

KIER has been developing a novel fuel processing system to provide hydrogen rich gas to residential PEMFCs system. For the effective design of a compact hydrogen production system, each unit process for steam reforming and water gas shift, has a steam generator and internal heat exchangers which are thermally and physically integrated into a single packaged hardware system. The newly designed fuel processor (prototype II) showed a thermal efficiency of 78% as a HHV basis with methane conversion of 89%. The preferential oxidation unit with two staged cascade reactors, reduces, the CO concentration to below 10 ppm without complicated temperature control hardware, which is the prerequisite CO limit for the PEMFC stack. After we achieve the initial performance of the fuel processor, partial load operation was carried out to test the performance and reliability of the fuel processor at various loads. The stability of the fuel processor was also demonstrated for three successive days with a stable composition of product gas and thermal efficiency. The CO concentration remained below 10 ppm during the test period and confirmed the stable performance of the two-stage PrOx reactors.

Unmixed fuel processors and methods for using the same

DOEpatents

Kulkarni, Parag Prakash; Cui, Zhe

2010-08-24

Disclosed herein are unmixed fuel processors and methods for using the same. In one embodiment, an unmixed fuel processor comprises: an oxidation reactor comprising an oxidation portion and a gasifier, a CO.sub.2 acceptor reactor, and a regeneration reactor. The oxidation portion comprises an air inlet, effluent outlet, and an oxygen transfer material. The gasifier comprises a solid hydrocarbon fuel inlet, a solids outlet, and a syngas outlet. The CO.sub.2 acceptor reactor comprises a water inlet, a hydrogen outlet, and a CO.sub.2 sorbent, and is configured to receive syngas from the gasifier. The regeneration reactor comprises a water inlet and a CO.sub.2 stream outlet. The regeneration reactor is configured to receive spent CO.sub.2 adsorption material from the gasification reactor and to return regenerated CO.sub.2 adsorption material to the gasification reactor, and configured to receive oxidized oxygen transfer material from the oxidation reactor and to return reduced oxygen transfer material to the oxidation reactor.

Water Ordering Controls the Dynamic Equilibrium of Micelle-Fiber Formation in Self-Assembly of Peptide Amphiphiles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deshmukh, Sanket; Solomon, Lee A.; Kamath, Ganesh

Understanding the role of water in governing the kinetics of the self-assembly processes of amphiphilic peptides has still remained elusive. Here, using a multi-stage atomistic-coarse-grained approach, complemented by circular dichroism/infra-red spectroscopy and dynamic light scattering experiments, we highlight the dual nature of water in dictating the mechanism and dynamics of self-assembly of peptide amphiphiles (PAs). Our computational study shows that (i) Water cage formation and breakage near the hydrophobic groups controls the fusion dynamics and aggregation of PAs in the micellar stage, and (ii) Enhanced structural ordering of vicinal water near the hydrophilic amino acids shifts the equilibrium towards themore » fiber phase and stimulates structure and order in the PAs when they assemble into a hexagonal nanofiber architecture. Finally, spectroscopy and microscopy studies authenticate our computational observation that water ordering near the PAs increases with increase in time. The measured infra-red O-H bond stretch frequency reminiscent of ice-like suggests that the solvated water becomes increasingly solid-like with increased structural order in the assembled peptide network – thus shedding light on the role of water in a self-assembly process.« less

Water Ordering Controls the Dynamic Equilibrium of Micelle-Fiber Formation in Self-Assembly of Peptide Amphiphiles

DOE PAGES

Deshmukh, Sanket; Solomon, Lee A.; Kamath, Ganesh; ...

2016-08-24

Understanding the role of water in governing the kinetics of the self-assembly processes of amphiphilic peptides has still remained elusive. Here, using a multi-stage atomistic-coarse-grained approach, complemented by circular dichroism/infra-red spectroscopy and dynamic light scattering experiments, we highlight the dual nature of water in dictating the mechanism and dynamics of self-assembly of peptide amphiphiles (PAs). Our computational study shows that (i) Water cage formation and breakage near the hydrophobic groups controls the fusion dynamics and aggregation of PAs in the micellar stage, and (ii) Enhanced structural ordering of vicinal water near the hydrophilic amino acids shifts the equilibrium towards themore » fiber phase and stimulates structure and order in the PAs when they assemble into a hexagonal nanofiber architecture. Finally, spectroscopy and microscopy studies authenticate our computational observation that water ordering near the PAs increases with increase in time. The measured infra-red O-H bond stretch frequency reminiscent of ice-like suggests that the solvated water becomes increasingly solid-like with increased structural order in the assembled peptide network – thus shedding light on the role of water in a self-assembly process.« less

Implementation of kernels on the Maestro processor

NASA Astrophysics Data System (ADS)

Suh, Jinwoo; Kang, D. I. D.; Crago, S. P.

Currently, most microprocessors use multiple cores to increase performance while limiting power usage. Some processors use not just a few cores, but tens of cores or even 100 cores. One such many-core microprocessor is the Maestro processor, which is based on Tilera's TILE64 processor. The Maestro chip is a 49-core, general-purpose, radiation-hardened processor designed for space applications. The Maestro processor, unlike the TILE64, has a floating point unit (FPU) in each core for improved floating point performance. The Maestro processor runs at 342 MHz clock frequency. On the Maestro processor, we implemented several widely used kernels: matrix multiplication, vector add, FIR filter, and FFT. We measured and analyzed the performance of these kernels. The achieved performance was up to 5.7 GFLOPS, and the speedup compared to single tile was up to 49 using 49 tiles.

Compact gasoline fuel processor for passenger vehicle APU

NASA Astrophysics Data System (ADS)

Severin, Christopher; Pischinger, Stefan; Ogrzewalla, Jürgen

Due to the increasing demand for electrical power in today's passenger vehicles, and with the requirements regarding fuel consumption and environmental sustainability tightening, a fuel cell-based auxiliary power unit (APU) becomes a promising alternative to the conventional generation of electrical energy via internal combustion engine, generator and battery. It is obvious that the on-board stored fuel has to be used for the fuel cell system, thus, gasoline or diesel has to be reformed on board. This makes the auxiliary power unit a complex integrated system of stack, air supply, fuel processor, electrics as well as heat and water management. Aside from proving the technical feasibility of such a system, the development has to address three major barriers:start-up time, costs, and size/weight of the systems. In this paper a packaging concept for an auxiliary power unit is presented. The main emphasis is placed on the fuel processor, as good packaging of this large subsystem has the strongest impact on overall size. The fuel processor system consists of an autothermal reformer in combination with water-gas shift and selective oxidation stages, based on adiabatic reactors with inter-cooling. The configuration was realized in a laboratory set-up and experimentally investigated. The results gained from this confirm a general suitability for mobile applications. A start-up time of 30 min was measured, while a potential reduction to 10 min seems feasible. An overall fuel processor efficiency of about 77% was measured. On the basis of the know-how gained by the experimental investigation of the laboratory set-up a packaging concept was developed. Using state-of-the-art catalyst and heat exchanger technology, the volumes of these components are fixed. However, the overall volume is higher mainly due to mixing zones and flow ducts, which do not contribute to the chemical or thermal function of the system. Thus, the concept developed mainly focuses on minimization of those

Neurovision processor for designing intelligent sensors

NASA Astrophysics Data System (ADS)

Gupta, Madan M.; Knopf, George K.

1992-03-01

A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

Parallel processor for real-time structural control

NASA Astrophysics Data System (ADS)

Tise, Bert L.

1993-07-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-to-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection to host computer, parallelizing code generator, and look- up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating- point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An OpenWindows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.

Parallel processor for real-time structural control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tise, B.L.

1992-01-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection tomore » host computer, parallelizing code generator, and look-up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating-point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An Open Windows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.« less

Hydrogen bonding directed self-assembly of small-molecule amphiphiles in water.

PubMed

Xu, Jiang-Fei; Niu, Li-Ya; Chen, Yu-Zhe; Wu, Li-Zhu; Tung, Chen-Ho; Yang, Qing-Zheng

2014-08-01

Compounds comprising one or two quadruply hydrogen bonding units, 2-ureido-4[1H]-pyrimidinone (UPy) and tris(tetraethylene glycol monomethyl ether) moieties, were reported to form highly stable hydrogen-bonded assemblies in water. Compound 1, containing one UPy, assembles into vesicles, and compound 2, containing two UPy units, forms micelles. The aggregates disassemble reversibly when the solution pH is raised to 9.0 or above. The results demonstrate the utility of hydrogen bonding to direct the self-assembly of small-molecule building blocks in aqueous media.

Lenslet array processors.

PubMed

Glaser, I

1982-04-01

By combining a lenslet array with masks it is possible to obtain a noncoherent optical processor capable of computing in parallel generalized 2-D discrete linear transformations. We present here an analysis of such lenslet array processors (LAP). The effect of several errors, including optical aberrations, diffraction, vignetting, and geometrical and mask errors, are calculated, and guidelines to optical design of LAP are derived. Using these results, both ultimate and practical performances of LAP are compared with those of competing techniques.

Rectangular Array Of Digital Processors For Planning Paths

NASA Technical Reports Server (NTRS)

Kemeny, Sabrina E.; Fossum, Eric R.; Nixon, Robert H.

1993-01-01

Prototype 24 x 25 rectangular array of asynchronous parallel digital processors rapidly finds best path across two-dimensional field, which could be patch of terrain traversed by robotic or military vehicle. Implemented as single-chip very-large-scale integrated circuit. Excepting processors on edges, each processor communicates with four nearest neighbors along paths representing travel to north, south, east, and west. Each processor contains delay generator in form of 8-bit ripple counter, preset to 1 of 256 possible values. Operation begins with choice of processor representing starting point. Transmits signals to nearest neighbor processors, which retransmits to other neighboring processors, and process repeats until signals propagated across entire field.

Optimal processor assignment for pipeline computations

NASA Technical Reports Server (NTRS)

Nicol, David M.; Simha, Rahul; Choudhury, Alok N.; Narahari, Bhagirath

1991-01-01

The availability of large scale multitasked parallel architectures introduces the following processor assignment problem for pipelined computations. Given a set of tasks and their precedence constraints, along with their experimentally determined individual responses times for different processor sizes, find an assignment of processor to tasks. Two objectives are of interest: minimal response given a throughput requirement, and maximal throughput given a response time requirement. These assignment problems differ considerably from the classical mapping problem in which several tasks share a processor; instead, it is assumed that a large number of processors are to be assigned to a relatively small number of tasks. Efficient assignment algorithms were developed for different classes of task structures. For a p processor system and a series parallel precedence graph with n constituent tasks, an O(np2) algorithm is provided that finds the optimal assignment for the response time optimization problem; it was found that the assignment optimizing the constrained throughput in O(np2log p) time. Special cases of linear, independent, and tree graphs are also considered.

Automobile Crash Sensor Signal Processor

DOT National Transportation Integrated Search

1973-11-01

The crash sensor signal processor described interfaces between an automobile-installed doppler radar and an air bag activating solenoid or equivalent electromechanical device. The processor utilizes both digital and analog techniques to produce an ou...

Power estimation on functional level for programmable processors

NASA Astrophysics Data System (ADS)

Schneider, M.; Blume, H.; Noll, T. G.

2004-05-01

In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW)-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA). Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW) -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA). This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated the input

Self-assembly of short amyloidogenic peptides at the air-water interface.

PubMed

Chaudhary, Nitin; Nagaraj, Ramakrishnan

2011-08-01

Short peptide stretches in amyloidogenic proteins can form amyloid fibrils in vitro and have served as good models for studying amyloid fibril formation. Recently, these amyloidogenic peptides have gained considerable attention, as non-amyloid ordered structures can be obtained from these peptides by carefully tuning the conditions of self-assembly, especially pH, temperature and presence of organic solvents. We have examined the effect of surface pressure on the self-assembled structures of two amyloidogenic peptides, Pβ(2)m (Ac-DWSFYLLYYTEFT-am) and AcPHF6 (Ac-VQIVYK-am) at the air-water interface when deposited from different solvents. Both the peptides are surface-active and form Thioflavin T (ThT) positive structures at the air-water interface. There is considerable hysteresis in the compression and expansion isotherms, suggesting the occurrence of structural rearrangements during compression. Preformed Pβ(2)m fibrillar structures at the air-water interface are disrupted as peptide is compressed to lower molecular areas but restored if the film is expanded, suggesting that the process is reversible. AcPHF6, on the other hand, shows largely sheet-like structures at lower molecular areas. The solvents used for dissolution of the peptides appear to influence the nature of the aggregates formed. Our results show that like hydrostatic pressure, surface pressure can also be utilized for modulating the self-assembly of the amyloidogenic and self-assembling peptides. Copyright © 2011 Elsevier Inc. All rights reserved.

A light hydrocarbon fuel processor producing high-purity hydrogen

NASA Astrophysics Data System (ADS)

Löffler, Daniel G.; Taylor, Kyle; Mason, Dylan

thermal efficiency is better than 67% operating at full load. This fuel processor has been integrated with a 5-kW fuel cell producing electricity and hot water.

Processor architecture for airborne SAR systems

NASA Technical Reports Server (NTRS)

Glass, C. M.

1983-01-01

Digital processors for spaceborne imaging radars and application of the technology developed for airborne SAR systems are considered. Transferring algorithms and implementation techniques from airborne to spaceborne SAR processors offers obvious advantages. The following topics are discussed: (1) a quantification of the differences in processing algorithms for airborne and spaceborne SARs; and (2) an overview of three processors for airborne SAR systems.

Analog Processor To Solve Optimization Problems

NASA Technical Reports Server (NTRS)

Duong, Tuan A.; Eberhardt, Silvio P.; Thakoor, Anil P.

1993-01-01

Proposed analog processor solves "traveling-salesman" problem, considered paradigm of global-optimization problems involving routing or allocation of resources. Includes electronic neural network and auxiliary circuitry based partly on concepts described in "Neural-Network Processor Would Allocate Resources" (NPO-17781) and "Neural Network Solves 'Traveling-Salesman' Problem" (NPO-17807). Processor based on highly parallel computing solves problem in significantly less time.

Orientation-controlled parallel assembly at the air-water interface

NASA Astrophysics Data System (ADS)

Park, Kwang Soon; Hao Hoo, Ji; Baskaran, Rajashree; Böhringer, Karl F.

2012-10-01

This paper presents an experimental and theoretical study with statistical analysis of a high-yield, orientation-specific fluidic self-assembly process on a preprogrammed template. We demonstrate self-assembly of thin (less than few hundred microns in thickness) parts, which is vital for many applications in miniaturized platforms but problematic for today's pick-and-place robots. The assembly proceeds row-by-row as the substrate is pulled up through an air-water interface. Experiments and analysis are presented with an emphasis on the combined effect of controlled surface waves and magnetic force. For various gap values between a magnet and Ni-patterned parts, magnetic force distributions are generated using Monte Carlo simulation and employed to predict assembly yield. An analysis of these distributions shows that a gradual decline in yield following the probability density function can be expected with degrading conditions. The experimentally determined critical magnetic force is in good agreement with a derived value from a model of competing forces acting on a part. A general set of design guidelines is also presented from the developed model and experimental data.

Enabling Future Robotic Missions with Multicore Processors

NASA Technical Reports Server (NTRS)

Powell, Wesley A.; Johnson, Michael A.; Wilmot, Jonathan; Some, Raphael; Gostelow, Kim P.; Reeves, Glenn; Doyle, Richard J.

2011-01-01

Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

Ultra-Reliable Digital Avionics (URDA) processor

NASA Astrophysics Data System (ADS)

Branstetter, Reagan; Ruszczyk, William; Miville, Frank

1994-10-01

Texas Instruments Incorporated (TI) developed the URDA processor design under contract with the U.S. Air Force Wright Laboratory and the U.S. Army Night Vision and Electro-Sensors Directorate. TI's approach couples advanced packaging solutions with advanced integrated circuit (IC) technology to provide a high-performance (200 MIPS/800 MFLOPS) modular avionics processor module for a wide range of avionics applications. TI's processor design integrates two Ada-programmable, URDA basic processor modules (BPM's) with a JIAWG-compatible PiBus and TMBus on a single F-22 common integrated processor-compatible form-factor SEM-E avionics card. A separate, high-speed (25-MWord/second 32-bit word) input/output bus is provided for sensor data. Each BPM provides a peak throughput of 100 MIPS scalar concurrent with 400-MFLOPS vector processing in a removable multichip module (MCM) mounted to a liquid-flowthrough (LFT) core and interfacing to a processor interface module printed wiring board (PWB). Commercial RISC technology coupled with TI's advanced bipolar complementary metal oxide semiconductor (BiCMOS) application specific integrated circuit (ASIC) and silicon-on-silicon packaging technologies are used to achieve the high performance in a miniaturized package. A Mips R4000-family reduced instruction set computer (RISC) processor and a TI 100-MHz BiCMOS vector coprocessor (VCP) ASIC provide, respectively, the 100 MIPS of a scalar processor throughput and 400 MFLOPS of vector processing throughput for each BPM. The TI Aladdim ASIC chipset was developed on the TI Aladdin Program under contract with the U.S. Army Communications and Electronics Command and was sponsored by the Advanced Research Projects Agency with technical direction from the U.S. Army Night Vision and Electro-Sensors Directorate.

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2011 CFR

2011-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2010 CFR

2010-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2014 CFR

2014-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2013 CFR

2013-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2012 CFR

2012-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

Trace Water as Prominent Factor to Induce Peptide Self-Assembly: Dynamic Evolution and Governing Interactions in Ionic Liquids.

PubMed

Wang, Juan; Yuan, Chengqian; Han, Yuchun; Wang, Yilin; Liu, Xiaomin; Zhang, Suojiang; Yan, Xuehai

2017-11-01

The interaction between water and biomolecules including peptides is of critical importance for forming high-level architectures and triggering life's functions. However, the bulk aqueous environment has limitations in detecting the kinetics and mechanisms of peptide self-assembly, especially relating to interactions of trace water. With ionic liquids (ILs) as a nonconventional medium, herein, it is discovered that trace amounts of water play a decisive role in triggering self-assembly of a biologically derived dipeptide. ILs provide a suitable nonaqueous environment, enabling us to mediate water content and follow the dynamic evolution of peptide self-assembly. The trace water is found to be involved in the assembly process of dipeptide, especially leading to the formation of stable noncovalent dipeptide oligomers in the early stage of nucleation, as evident by both experimental studies and theoretical simulations. The thermodynamics of the growth process is mainly governed by a synergistic effect of hydrophobic interaction and hydrogen bonds. Each step of assembly presents a different trend in thermodynamic energy. The dynamic evolution of assembly process can be efficiently mediated by changing trace water content. The decisive role of trace water in triggering and mediating self-assembly of biomolecules provides a new perspective in understanding supramolecular chemistry and molecular self-organization in biology. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Communications systems and methods for subsea processors

DOEpatents

Gutierrez, Jose; Pereira, Luis

2016-04-26

A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. A shared communications bus may interconnect the subsea processor and underwater components and the subsea processor and a surface or onshore network. The shared communications bus may be operated according to a time division multiple access (TDMA) scheme.

Impact of diet on the design of waste processors in CELSS

NASA Technical Reports Server (NTRS)

Waleh, Ahmad; Kanevsky, Valery; Nguyen, Thoi K.; Upadhye, Ravi; Wydeven, Theodore

1991-01-01

The preliminary results of a design analysis for a waste processor which employs existing technologies and takes into account the constraints of human diet are presented. The impact of diet is determined by using a model and an algorithm developed for the control and management of diet in a Controlled Ecological Life Support System (CELSS). A material and energy balance model for thermal oxidation of waste is developed which is consistent with both physical/chemical methods of incineration and supercritical water oxidation. The two models yield quantitative analysis of the diet and waste streams and the specific design parameters for waste processors, respectively. The results demonstrate that existing technologies can meet the demands of waste processing, but the choice and design of the processors or processing methods will be sensitive to the constraints of diet. The numerical examples are chosen to display the nature and extent of the gap in the available experiment information about CELSS requirements.

Ray Meta: scalable de novo metagenome assembly and profiling

PubMed Central

2012-01-01

Voluminous parallel sequencing datasets, especially metagenomic experiments, require distributed computing for de novo assembly and taxonomic profiling. Ray Meta is a massively distributed metagenome assembler that is coupled with Ray Communities, which profiles microbiomes based on uniquely-colored k-mers. It can accurately assemble and profile a three billion read metagenomic experiment representing 1,000 bacterial genomes of uneven proportions in 15 hours with 1,024 processor cores, using only 1.5 GB per core. The software will facilitate the processing of large and complex datasets, and will help in generating biological insights for specific environments. Ray Meta is open source and available at http://denovoassembler.sf.net. PMID:23259615

Parallel processor-based raster graphics system architecture

DOEpatents

Littlefield, Richard J.

1990-01-01

An apparatus for generating raster graphics images from the graphics command stream includes a plurality of graphics processors connected in parallel, each adapted to receive any part of the graphics command stream for processing the command stream part into pixel data. The apparatus also includes a frame buffer for mapping the pixel data to pixel locations and an interconnection network for interconnecting the graphics processors to the frame buffer. Through the interconnection network, each graphics processor may access any part of the frame buffer concurrently with another graphics processor accessing any other part of the frame buffer. The plurality of graphics processors can thereby transmit concurrently pixel data to pixel locations in the frame buffer.

Multimode power processor

DOEpatents

O'Sullivan, G.A.; O'Sullivan, J.A.

1999-07-27

In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources. 31 figs.

Multimode power processor

DOEpatents

O'Sullivan, George A.; O'Sullivan, Joseph A.

1999-01-01

In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

PixonVision real-time video processor

NASA Astrophysics Data System (ADS)

Puetter, R. C.; Hier, R. G.

2007-09-01

PixonImaging LLC and DigiVision, Inc. have developed a real-time video processor, the PixonVision PV-200, based on the patented Pixon method for image deblurring and denoising, and DigiVision's spatially adaptive contrast enhancement processor, the DV1000. The PV-200 can process NTSC and PAL video in real time with a latency of 1 field (1/60 th of a second), remove the effects of aerosol scattering from haze, mist, smoke, and dust, improve spatial resolution by up to 2x, decrease noise by up to 6x, and increase local contrast by up to 8x. A newer version of the processor, the PV-300, is now in prototype form and can handle high definition video. Both the PV-200 and PV-300 are FPGA-based processors, which could be spun into ASICs if desired. Obvious applications of these processors include applications in the DOD (tanks, aircraft, and ships), homeland security, intelligence, surveillance, and law enforcement. If developed into an ASIC, these processors will be suitable for a variety of portable applications, including gun sights, night vision goggles, binoculars, and guided munitions. This paper presents a variety of examples of PV-200 processing, including examples appropriate to border security, battlefield applications, port security, and surveillance from unmanned aerial vehicles.

7 CFR 926.13 - Processor.

Code of Federal Regulations, 2014 CFR

2014-01-01

... RECORDKEEPING REQUIREMENTS APPLICABLE TO CRANBERRIES NOT SUBJECT TO THE CRANBERRY MARKETING ORDER § 926.13 Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in... uses such cranberries or concentrate, with or without other ingredients, in the production of a product...

7 CFR 926.13 - Processor.

Code of Federal Regulations, 2013 CFR

2013-01-01

... RECORDKEEPING REQUIREMENTS APPLICABLE TO CRANBERRIES NOT SUBJECT TO THE CRANBERRY MARKETING ORDER § 926.13 Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in... uses such cranberries or concentrate, with or without other ingredients, in the production of a product...

7 CFR 926.13 - Processor.

Code of Federal Regulations, 2011 CFR

2011-01-01

... RECORDKEEPING REQUIREMENTS APPLICABLE TO CRANBERRIES NOT SUBJECT TO THE CRANBERRY MARKETING ORDER § 926.13 Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in... uses such cranberries or concentrate, with or without other ingredients, in the production of a product...

7 CFR 926.13 - Processor.

Code of Federal Regulations, 2012 CFR

2012-01-01

... RECORDKEEPING REQUIREMENTS APPLICABLE TO CRANBERRIES NOT SUBJECT TO THE CRANBERRY MARKETING ORDER § 926.13 Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in... uses such cranberries or concentrate, with or without other ingredients, in the production of a product...

Evaluation of Technologies to Prevent Precipitation During Water Recovery from Urine

NASA Technical Reports Server (NTRS)

Broyan, James L., Jr.; Pickering, Karen D.; Adam, Niklas M.; Mitchell, Julie L.; Anderson, Molly S.; Carter, Layne; Muirhead, Dean; Gazda, Daniel B.

2011-01-01

The International Space Station (ISS) Urine Processor Assembly (UPA) experienced a hardware failure in the Distillation Assembly (DA) in October 2010. Initially the UPA was operated to recover 85% of the water from urine through distillation, concentrating the contaminants in the remaining urine. The DA failed due to precipitation of calcium sulfate (gypsum) which caused a loss of UPA function. The ISS UPA operations have been modified to only recover 70% of the water minimizing gypsum precipitation risk but substantially increasing water resupply needs. This paper describes the feasibility assessment of several technologies (ion exchange, chelating agents, threshold inhibitors, and Lorentz devices) to prevent gypsum precipitation. The feasibility assessment includes the development of assessment methods, chemical modeling, bench top testing, and validation testing in a flight-like ground UPA unit. Ion exchange technology has been successfully demonstrated and has been recommended for further development. The incorporation of the selected technology will enable water recovery to be increased from 70% back to the original 85% and improve the ISS water balance.

Fuel assembly for the production of tritium in light water reactors

DOEpatents

Cawley, W.E.; Trapp, T.J.

1983-06-10

A nuclear fuel assembly is described for producing tritium in a light water moderated reactor. The assembly consists of two intermeshing arrays of subassemblies. The first subassemblies comprise concentric annular elements of an outer containment tube, an annular target element, an annular fuel element, and an inner neutron spectrums shifting rod. The second subassemblies comprise an outer containment tube and an inner rod of either fuel, target, or neutron spectrum shifting neutral.

Fuel assembly for the production of tritium in light water reactors

DOEpatents

Cawley, William E.; Trapp, Turner J.

1985-01-01

A nuclear fuel assembly is described for producing tritium in a light water moderated reactor. The assembly consists of two intermeshing arrays of subassemblies. The first subassemblies comprise concentric annular elements of an outer containment tube, an annular target element, an annular fuel element, and an inner neutron spectrums shifting rod. The second subassemblies comprise an outer containment tube and an inner rod of either fuel, target, or neutron spectrum shifting neutral.

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 9 2013-01-01 2013-01-01 false Fluid milk processor. 1160.108 Section 1160.108... AGREEMENTS AND ORDERS; MILK), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 9 2012-01-01 2012-01-01 false Fluid milk processor. 1160.108 Section 1160.108... Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 9 2014-01-01 2013-01-01 true Fluid milk processor. 1160.108 Section 1160.108... AGREEMENTS AND ORDERS; MILK), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 9 2010-01-01 2009-01-01 true Fluid milk processor. 1160.108 Section 1160.108... Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 9 2011-01-01 2011-01-01 false Fluid milk processor. 1160.108 Section 1160.108... Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

Development of compact fuel processor for 2 kW class residential PEMFCs

NASA Astrophysics Data System (ADS)

Seo, Yu Taek; Seo, Dong Joo; Jeong, Jin Hyeok; Yoon, Wang Lai

Korea Institute of Energy Research (KIER) has been developing a novel fuel processing system to provide hydrogen rich gas to residential polymer electrolyte membrane fuel cells (PEMFCs) cogeneration system. For the effective design of a compact hydrogen production system, the unit processes of steam reforming, high and low temperature water gas shift, steam generator and internal heat exchangers are thermally and physically integrated into a packaged hardware system. Several prototypes are under development and the prototype I fuel processor showed thermal efficiency of 73% as a HHV basis with methane conversion of 81%. Recently tested prototype II has been shown the improved performance of thermal efficiency of 76% with methane conversion of 83%. In both prototypes, two-stage PrOx reactors reduce CO concentration less than 10 ppm, which is the prerequisite CO limit condition of product gas for the PEMFCs stack. After confirming the initial performance of prototype I fuel processor, it is coupled with PEMFC single cell to test the durability and demonstrated that the fuel processor is operated for 3 days successfully without any failure of fuel cell voltage. Prototype II fuel processor also showed stable performance during the durability test.

Modeling heterogeneous processor scheduling for real time systems

NASA Technical Reports Server (NTRS)

Leathrum, J. F.; Mielke, R. R.; Stoughton, J. W.

1994-01-01

A new model is presented to describe dataflow algorithms implemented in a multiprocessing system. Called the resource/data flow graph (RDFG), the model explicitly represents cyclo-static processor schedules as circuits of processor arcs which reflect the order that processors execute graph nodes. The model also allows the guarantee of meeting hard real-time deadlines. When unfolded, the model identifies statically the processor schedule. The model therefore is useful for determining the throughput and latency of systems with heterogeneous processors. The applicability of the model is demonstrated using a space surveillance algorithm.

Onboard processor technology review

NASA Technical Reports Server (NTRS)

Benz, Harry F.

1990-01-01

The general need and requirements for the onboard embedded processors necessary to control and manipulate data in spacecraft systems are discussed. The current known requirements are reviewed from a user perspective, based on current practices in the spacecraft development process. The current capabilities of available processor technologies are then discussed, and these are projected to the generation of spacecraft computers currently under identified, funded development. An appraisal is provided for the current national developmental effort.

Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors

NASA Technical Reports Server (NTRS)

Fijany, Amir (Inventor); Bejczy, Antal K. (Inventor)

1994-01-01

In a computer having a large number of single-instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register file units where data is stored. The register files input and output data in synchronism with a minor cycle clock under control of two slave control units controlling the register file units connected to respective ones of the two sets of processor elements. Depending upon which ones of the register file units are enabled to store or transmit data during a particular minor clock cycle, the processor elements within an SIMD processor are connected in rings or in pipeline arrays, and may exchange data with the internal bus or with neighboring SIMD processors through interface units controlled by respective ones of the two slave control units.

A fully reconfigurable photonic integrated signal processor

NASA Astrophysics Data System (ADS)

Liu, Weilin; Li, Ming; Guzzon, Robert S.; Norberg, Erik J.; Parker, John S.; Lu, Mingzhi; Coldren, Larry A.; Yao, Jianping

2016-03-01

Photonic signal processing has been considered a solution to overcome the inherent electronic speed limitations. Over the past few years, an impressive range of photonic integrated signal processors have been proposed, but they usually offer limited reconfigurability, a feature highly needed for the implementation of large-scale general-purpose photonic signal processors. Here, we report and experimentally demonstrate a fully reconfigurable photonic integrated signal processor based on an InP-InGaAsP material system. The proposed photonic signal processor is capable of performing reconfigurable signal processing functions including temporal integration, temporal differentiation and Hilbert transformation. The reconfigurability is achieved by controlling the injection currents to the active components of the signal processor. Our demonstration suggests great potential for chip-scale fully programmable all-optical signal processing.

Fuel processor and method for generating hydrogen for fuel cells

DOEpatents

Ahmed, Shabbir [Naperville, IL; Lee, Sheldon H. D. [Willowbrook, IL; Carter, John David [Bolingbrook, IL; Krumpelt, Michael [Naperville, IL; Myers, Deborah J [Lisle, IL

2009-07-21

A method of producing a H.sub.2 rich gas stream includes supplying an O.sub.2 rich gas, steam, and fuel to an inner reforming zone of a fuel processor that includes a partial oxidation catalyst and a steam reforming catalyst or a combined partial oxidation and stream reforming catalyst. The method also includes contacting the O.sub.2 rich gas, steam, and fuel with the partial oxidation catalyst and the steam reforming catalyst or the combined partial oxidation and stream reforming catalyst in the inner reforming zone to generate a hot reformate stream. The method still further includes cooling the hot reformate stream in a cooling zone to produce a cooled reformate stream. Additionally, the method includes removing sulfur-containing compounds from the cooled reformate stream by contacting the cooled reformate stream with a sulfur removal agent. The method still further includes contacting the cooled reformate stream with a catalyst that converts water and carbon monoxide to carbon dioxide and H.sub.2 in a water-gas-shift zone to produce a final reformate stream in the fuel processor.

ISFET-based sensor signal processor chip design for environment monitoring applications

NASA Astrophysics Data System (ADS)

Chung, Wen-Yaw; Yang, Chung-Huang; Wang, Ming-Ga

2004-12-01

In recent years Ion-Sensitive Field Effect Transistor (ISFET) based transducers create valuable applications in physiological data acquisition and environment monitoring. This paper presents a mixed-mode ASIC design for potentiometric ISFET-based bio-chemical sensor applications including H+ sensing and hand-held pH meter. For battery power consideration, the proposed system consists of low voltage (3V) analog front-end readout circuits and digital processor has been developed and fabricated in a 0.5mm double-poly double-metal CMOS technology. To assure that the correct pH value can be measured, the two-point calibration circuitry based on the response of standard pH4 and pH7 buffer solution has been implemented by using algorithmic state machine hardware algorithms. The measurement accuracy of the chip is 10 bits and the measured range between pH 2 to pH 12 compared to ideal values is within the accuracy of 0.1pH. For homeland environmental applications, the system provide rapid, easy to use, and cost-effective on-site testing on the quality of water, such as drinking water, ground water and river water. The processor has a potential usage in battery-operated and portable devices in environmental monitoring applications compared to commercial hand-held pH meter.

Water Processing Assembly Particulate Filter Remove and Replace (R&R)

NASA Image and Video Library

2013-07-12

ISS036-E-018008 (12 July 2013) --- European Space Agency astronaut Luca Parmitano, Expedition 36 flight engineer, removes and replaces the particulate filter for the Water Pump Assembly 2 (WPA2) in Tranquility (also called Node 3) on the International Space Station.

Water Processing Assembly Particulate Filter Remove and Replace (R&R)

NASA Image and Video Library

2013-07-12

ISS036-E-018007 (12 July 2013) --- European Space Agency astronaut Luca Parmitano, Expedition 36 flight engineer, removes and replaces the particulate filter for the Water Pump Assembly 2 (WPA2) in Tranquility (also called Node 3) on the International Space Station.

STS-34 onboard view of iodine comparator assembly used to check water quality

NASA Technical Reports Server (NTRS)

1989-01-01

STS-34 closeup view taken onboard Atlantis, Orbiter Vehicle (OV) 104, is of the iodine comparator assembly. Potable water quality is checked by comparing the water color to the color chart on the surrounding board.

Passive gamma analysis of the boiling-water-reactor assemblies

NASA Astrophysics Data System (ADS)

Vo, D.; Favalli, A.; Grogan, B.; Jansson, P.; Liljenfeldt, H.; Mozin, V.; Schwalbach, P.; Sjöland, A.; Tobin, S.; Trellue, H.; Vaccaro, S.

2016-09-01

This research focused on the analysis of a set of stationary passive gamma measurements taken on the spent nuclear fuel assemblies from a boiling water reactor (BWR) using pulse height analysis data acquisition. The measurements were performed on 25 different BWR assemblies in 2014 at Sweden's Central Interim Storage Facility for Spent Nuclear Fuel (Clab). This study was performed as part of the Next Generation of Safeguards Initiative-Spent Fuel project to research the application of nondestructive assay (NDA) to spent fuel assemblies. The NGSI-SF team is working to achieve the following technical goals more easily and efficiently than in the past using nondestructive assay (NDA) measurements of spent fuel assemblies: (1) verify the initial enrichment, burnup, and cooling time of facility declaration; (2) detect the diversion or replacement of pins, (3) estimate the plutonium mass, (4) estimate the decay heat, and (5) determine the reactivity of spent fuel assemblies. The final objective of this project is to quantify the capability of several integrated NDA instruments to meet the aforementioned goals using the combined signatures of neutrons, gamma rays, and heat. This report presents a selection of the measured data and summarizes an analysis of the results. Specifically, trends in the count rates measured for spectral lines from the following isotopes were analyzed as a function of the declared burnup and cooling time: 137Cs, 154Eu, 134Cs, and to a lesser extent, 106Ru and 144Ce. From these measured count rates, predictive algorithms were developed to enable the estimation of the burnup and cooling time. Furthermore, these algorithms were benchmarked on a set of assemblies not included in the standard assemblies set used by this research team.

Passive gamma analysis of the boiling-water-reactor assemblies

DOE PAGES

Vo, D.; Favalli, A.; Grogan, B.; ...

2016-09-01

This research focused on the analysis of a set of stationary passive gamma measurements taken on the spent nuclear fuel assemblies from a boiling water reactor (BWR) using pulse height analysis data acquisition. The measurements were performed on 25 different BWR assemblies in 2014 at Sweden’s Central Interim Storage Facility for Spent Nuclear Fuel (Clab). This study was performed as part of the Next Generation of Safeguards Initiative–Spent Fuel project to research the application of nondestructive assay (NDA) to spent fuel assemblies. The NGSI–SF team is working to achieve the following technical goals more easily and efficiently than in themore » past using nondestructive assay (NDA) measurements of spent fuel assemblies: (1) verify the initial enrichment, burnup, and cooling time of facility declaration; (2) detect the diversion or replacement of pins, (3) estimate the plutonium mass, (4) estimate the decay heat, and (5) determine the reactivity of spent fuel assemblies. The final objective of this project is to quantify the capability of several integrated NDA instruments to meet the aforementioned goals using the combined signatures of neutrons, gamma rays, and heat. This report presents a selection of the measured data and summarizes an analysis of the results. Specifically, trends in the count rates measured for spectral lines from the following isotopes were analyzed as a function of the declared burnup and cooling time: 137Cs, 154Eu, 134Cs, and to a lesser extent, 106Ru and 144Ce. From these measured count rates, predictive algorithms were developed to enable the estimation of the burnup and cooling time. Furthermore, these algorithms were benchmarked on a set of assemblies not included in the standard assemblies set used by this research team.« less

Effect of processor temperature on film dosimetry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Srivastava, Shiv P.; Das, Indra J., E-mail: idas@iupui.edu

2012-07-01

Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d{sub max.}, 10 Multiplication-Sign 10 cm{sup 2}, 100 cm) to a given dose. Anmore » automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4-40.6 Degree-Sign C (85-105 Degree-Sign F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used.« less

Self-assembled multilayers and photoluminescence properties of a new water-soluble poly(para-phenylene)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, X.; Li, D.; Luett, M.

1998-07-01

This paper reports the synthesis and characterizations of a new water-soluble poly(paraphenylene) (PPP) and its applications in preparing self-assembled multi-layer films. This new water-soluble conducting polymer was prepared through the sulfonation reaction of poly(p-quarterphenylene-2,2{prime}-dicarboxylic acid). The incorporation of sulfonate groups has dramatically improved PPP's solubility in water at a wide pH range, whereas previous PPP is only slightly soluble in basic solutions. Dilute aqueous solutions of this polymer with acidic, neutral or basic pH emit brilliant blue light while irradiated with UV light. The sulfonated PPP emits from 350 nm to 455 nm with a maximum intensity at 380 nm.more » Self-assembled multilayers of this sulfonated PPP were constructed with a positively charged polymer poly(diallyl dimethyl ammonium chloride) and characterized with various surface analyses. Conductive (RuO{sub 2} and ITO), semiconductive (Si wafer), and non-conductive (SiO{sub 2}) substrates were used in the preparation of self-assembled multilayers. Electrical, optical and structural properties of these novel self-assembled thin films will be discussed.« less

Self-assembled multilayers and photoluminescence properties of a new water-soluble poly(para-phenylene)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, X.; Li, D.Q.; Luett, M.

1998-03-01

This paper reports the synthesis and characterizations of a new water-soluble poly(para-phenylene) (PPP) and its applications in preparing self-assembled multilayer films. This new water-soluble conducting polymer was prepared through the sulfonation reaction of poly(p-quarterphenylene-2,2{prime}-dicarboxylic acid). The incorporation of sulfonate groups has dramatically improved PPP`s solubility in water at a wide pH range, whereas previous PPP is only slightly soluble in basic solutions. Dilute aqueous solutions of this polymer with acidic, neutral or basic pH emit brilliant blue light while irradiated with UV light. The sulfonated PPP emits from 350 nm to 455 nm with a maximum intensity at 380 nm.more » Self-assembled multilayers of this sulfonated PPP were constructed with a positively charged polymer poly(diallyl dimethyl ammonium chloride) and characterized with various surface analyses. Conductive (RuO{sub 2} and ITO), semiconductive (Si wafer), and non-conductive (SiO{sub 2}) substrates were used in the preparation of self-assembled multilayers. Electrical, optical and structural properties of these novel self-assembled thin films will be discussed.« less

Monolayer Colloidal Crystals by Modified Air-Water Interface Self-Assembly Approach

PubMed Central

Ye, Xin; Huang, Jin; Zeng, Yong; Sun, Lai-Xi; Geng, Feng; Liu, Hong-Jie; Wang, Feng-Rui; Jiang, Xiao-Dong; Wu, Wei-Dong; Zheng, Wan-Guo

2017-01-01

Hexagonally ordered arrays of polystyrene (PS) microspheres were prepared by a modified air-water self-assembly method. A detailed analysis of the air-water interface self-assembly process was conducted. Several parameters affect the quality of the monolayer colloidal crystals, i.e., the colloidal microsphere concentration on the latex, the surfactant concentration, the polystyrene microsphere diameter, the microsphere polydispersity, and the degree of sphericity of polystyrene microspheres. An abrupt change in surface tension was used to improve the quality of the monolayer colloidal crystal. Three typical microstructures, i.e., a cone, a pillar, and a binary structure were prepared by reactive-ion etching using a high-quality colloidal crystal mask. This study provides insight into the production of microsphere templates with flexible structures for large-area patterned materials. PMID:28946664

Multiple Embedded Processors for Fault-Tolerant Computing

NASA Technical Reports Server (NTRS)

Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

2005-01-01

A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

Never Trust Your Word Processor

ERIC Educational Resources Information Center

Linke, Dirk

2009-01-01

In this article, the author talks about the auto correction mode of word processors that leads to a number of problems and describes an example in biochemistry exams that shows how word processors can lead to mistakes in databases and in papers. The author contends that, where this system is applied, spell checking should not be left to a word…

Programmable DNA-Mediated Multitasking Processor.

PubMed

Shu, Jian-Jun; Wang, Qi-Wen; Yong, Kian-Yan; Shao, Fangwei; Lee, Kee Jin

2015-04-30

Because of DNA appealing features as perfect material, including minuscule size, defined structural repeat and rigidity, programmable DNA-mediated processing is a promising computing paradigm, which employs DNAs as information storing and processing substrates to tackle the computational problems. The massive parallelism of DNA hybridization exhibits transcendent potential to improve multitasking capabilities and yield a tremendous speed-up over the conventional electronic processors with stepwise signal cascade. As an example of multitasking capability, we present an in vitro programmable DNA-mediated optimal route planning processor as a functional unit embedded in contemporary navigation systems. The novel programmable DNA-mediated processor has several advantages over the existing silicon-mediated methods, such as conducting massive data storage and simultaneous processing via much fewer materials than conventional silicon devices.

Thermodynamics of hydrogen bond patterns in supramolecular assemblies of water molecules.

PubMed

Henry, Marc

2002-07-02

The PACHA (Partial Atomic Charges and Hardnesses Analysis) formalism is applied to various supramolecular assemblies of water molecules. After a detailed study of all available crystal structures for ice polymorphs, we shown that the hydrogen bond strength is roughly constant below 1 GPa and considerably weakened above that value. New hydrogen bond patterns are proposed for ice IV, V, and VI after (EB) (electrostatic balance) minimization. For other polymorphs, there is an almost perfect coincidence between experimental and predicted hydrogen bond patterns. The evolution of hydrogen bond energy as a function of molecular geometry in water clusters with up to 280 water molecules and in large supramolecular compounds is quantitatively described. Intermolecular hydrogen bonds are found to lie between -9 and -32 kJ mol-1, the stronger interaction occurs within the spherical fully disordered water droplet buried at the heart of Müller's superfullerene keplerate. The weakest one occurs in a chiral molecular snub cube built from six calix[4]resorcinarene and eight water molecules. Intramolecular hydrogen bonds are found in the range -10-100 kJ mol-1 and can thus be considerably stronger than intermolecular bonds. Finally, through the investigation of a clathrate type I compound, it was possible to obtain a deep insight of the host-guest interactions and self-assembly rules of water cages in these materials.

Water droplets as template for next-generation self-assembled poly-(etheretherketone) with cardo membranes.

PubMed

Gugliuzza, Annarosa; Aceto, Marianna Carmela; Macedonio, Francesca; Drioli, Enrico

2008-08-28

Next generation PEEK-WC membranes have been fabricated by using an innovative self-assembly technique. Patterned architectures have been achieved via a solvent-reduced and water-assisted process, resulting in honeycomb packed geometry. The membranes exhibit monodisperse pores with size and shape comparable to those left by templating water droplets. Influencing factors for the formation of self-assembled poly-(etheretherketone) with Cardo [PEEK-WC] membranes have been evaluated, identifying the critical parameters for nucleation, growth, and propagation of the droplet-mobile arrays through the overall films. Structure-transport relationships have been discussed according to the results achieved from the implementation of membrane distillation processes, yielding indication about the suitability of self-assembled PEEK-WC films to work as interfaces in contactor operations.

Multi-Core Processor Memory Contention Benchmark Analysis Case Study

NASA Technical Reports Server (NTRS)

Simon, Tyler; McGalliard, James

2009-01-01

Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

Limit characteristics of digital optoelectronic processor

NASA Astrophysics Data System (ADS)

Kolobrodov, V. G.; Tymchik, G. S.; Kolobrodov, M. S.

2018-01-01

In this article, the limiting characteristics of a digital optoelectronic processor are explored. The limits are defined by diffraction effects and a matrix structure of the devices for input and output of optical signals. The purpose of a present research is to optimize the parameters of the processor's components. The developed physical and mathematical model of DOEP allowed to establish the limit characteristics of the processor, restricted by diffraction effects and an array structure of the equipment for input and output of optical signals, as well as to optimize the parameters of the processor's components. The diameter of the entrance pupil of the Fourier lens is determined by the size of SLM and the pixel size of the modulator. To determine the spectral resolution, it is offered to use a concept of an optimum phase when the resolved diffraction maxima coincide with the pixel centers of the radiation detector.

21 CFR 892.1900 - Automatic radiographic film processor.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Automatic radiographic film processor. 892.1900... (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1900 Automatic radiographic film processor. (a) Identification. An automatic radiographic film processor is a device intended to be used to...

21 CFR 892.1900 - Automatic radiographic film processor.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Automatic radiographic film processor. 892.1900... (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1900 Automatic radiographic film processor. (a) Identification. An automatic radiographic film processor is a device intended to be used to...

21 CFR 892.1900 - Automatic radiographic film processor.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Automatic radiographic film processor. 892.1900... (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1900 Automatic radiographic film processor. (a) Identification. An automatic radiographic film processor is a device intended to be used to...

21 CFR 892.1900 - Automatic radiographic film processor.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Automatic radiographic film processor. 892.1900... (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1900 Automatic radiographic film processor. (a) Identification. An automatic radiographic film processor is a device intended to be used to...

21 CFR 892.1900 - Automatic radiographic film processor.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Automatic radiographic film processor. 892.1900... (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1900 Automatic radiographic film processor. (a) Identification. An automatic radiographic film processor is a device intended to be used to...

A natural-gas fuel processor for a residential fuel cell system

NASA Astrophysics Data System (ADS)

Adachi, H.; Ahmed, S.; Lee, S. H. D.; Papadias, D.; Ahluwalia, R. K.; Bendert, J. C.; Kanner, S. A.; Yamazaki, Y.

A system model was used to develop an autothermal reforming fuel processor to meet the targets of 80% efficiency (higher heating value) and start-up energy consumption of less than 500 kJ when operated as part of a 1-kWe natural-gas fueled fuel cell system for cogeneration of heat and power. The key catalytic reactors of the fuel processor - namely the autothermal reformer, a two-stage water gas shift reactor and a preferential oxidation reactor - were configured and tested in a breadboard apparatus. Experimental results demonstrated a reformate containing ∼48% hydrogen (on a dry basis and with pure methane as fuel) and less than 5 ppm CO. The effects of steam-to-carbon and part load operations were explored.

Testing and operating a multiprocessor chip with processor redundancy

DOEpatents

Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

2014-10-21

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Database for LDV Signal Processor Performance Analysis

NASA Technical Reports Server (NTRS)

Baker, Glenn D.; Murphy, R. Jay; Meyers, James F.

1989-01-01

A comparative and quantitative analysis of various laser velocimeter signal processors is difficult because standards for characterizing signal bursts have not been established. This leaves the researcher to select a signal processor based only on manufacturers' claims without the benefit of direct comparison. The present paper proposes the use of a database of digitized signal bursts obtained from a laser velocimeter under various configurations as a method for directly comparing signal processors.

Communications Processor Operating System Study. Executive Summary,

DTIC Science & Technology

1980-11-01

AD-A095 b36 ROME AIR DEVELOPMENT CENTER GRIFFISS AFB NY F/e 17/2 COMMUNICATIONS PROCESSOR OPERATING SYSTEM STUDY. EXECUTIVE SUMM—ETC(U) NOV 80 J...COMMUNICATIONS PROCESSOR OPERATING SYSTEM STUDY Julian Gitlih SPTIC ELECTE«^ FEfi 2 6 1981^ - E APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED "a O...Subtitle) EXECUTIVE^SUMMARY 0F> COMMUNICATIONS PROCESSOR OPERATING SYSTEM $t - • >X W tdLl - ’•• • 7 AUTHORf«! ! , Julian

Soft-core processor study for node-based architectures.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Van Houten, Jonathan Roger; Jarosz, Jason P.; Welch, Benjamin James

2008-09-01

Node-based architecture (NBA) designs for future satellite projects hold the promise of decreasing system development time and costs, size, weight, and power and positioning the laboratory to address other emerging mission opportunities quickly. Reconfigurable Field Programmable Gate Array (FPGA) based modules will comprise the core of several of the NBA nodes. Microprocessing capabilities will be necessary with varying degrees of mission-specific performance requirements on these nodes. To enable the flexibility of these reconfigurable nodes, it is advantageous to incorporate the microprocessor into the FPGA itself, either as a hardcore processor built into the FPGA or as a soft-core processor builtmore » out of FPGA elements. This document describes the evaluation of three reconfigurable FPGA based processors for use in future NBA systems--two soft cores (MicroBlaze and non-fault-tolerant LEON) and one hard core (PowerPC 405). Two standard performance benchmark applications were developed for each processor. The first, Dhrystone, is a fixed-point operation metric. The second, Whetstone, is a floating-point operation metric. Several trials were run at varying code locations, loop counts, processor speeds, and cache configurations. FPGA resource utilization was recorded for each configuration. Cache configurations impacted the results greatly; for optimal processor efficiency it is necessary to enable caches on the processors. Processor caches carry a penalty; cache error mitigation is necessary when operating in a radiation environment.« less

Environmental Control and Life Support Systems Testing Facility at MSFC

NASA Technical Reports Server (NTRS)

2001-01-01

The Marshall Space Flight Center (MSFC) is responsible for designing and building the life support systems that will provide the crew of the International Space Station (ISS) a comfortable environment in which to live and work. Scientists and engineers at the MSFC are working together to provide the ISS with systems that are safe, efficient, and cost-effective. These compact and powerful systems are collectively called the Environmental Control and Life Support Systems, or simply, ECLSS. This photograph shows the Urine Processor Assembly (UPA) which utilizes the Vapor Compression Distillation (VCD) technology. The VCD is used for integrated testing of the entire Water Recovery System (WRS) and development testing of the Urine Processor Assembly. The UPA accepts and processes pretreated crewmember urine to allow it to be processed along with other wastewaters in the Water Processor Assembly (WPA). The WPA removes free gas, organic, and nonorganic constituents before the water goes through a series of multifiltration beds for further purification. Product water quality is monitored primarily through conductivity measurements. Unacceptable water is sent back through the WPA for reprocessing. Clean water is sent to a storage tank.

The interfacial-organized monolayer water film (MWF) induced ``two-step'' aggregation of nanographene: both in stacking and sliding assembly pathways

NASA Astrophysics Data System (ADS)

Lv, Wenping; Wu, Ren'an

2013-03-01

A computational investigation was carried out to understand the aggregation of nanoscale graphene with two typical pathways of stacking assembly and sliding assembly in water. The interfacial-organized monolayer water film (MWF) induced ``two-step'' aggregation of nanographene in both stacking and sliding assembly pathways was reported for the first time. By means of potential mean forces (PMFs) calculation, no energy barrier was observed during the sliding assembly of two graphene nanosheets, while the PMF profiles could be impacted by the contact forms of nanographene and the MWF within the interplate of two graphene nanosheets. To explore the potential physical basis of the ``hindering role'' of self-organized interfacial water, the dynamical and structural properties as well as the status of hydrogen bonds (H-bonds) for interfacial water were investigated. We found that the compact, ordered structure and abundant H-bonds of the MWF could be taken as the fundamental aspects of the ``hindering role'' of interfacial water for the hydrophobic assembly of nanographene. These findings are displaying a potential to further understand the hydrophobic assembly which mostly dominate the behaviors of nanomaterials, proteins etc. in aqueous solutions.A computational investigation was carried out to understand the aggregation of nanoscale graphene with two typical pathways of stacking assembly and sliding assembly in water. The interfacial-organized monolayer water film (MWF) induced ``two-step'' aggregation of nanographene in both stacking and sliding assembly pathways was reported for the first time. By means of potential mean forces (PMFs) calculation, no energy barrier was observed during the sliding assembly of two graphene nanosheets, while the PMF profiles could be impacted by the contact forms of nanographene and the MWF within the interplate of two graphene nanosheets. To explore the potential physical basis of the ``hindering role'' of self-organized interfacial

An optical/digital processor - Hardware and applications

NASA Technical Reports Server (NTRS)

Casasent, D.; Sterling, W. M.

1975-01-01

A real-time two-dimensional hybrid processor consisting of a coherent optical system, an optical/digital interface, and a PDP-11/15 control minicomputer is described. The input electrical-to-optical transducer is an electron-beam addressed potassium dideuterium phosphate (KD2PO4) light valve. The requirements and hardware for the output optical-to-digital interface, which is constructed from modular computer building blocks, are presented. Initial experimental results demonstrating the operation of this hybrid processor in phased-array radar data processing, synthetic-aperture image correlation, and text correlation are included. The applications chosen emphasize the role of the interface in the analysis of data from an optical processor and possible extensions to the digital feedback control of an optical processor.

Self-Assembly Behavior of Amphiphilic Janus Dendrimers in Water: A Combined Experimental and Coarse-Grained Molecular Dynamics Simulation Approach.

PubMed

Elizondo-García, Mariana E; Márquez-Miranda, Valeria; Araya-Durán, Ingrid; Valencia-Gallegos, Jesús A; González-Nilo, Fernando D

2018-04-21

Amphiphilic Janus dendrimers (JDs) are repetitively branched molecules with hydrophilic and hydrophobic components that self-assemble in water to form a variety of morphologies, including vesicles analogous to liposomes with potential pharmaceutical and medical application. To date, the self-assembly of JDs has not been fully investigated thus it is important to gain insight into its mechanism and dependence on JDs’ molecular structure. In this study, the aggregation behavior in water of a second-generation bis-MPA JD was evaluated using experimental and computational methods. Dispersions of JDs in water were carried out using the thin-film hydration and ethanol injection methods. Resulting assemblies were characterized by dynamic light scattering, confocal microscopy, and atomic force microscopy. Furthermore, a coarse-grained molecular dynamics (CG-MD) simulation was performed to study the mechanism of JDs aggregation. The obtaining of assemblies in water with no interdigitated bilayers was confirmed by the experimental characterization and CG-MD simulation. Assemblies with dendrimersome characteristics were obtained using the ethanol injection method. The results of this study establish a relationship between the molecular structure of the JD and the properties of its aggregates in water. Thus, our findings could be relevant for the design of novel JDs with tailored assemblies suitable for drug delivery systems.

Detecting pin diversion from pressurized water reactors spent fuel assemblies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ham, Young S.; Sitaraman, Shivakumar

Detecting diversion of spent fuel from Pressurized Water Reactors (PWR) by determining possible diversion including the steps of providing a detector cluster containing gamma ray and neutron detectors, inserting the detector cluster containing the gamma ray and neutron detectors into the spent fuel assembly through the guide tube holes in the spent fuel assembly, measuring gamma ray and neutron radiation responses of the gamma ray and neutron detectors in the guide tube holes, processing the gamma ray and neutron radiation responses at the guide tube locations by normalizing them to the maximum value among each set of responses and takingmore » the ratio of the gamma ray and neutron responses at the guide tube locations and normalizing the ratios to the maximum value among them and producing three signatures, gamma, neutron, and gamma-neutron ratio, based on these normalized values, and producing an output that consists of these signatures that can indicate possible diversion of the pins from the spent fuel assembly.« less

The GF-3 SAR Data Processor

PubMed Central

Han, Bing; Ding, Chibiao; Zhong, Lihua; Liu, Jiayin; Qiu, Xiaolan; Hu, Yuxin; Lei, Bin

2018-01-01

The Gaofen-3 (GF-3) data processor was developed as a workstation-based GF-3 synthetic aperture radar (SAR) data processing system. The processor consists of two vital subsystems of the GF-3 ground segment, which are referred to as data ingesting subsystem (DIS) and product generation subsystem (PGS). The primary purpose of DIS is to record and catalogue GF-3 raw data with a transferring format, and PGS is to produce slant range or geocoded imagery from the signal data. This paper presents a brief introduction of the GF-3 data processor, including descriptions of the system architecture, the processing algorithms and its output format. PMID:29534464

A digital retina-like low-level vision processor.

PubMed

Mertoguno, S; Bourbakis, N G

2003-01-01

This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.

Simulation of a master-slave event set processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Comfort, J.C.

1984-03-01

Event set manipulation may consume a considerable amount of the computation time spent in performing a discrete-event simulation. One way of minimizing this time is to allow event set processing to proceed in parallel with the remainder of the simulation computation. The paper describes a multiprocessor simulation computer, in which all non-event set processing is performed by the principal processor (called the host). Event set processing is coordinated by a front end processor (the master) and actually performed by several other functionally identical processors (the slaves). A trace-driven simulation program modeling this system was constructed, and was run with tracemore » output taken from two different simulation programs. Output from this simulation suggests that a significant reduction in run time may be realized by this approach. Sensitivity analysis was performed on the significant parameters to the system (number of slave processors, relative processor speeds, and interprocessor communication times). A comparison between actual and simulation run times for a one-processor system was used to assist in the validation of the simulation. 7 references.« less

Middle School Pupil Writing and the Word Processor.

ERIC Educational Resources Information Center

Ediger, Marlow

Pupils in middle schools should have ample opportunities to write with the use of word processors. Legible writing in longhand will always be necessary in selected situations but, nevertheless, much drudgery is taken care of when using a word processor. Word processors tend to be very user friendly in that few mechanical skills are needed by the…

Getting Out of Orbit: Water Recycling Requirements and Technology Needs for Long Duration Missions Away from Earth

NASA Technical Reports Server (NTRS)

Barta, Daniel J.

2017-01-01

Deep-space crewed missions will not have regular access to the Earth's resources or the ability to rapidly return to Earth if a system fails. As crewed missions extend farther from Earth for longer periods, habitation systems must become more self-sufficient and reliable for safe, healthy, and sustainable human exploration. For human missions to Mars, Environmental Control and Life Support Systems (ECLSS) must be able operate for up to 1,100 days with minimal spares and consumables. These missions will require capabilities to more fully recycle atmospheric gases and wastewater to substantially reduce mission costs. Even with relatively austere requirements for use, water represents one of the largest consumables by mass. Systems must be available to extract and recycle water from all sources of waste. And given that there will be no opportunity to send samples back to Earth for analysis, analytical measurements will be limited to monitoring hardware brought on board the spacecraft. The Earth Reliant phase of NASA's exploration strategy includes leveraging the International Space Station (ISS) to demonstrate advanced capabilities for a robust and reliable ECLSS. The ISS Water Recovery System (WRS) includes a Urine Processor Assembly (UPA) for distillation and recovery of water from urine and a Water Processor Assembly (WPA) to process humidity condensate and urine distillate into potable water. Possible enhancements to more fully "close the water loop" include recovery of water from waste brines and solid wastes. A possible game changer is the recovery of water from local planetary resources through use of In Situ Resource Utilization (ISRU) technologies. As part of the development and demonstration sequence, NASA intends to utilize cis-Lunar space as a Proving Ground to verify systems for deep space habitation by conducting extended duration missions to validate our readiness for Mars.

The computational structural mechanics testbed generic structural-element processor manual

NASA Technical Reports Server (NTRS)

Stanley, Gary M.; Nour-Omid, Shahram

1990-01-01

The usage and development of structural finite element processors based on the CSM Testbed's Generic Element Processor (GEP) template is documented. By convention, such processors have names of the form ESi, where i is an integer. This manual is therefore intended for both Testbed users who wish to invoke ES processors during the course of a structural analysis, and Testbed developers who wish to construct new element processors (or modify existing ones).

Multiple core computer processor with globally-accessible local memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shalf, John; Donofrio, David; Oliker, Leonid

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality ofmore » processor cores.« less

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2011 CFR

2011-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2010 CFR

2010-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2012 CFR

2012-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2014 CFR

2014-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2013 CFR

2013-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

Compartmentalization Technologies via Self-Assembly and Cross-Linking of Amphiphilic Random Block Copolymers in Water.

PubMed

Matsumoto, Mayuko; Terashima, Takaya; Matsumoto, Kazuma; Takenaka, Mikihito; Sawamoto, Mitsuo

2017-05-31

Orthogonal self-assembly and intramolecular cross-linking of amphiphilic random block copolymers in water afforded an approach to tailor-make well-defined compartments and domains in single polymer chains and nanoaggregates. For a double compartment single-chain polymer, an amphiphilic random block copolymer bearing hydrophilic poly(ethylene glycol) (PEG) and hydrophobic dodecyl, benzyl, and olefin pendants was synthesized by living radical polymerization (LRP) and postfunctionalization; the dodecyl and benzyl units were incorporated into the different block segments, whereas PEG pendants were statistically attached along a chain. The copolymer self-folded via the orthogonal self-assembly of hydrophobic dodecyl and benzyl pendants in water, followed by intramolecular cross-linking, to form a single-chain polymer carrying double yet distinct hydrophobic nanocompartments. A single-chain cross-linked polymer with a chlorine terminal served as a globular macroinitiator for LRP to provide an amphiphilic tadpole macromolecule comprising a hydrophilic nanoparticle and a hydrophobic polymer tail; the tadpole thus self-assembled into multicompartment aggregates in water.

Acoustooptic linear algebra processors - Architectures, algorithms, and applications

NASA Technical Reports Server (NTRS)

Casasent, D.

1984-01-01

Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

A GLM Post-processor to Adjust Ensemble Forecast Traces

NASA Astrophysics Data System (ADS)

Thiemann, M.; Day, G. N.; Schaake, J. C.; Draijer, S.; Wang, L.

2011-12-01

The skill of hydrologic ensemble forecasts has improved in the last years through a better understanding of climate variability, better climate forecasts and new data assimilation techniques. Having been extensively utilized for probabilistic water supply forecasting, interest is developing to utilize these forecasts in operational decision making. Hydrologic ensemble forecast members typically have inherent biases in flow timing and volume caused by (1) structural errors in the models used, (2) systematic errors in the data used to calibrate those models, (3) uncertain initial hydrologic conditions, and (4) uncertainties in the forcing datasets. Furthermore, hydrologic models have often not been developed for operational decision points and ensemble forecasts are thus not always available where needed. A statistical post-processor can be used to address these issues. The post-processor should (1) correct for systematic biases in flow timing and volume, (2) preserve the skill of the available raw forecasts, (3) preserve spatial and temporal correlation as well as the uncertainty in the forecasted flow data, (4) produce adjusted forecast ensembles that represent the variability of the observed hydrograph to be predicted, and (5) preserve individual forecast traces as equally likely. The post-processor should also allow for the translation of available ensemble forecasts to hydrologically similar locations where forecasts are not available. This paper introduces an ensemble post-processor (EPP) developed in support of New York City water supply operations. The EPP employs a general linear model (GLM) to (1) adjust available ensemble forecast traces and (2) create new ensembles for (nearby) locations where only historic flow observations are available. The EPP is calibrated by developing daily and aggregated statistical relationships form historical flow observations and model simulations. These are then used in operation to obtain the conditional probability density

A slippery molecular assembly allows water as a self-erasable security marker

PubMed Central

Thirumalai, Rajasekaran; Mukhopadhyay, Rahul Dev; Praveen, Vakayil K.; Ajayaghosh, Ayyappanpillai

2015-01-01

Protection of currency and valuable documents from counterfeit continues to be a challenge. While there are many embedded security features available for document safety, they are not immune to forgery. Fluorescence is a sensitive property, which responds to external stimuli such as solvent polarity, temperature or mechanical stress, however practical use in security applications is hampered due to several reasons. Therefore, a simple and specific stimuli responsive security feature that is difficult to duplicate is of great demand. Herein we report the design of a fluorescent molecular assembly on which water behaves as a self-erasable security marker for checking the authenticity of documents at point of care. The underlying principle involves the disciplined self-assembly of a tailor-made fluorescent molecule, which initially form a weak blue fluorescence (λem = 425 nm, Φf = 0.13) and changes to cyan emission (λem = 488 nm,Φf = 0.18) in contact with water due to a reversible molecular slipping motion. This simple chemical tool, based on the principles of molecular self-assembly and fluorescence modulation, allows creation of security labels and optically masked barcodes for multiple documents authentication. PMID:25940779

A slippery molecular assembly allows water as a self-erasable security marker.

PubMed

Thirumalai, Rajasekaran; Mukhopadhyay, Rahul Dev; Praveen, Vakayil K; Ajayaghosh, Ayyappanpillai

2015-05-05

Protection of currency and valuable documents from counterfeit continues to be a challenge. While there are many embedded security features available for document safety, they are not immune to forgery. Fluorescence is a sensitive property, which responds to external stimuli such as solvent polarity, temperature or mechanical stress, however practical use in security applications is hampered due to several reasons. Therefore, a simple and specific stimuli responsive security feature that is difficult to duplicate is of great demand. Herein we report the design of a fluorescent molecular assembly on which water behaves as a self-erasable security marker for checking the authenticity of documents at point of care. The underlying principle involves the disciplined self-assembly of a tailor-made fluorescent molecule, which initially form a weak blue fluorescence (λem = 425 nm, Φf = 0.13) and changes to cyan emission (λem = 488 nm,Φf = 0.18) in contact with water due to a reversible molecular slipping motion. This simple chemical tool, based on the principles of molecular self-assembly and fluorescence modulation, allows creation of security labels and optically masked barcodes for multiple documents authentication.

Dynamic and programmable self-assembly of micro-rafts at the air-water interface

PubMed Central

Wang, Wendong; Giltinan, Joshua; Zakharchenko, Svetlana; Sitti, Metin

2017-01-01

Dynamic self-assembled material systems constantly consume energy to maintain their spatiotemporal structures and functions. Programmable self-assembly translates information from individual parts to the collective whole. Combining dynamic and programmable self-assembly in a single platform opens up the possibilities to investigate both types of self-assembly simultaneously and to explore their synergy. This task is challenging because of the difficulty in finding suitable interactions that are both dissipative and programmable. We present a dynamic and programmable self-assembling material system consisting of spinning at the air-water interface circular magnetic micro-rafts of radius 50 μm and with cosinusoidal edge-height profiles. The cosinusoidal edge-height profiles not only create a net dissipative capillary repulsion that is sustained by continuous torque input but also enable directional assembly of micro-rafts. We uncover the layered arrangement of micro-rafts in the patterns formed by dynamic self-assembly and offer mechanistic insights through a physical model and geometric analysis. Furthermore, we demonstrate programmable self-assembly and show that a 4-fold rotational symmetry encoded in individual micro-rafts translates into 90° bending angles and square-based tiling in the assembled structures of micro-rafts. We anticipate that our dynamic and programmable material system will serve as a model system for studying nonequilibrium dynamics and statistical mechanics in the future. PMID:28560332

Dynamic and programmable self-assembly of micro-rafts at the air-water interface.

PubMed

Wang, Wendong; Giltinan, Joshua; Zakharchenko, Svetlana; Sitti, Metin

2017-05-01

Dynamic self-assembled material systems constantly consume energy to maintain their spatiotemporal structures and functions. Programmable self-assembly translates information from individual parts to the collective whole. Combining dynamic and programmable self-assembly in a single platform opens up the possibilities to investigate both types of self-assembly simultaneously and to explore their synergy. This task is challenging because of the difficulty in finding suitable interactions that are both dissipative and programmable. We present a dynamic and programmable self-assembling material system consisting of spinning at the air-water interface circular magnetic micro-rafts of radius 50 μm and with cosinusoidal edge-height profiles. The cosinusoidal edge-height profiles not only create a net dissipative capillary repulsion that is sustained by continuous torque input but also enable directional assembly of micro-rafts. We uncover the layered arrangement of micro-rafts in the patterns formed by dynamic self-assembly and offer mechanistic insights through a physical model and geometric analysis. Furthermore, we demonstrate programmable self-assembly and show that a 4-fold rotational symmetry encoded in individual micro-rafts translates into 90° bending angles and square-based tiling in the assembled structures of micro-rafts. We anticipate that our dynamic and programmable material system will serve as a model system for studying nonequilibrium dynamics and statistical mechanics in the future.

Self-assembling nucleic acid delivery vehicles via linear, water-soluble, cyclodextrin-containing polymers.

PubMed

Davis, M E; Pun, S H; Bellocq, N C; Reineke, T M; Popielarski, S R; Mishra, S; Heidel, J D

2004-01-01

Non-viral (synthetic) nucleic acid delivery systems have the potential to provide for the practical application of nucleic acid-based therapeutics. We have designed and prepared a tunable, non-viral nucleic acid delivery system that self-assembles with nucleic acids and centers around a new class of polymeric materials; namely, linear, water-soluble cyclodextrin-containing polymers. The relationships between polymer structure and gene delivery are illustrated, and the roles of the cyclodextrin moieties for minimizing toxicity and forming inclusion complexes in the self-assembly processes are highlighted. This vehicle is the first example of a polymer-based gene delivery system formed entirely by self-assembly.

Embedded processor extensions for image processing

NASA Astrophysics Data System (ADS)

Thevenin, Mathieu; Paindavoine, Michel; Letellier, Laurent; Heyrman, Barthélémy

2008-04-01

The advent of camera phones marks a new phase in embedded camera sales. By late 2009, the total number of camera phones will exceed that of both conventional and digital cameras shipped since the invention of photography. Use in mobile phones of applications like visiophony, matrix code readers and biometrics requires a high degree of component flexibility that image processors (IPs) have not, to date, been able to provide. For all these reasons, programmable processor solutions have become essential. This paper presents several techniques geared to speeding up image processors. It demonstrates that a gain of twice is possible for the complete image acquisition chain and the enhancement pipeline downstream of the video sensor. Such results confirm the potential of these computing systems for supporting future applications.

The CSM testbed matrix processors internal logic and dataflow descriptions

NASA Technical Reports Server (NTRS)

Regelbrugge, Marc E.; Wright, Mary A.

1988-01-01

This report constitutes the final report for subtask 1 of Task 5 of NASA Contract NAS1-18444, Computational Structural Mechanics (CSM) Research. This report contains a detailed description of the coded workings of selected CSM Testbed matrix processors (i.e., TOPO, K, INV, SSOL) and of the arithmetic utility processor AUS. These processors and the current sparse matrix data structures are studied and documented. Items examined include: details of the data structures, interdependence of data structures, data-blocking logic in the data structures, processor data flow and architecture, and processor algorithmic logic flow.

Development of a Soldier-Portable Fuel Cell Power System, Part I: A Bread-Board Methanol Fuel Processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Palo, Daniel R.; Holladay, Jamelyn D.; Rozmiarek, Robert T.

A 15-We portable power system is being developed for the US Army, comprised of a hydrogen-generating fuel reformer coupled to a hydrogen-converting fuel cell. As a first phase of this project, a methanol steam reformer system was developed and demonstrated. The reformer system included a combustor, two vaporizers, and a steam-reforming reactor. The device was demonstrated as a thermally independent unit over the range of 14 to 80 Wt output. Assuming a 14-day mission life and an ultimate 1-kg fuel processor/fuel cell assembly, a base case was chosen to illustrate the expected system performance. Operating at 13 We, the systemmore » yielded a fuel processor efficiency of 45% (LHV of H2 out/LHV of fuel in) and an estimated net efficiency of 22% (assuming a fuel cell efficiency of 48%). The resulting energy density of 720 W-hr/kg is several times the energy density of the best lithium-ion batteries. Some immediate areas of improvement in thermal management also have been identified and an integrated fuel processor is under development. The final system will be a hybrid, containing a fuel reformer, fuel cell, and rechargeable battery. The battery will provide power for startup and added capacity for times of peak power demand.« less

A novel VLSI processor architecture for supercomputing arrays

NASA Technical Reports Server (NTRS)

Venkateswaran, N.; Pattabiraman, S.; Devanathan, R.; Ahmed, Ashaf; Venkataraman, S.; Ganesh, N.

1993-01-01

Design of the processor element for general purpose massively parallel supercomputing arrays is highly complex and cost ineffective. To overcome this, the architecture and organization of the functional units of the processor element should be such as to suit the diverse computational structures and simplify mapping of complex communication structures of different classes of algorithms. This demands that the computation and communication structures of different class of algorithms be unified. While unifying the different communication structures is a difficult process, analysis of a wide class of algorithms reveals that their computation structures can be expressed in terms of basic IP,IP,OP,CM,R,SM, and MAA operations. The execution of these operations is unified on the PAcube macro-cell array. Based on this PAcube macro-cell array, we present a novel processor element called the GIPOP processor, which has dedicated functional units to perform the above operations. The architecture and organization of these functional units are such to satisfy the two important criteria mentioned above. The structure of the macro-cell and the unification process has led to a very regular and simpler design of the GIPOP processor. The production cost of the GIPOP processor is drastically reduced as it is designed on high performance mask programmable PAcube arrays.

Design of a MIMD neural network processor

NASA Astrophysics Data System (ADS)

Saeks, Richard E.; Priddy, Kevin L.; Pap, Robert M.; Stowell, S.

1994-03-01

The Accurate Automation Corporation (AAC) neural network processor (NNP) module is a fully programmable multiple instruction multiple data (MIMD) parallel processor optimized for the implementation of neural networks. The AAC NNP design fully exploits the intrinsic sparseness of neural network topologies. Moreover, by using a MIMD parallel processing architecture one can update multiple neurons in parallel with efficiency approaching 100 percent as the size of the network increases. Each AAC NNP module has 8 K neurons and 32 K interconnections and is capable of 140,000,000 connections per second with an eight processor array capable of over one billion connections per second.

Novel thermoresponsive assemblies of co-grafted natural and synthetic polymers for water purification.

PubMed

Paneysar, Joginder Singh; Barton, Stephen; Chandra, Sudeshna; Ambre, Premlata; Coutinho, Evans

2017-03-01

Water contamination and its purification are a global problem. The current approach to purify water is reduction of impurities to acceptable levels. One of the ways to achieve this is by use of water-soluble polymers that extract organic and metallic contaminants, from water. This paper presents a blend of composite polymers that eliminates both the contaminants simultaneously by the principle of adsorption at lower critical solution temperature. These composite polymers have been synthesized by grafting poly(N,N-diethylacrylamide), poly(N-isopropylacrylamide) and poly(N-vinylcaprolactam) on-to the natural polymer chitosan or its derivatives, giving smart graft polymeric assemblies (GPAs). One of the graft polymers, GPA-2, exhibits excellent adsorption properties able to remove metal ions like cadmium, cobalt, copper, lead, iron and also organic impurities like chlorophenol and phthalic anhydride. Studies reveal that 6 mg/ml GPA-2 is able to effect a 100% removal of organic impurities - chlorophenol (50 ppm) and phthalic anhydride (70 ppm) - from water, while complete removal of the heavy metal ions (Cu +2 , Co +2 and Cd +2 ) together at 30 ppm concentration has been achieved with 7.5 mg/ml GPA-2. The reduction in level of impurities along with recyclability and reproducibility in the elimination spectrum makes these assemblies promising materials in water treatment.

Infrared light-induced protein crystallization. Structuring of protein interfacial water and periodic self-assembly

NASA Astrophysics Data System (ADS)

Kowacz, Magdalena; Marchel, Mateusz; Juknaité, Lina; Esperança, José M. S. S.; Romão, Maria João; Carvalho, Ana Luísa; Rebelo, Luís Paulo N.

2017-01-01

We show that a physical trigger, a non-ionizing infrared (IR) radiation at wavelengths strongly absorbed by liquid water, can be used to induce and kinetically control protein (periodic) self-assembly in solution. This phenomenon is explained by considering the effect of IR light on the structuring of protein interfacial water. Our results indicate that the IR radiation can promote enhanced mutual correlations of water molecules in the protein hydration shell. We report on the radiation-induced increase in both the strength and cooperativeness of H-bonds. The presence of a structured dipolar hydration layer can lead to attractive interactions between like-charged biomacromolecules in solution (and crystal nucleation events). Furthermore, our study suggests that enveloping the protein within a layer of structured solvent (an effect enhanced by IR light) can prevent the protein non-specific aggregation favoring periodic self-assembly. Recognizing the ability to affect protein-water interactions by means of IR radiation may have important implications for biological and bio-inspired systems.

MBASIC batch processor architectural overview

NASA Technical Reports Server (NTRS)

Reynolds, S. M.

1978-01-01

The MBASIC (TM) batch processor, a language translator designed to operate in the MBASIC (TM) environment is described. Features include: (1) a CONVERT TO BATCH command, usable from the ready mode; and (2) translation of the users program in stages through several levels of intermediate language and optimization. The processor is to be designed and implemented in both machine-independent and machine-dependent sections. The architecture is planned so that optimization processes are transparent to the rest of the system and need not be included in the first design implementation cycle.

Coding, testing and documentation of processors for the flight design system

NASA Technical Reports Server (NTRS)

1980-01-01

The general functional design and implementation of processors for a space flight design system are briefly described. Discussions of a basetime initialization processor; conic, analytical, and precision coasting flight processors; and an orbit lifetime processor are included. The functions of several utility routines are also discussed.

Design of RISC Processor Using VHDL and Cadence

NASA Astrophysics Data System (ADS)

Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram

The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.

Assimilation of satellite altimetry data in hydrological models for improved inland surface water information: Case studies from the "Sentinel-3 Hydrologic Altimetry Processor prototypE" project (SHAPE)

NASA Astrophysics Data System (ADS)

Gustafsson, David; Pimentel, Rafael; Fabry, Pierre; Bercher, Nicolas; Roca, Mónica; Garcia-Mondejar, Albert; Fernandes, Joana; Lázaro, Clara; Ambrózio, Américo; Restano, Marco; Benveniste, Jérôme

2017-04-01

This communication is about the Sentinel-3 Hydrologic Altimetry Processor prototypE (SHAPE) project, with a focus on the components dealing with assimilation of satellite altimetry data into hydrological models. The SHAPE research and development project started in September 2015, within the Scientific Exploitation of Operational Missions (SEOM) programme of the European Space Agency. The objectives of the project are to further develop and assess recent improvement in altimetry data, processing algorithms and methods for assimilation in hydrological models, with the overarching goal to support improved scientific use of altimetry data and improved inland water information. The objective is also to take scientific steps towards a future Inland Water dedicated processor on the Sentinel-3 ground segment. The study focuses on three main variables of interest in hydrology: river stage, river discharge and lake level. The improved altimetry data from the project is used to estimate river stage, river discharge and lake level information in a data assimilation framework using the hydrological dynamic and semi-distributed model HYPE (Hydrological Predictions for the Environment). This model has been developed by SMHI and includes data assimilation module based on the Ensemble Kalman filter method. The method will be developed and assessed for a number of case studies with available in situ reference data and satellite altimetry data based on mainly the CryoSat-2 mission on which the new processor will be run; Results will be presented from case studies on the Amazon and Danube rivers and Lake Vänern (Sweden). The production of alti-hydro products (water level time series) are improved thanks to the use of water masks. This eases the geo-selection of the CryoSat-2 altimetric measurements since there are acquired from a geodetic orbit and are thus spread along the river course in space and and time. The specific processing of data from this geodetic orbit space

Water Dynamics in Gyroid Phases of Self-Assembled Gemini Surfactants

DOE PAGES

Roy, Santanu; Skoff, David; Perroni, Dominic V.; ...

2016-02-14

Water-mediated ion transport through functional nanoporous materials depends on the dynamics of water confined within a given nanostructured morphology. In this study, we investigate hydrogen-bonding dynamics of interfacial water within a ‘normal’ (Type I) lyotropic gyroid phase formed by a gemini dicarboxylate surfactant self-assembly using a combina- tion of 2DIR spectroscopy and molecular dynamics simulations. Experiments and simulations demonstrate that water dynamics in the normal gyroid phase is one order of magnitude slower than that in bulk water, due to specific interactions between water, the ionic surfactant headgroups, and counterions. However, the dynamics of water in the normal gyroid phasemore » are faster than those of water confined in a reverse spherical micelle of a sulfonate surfactant, given that the water pool in the reverse micelle and the water pore in the gyroid phase have roughly the same diameters. This difference in confined water dynamics likely arises from the significantly reduced curvature- induced frustration at the convex interfaces of the normal gyroid, as compared to the concave interfaces of a reverse spherical micelle. These detailed insights into confined water dynamics may guide the future design of artificial membranes that rapidly transport protons and other ions.« less

Real time processor for array speckle interferometry

NASA Astrophysics Data System (ADS)

Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

1989-02-01

The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

Real time processor for array speckle interferometry

NASA Technical Reports Server (NTRS)

Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

1989-01-01

The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

Advanced Multiple Processor Configuration Study. Final Report.

ERIC Educational Resources Information Center

Clymer, S. J.

This summary of a study on multiple processor configurations includes the objectives, background, approach, and results of research undertaken to provide the Air Force with a generalized model of computer processor combinations for use in the evaluation of proposed flight training simulator computational designs. An analysis of a real-time flight…

Noncoherent parallel optical processor for discrete two-dimensional linear transformations.

PubMed

Glaser, I

1980-10-01

We describe a parallel optical processor, based on a lenslet array, that provides general linear two-dimensional transformations using noncoherent light. Such a processor could become useful in image- and signal-processing applications in which the throughput requirements cannot be adequately satisfied by state-of-the-art digital processors. Experimental results that illustrate the feasibility of the processor by demonstrating its use in parallel optical computation of the two-dimensional Walsh-Hadamard transformation are presented.

Software-Reconfigurable Processors for Spacecraft

NASA Technical Reports Server (NTRS)

Farrington, Allen; Gray, Andrew; Bell, Bryan; Stanton, Valerie; Chong, Yong; Peters, Kenneth; Lee, Clement; Srinivasan, Jeffrey

2005-01-01

A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

A Medical Language Processor for Two Indo-European Languages

PubMed Central

Nhan, Ngo Thanh; Sager, Naomi; Lyman, Margaret; Tick, Leo J.; Borst, François; Su, Yun

1989-01-01

The syntax and semantics of clinical narrative across Indo-European languages are quite similar, making it possible to envison a single medical language processor that can be adapted for different European languages. The Linguistic String Project of New York University is continuing the development of its Medical Language Processor in this direction. The paper describes how the processor operates on English and French.

Application Driven Self-Assembly of Discrete, Three-Dimensional Architectures in Water.

PubMed

Taylor, Lauren; Riddell, Imogen; Smulders, Maarten M J

2018-06-25

In this review we discuss the recent advances in the construction of discrete, self-assembled architectures in water, a field that has gained significant interest in recent years because of the wide range of applications that arises from their well-defined 3D structure. We jointly discuss the efforts undertaken by supramolecular chemists and biotechnologists who previously worked independently to overcome discipline-specific challenges associated with construction of assemblies from synthetic and bio-derived components, respectively. We propose that going forward a more interdisciplinary research approach will expedite development of both synthetic and bio-derived complexes with real-world applications that exploit the benefits of compartmentalisation. In support of this, we summarise advances made in the development of discrete, water-soluble architectures, paying particular attention to their current and prospective applications. We also highlight keys areas where understanding and methodologies developed in the field of synthetic supramolecular chemistry can be integrated into the field of biotechnology and vice versa, in anticipation this will yield advances not possible from either field alone. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Substrateless Welding of Self-Assembled Silver Nanowires at Air/Water Interface.

PubMed

Hu, Hang; Wang, Zhongyong; Ye, Qinxian; He, Jiaqing; Nie, Xiao; He, Gufeng; Song, Chengyi; Shang, Wen; Wu, Jianbo; Tao, Peng; Deng, Tao

2016-08-10

Integrating connected silver nanowire networks with flexible polymers has appeared as a popular way to prepare flexible electronics. To reduce the contact resistance and enhance the connectivity between silver nanowires, various welding techniques have been developed. Herein, rather than welding on solid supporting substrates, which often requires complicated transferring operations and also may pose damage to heat-sensitive substrates, we report an alternative approach to prepare easily transferrable conductive networks through welding of self-assembled silver nanowires at the air/water interface using plasmonic heating. The intriguing welding behavior of partially aligned silver nanowires was analyzed with combined experimental observation and theoretical modeling. The underlying water not only physically supports the assembled silver nanowires but also buffers potential overheating during the welding process, thereby enabling effective welding within a broad range of illumination power density and illumination duration. The welded networks could be directly integrated with PDMS substrates to prepare high-performance stable flexible heaters that are stretchable, bendable, and can be easily patterned to explore selective heating applications.

Methanation assembly using multiple reactors

DOEpatents

Jahnke, Fred C.; Parab, Sanjay C.

2007-07-24

A methanation assembly for use with a water supply and a gas supply containing gas to be methanated in which a reactor assembly has a plurality of methanation reactors each for methanating gas input to the assembly and a gas delivery and cooling assembly adapted to deliver gas from the gas supply to each of said methanation reactors and to combine water from the water supply with the output of each methanation reactor being conveyed to a next methanation reactor and carry the mixture to such next methanation reactor.

Baseband processor development for the Advanced Communications Satellite Program

NASA Technical Reports Server (NTRS)

Moat, D.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

Formation of Supramolecular Nanotubes by Self-assembly of a Phosphate-linked Dimeric Anthracene in Water.

PubMed

Yu, Hao; Sabetti, Mattia; Häner, Robert

2018-04-16

The assembly of supramolecular polymers from a phosphodiester-linked dimeric anthracene is described. AFM and TEM imaging reveals that the supramolecular polymers self-assemble into nanotubes in water. Subsequent photodimerization experiments indicate that the supramolecular polymerization occurs via end-to-end stacking rather than an interdigitation arrangement of the building blocks. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Air-Lubricated Thermal Processor For Dry Silver Film

NASA Astrophysics Data System (ADS)

Siryj, B. W.

1980-09-01

Since dry silver film is processed by heat, it may be viewed on a light table only seconds after exposure. On the other hand, wet films require both bulky chemicals and substantial time before an image can be analyzed. Processing of dry silver film, although simple in concept, is not so simple when reduced to practice. The main concern is the effect of film temperature gradients on uniformity of optical film density. RCA has developed two thermal processors, different in implementation but based on the same philosophy. Pressurized air is directed to both sides of the film to support the film and to conduct the heat to the film. Porous graphite is used as the medium through which heat and air are introduced. The initial thermal processor was designed to process 9.5-inch-wide film moving at speeds ranging from 0.0034 to 0.008 inch per second. The processor configuration was curved to match the plane generated by the laser recording beam. The second thermal processor was configured to process 5-inch-wide film moving at a continuously variable rate ranging from 0.15 to 3.5 inches per second. Due to field flattening optics used in this laser recorder, the required film processing area was plane. In addition, this processor was sectioned in the direction of film motion, giving the processor the capability of varying both temperature and effective processing area.

Automatic film processors' quality control test in Greek military hospitals.

PubMed

Lymberis, C; Efstathopoulos, E P; Manetou, A; Poudridis, G

1993-04-01

The two major military radiology installations (Athens, Greece) using a total of 15 automatic film processors were assessed using the 21-step-wedge method. The results of quality control in all these processors are presented. The parameters measured under actual working conditions were base and fog, contrast and speed. Base and fog as well as speed displayed large variations with average values generally higher than acceptable, whilst contrast displayed greater stability. Developer temperature was measured daily during the test and was found to be outside the film manufacturers' recommended limits in nine of the 15 processors. In only one processor did film passing time vary on an every day basis and this was due to maloperation. Developer pH test was not part of the daily monitoring service being performed every 5 days for each film processor and found to be in the range 9-12; 10 of the 15 processors presented pH values outside the limits specified by the film manufacturers.

Using the Word Processor in Writing Groups.

ERIC Educational Resources Information Center

Melia, Josie

Writing groups can use word processors or microcomputers in many different types of writing activities. Four hour-long sessions at a word processor with the help of a skilled word processing tutor have been found to be sufficient to provide a working knowledge of word processing. When two or three students enrolled in a writing class are assigned…

Geospace simulations on the Cell BE processor

NASA Astrophysics Data System (ADS)

Germaschewski, K.; Raeder, J.; Larson, D.

2008-12-01

OpenGGCM (Open Geospace General circulation Model) is an established numerical code that simulates the Earth's space environment. The most computing intensive part is the MHD (magnetohydrodynamics) solver that models the plasma surrounding Earth and its interaction with Earth's magnetic field and the solar wind flowing in from the sun. Like other global magnetosphere codes, OpenGGCM's realism is limited by computational constraints on grid resolution. We investigate porting of the MHD solver to the Cell BE architecture, a novel inhomogeneous multicore architecture capable of up to 230 GFlops per processor. Realizing this high performance on the Cell processor is a programming challenge, though. We implemented the MHD solver using a multi-level parallel approach: On the coarsest level, the problem is distributed to processors based upon the usual domain decomposition approach. Then, on each processor, the problem is divided into 3D columns, each of which is handled by the memory limited SPEs (synergistic processing elements) slice by slice. Finally, SIMD instructions are used to fully exploit the vector/SIMD FPUs in each SPE. Memory management needs to be handled explicitly by the code, using DMA to move data from main memory to the per-SPE local store and vice versa. We obtained excellent performance numbers, a speed-up of a factor of 25 compared to just using the main processor, while still keeping the numerical implementation details of the code maintainable.

Development of a soldier-portable fuel cell power system. Part I: A bread-board methanol fuel processor

NASA Astrophysics Data System (ADS)

Palo, Daniel R.; Holladay, Jamie D.; Rozmiarek, Robert T.; Guzman-Leong, Consuelo E.; Wang, Yong; Hu, Jianli; Chin, Ya-Huei; Dagle, Robert A.; Baker, Eddie G.

A 15-W e portable power system is being developed for the US Army that consists of a hydrogen-generating fuel reformer coupled to a proton-exchange membrane fuel cell. In the first phase of this project, a methanol steam reformer system was developed and demonstrated. The reformer system included a combustor, two vaporizers, and a steam reforming reactor. The device was demonstrated as a thermally independent unit over the range of 14-80 W t output. Assuming a 14-day mission life and an ultimate 1-kg fuel processor/fuel cell assembly, a base case was chosen to illustrate the expected system performance. Operating at 13 W e, the system yielded a fuel processor efficiency of 45% (LHV of H 2 out/LHV of fuel in) and an estimated net efficiency of 22% (assuming a fuel cell efficiency of 48%). The resulting energy density of 720 Wh/kg is several times the energy density of the best lithium-ion batteries. Some immediate areas of improvement in thermal management also have been identified, and an integrated fuel processor is under development. The final system will be a hybrid, containing a fuel reformer, a fuel cell, and a rechargeable battery. The battery will provide power for start-up and added capacity for times of peak power demand.

Ordered Nanostructured Amphiphile Self-Assembly Materials from Endogenous Nonionic Unsaturated Monoethanolamide Lipids in Water

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sagnella, Sharon M.; Conn, Charlotte E.; Krodkiewska, Irena

2010-08-23

The self-assembly, solid state and lyotropic liquid crystalline phase behavior of a series of endogenous n-acylethanolamides (NAEs) with differing degrees of unsaturation, viz., oleoyl monoethanolamide, linoleoyl monoethanolamide, and linolenoyl monoethanolamide, have been examined. The studied molecules are known to possess inherent biological function. Both the monoethanolamide headgroup and the unsaturated hydrophobe are found to be important in dictating the self-assembly behavior of these molecules. In addition, all three molecules form lyotropic liquid crystalline phases in water, including the inverse bicontinuous cubic diamond (Q{sub II}{sup D}) and gyroid (Q{sub II}{sup G}) phases. The ability of the NAE's to form inverse cubicmore » phases and to be dispersed into ordered nanostructured colloidal particles, cubosomes, in excess water, combined with their endogenous nature and natural medicinal properties, makes this new class of soft mesoporous amphiphile self-assembly materials suitable candidates for investigation in a variety of advanced multifunctional applications, including encapsulation and controlled release of therapeutic agents and incorporation of medical imaging agents.« less

Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

NASA Astrophysics Data System (ADS)

Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

2013-03-01

With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

Optical backplane interconnect switch for data processors and computers

NASA Technical Reports Server (NTRS)

Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

1989-01-01

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

Adsorption at air-water and oil-water interfaces and self-assembly in aqueous solution of ethoxylated polysorbate nonionic surfactants.

PubMed

Penfold, Jeffrey; Thomas, Robert K; Li, Peixun X; Petkov, Jordan T; Tucker, Ian; Webster, John R P; Terry, Ann E

2015-03-17

The Tween nonionic surfactants are ethoxylated sorbitan esters, which have 20 ethylene oxide groups attached to the sorbitan headgroup and a single alkyl chain, lauryl, palmityl, stearyl, or oleyl. They are an important class of surfactants that are extensively used in emulsion and foam stabilization and in applications associated with foods, cosmetics and pharmaceuticals. A range of ethoxylated polysorbate surfactants, with differing degrees of ethoxylation from 3 to 50 ethylene oxide groups, have been synthesized and characterized by neutron reflection, small-angle neutron scattering, and surface tension. In conjunction with different alkyl chain groups, this provides the opportunity to modify their surface properties, their self-assembly in solution, and their interaction with macromolecules, such as proteins. Adsorption at the air-water and oil-water interfaces and solution self-assembly of the range of ethoxylated polysorbate surfactants synthesized are presented and discussed.

Reversible assembly of magnetized particles: Application to water-borne pathogen enumeration

NASA Astrophysics Data System (ADS)

Ramadan, Qasem

2009-12-01

Reversible assembly of magnetized particles and cells has been proposed and implemented. The approach is based on magnetized particles or magnetically labeled cell immobilization in an array of individual particle/cell for optical counting. The device has been tested for few types of magnetic particles and one water-borne pathogen: Giardia Lamblia. An individual particle immobilization efficiency of 92% was achieved.

Accelerating molecular dynamic simulation on the cell processor and Playstation 3.

PubMed

Luttmann, Edgar; Ensign, Daniel L; Vaidyanathan, Vishal; Houston, Mike; Rimon, Noam; Øland, Jeppe; Jayachandran, Guha; Friedrichs, Mark; Pande, Vijay S

2009-01-30

Implementation of molecular dynamics (MD) calculations on novel architectures will vastly increase its power to calculate the physical properties of complex systems. Herein, we detail algorithmic advances developed to accelerate MD simulations on the Cell processor, a commodity processor found in PlayStation 3 (PS3). In particular, we discuss issues regarding memory access versus computation and the types of calculations which are best suited for streaming processors such as the Cell, focusing on implicit solvation models. We conclude with a comparison of improved performance on the PS3's Cell processor over more traditional processors. (c) 2008 Wiley Periodicals, Inc.

An Efficient Functional Test Generation Method For Processors Using Genetic Algorithms

NASA Astrophysics Data System (ADS)

Hudec, Ján; Gramatová, Elena

2015-07-01

The paper presents a new functional test generation method for processors testing based on genetic algorithms and evolutionary strategies. The tests are generated over an instruction set architecture and a processor description. Such functional tests belong to the software-oriented testing. Quality of the tests is evaluated by code coverage of the processor description using simulation. The presented test generation method uses VHDL models of processors and the professional simulator ModelSim. The rules, parameters and fitness functions were defined for various genetic algorithms used in automatic test generation. Functionality and effectiveness were evaluated using the RISC type processor DP32.

Multi-scale interactions between local hydrography, seabed topography, and community assembly on cold-water coral reefs

NASA Astrophysics Data System (ADS)

Henry, L.-A.; Moreno Navas, J.; Roberts, J. M.

2013-04-01

We investigated how interactions between hydrography, topography and species ecology influence the assembly of species and functional traits across multiple spatial scales of a cold-water coral reef seascape. In a novel approach for these ecosystems, we used a spatially resolved complex three-dimensional flow model of hydrography to help explain assembly patterns. Forward-selection of distance-based Moran's eigenvector mapping (dbMEM) variables identified two submodels of spatial scales at which communities change: broad-scale (across reef) and fine-scale (within reef). Variance partitioning identified bathymetric and hydrographic gradients important in creating broad-scale assembly of species and traits. In contrast, fine-scale assembly was related more to processes that created spatially autocorrelated patches of fauna, such as philopatric recruitment in sessile fauna, and social interactions and food supply in scavenging detritivores and mobile predators. Our study shows how habitat modification of reef connectivity and hydrography by bottom fishing and renewable energy installations could alter the structure and function of an entire cold-water coral reef seascape.

Water-induced nanochannel networks in self-assembled block ionomers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mineart, Kenneth P.; Al-Mohsin, Heba A.; Lee, Byeongdu

2016-03-07

Block ionomers cast from solution exhibit solvent-templated morphologies that can be altered by solvent-vapor annealing. When cast from a mixed solvent, a midblock-sulfonated pentablock ion- omer self-assembles into spherical ionic microdomains that are loosely connected. Upon exposure to liquid water, nanoscale channels irreversibly develop between the microdomains due to swelling and form a continuous mesoscale network. We use electron tomography and real-time X-ray scat- tering to follow this transformation and show that the resultant morphology provides a highly effec- tive diffusive pathway.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

NASA Astrophysics Data System (ADS)

Barr, David R. W.; Dudek, Piotr

2009-12-01

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

Flood replenishment: a new method of processor control.

PubMed

Frank, E D; Gray, J E; Wilken, D A

1980-01-01

In mechanized radiographic film processors that process medium to low volumes of film, roll films, and those that process single-emulsion films from nuclear medicine scans, computed tomography, and ultrasound, it is difficult to maintain the developer solution at a stable processing level. We describe our experience using flood replenishment, which is a method in which developer replenisher containing starter solution is introduced in the processor at timed intervals, independent of the number of films being processed. By this process, a stable level of developer activity is maintained in a processor used to develop a medium to low volume of single-emulsion film.

Control structures for high speed processors

NASA Technical Reports Server (NTRS)

Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

1982-01-01

A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

Graphics Processor Units (GPUs)

NASA Technical Reports Server (NTRS)

Wyrwas, Edward J.

2017-01-01

This presentation will include information about Graphics Processor Units (GPUs) technology, NASA Electronic Parts and Packaging (NEPP) tasks, The test setup, test parameter considerations, lessons learned, collaborations, a roadmap, NEPP partners, results to date, and future plans.

Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

NASA Technical Reports Server (NTRS)

Downie, John D.; Goodman, Joseph W.

1989-01-01

The accuracy requirements of optical processors in adaptive optics systems are determined by estimating the required accuracy in a general optical linear algebra processor (OLAP) that results in a smaller average residual aberration than that achieved with a conventional electronic digital processor with some specific computation speed. Special attention is given to an error analysis of a general OLAP with regard to the residual aberration that is created in an adaptive mirror system by the inaccuracies of the processor, and to the effect of computational speed of an electronic processor on the correction. Results are presented on the ability of an OLAP to compete with a digital processor in various situations.

SPROC: A multiple-processor DSP IC

NASA Technical Reports Server (NTRS)

Davis, R.

1991-01-01

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Fault tolerant, radiation hard, high performance digital signal processor

NASA Technical Reports Server (NTRS)

Holmann, Edgar; Linscott, Ivan R.; Maurer, Michael J.; Tyler, G. L.; Libby, Vibeke

1990-01-01

An architecture has been developed for a high-performance VLSI digital signal processor that is highly reliable, fault-tolerant, and radiation-hard. The signal processor, part of a spacecraft receiver designed to support uplink radio science experiments at the outer planets, organizes the connections between redundant arithmetic resources, register files, and memory through a shuffle exchange communication network. The configuration of the network and the state of the processor resources are all under microprogram control, which both maps the resources according to algorithmic needs and reconfigures the processing should a failure occur. In addition, the microprogram is reloadable through the uplink to accommodate changes in the science objectives throughout the course of the mission. The processor will be implemented with silicon compiler tools, and its design will be verified through silicon compilation simulation at all levels from the resources to full functionality. By blending reconfiguration with redundancy the processor implementation is fault-tolerant and reliable, and possesses the long expected lifetime needed for a spacecraft mission to the outer planets.

Monolayers of the lipid derivatives of isoniazid at the air/water interface and the formation of self-assembled nanostructures in water.

PubMed

Jin, Yiguang; Chen, Shufeng; Xin, Rui; Zhou, Yisheng

2008-07-15

Isoniazid (INH, isonicotinic acid hydrazide) is one of the most commonly used anti-tubercular drugs. However, resistance of Mycobacterium tuberculosis strains to anti-mycobacterial agents including INH is an increasing problem worldwide. Development of new anti-mycobacterial agents thus has attracted attention. Five lipid derivatives of INH were prepared in this study. They formed monolayers at the air/water interface, and some nanostructures with different morphologies were obtained through molecular self-assembly in water. The derivatives included one fatty acyl derivative containing a 12-C hydrocarbon-long chain (1), three fatty alcohol derivatives with a succinyl as spacer and an 8, 12 or 16-C hydrocarbon-long chain (2, 3 and 4), and one tetrahydro-2H-1,3,5-thiadiazine-2-thione (THTT) derivative containing a 12-C hydrocarbon-long chain (5). The surface pressure-area isotherms depended on the volume and configuration of heads and the length of tails of derivatives. Compound 2 had a relatively large head and a short tail, easily standing uprightly at the interface. Under a certain surface pressure, the linear polar head groups of 3 could be partly squeezed out and insert into subphase because the length of heads were comparable to the one of tails. The very long tails of 4 always maintained above the interface and led to a high collapse pressure. Compound 5 possessed an extended and large head consisting of the THTT and INH groups so that the relatively short tails tilted at the interface and difficultly contact with each other. The THTT rings might be partly squeezed out and enter into air under a certain surface pressure. The self-assembly behaviours of derivatives in water depended on the molecular configuration and agreed with the corresponding monolayer behaviours. The flexible and medium-long tails (1 and 3) led to the derivatives to form nanoscale vesicles, though the short or very long tails did not (2 and 4). Interestingly, intermolecular hydrogen

ISS Potable Water Sampling and Chemical Analysis Results for 2016

NASA Technical Reports Server (NTRS)

Straub, John E., II; Plumlee, Debrah K.; Wallace William T.; Alverson, James T.; Benoit, Mickie J.; Gillispie, Robert L.; Hunter, David; Kuo, Mike; Rutz, Jeffrey A.; Hudson, Edgar K.;

ISS Potable Water Sampling and Chemical Analysis Results for 2016

NASA Technical Reports Server (NTRS)

Straub, John E., II; Plumlee, Debrah K.; Wallace, William T.; Alverson, James T.; Benoit, Mickie J.; Gillispie, Robert L.; Hunter, David; Kuo, Mike; Rutz, Jeffrey A.; Hudson, Edgar K.;

Processing techniques for software based SAR processors

NASA Technical Reports Server (NTRS)

Leung, K.; Wu, C.

1983-01-01

Software SAR processing techniques defined to treat Shuttle Imaging Radar-B (SIR-B) data are reviewed. The algorithms are devised for the data processing procedure selection, SAR correlation function implementation, multiple array processors utilization, cornerturning, variable reference length azimuth processing, and range migration handling. The Interim Digital Processor (IDP) originally implemented for handling Seasat SAR data has been adapted for the SIR-B, and offers a resolution of 100 km using a processing procedure based on the Fast Fourier Transformation fast correlation approach. Peculiarities of the Seasat SAR data processing requirements are reviewed, along with modifications introduced for the SIR-B. An Advanced Digital SAR Processor (ADSP) is under development for use with the SIR-B in the 1986 time frame as an upgrade for the IDP, which will be in service in 1984-5.

Construction and Self-Assembly of Single-Chain Polymer Nanoparticles via Coordination Association and Electrostatic Repulsion in Water.

PubMed

Zhu, Zhengguang; Xu, Na; Yu, Qiuping; Guo, Lei; Cao, Hui; Lu, Xinhua; Cai, Yuanli

2015-08-01

Simultaneous coordination-association and electrostatic-repulsion interactions play critical roles in the construction and stabilization of enzymatic function metal centers in water media. These interactions are promising for construction and self-assembly of artificial aqueous polymer single-chain nanoparticles (SCNPs). Herein, the construction and self-assembly of dative-bonded aqueous SCNPs are reported via simultaneous coordination-association and electrostatic-repulsion interactions within single chains of histamine-based hydrophilic block copolymer. The electrostatic-repulsion interactions are tunable through adjusting the imidazolium/imidazole ratio in response to pH, and in situ Cu(II)-coordination leads to the intramolecular association and single-chain collapse in acidic water. SCNPs are stabilized by the electrostatic repulsion of dative-bonded block and steric shielding of nonionic water-soluble block, and have a huge specific surface area of function metal centers accessible to substrates in acidic water. Moreover, SCNPs can assemble into micelles, networks, and large particles programmably in response to the solution pH. These unique media-sensitive phase-transformation behaviors provide a general, facile, and versatile platform for the fabrication of enzyme-inspired smart aqueous catalysts. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Analysis of a water moderated critical assembly with anisn-Vitamin C

DOE Office of Scientific and Technical Information (OSTI.GOV)

Green, L.

1979-03-01

A tightly packed water moderated /sup 233/UO/sub 2/--ThO/sub 2/ critical assembly was analyzed with the Vitamin C library and the 1-D S/s n/ code, ANISN (S/sub 8/,P/sub 3/). The purpose of the study was to provide validation of this calculational model as applied to water-cooled hybrid fusion blankets. The quantities compared were the core eigenvalue and various activation shapes. The calculated eigenvalue was 1.02 +- 0.01. The /sup 233/U fission and /sup 232/Th capture shapes were found to be in good agreement (+-5%) with experiment, except near water--metal boundaries where differences up to 24% were observed. No such error peakingmore » was observed in the /sup 232/Th fast fission shape. We conclude that the model provides good volume averaged reaction rates in water-cooled systems. However, care must be exercised near water boundaries where thermally dependent reaction rates are significantly underestimated.« less

Measuring spent fuel assembly multiplication in borated water with a passive neutron albedo reactivity instrument

NASA Astrophysics Data System (ADS)

Tobin, Stephen J.; Peura, Pauli; Bélanger-Champagne, Camille; Moring, Mikael; Dendooven, Peter; Honkamaa, Tapani

2018-07-01

The performance of a passive neutron albedo reactivity (PNAR) instrument to measure neutron multiplication of spent nuclear fuel in borated water is investigated as part of an integrated non-destructive assay safeguards system. To measure the PNAR Ratio, which is proportional to the neutron multiplication, the total neutron count rate is measured in high- and low-multiplying environments by the PNAR instrument. The integrated system also contains a load cell and a passive gamma emission tomograph, and as such meets all the recommendations of the IAEA's recent ASTOR Experts Group report. A virtual spent fuel library for VVER-440 fuel was used in conjunction with MCNP simulations of the PNAR instrument to estimate the measurement uncertainties from (1) variation in the water boron content, (2) assembly positioning in the detector and (3) counting statistics. The estimated aggregate measurement uncertainty on the PNAR Ratio measurement is 0.008, to put this uncertainty in context, the difference in the PNAR Ratio between a fully irradiated assembly and this same assembly when fissile isotopes only absorb neutrons, but do not emit neutrons, is 0.106, a 13-sigma effect. The 1-sigma variation of 0.008 in the PNAR Ratio is estimated to correspond to a 3.2 GWd/tU change in assembly burnup.

The emerging conceptualization of groups as information processors.

PubMed

Hinsz, V B; Tindale, R S; Vollrath, D A

1997-01-01

A selective review of research highlights the emerging view of groups as information processors. In this review, the authors include research on processing objectives, attention, encoding, storage, retrieval, processing, response, feedback, and learning in small interacting task groups. The groups as information processors perspective underscores several characteristic dimensions of variability in group performance of cognitive tasks, namely, commonality-uniqueness of information, convergence-diversity of ideas, accentuation-attenuation of cognitive processes, and belongingness-distinctiveness of members. A combination of contributions framework provides an additional conceptualization of information processing in groups. The authors also address implications, caveats, and questions for future research and theory regarding groups as information processors.

Multitask neurovision processor with extensive feedback and feedforward connections

NASA Astrophysics Data System (ADS)

Gupta, Madan M.; Knopf, George K.

1991-11-01

A multi-task neuro-vision parameter which performs a variety of information processing operations associated with the early stages of biological vision is presented. The network architecture of this neuro-vision processor, called the positive-negative (PN) neural processor, is loosely based on the neural activity fields exhibited by thalamic and cortical nervous tissue layers. The computational operation performed by the processor arises from the strength of the recurrent feedback among the numerous positive and negative neural computing units. By adjusting the feedback connections it is possible to generate diverse dynamic behavior that may be used for short-term visual memory (STVM), spatio-temporal filtering (STF), and pulse frequency modulation (PFM). The information attributes that are to be processes may be regulated by modifying the feedforward connections from the signal space to the neural processor.

Software-defined reconfigurable microwave photonics processor.

PubMed

Pérez, Daniel; Gasulla, Ivana; Capmany, José

2015-06-01

We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

Ssip-a processor interconnection simulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Navaux, P.; Weber, R.; Prezzi, J.

1982-01-01

Recent growing interest in multiple processor architectures has given rise to the study of procesor-memory interconnections for the determination of better architectures. This paper concerns the development of the SSIP-sistema simulador de interconexao de processadores (processor interconnection simulating system) which allows the evaluation of different interconnection structures comparing its performance in order to provide parameters which would help the designer to define an architcture. A wide spectrum of systems may be evaluated, and their behaviour observed due to the features incorporated into the simulator program. The system modelling and the simulator program implementation are described. Some results that can bemore » obtained are shown, along with the discussion of their usefulness. 12 references.« less

High-performance ultra-low power VLSI analog processor for data compression

NASA Technical Reports Server (NTRS)

Tawel, Raoul (Inventor)

1996-01-01

An apparatus for data compression employing a parallel analog processor. The apparatus includes an array of processor cells with N columns and M rows wherein the processor cells have an input device, memory device, and processor device. The input device is used for inputting a series of input vectors. Each input vector is simultaneously input into each column of the array of processor cells in a pre-determined sequential order. An input vector is made up of M components, ones of which are input into ones of M processor cells making up a column of the array. The memory device is used for providing ones of M components of a codebook vector to ones of the processor cells making up a column of the array. A different codebook vector is provided to each of the N columns of the array. The processor device is used for simultaneously comparing the components of each input vector to corresponding components of each codebook vector, and for outputting a signal representative of the closeness between the compared vector components. A combination device is used to combine the signal output from each processor cell in each column of the array and to output a combined signal. A closeness determination device is then used for determining which codebook vector is closest to an input vector from the combined signals, and for outputting a codebook vector index indicating which of the N codebook vectors was the closest to each input vector input into the array.

DFT algorithms for bit-serial GaAs array processor architectures

NASA Technical Reports Server (NTRS)

Mcmillan, Gary B.

1988-01-01

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.

International Space Station (ISS)

NASA Image and Video Library

2001-02-01

The Marshall Space Flight Center (MSFC) is responsible for designing and building the life support systems that will provide the crew of the International Space Station (ISS) a comfortable environment in which to live and work. Scientists and engineers at the MSFC are working together to provide the ISS with systems that are safe, efficient, and cost-effective. These compact and powerful systems are collectively called the Environmental Control and Life Support Systems, or simply, ECLSS. This photograph shows the fifth generation Urine Processor Development Hardware. The Urine Processor Assembly (UPA) is a part of the Water Recovery System (WRS) on the ISS. It uses a chase change process called vapor compression distillation technology to remove contaminants from urine. The UPA accepts and processes pretreated crewmember urine to allow it to be processed along with other wastewaters in the Water Processor Assembly (WPA). The WPA removes free gas, organic, and nonorganic constituents before the water goes through a series of multifiltration beds for further purification. Product water quality is monitored primarily through conductivity measurements. Unacceptable water is sent back through the WPA for reprocessing. Clean water is sent to a storage tank.

Environmental Control and Life Support Systems Testing Facility at MSFC

NASA Technical Reports Server (NTRS)

2001-01-01

The Marshall Space Flight Center (MSFC) is responsible for designing and building the life support systems that will provide the crew of the International Space Station (ISS) a comfortable environment in which to live and work. Scientists and engineers at the MSFC are working together to provide the ISS with systems that are safe, efficient, and cost-effective. These compact and powerful systems are collectively called the Environmental Control and Life Support Systems, or simply, ECLSS. This photograph shows the fifth generation Urine Processor Development Hardware. The Urine Processor Assembly (UPA) is a part of the Water Recovery System (WRS) on the ISS. It uses a chase change process called vapor compression distillation technology to remove contaminants from urine. The UPA accepts and processes pretreated crewmember urine to allow it to be processed along with other wastewaters in the Water Processor Assembly (WPA). The WPA removes free gas, organic, and nonorganic constituents before the water goes through a series of multifiltration beds for further purification. Product water quality is monitored primarily through conductivity measurements. Unacceptable water is sent back through the WPA for reprocessing. Clean water is sent to a storage tank.

Fuel processors for fuel cell APU applications

NASA Astrophysics Data System (ADS)

Aicher, T.; Lenz, B.; Gschnell, F.; Groos, U.; Federici, F.; Caprile, L.; Parodi, L.

The conversion of liquid hydrocarbons to a hydrogen rich product gas is a central process step in fuel processors for auxiliary power units (APUs) for vehicles of all kinds. The selection of the reforming process depends on the fuel and the type of the fuel cell. For vehicle power trains, liquid hydrocarbons like gasoline, kerosene, and diesel are utilized and, therefore, they will also be the fuel for the respective APU systems. The fuel cells commonly envisioned for mobile APU applications are molten carbonate fuel cells (MCFC), solid oxide fuel cells (SOFC), and proton exchange membrane fuel cells (PEMFC). Since high-temperature fuel cells, e.g. MCFCs or SOFCs, can be supplied with a feed gas that contains carbon monoxide (CO) their fuel processor does not require reactors for CO reduction and removal. For PEMFCs on the other hand, CO concentrations in the feed gas must not exceed 50 ppm, better 20 ppm, which requires additional reactors downstream of the reforming reactor. This paper gives an overview of the current state of the fuel processor development for APU applications and APU system developments. Furthermore, it will present the latest developments at Fraunhofer ISE regarding fuel processors for high-temperature fuel cell APU systems on board of ships and aircrafts.

Implementing wavelet inverse-transform processor with surface acoustic wave device.

PubMed

Lu, Wenke; Zhu, Changchun; Liu, Qinghong; Zhang, Jingduan

2013-02-01

The objective of this research was to investigate the implementation schemes of the wavelet inverse-transform processor using surface acoustic wave (SAW) device, the length function of defining the electrodes, and the possibility of solving the load resistance and the internal resistance for the wavelet inverse-transform processor using SAW device. In this paper, we investigate the implementation schemes of the wavelet inverse-transform processor using SAW device. In the implementation scheme that the input interdigital transducer (IDT) and output IDT stand in a line, because the electrode-overlap envelope of the input IDT is identical with the one of the output IDT (i.e. the two transducers are identical), the product of the input IDT's frequency response and the output IDT's frequency response can be implemented, so that the wavelet inverse-transform processor can be fabricated. X-112(0)Y LiTaO(3) is used as a substrate material to fabricate the wavelet inverse-transform processor. The size of the wavelet inverse-transform processor using this implementation scheme is small, so its cost is low. First, according to the envelope function of the wavelet function, the length function of the electrodes is defined, then, the lengths of the electrodes can be calculated from the length function of the electrodes, finally, the input IDT and output IDT can be designed according to the lengths and widths for the electrodes. In this paper, we also present the load resistance and the internal resistance as the two problems of the wavelet inverse-transform processor using SAW devices. The solutions to these problems are achieved in this study. When the amplifiers are subjected to the input end and output end for the wavelet inverse-transform processor, they can eliminate the influence of the load resistance and the internal resistance on the output voltage of the wavelet inverse-transform processor using SAW device. Copyright © 2012 Elsevier B.V. All rights reserved.

A high-accuracy optical linear algebra processor for finite element applications

NASA Technical Reports Server (NTRS)

Casasent, D.; Taylor, B. K.

1984-01-01

Optical linear processors are computationally efficient computers for solving matrix-matrix and matrix-vector oriented problems. Optical system errors limit their dynamic range to 30-40 dB, which limits their accuray to 9-12 bits. Large problems, such as the finite element problem in structural mechanics (with tens or hundreds of thousands of variables) which can exploit the speed of optical processors, require the 32 bit accuracy obtainable from digital machines. To obtain this required 32 bit accuracy with an optical processor, the data can be digitally encoded, thereby reducing the dynamic range requirements of the optical system (i.e., decreasing the effect of optical errors on the data) while providing increased accuracy. This report describes a new digitally encoded optical linear algebra processor architecture for solving finite element and banded matrix-vector problems. A linear static plate bending case study is described which quantities the processor requirements. Multiplication by digital convolution is explained, and the digitally encoded optical processor architecture is advanced.

Specific and reversible DNA-directed self-assembly of oil-in-water emulsion droplets

PubMed Central

Hadorn, Maik; Boenzli, Eva; Sørensen, Kristian T.; Fellermann, Harold; Eggenberger Hotz, Peter; Hanczyc, Martin M.

2012-01-01

Higher-order structures that originate from the specific and reversible DNA-directed self-assembly of microscopic building blocks hold great promise for future technologies. Here, we functionalized biotinylated soft colloid oil-in-water emulsion droplets with biotinylated single-stranded DNA oligonucleotides using streptavidin as an intermediary linker. We show the components of this modular linking system to be stable and to induce sequence-specific aggregation of binary mixtures of emulsion droplets. Three length scales were thereby involved: nanoscale DNA base pairing linking microscopic building blocks resulted in macroscopic aggregates visible to the naked eye. The aggregation process was reversible by changing the temperature and electrolyte concentration and by the addition of competing oligonucleotides. The system was reset and reused by subsequent refunctionalization of the emulsion droplets. DNA-directed self-assembly of oil-in-water emulsion droplets, therefore, offers a solid basis for programmable and recyclable soft materials that undergo structural rearrangements on demand and that range in application from information technology to medicine. PMID:23175791

Satellite on-board real-time SAR processor prototype

NASA Astrophysics Data System (ADS)

Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François

2017-11-01

A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and

Radio astronomy Explorer B antenna aspect processor

NASA Technical Reports Server (NTRS)

Miller, W. H.; Novello, J.; Reeves, C. C.

1972-01-01

The antenna aspect system used on the Radio Astronomy Explorer B spacecraft is described. This system consists of two facsimile cameras, a data encoder, and a data processor. Emphasis is placed on the discussion of the data processor, which contains a data compressor and a source encoder. With this compression scheme a compression ratio of 8 is achieved on a typical line of camera data. These compressed data are then convolutionally encoded.

Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

DOEpatents

Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

2009-03-17

A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

Optimal partitioning of random programs across two processors

NASA Technical Reports Server (NTRS)

Nicol, D. M.

1986-01-01

The optimal partitioning of random distributed programs is discussed. It is concluded that the optimal partitioning of a homogeneous random program over a homogeneous distributed system either assigns all modules to a single processor, or distributes the modules as evenly as possible among all processors. The analysis rests heavily on the approximation which equates the expected maximum of a set of independent random variables with the set's maximum expectation. The results are strengthened by providing an approximation-free proof of this result for two processors under general conditions on the module execution time distribution. It is also shown that use of this approximation causes two of the previous central results to be false.

CoNNeCT Baseband Processor Module

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K; Jedrey, Thomas C.; Gutrich, Daniel G.; Goodpasture, Richard L.

2011-01-01

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

International Space Station (ISS) Advanced Recycle Filter Tank Assembly (ARFTA)

NASA Technical Reports Server (NTRS)

Nasrullah, Mohammed K.

2013-01-01

The International Space Station (ISS) Recycle Filter Tank Assembly (RFTA) provides the following three primary functions for the Urine Processor Assembly (UPA): volume for concentrating/filtering pretreated urine, filtration of product distillate, and filtration of the Pressure Control and Pump Assembly (PCPA) effluent. The RFTAs, under nominal operations, are to be replaced every 30 days. This poses a significant logistical resupply problem, as well as cost in upmass and new tanks purchase. In addition, it requires significant amount of crew time. To address and resolve these challenges, NASA required Boeing to develop a design which eliminated the logistics and upmass issues and minimize recurring costs. Boeing developed the Advanced Recycle Filter Tank Assembly (ARFTA) that allowed the tanks to be emptied on-orbit into disposable tanks that eliminated the need for bringing the fully loaded tanks to earth for refurbishment and relaunch, thereby eliminating several hundred pounds of upmass and its associated costs. The ARFTA will replace the RFTA by providing the same functionality, but with reduced resupply requirements

A high capacity data recording device based on a digital audio processor and a video cassette recorder.

PubMed

Bezanilla, F

1985-03-01

A modified digital audio processor, a video cassette recorder, and some simple added circuitry are assembled into a recording device of high capacity. The unit converts two analog channels into digital form at 44-kHz sampling rate and stores the information in digital form in a common video cassette. Bandwidth of each channel is from direct current to approximately 20 kHz and the dynamic range is close to 90 dB. The total storage capacity in a 3-h video cassette is 2 Gbytes. The information can be retrieved in analog or digital form.

A high capacity data recording device based on a digital audio processor and a video cassette recorder.

PubMed Central

Bezanilla, F

1985-01-01

A modified digital audio processor, a video cassette recorder, and some simple added circuitry are assembled into a recording device of high capacity. The unit converts two analog channels into digital form at 44-kHz sampling rate and stores the information in digital form in a common video cassette. Bandwidth of each channel is from direct current to approximately 20 kHz and the dynamic range is close to 90 dB. The total storage capacity in a 3-h video cassette is 2 Gbytes. The information can be retrieved in analog or digital form. PMID:3978213

Performance of the Cell processor for biomolecular simulations

NASA Astrophysics Data System (ADS)

De Fabritiis, G.

2007-06-01

The new Cell processor represents a turning point for computing intensive applications. Here, I show that for molecular dynamics it is possible to reach an impressive sustained performance in excess of 30 Gflops with a peak of 45 Gflops for the non-bonded force calculations, over one order of magnitude faster than a single core standard processor.

Concept of a programmable maintenance processor applicable to multiprocessing systems

NASA Technical Reports Server (NTRS)

Glover, Richard D.

1988-01-01

A programmable maintenance processor concept applicable to multiprocessing systems has been developed at the NASA Ames Research Center's Dryden Flight Research Facility. This stand-alone-processor is intended to provide support for system and application software testing as well as hardware diagnostics. An initial machanization has been incorporated into the extended aircraft interrogation and display system (XAIDS) which is multiprocessing general-purpose ground support equipment. The XAIDS maintenance processor has independent terminal and printer interfaces and a dedicated magnetic bubble memory that stores system test sequences entered from the terminal. This report describes the hardware and software embodied in this processor and shows a typical application in the check-out of a new XAIDS.

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Optoelectronic processors with scanning CCD photodetectors

NASA Astrophysics Data System (ADS)

Esepkina, N. A.; Lavrov, A. P.; Anan'ev, M. N.; Blagodarnyi, V. S.; Ivanov, S. I.; Mansyrev, M. I.; Molodyakov, S. A.

1995-10-01

Two new types of optoelectronic radio-signal processors were investigated. Charge-coupled device (CCD) photodetectors are used in these processors under continuous scanning conditions, i.e. in a time delay and storage mode. One of these processors is based on a CCD photodetector array with a reference-signal amplitude transparency and the other is an adaptive acousto-optical signal processor with linear frequency modulation. The processor with the transparency performs multichannel discrete—analogue convolution of an input signal with a corresponding kernel of the transformation determined by the transparency. If a light source is an array of light-emitting diodes of special (stripe) geometry, the optical stages of the processor can be made from optical fibre components and the whole processor then becomes a rigid 'sandwich' (a compact hybrid optoelectronic microcircuit). A report is given also of a study of a prototype processor with optical fibre components for the reception of signals from a system with antenna aperture synthesis, which forms a radio image of the Earth.

Reconfigurable signal processor designs for advanced digital array radar systems

NASA Astrophysics Data System (ADS)

Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

2017-05-01

The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

Implementation and Assessment of Advanced Analog Vector-Matrix Processor

NASA Technical Reports Server (NTRS)

Gary, Charles K.; Bualat, Maria G.; Lum, Henry, Jr. (Technical Monitor)

1994-01-01

This paper discusses the design and implementation of an analog optical vecto-rmatrix coprocessor with a throughput of 128 Mops for a personal computer. Vector matrix calculations are inherently parallel, providing a promising domain for the use of optical calculators. However, to date, digital optical systems have proven too cumbersome to replace electronics, and analog processors have not demonstrated sufficient accuracy in large scale systems. The goal of the work described in this paper is to demonstrate a viable optical coprocessor for linear operations. The analog optical processor presented has been integrated with a personal computer to provide full functionality and is the first demonstration of an optical linear algebra processor with a throughput greater than 100 Mops. The optical vector matrix processor consists of a laser diode source, an acoustooptical modulator array to input the vector information, a liquid crystal spatial light modulator to input the matrix information, an avalanche photodiode array to read out the result vector of the vector matrix multiplication, as well as transport optics and the electronics necessary to drive the optical modulators and interface to the computer. The intent of this research is to provide a low cost, highly energy efficient coprocessor for linear operations. Measurements of the analog accuracy of the processor performing 128 Mops are presented along with an assessment of the implications for future systems. A range of noise sources, including cross-talk, source amplitude fluctuations, shot noise at the detector, and non-linearities of the optoelectronic components are measured and compared to determine the most significant source of error. The possibilities for reducing these sources of error are discussed. Also, the total error is compared with that expected from a statistical analysis of the individual components and their relation to the vector-matrix operation. The sufficiency of the measured accuracy of the

Optical systolic array processor using residue arithmetic

NASA Technical Reports Server (NTRS)

Jackson, J.; Casasent, D.

1983-01-01

The use of residue arithmetic to increase the accuracy and reduce the dynamic range requirements of optical matrix-vector processors is evaluated. It is determined that matrix-vector operations and iterative algorithms can be performed totally in residue notation. A new parallel residue quantizer circuit is developed which significantly improves the performance of the systolic array feedback processor. Results are presented of a computer simulation of this system used to solve a set of three simultaneous equations.

Geospace simulations using modern accelerator processor technology

NASA Astrophysics Data System (ADS)

Germaschewski, K.; Raeder, J.; Larson, D. J.

2009-12-01

OpenGGCM (Open Geospace General Circulation Model) is a well-established numerical code simulating the Earth's space environment. The most computing intensive part is the MHD (magnetohydrodynamics) solver that models the plasma surrounding Earth and its interaction with Earth's magnetic field and the solar wind flowing in from the sun. Like other global magnetosphere codes, OpenGGCM's realism is currently limited by computational constraints on grid resolution. OpenGGCM has been ported to make use of the added computational powerof modern accelerator based processor architectures, in particular the Cell processor. The Cell architecture is a novel inhomogeneous multicore architecture capable of achieving up to 230 GFLops on a single chip. The University of New Hampshire recently acquired a PowerXCell 8i based computing cluster, and here we will report initial performance results of OpenGGCM. Realizing the high theoretical performance of the Cell processor is a programming challenge, though. We implemented the MHD solver using a multi-level parallelization approach: On the coarsest level, the problem is distributed to processors based upon the usual domain decomposition approach. Then, on each processor, the problem is divided into 3D columns, each of which is handled by the memory limited SPEs (synergistic processing elements) slice by slice. Finally, SIMD instructions are used to fully exploit the SIMD FPUs in each SPE. Memory management needs to be handled explicitly by the code, using DMA to move data from main memory to the per-SPE local store and vice versa. We use a modern technique, automatic code generation, which shields the application programmer from having to deal with all of the implementation details just described, keeping the code much more easily maintainable. Our preliminary results indicate excellent performance, a speed-up of a factor of 30 compared to the unoptimized version.

Effect of poor control of film processors on mammographic image quality.

PubMed

Kimme-Smith, C; Sun, H; Bassett, L W; Gold, R H

1992-11-01

With the increasingly stringent standards of image quality in mammography, film processor quality control is especially important. Current methods are not sufficient for ensuring good processing. The authors used a sensitometer and densitometer system to evaluate the performance of 22 processors at 16 mammographic facilities. Standard sensitometric values of two films were established, and processor performance was assessed for variations from these standards. Developer chemistry of each processor was analyzed and correlated with its sensitometric values. Ten processors were retested, and nine were found to be out of calibration. The developer components of hydroquinone, sulfites, bromide, and alkalinity varied the most, and low concentrations of hydroquinone were associated with lower average gradients at two facilities. Use of the sensitometer and densitometer system helps identify out-of-calibration processors, but further study is needed to correlate sensitometric values with developer component values. The authors believe that present quality control would be improved if sensitometric or other tests could be used to identify developer components that are out of calibration.

Benchmarking NWP Kernels on Multi- and Many-core Processors

NASA Astrophysics Data System (ADS)

Michalakes, J.; Vachharajani, M.

2008-12-01

Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.

Processors for wavelet analysis and synthesis: NIFS and TI-C80 MVP

NASA Astrophysics Data System (ADS)

Brooks, Geoffrey W.

1996-03-01

Two processors are considered for image quadrature mirror filtering (QMF). The neuromorphic infrared focal-plane sensor (NIFS) is an existing prototype analog processor offering high speed spatio-temporal Gaussian filtering, which could be used for the QMF low- pass function, and difference of Gaussian filtering, which could be used for the QMF high- pass function. Although not designed specifically for wavelet analysis, the biologically- inspired system accomplishes the most computationally intensive part of QMF processing. The Texas Instruments (TI) TMS320C80 Multimedia Video Processor (MVP) is a 32-bit RISC master processor with four advanced digital signal processors (DSPs) on a single chip. Algorithm partitioning, memory management and other issues are considered for optimal performance. This paper presents these considerations with simulated results leading to processor implementation of high-speed QMF analysis and synthesis.

Real-time trajectory optimization on parallel processors

NASA Technical Reports Server (NTRS)

Psiaki, Mark L.

1993-01-01

A parallel algorithm has been developed for rapidly solving trajectory optimization problems. The goal of the work has been to develop an algorithm that is suitable to do real-time, on-line optimal guidance through repeated solution of a trajectory optimization problem. The algorithm has been developed on an INTEL iPSC/860 message passing parallel processor. It uses a zero-order-hold discretization of a continuous-time problem and solves the resulting nonlinear programming problem using a custom-designed augmented Lagrangian nonlinear programming algorithm. The algorithm achieves parallelism of function, derivative, and search direction calculations through the principle of domain decomposition applied along the time axis. It has been encoded and tested on 3 example problems, the Goddard problem, the acceleration-limited, planar minimum-time to the origin problem, and a National Aerospace Plane minimum-fuel ascent guidance problem. Execution times as fast as 118 sec of wall clock time have been achieved for a 128-stage Goddard problem solved on 32 processors. A 32-stage minimum-time problem has been solved in 151 sec on 32 processors. A 32-stage National Aerospace Plane problem required 2 hours when solved on 32 processors. A speed-up factor of 7.2 has been achieved by using 32-nodes instead of 1-node to solve a 64-stage Goddard problem.

Power processor for a 30cm ion thruster

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.

1974-01-01

A thermal vacuum power processor for the NASA Lewis 30cm Mercury Ion Engine was designed, fabricated and tested to determine compliance with electrical specifications. The power processor breadboard used the silicon controlled rectifier (SCR) series resonant inverter as the basic power stage to process all the power to an ion engine. The power processor includes a digital interface unit to process all input commands and internal telemetry signals so that operation is compatible with a central computer system. The breadboard was tested in a thermal vacuum environment. Integration tests were performed with the ion engine and demonstrate operational compatibility and reliable operation without any component failures. Electromagnetic interference data were also recorded on the design to provide information on the interaction with total spacecraft.

A general natural-language text processor for clinical radiology.

PubMed Central

Friedman, C; Alderson, P O; Austin, J H; Cimino, J J; Johnson, S B

1994-01-01

OBJECTIVE: Development of a general natural-language processor that identifies clinical information in narrative reports and maps that information into a structured representation containing clinical terms. DESIGN: The natural-language processor provides three phases of processing, all of which are driven by different knowledge sources. The first phase performs the parsing. It identifies the structure of the text through use of a grammar that defines semantic patterns and a target form. The second phase, regularization, standardizes the terms in the initial target structure via a compositional mapping of multi-word phrases. The third phase, encoding, maps the terms to a controlled vocabulary. Radiology is the test domain for the processor and the target structure is a formal model for representing clinical information in that domain. MEASUREMENTS: The impression sections of 230 radiology reports were encoded by the processor. Results of an automated query of the resultant database for the occurrences of four diseases were compared with the analysis of a panel of three physicians to determine recall and precision. RESULTS: Without training specific to the four diseases, recall and precision of the system (combined effect of the processor and query generator) were 70% and 87%. Training of the query component increased recall to 85% without changing precision. PMID:7719797

ELIPS: Toward a Sensor Fusion Processor on a Chip

NASA Technical Reports Server (NTRS)

Daud, Taher; Stoica, Adrian; Tyson, Thomas; Li, Wei-te; Fabunmi, James

1998-01-01

The paper presents the concept and initial tests from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) processor is developed to seamlessly combine rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor in compact low power VLSI. The first demonstration of the ELIPS concept targets interceptor functionality; other applications, mainly in robotics and autonomous systems are considered for the future. The main assumption behind ELIPS is that fuzzy, rule-based and neural forms of computation can serve as the main primitives of an "intelligent" processor. Thus, in the same way classic processors are designed to optimize the hardware implementation of a set of fundamental operations, ELIPS is developed as an efficient implementation of computational intelligence primitives, and relies on a set of fuzzy set, fuzzy inference and neural modules, built in programmable analog hardware. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Following software demonstrations on several interceptor data, three important ELIPS building blocks (a fuzzy set preprocessor, a rule-based fuzzy system and a neural network) have been fabricated in analog VLSI hardware and demonstrated microsecond-processing times.

[Improving speech comprehension using a new cochlear implant speech processor].

PubMed

Müller-Deile, J; Kortmann, T; Hoppe, U; Hessel, H; Morsnowski, A

2009-06-01

The aim of this multicenter clinical field study was to assess the benefits of the new Freedom 24 sound processor for cochlear implant (CI) users implanted with the Nucleus 24 cochlear implant system. The study included 48 postlingually profoundly deaf experienced CI users who demonstrated speech comprehension performance with their current speech processor on the Oldenburg sentence test (OLSA) in quiet conditions of at least 80% correct scores and who were able to perform adaptive speech threshold testing using the OLSA in noisy conditions. Following baseline measures of speech comprehension performance with their current speech processor, subjects were upgraded to the Freedom 24 speech processor. After a take-home trial period of at least 2 weeks, subject performance was evaluated by measuring the speech reception threshold with the Freiburg multisyllabic word test and speech intelligibility with the Freiburg monosyllabic word test at 50 dB and 70 dB in the sound field. The results demonstrated highly significant benefits for speech comprehension with the new speech processor. Significant benefits for speech comprehension were also demonstrated with the new speech processor when tested in competing background noise.In contrast, use of the Abbreviated Profile of Hearing Aid Benefit (APHAB) did not prove to be a suitably sensitive assessment tool for comparative subjective self-assessment of hearing benefits with each processor. Use of the preprocessing algorithm known as adaptive dynamic range optimization (ADRO) in the Freedom 24 led to additional improvements over the standard upgrade map for speech comprehension in quiet and showed equivalent performance in noise. Through use of the preprocessing beam-forming algorithm BEAM, subjects demonstrated a highly significant improved signal-to-noise ratio for speech comprehension thresholds (i.e., signal-to-noise ratio for 50% speech comprehension scores) when tested with an adaptive procedure using the Oldenburg

Fault detection and bypass in a sequence information signal processor

NASA Technical Reports Server (NTRS)

Peterson, John C. (Inventor); Chow, Edward T. (Inventor)

1992-01-01

The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.

On nonlinear finite element analysis in single-, multi- and parallel-processors

NASA Technical Reports Server (NTRS)

Utku, S.; Melosh, R.; Islam, M.; Salama, M.

1982-01-01

Numerical solution of nonlinear equilibrium problems of structures by means of Newton-Raphson type iterations is reviewed. Each step of the iteration is shown to correspond to the solution of a linear problem, therefore the feasibility of the finite element method for nonlinear analysis is established. Organization and flow of data for various types of digital computers, such as single-processor/single-level memory, single-processor/two-level-memory, vector-processor/two-level-memory, and parallel-processors, with and without sub-structuring (i.e. partitioning) are given. The effect of the relative costs of computation, memory and data transfer on substructuring is shown. The idea of assigning comparable size substructures to parallel processors is exploited. Under Cholesky type factorization schemes, the efficiency of parallel processing is shown to decrease due to the occasional shared data, just as that due to the shared facilities.

Post-Flight Microbial Analysis of Samples from the International Space Station Water Recovery System and Oxygen Generation System

NASA Technical Reports Server (NTRS)

Birmele, Michele N.

2011-01-01

The Regenerative, Environmental Control and Life Support System (ECLSS) on the International Space Station (ISS) includes the the Water Recovery System (WRS) and the Oxygen Generation System (OGS). The WRS consists of a Urine Processor Assembly (UPA) and Water Processor Assembly (WPA). This report describes microbial characterization of wastewater and surface samples collected from the WRS and OGS subsystems, returned to KSC, JSC, and MSFC on consecutive shuttle flights (STS-129 and STS-130) in 2009-10. STS-129 returned two filters that contained fluid samples from the WPA Waste Tank Orbital Recovery Unit (ORU), one from the waste tank and the other from the ISS humidity condensate. Direct count by microscopic enumeration revealed 8.38 x 104 cells per mL in the humidity condensate sample, but none of those cells were recoverable on solid agar media. In contrast, 3.32 x lOs cells per mL were measured from a surface swab of the WRS waste tank, including viable bacteria and fungi recovered after S12 days of incubation on solid agar media. Based on rDNA sequencing and phenotypic characterization, a fungus recovered from the filter was determined to be Lecythophora mutabilis. The bacterial isolate was identified by rDNA sequence data to be Methylobacterium radiotolerans. Additional UPA subsystem samples were returned on STS-130 for analysis. Both liquid and solid samples were collected from the Russian urine container (EDV), Distillation Assembly (DA) and Recycle Filter Tank Assembly (RFTA) for post-flight analysis. The bacterium Pseudomonas aeruginosa and fungus Chaetomium brasiliense were isolated from the EDV samples. No viable bacteria or fungi were recovered from RFTA brine samples (N= 6), but multiple samples (N = 11) from the DA and RFTA were found to contain fungal and bacterial cells. Many recovered cells have been identified to genus by rDNA sequencing and carbon source utilization profiling (BiOLOG Gen III). The presence of viable bacteria and fungi from WRS

Multibus-based parallel processor for simulation

NASA Technical Reports Server (NTRS)

Ogrady, E. P.; Wang, C.-H.

1983-01-01

A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.

Peake works on the WPA

NASA Image and Video Library

2016-03-22

ISS047e013845 (03/22/2016) --- ESA (European Space Agency) astronaut Tim Peake works on the Water Processor Assembly (WPA) aboard the International Space Station. The WPA is is responsible for treating waste water aboard the station for recycling back into potable water.

Meteorological Processors and Accessory Programs

EPA Pesticide Factsheets

Surface and upper air data, provided by NWS, are important inputs for air quality models. Before these data are used in some of the EPA dispersion models, meteorological processors are used to manipulate the data.

Characterization of Heat Melt Compactor (HMC) Product Water

NASA Technical Reports Server (NTRS)

Harris, Linden; Wignarajah, Kanapathipi; Alba, Richard Gilbert; Pace, Gregory S.; Fisher, John W.

2013-01-01

The Heat Melt Compactor (HMC) is designed to sterilize and process wastes produced during space missions. Benefits of the HMC include reduction of biohazards to the crew, reduction in volume of wastes that would otherwise require storage, production of radiation shielding tiles, and recovery of water and other resources. Water reuse is critical onboard spacecrafts; it reduces the need for resupply missions and saves valuable storage space. The main sources of water in HMC batches are food, beverages, shampoo, disinfecting wipes, toothpaste, and diapers. Water reclaimed by the HMC was analyzed for concentrations of Na+, NH4+, K+, Mg2+, Ca2+, Cl-­-, NO2-­-, Br-­-, NO3-­-, PO43-­-, SO42-­-, total organic carbon (TOC), total inorganic carbon (TIC), % total solids, and pH. The data are discussed in relation to the current water input characteristics established for the International Space Station Water Processor Assembly system. Batches with higher than average amounts of food produced HMC product water with higher sulfate content, and batches with higher proportions of disinfectant wipes and food yielded HMC product water with higher ammonium concentration. We also compared theoretical chemical composition of HMC product water based on food labels and literature values to experimental results.

The Engineer Topographic Laboratories /ETL/ hybrid optical/digital image processor

NASA Astrophysics Data System (ADS)

Benton, J. R.; Corbett, F.; Tuft, R.

1980-01-01

An optical-digital processor for generalized image enhancement and filtering is described. The optical subsystem is a two-PROM Fourier filter processor. Input imagery is isolated, scaled, and imaged onto the first PROM; this input plane acts like a liquid gate and serves as an incoherent-to-coherent converter. The image is transformed onto a second PROM which also serves as a filter medium; filters are written onto the second PROM with a laser scanner in real time. A solid state CCTV camera records the filtered image, which is then digitized and stored in a digital image processor. The operator can then manipulate the filtered image using the gray scale and color remapping capabilities of the video processor as well as the digital processing capabilities of the minicomputer.

A word processor optimized for preparing journal articles and student papers.

PubMed

Wolach, A H; McHale, M A

2001-11-01

A new Windows-based word processor for preparing journal articles and student papers is described. In addition to standard features found in word processors, the present word processor provides specific help in preparing manuscripts. Clicking on "Reference Help (APA Form)" in the "File" menu provides a detailed help system for entering the references in a journal article. Clicking on "Examples and Explanations of APA Form" provides a help system with examples of the various sections of a review article, journal article that has one experiment, or journal article that has two or more experiments. The word processor can automatically place the manuscript page header and page number at the top of each page using the form required by APA and Psychonomic Society journals. The "APA Form" submenu of the "Help" menu provides detailed information about how the word processor is optimized for preparing articles and papers.

Ethernet-Enabled Power and Communication Module for Embedded Processors

NASA Technical Reports Server (NTRS)

Perotti, Jose; Oostdyk, Rebecca

2010-01-01

The power and communications module is a printed circuit board (PCB) that has the capability of providing power to an embedded processor and converting Ethernet packets into serial data to transfer to the processor. The purpose of the new design is to address the shortcomings of previous designs, including limited bandwidth and program memory, lack of control over packet processing, and lack of support for timing synchronization. The new design of the module creates a robust serial-to-Ethernet conversion that is powered using the existing Ethernet cable. This innovation has a small form factor that allows it to power processors and transducers with minimal space requirements.

Extended performance electric propulsion power processor design study. Volume 2: Technical summary

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Electric propulsion power processor technology has processed during the past decade to the point that it is considered ready for application. Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30 cm ion thruster power processor with a beam power rating supply of 2.2KW to 10KW for the main propulsion power stage. Extension in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. A detail design was performed on a microprocessor as the thyristor power processor controller. A reliability analysis was performed to evaluate the effect of the control electronics redesign. Preliminary electrical design, mechanical design and thermal analysis were performed on a 6KW power transformer for the beam supply. Bi-Mod mechanical, structural and thermal control configurations were evaluated for the power processor and preliminary estimates of mechanical weight were determined.

Cache Energy Optimization Techniques For Modern Processors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

2013-01-01

Modern multicore processors are employing large last-level caches, for example Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage energy has been dramatically increasing and hence, leakage energy is expected to become a major source of energy dissipation, especially in last-level caches (LLCs). The conventional schemes of cache energy saving either aim at saving dynamic energy or are based on properties specific to first-level caches, and thus these schemes have limited utility for last-level caches. Further, several other techniques require offline profiling or per-application tuning and hence are not suitable for product systems. In thismore » book, we present novel cache leakage energy saving schemes for single-core and multicore systems; desktop, QoS, real-time and server systems. Also, we present cache energy saving techniques for caches designed with both conventional SRAM devices and emerging non-volatile devices such as STT-RAM (spin-torque transfer RAM). We present software-controlled, hardware-assisted techniques which use dynamic cache reconfiguration to configure the cache to the most energy efficient configuration while keeping the performance loss bounded. To profile and test a large number of potential configurations, we utilize low-overhead, micro-architecture components, which can be easily integrated into modern processor chips. We adopt a system-wide approach to save energy to ensure that cache reconfiguration does not increase energy consumption of other components of the processor. We have compared our techniques with state-of-the-art techniques and have found that our techniques outperform them in terms of energy efficiency and other relevant metrics. The techniques presented in this book have important applications in improving energy-efficiency of higher-end embedded, desktop, QoS, real-time, server processors and multitasking systems. This book is intended to be a valuable guide for both

Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

NASA Astrophysics Data System (ADS)

Hristov, Ivan; Goranov, Goran; Hristova, Radoslava

2018-02-01

We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named "Ivy Bridge-EP") in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named "Knights Landing" (KNL). The results show 2 times better performance on KNL processor.

Finite elements and the method of conjugate gradients on a concurrent processor

NASA Technical Reports Server (NTRS)

Lyzenga, G. A.; Raefsky, A.; Hager, G. H.

1985-01-01

An algorithm for the iterative solution of finite element problems on a concurrent processor is presented. The method of conjugate gradients is used to solve the system of matrix equations, which is distributed among the processors of a MIMD computer according to an element-based spatial decomposition. This algorithm is implemented in a two-dimensional elastostatics program on the Caltech Hypercube concurrent processor. The results of tests on up to 32 processors show nearly linear concurrent speedup, with efficiencies over 90 percent for sufficiently large problems.

Finite elements and the method of conjugate gradients on a concurrent processor

NASA Technical Reports Server (NTRS)

Lyzenga, G. A.; Raefsky, A.; Hager, B. H.

1984-01-01

An algorithm for the iterative solution of finite element problems on a concurrent processor is presented. The method of conjugate gradients is used to solve the system of matrix equations, which is distributed among the processors of a MIMD computer according to an element-based spatial decomposition. This algorithm is implemented in a two-dimensional elastostatics program on the Caltech Hypercube concurrent processor. The results of tests on up to 32 processors show nearly linear concurrent speedup, with efficiencies over 90% for sufficiently large problems.

Extended performance electric propulsion power processor design study. Volume 1: Executive summary

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30cm ion thruster power processor with a beam supply rating of 2.2kW to 10kW. Extensions in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. Preliminary electrical design, mechanical design, and thermal analysis were performed on a 6kW power transformer for the beam supply. Bi-Mod mechanical, structural, and thermal control configurations were evaluated for the power processor, and preliminary estimates of mechanical weight were determined. A program development plan was formulated that outlines the work breakdown structure for the development, qualification and fabrication of the power processor flight hardware.

Conditions for space invariance in optical data processors used with coherent or noncoherent light.

PubMed

Arsenault, H R

1972-10-01

The conditions for space invariance in coherent and noncoherent optical processors are considered. All linear optical processors are shown to belong to one of two types. The conditions for space invariance are more stringent for noncoherent processors than for coherent processors, so that a system that is linear in coherent light may be nonlinear in noncoherent light. However, any processor that is linear in noncoherent light is also linear in the coherent limit.

Scheduling time-critical graphics on multiple processors

NASA Technical Reports Server (NTRS)

Meyer, Tom W.; Hughes, John F.

1995-01-01

This paper describes an algorithm for the scheduling of time-critical rendering and computation tasks on single- and multiple-processor architectures, with minimal pipelining. It was developed to manage scientific visualization scenes consisting of hundreds of objects, each of which can be computed and displayed at thousands of possible resolution levels. The algorithm generates the time-critical schedule using progressive-refinement techniques; it always returns a feasible schedule and, when allowed to run to completion, produces a near-optimal schedule which takes advantage of almost the entire multiple-processor system.

SSC 254 Screen-Based Word Processors: Production Tests. The Lanier Word Processor.

ERIC Educational Resources Information Center

Moyer, Ruth A.

Designed for use in Trident Technical College's Secretarial Lab, this series of 12 production tests focuses on the use of the Lanier Word Processor for a variety of tasks. In tests 1 and 2, students are required to type and print out letters. Tests 3 through 8 require students to reformat a text; make corrections on a letter; divide and combine…

Accuracy of the lattice-Boltzmann method using the Cell processor

NASA Astrophysics Data System (ADS)

Harvey, M. J.; de Fabritiis, G.; Giupponi, G.

2008-11-01

Accelerator processors like the new Cell processor are extending the traditional platforms for scientific computation, allowing orders of magnitude more floating-point operations per second (flops) compared to standard central processing units. However, they currently lack double-precision support and support for some IEEE 754 capabilities. In this work, we develop a lattice-Boltzmann (LB) code to run on the Cell processor and test the accuracy of this lattice method on this platform. We run tests for different flow topologies, boundary conditions, and Reynolds numbers in the range Re=6 350 . In one case, simulation results show a reduced mass and momentum conservation compared to an equivalent double-precision LB implementation. All other cases demonstrate the utility of the Cell processor for fluid dynamics simulations. Benchmarks on two Cell-based platforms are performed, the Sony Playstation3 and the QS20/QS21 IBM blade, obtaining a speed-up factor of 7 and 21, respectively, compared to the original PC version of the code, and a conservative sustained performance of 28 gigaflops per single Cell processor. Our results suggest that choice of IEEE 754 rounding mode is possibly as important as double-precision support for this specific scientific application.

Potential of minicomputer/array-processor system for nonlinear finite-element analysis

NASA Technical Reports Server (NTRS)

Strohkorb, G. A.; Noor, A. K.

1983-01-01

The potential of using a minicomputer/array-processor system for the efficient solution of large-scale, nonlinear, finite-element problems is studied. A Prime 750 is used as the host computer, and a software simulator residing on the Prime is employed to assess the performance of the Floating Point Systems AP-120B array processor. Major hardware characteristics of the system such as virtual memory and parallel and pipeline processing are reviewed, and the interplay between various hardware components is examined. Effective use of the minicomputer/array-processor system for nonlinear analysis requires the following: (1) proper selection of the computational procedure and the capability to vectorize the numerical algorithms; (2) reduction of input-output operations; and (3) overlapping host and array-processor operations. A detailed discussion is given of techniques to accomplish each of these tasks. Two benchmark problems with 1715 and 3230 degrees of freedom, respectively, are selected to measure the anticipated gain in speed obtained by using the proposed algorithms on the array processor.

Software for embedded processors: Problems and solutions

NASA Astrophysics Data System (ADS)

Bogaerts, J. A. C.

1990-08-01

Data Acquistion systems in HEP experiments use a wide spectrum of computers to cope with two major problems: high event rates and a large data volume. They do this by using special fast trigger processors at the source to reduce the event rate by several orders of magnitude. The next stage of a data acquisition system consists of a network of fast but conventional microprocessors which are embedded in high speed bus systems where data is still further reduced, filtered and merged. In the final stage complete events are farmed out to a another collection of processors, which reconstruct the events and perhaps achieve a further event rejection by a small factor, prior to recording onto magnetic tape. Detectors are monitored by analyzing a fraction of the data. This may be done for individual detectors at an early state of the data acquisition or it may be delayed till the complete events are available. A network of workstations is used for monitoring, displays and run control. Software for trigger processors must have a simple structure. Rejection algorithms are carefully optimized, and overheads introduced by system software cannot be tolerated. The embedded microprocessors have to co-operate, and need to be synchronized with the preceding and following stages. Real time kernels are typically used to solve synchronization and communication problems. Applications are usually coded in C, which is reasonably efficient and allows direct control over low level hardware functions. Event reconstruction software is very similar or even identical to offline software, predominantly written in FORTRAN. With the advent of powerful RISC processors, and with manufacturers tending to adopt open bus architectures, there is a move towards commercial processors and hence the introduction of the UNIX operating system. Building and controlling such a heterogeneous data acquisition system puts a heavy strain on the software. Communications is now as important as CPU capacity and I

First Results of an “Artificial Retina” Processor Prototype

DOE PAGES

Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; ...

2016-11-15

We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. Also, the prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHzmore » crossing rate.« less

First Results of an “Artificial Retina” Processor Prototype

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro

We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. Also, the prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHzmore » crossing rate.« less

Interactive Digital Signal Processor

NASA Technical Reports Server (NTRS)

Mish, W. H.

1985-01-01

Interactive Digital Signal Processor, IDSP, consists of set of time series analysis "operators" based on various algorithms commonly used for digital signal analysis. Processing of digital signal time series to extract information usually achieved by applications of number of fairly standard operations. IDSP excellent teaching tool for demonstrating application for time series operators to artificially generated signals.

Efficient Parallel Algorithms on Restartable Fail-Stop Processors

DTIC Science & Technology

1991-01-01

resource (memory), and ( 3 ) that processors, memory and their interconnection must be The model of parallel computation known as the Par- perfectly...setting), arid ure an(I restart errors. We describe these arguments if] [AAtPS 871 (in a deterministic setting). Fault-tolerance Section 3 . of...grannmarity at the processor level --- for recent work on where Al is the nmber of failures during this step’s gate granilarities see [All 90, Pip 85

A Simple and Affordable TTL Processor for the Classroom

ERIC Educational Resources Information Center

Feinberg, Dave

2007-01-01

This paper presents a simple 4 bit computer processor design that may be built using TTL chips for less than $65. In addition to describing the processor itself in detail, we discuss our experience using the laboratory kit and its associated machine instruction set to teach computer architecture to high school students. (Contains 3 figures and 5…

Computer program documentation for the pasture/range condition assessment processor

NASA Technical Reports Server (NTRS)

Mcintyre, K. S.; Miller, T. G. (Principal Investigator)

1982-01-01

The processor which drives for the RANGE software allows the user to analyze LANDSAT data containing pasture and rangeland. Analysis includes mapping, generating statistics, calculating vegetative indexes, and plotting vegetative indexes. Routines for using the processor are given. A flow diagram is included.

Enabling Graph Appliance for Genome Assembly

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singh, Rina; Graves, Jeffrey A; Lee, Sangkeun

2015-01-01

In recent years, there has been a huge growth in the amount of genomic data available as reads generated from various genome sequencers. The number of reads generated can be huge, ranging from hundreds to billions of nucleotide, each varying in size. Assembling such large amounts of data is one of the challenging computational problems for both biomedical and data scientists. Most of the genome assemblers developed have used de Bruijn graph techniques. A de Bruijn graph represents a collection of read sequences by billions of vertices and edges, which require large amounts of memory and computational power to storemore » and process. This is the major drawback to de Bruijn graph assembly. Massively parallel, multi-threaded, shared memory systems can be leveraged to overcome some of these issues. The objective of our research is to investigate the feasibility and scalability issues of de Bruijn graph assembly on Cray s Urika-GD system; Urika-GD is a high performance graph appliance with a large shared memory and massively multithreaded custom processor designed for executing SPARQL queries over large-scale RDF data sets. However, to the best of our knowledge, there is no research on representing a de Bruijn graph as an RDF graph or finding Eulerian paths in RDF graphs using SPARQL for potential genome discovery. In this paper, we address the issues involved in representing a de Bruin graphs as RDF graphs and propose an iterative querying approach for finding Eulerian paths in large RDF graphs. We evaluate the performance of our implementation on real world ebola genome datasets and illustrate how genome assembly can be accomplished with Urika-GD using iterative SPARQL queries.« less

Williams in US Lab

NASA Image and Video Library

2010-02-10

S130-E-006844 (10 Feb. 2010) --- NASA astronaut Jeffrey Williams, Expedition 22 commander, installs a Urine Processor Assembly / Distillation Assembly (UPA DA) in the Water Recovery System (WRS) rack in the Destiny laboratory of the International Space Station while space shuttle Endeavour (STS-130) remains docked with the station.

Safe and Efficient Support for Embeded Multi-Processors in ADA

NASA Astrophysics Data System (ADS)

Ruiz, Jose F.

2010-08-01

New software demands increasing processing power, and multi-processor platforms are spreading as the answer to achieve the required performance. Embedded real-time systems are also subject to this trend, but in the case of real-time mission-critical systems, the properties of reliability, predictability and analyzability are also paramount. The Ada 2005 language defined a subset of its tasking model, the Ravenscar profile, that provides the basis for the implementation of deterministic and time analyzable applications on top of a streamlined run-time system. This Ravenscar tasking profile, originally designed for single processors, has proven remarkably useful for modelling verifiable real-time single-processor systems. This paper proposes a simple extension to the Ravenscar profile to support multi-processor systems using a fully partitioned approach. The implementation of this scheme is simple, and it can be used to develop applications amenable to schedulability analysis.

7 CFR 989.13 - Processor.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 8 2012-01-01 2012-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (Marketing Agreements and Orders; Fruits, Vegetables, Nuts), DEPARTMENT OF AGRICULTURE RAISINS PRODUCED FROM GRAPES GROWN IN...

7 CFR 989.13 - Processor.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 8 2013-01-01 2013-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS AND ORDERS; FRUITS, VEGETABLES, NUTS), DEPARTMENT OF AGRICULTURE RAISINS PRODUCED FROM GRAPES GROWN IN...

7 CFR 989.13 - Processor.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 8 2010-01-01 2010-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (Marketing Agreements and Orders; Fruits, Vegetables, Nuts), DEPARTMENT OF AGRICULTURE RAISINS PRODUCED FROM GRAPES GROWN IN...

7 CFR 989.13 - Processor.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 8 2014-01-01 2014-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS AND ORDERS; FRUITS, VEGETABLES, NUTS), DEPARTMENT OF AGRICULTURE RAISINS PRODUCED FROM GRAPES GROWN IN...

7 CFR 989.13 - Processor.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 8 2011-01-01 2011-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (Marketing Agreements and Orders; Fruits, Vegetables, Nuts), DEPARTMENT OF AGRICULTURE RAISINS PRODUCED FROM GRAPES GROWN IN...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2010 CFR

2010-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2011 CFR

2011-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2013 CFR

2013-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2014 CFR

2014-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2012 CFR

2012-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

Self-sustained operation of a kW e-class kerosene-reforming processor for solid oxide fuel cells

NASA Astrophysics Data System (ADS)

Yoon, Sangho; Bae, Joongmyeon; Kim, Sunyoung; Yoo, Young-Sung

In this paper, fuel-processing technologies are developed for application in residential power generation (RPG) in solid oxide fuel cells (SOFCs). Kerosene is selected as the fuel because of its high hydrogen density and because of the established infrastructure that already exists in South Korea. A kerosene fuel processor with two different reaction stages, autothermal reforming (ATR) and adsorptive desulfurization reactions, is developed for SOFC operations. ATR is suited to the reforming of liquid hydrocarbon fuels because oxygen-aided reactions can break the aromatics in the fuel and steam can suppress carbon deposition during the reforming reaction. ATR can also be implemented as a self-sustaining reactor due to the exothermicity of the reaction. The kW e self-sustained kerosene fuel processor, including the desulfurizer, operates for about 250 h in this study. This fuel processor does not require a heat exchanger between the ATR reactor and the desulfurizer or electric equipment for heat supply and fuel or water vaporization because a suitable temperature of the ATR reformate is reached for H 2S adsorption on the ZnO catalyst beds in desulfurizer. Although the CH 4 concentration in the reformate gas of the fuel processor is higher due to the lower temperature of ATR tail gas, SOFCs can directly use CH 4 as a fuel with the addition of sufficient steam feeds (H 2O/CH 4 ≥ 1.5), in contrast to low-temperature fuel cells. The reforming efficiency of the fuel processor is about 60%, and the desulfurizer removed H 2S to a sufficient level to allow for the operation of SOFCs.

Spaceborne Processor Array

NASA Technical Reports Server (NTRS)

Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

2008-01-01

A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

Toward three-dimensional microelectronic systems: directed self-assembly of silicon microcubes via DNA surface functionalization.

PubMed

Lämmerhardt, Nico; Merzsch, Stephan; Ledig, Johannes; Bora, Achyut; Waag, Andreas; Tornow, Marc; Mischnick, Petra

2013-07-02

The huge and intelligent processing power of three-dimensional (3D) biological "processors" like the human brain with clock speeds of only 0.1 kHz is an extremely fascinating property, which is based on a massively parallel interconnect strategy. Artificial silicon microprocessors are 7 orders of magnitude faster. Nevertheless, they do not show any indication of intelligent processing power, mostly due to their very limited interconnectivity. Massively parallel interconnectivity can only be realized in three dimensions. Three-dimensional artificial processors would therefore be at the root of fabricating artificially intelligent systems. A first step in this direction would be the self-assembly of silicon based building blocks into 3D structures. We report on the self-assembly of such building blocks by molecular recognition, and on the electrical characterization of the formed assemblies. First, planar silicon substrates were functionalized with self-assembling monolayers of 3-aminopropyltrimethoxysilane for coupling of oligonucleotides (single stranded DNA) with glutaric aldehyde. The oligonucleotide immobilization was confirmed and quantified by hybridization with fluorescence-labeled complementary oligonucleotides. After the individual processing steps, the samples were analyzed by contact angle measurements, ellipsometry, atomic force microscopy, and fluorescence microscopy. Patterned DNA-functionalized layers were fabricated by microcontact printing (μCP) and photolithography. Silicon microcubes of 3 μm edge length as model objects for first 3D self-assembly experiments were fabricated out of silicon-on-insulator (SOI) wafers by a combination of reactive ion etching (RIE) and selective wet etching. The microcubes were then surface-functionalized using the same protocol as on planar substrates, and their self-assembly was demonstrated both on patterned silicon surfaces (88% correctly placed cubes), and to cube aggregates by complementary DNA

A Modular Pipelined Processor for High Resolution Gamma-Ray Spectroscopy

NASA Astrophysics Data System (ADS)

Veiga, Alejandro; Grunfeld, Christian

2016-02-01

The design of a digital signal processor for gamma-ray applications is presented in which a single ADC input can simultaneously provide temporal and energy characterization of gamma radiation for a wide range of applications. Applying pipelining techniques, the processor is able to manage and synchronize very large volumes of streamed real-time data. Its modular user interface provides a flexible environment for experimental design. The processor can fit in a medium-sized FPGA device operating at ADC sampling frequency, providing an efficient solution for multi-channel applications. Two experiments are presented in order to characterize its temporal and energy resolution.

A distributed fault-tolerant signal processor /FTSP/

NASA Astrophysics Data System (ADS)

Bonneau, R. J.; Evett, R. C.; Young, M. J.

1980-01-01

A digital fault-tolerant signal processor (FTSP), an example of a self-repairing programmable system is analyzed. The design configuration is discussed in terms of fault tolerance, system-level fault detection, isolation and common memory. Special attention is given to the FDIR (fault detection isolation and reconfiguration) logic, noting that the reconfiguration decisions are based on configuration, summary status, end-around tests, and north marker/synchro data. Several mechanisms of fault detection are described which initiate reconfiguration at different levels. It is concluded that the reliability of a signal processor can be significantly enhanced by the use of fault-tolerant techniques.

An innovative on-board processor for lightsats

NASA Technical Reports Server (NTRS)

Henshaw, R. M.; Ballard, B. W.; Hayes, J. R.; Lohr, D. A.

1990-01-01

The Applied Physics Laboratory (APL) has developed a flightworthy custom microprocessor that increases capability and reduces development costs of lightsat science instruments. This device, called the FRISC (FORTH Reduced Instruction Set Computer), directly executes the high-level language called FORTH, which is ideally suited to the multitasking control and data processing environment of a spaceborne instrument processor. The FRISC will be flown as the onboard processor in the Magnetic Field Experiment on the Freja satllite. APL has achieved a significant increase in onboard processing capability with no increase in cost when compared to the magnetometer instrument on Freja's predecessor, the Viking satellite.

Carbon Dioxide Reduction Post-Processing Sub-System Development

NASA Technical Reports Server (NTRS)

Abney, Morgan B.; Miller, Lee A.; Greenwood, Zachary; Barton, Katherine

2012-01-01

The state-of-the-art Carbon Dioxide (CO2) Reduction Assembly (CRA) on the International Space Station (ISS) facilitates the recovery of oxygen from metabolic CO2. The CRA utilizes the Sabatier process to produce water with methane as a byproduct. The methane is currently vented overboard as a waste product. Because the CRA relies on hydrogen for oxygen recovery, the loss of methane ultimately results in a loss of oxygen. For missions beyond low earth orbit, it will prove essential to maximize oxygen recovery. For this purpose, NASA is exploring an integrated post-processor system to recover hydrogen from CRA methane. The post-processor, called a Plasma Pyrolysis Assembly (PPA) partially pyrolyzes methane to recover hydrogen with acetylene as a byproduct. In-flight operation of post-processor will require a Methane Purification Assembly (MePA) and an Acetylene Separation Assembly (ASepA). Recent efforts have focused on the design, fabrication, and testing of these components. The results and conclusions of these efforts will be discussed as well as future plans.

Performance of Water Recirculation Loop Maintenance Components for the Advanced Spacesuit Water Membrane Evaporator

NASA Technical Reports Server (NTRS)

Rector, Tony; Peyton, Barbara M.; Steele, John W.; Makinen, Janice; Bue, Grant C.; Campbell, Colin

2014-01-01

Water loop maintenance components to maintain the water quality of the Advanced Spacesuit Water Membrane Evaporation (SWME) water recirculation loop have undergone a comparative performance evaluation with a second SWME water recirculation loop with no water quality maintenance. Results show the benefits of periodic water maintenance. The SWME is a heat rejection device under development at the NASA Johnson Space Center to perform thermal control for advanced spacesuits. One advantage to this technology is the potential for a significantly greater degree of tolerance to contamination when compared to the existing Sublimator technology. The driver for the evaluation of water recirculation maintenance components was to further enhance this advantage through the leveraging of fluid loop management lessons learned from the International Space Station (ISS). A bed design that was developed for a UTAS military application, and considered for a potential ISS application with the Urine Processor Assembly, provided a low pressure drop means for water maintenance in a recirculation loop. The bed design is coupled with high capacity ion exchange resins, organic adsorbents, and a cyclic methodology developed for the Extravehicular Mobility Unit (EMU) Transport Water loop. The maintenance cycle included the use of a biocide delivery component developed for ISS to introduce a biocide in a microgravity compatible manner for the Internal Active Thermal Control System (IATCS). The leveraging of these water maintenance technologies to the SWME recirculation loop is a unique demonstration of applying the valuable lessons learned on the ISS to the next generation of manned spaceflight Environmental Control and Life Support System (ECLSS) hardware.

Performance of Water Recirculation Loop Maintentance Components for the Advanced Spacesuit Water Membrane Evaporator

NASA Technical Reports Server (NTRS)

Rector, Tony; Peyton, Barbara; Steele, John W.; Bue, Grant C.; Campbell, Colin; Makinen, Janice

2014-01-01

Water loop maintenance components to maintain the water quality of the Advanced Spacesuit Water Membrane Evaporation (SWME) water recirculation loop have undergone a comparative performance evaluation with a second SWME water recirculation loop with no water quality maintenance. Results show the benefits of periodic water maintenance. The SWME is a heat rejection device under development at the NASA Johnson Space Center to perform thermal control for advanced spacesuits. One advantage to this technology is the potential for a significantly greater degree of tolerance to contamination when compared to the existing Sublimator technology. The driver for the evaluation of water recirculation maintenance components was to further enhance this advantage through the leveraging of fluid loop management lessonslearned from the International Space Station (ISS). A bed design that was developed for a UTAS military application, and considered for a potential ISS application with the Urine Processor Assembly, provided a low pressure drop means for water maintenance in a recirculation loop. The bed design is coupled with high capacity ion exchange resins, organic adsorbents, and a cyclic methodology developed for the Extravehicular Mobility Unit (EMU) Transport Water loop. The maintenance cycle included the use of a biocide delivery component developed for ISS to introduce a biocide in a microgravity-compatible manner for the Internal Active Thermal Control System (IATCS). The leveraging of these water maintenance technologies to the SWME recirculation loop is a unique demonstration of applying the valuable lessons learned on the ISS to the next generation of manned spaceflight Environmental Control and Life Support System (ECLSS) hardware.

Backend Control Processor for a Multi-Processor Relational Database Computer System.

DTIC Science & Technology

1984-12-01

SCHOOL OF ENGI. UNCRSIFID MPONTIFF DEC 84 AFXT/GCS/ENG/84D-22 F/O 9/2 L ommhhhhmhhml mhhhommhhhhhm i-2 8 -- U0. 11111= Q. 2 111.8IIII- 1111111..6...THESIS Presented to the Faculty of the School of Engineering of the Air Force Institute of Technology Air University In Partial Fulfillment of the...development of a Backend Multi-Processor Relational Database Computer System. This thesis addresses a single component of this system, the Backend Control

Self-checking self-repairing computer nodes using the mirror processor

NASA Technical Reports Server (NTRS)

Tamir, Yuval

1992-01-01

Circuitry added to fault-tolerant systems for concurrent error deduction usually reduces performance. Using a technique called micro rollback, it is possible to eliminate most of the performance penalty of concurrent error detection. Error detection is performed in parallel with intermodule communication, and erroneous state changes are later undone. The author reports on the design and implementation of a VLSI RISC microprocessor, called the Mirror Processor (MP), which is capable of micro rollback. In order to achieve concurrent error detection, two MP chips operate in lockstep, comparing external signals and a signature of internal signals every clock cycle. If a mismatch is detected, both processors roll back to the beginning of the cycle when the error occurred. In some cases the erroneous state is corrected by copying a value from the fault-free processor to the faulty processor. The architecture, microarchitecture, and VLSI implementation of the MP, emphasizing its error-detection, error-recovery, and self-diagnosis capabilities, are described.

Durable pectin/chitosan membranes with self-assembling, water resistance and enhanced mechanical properties.

PubMed

Martins, Jéssica G; de Oliveira, Ariel C; Garcia, Patrícia S; Kipper, Matt J; Martins, Alessandro F

2018-05-15

Processing water-soluble polysaccharides, like pectin (PT), into materials with desirable stability and mechanical properties has been challenging. Here we report a new method to create water stable and mechanical resistant polyelectrolyte complex (PEC) membranes from PT and chitosan (CS) assemblies, without covalent crosslinking. This new method overcomes challenges of obtaining stable and durable complexes, by performing the complexation at low pH, enabling complex formation even when using an excess of PT, and when using PT with high degree of O-methoxylation. By performing the complexation at low pH, the complexes form with a high degree of intermolecular association, instead of forming by electrostatic complexation. This method avoids precipitation, and overcomes the aqueous instability typical of PT/CS complexes. After neutralization, the PEC membranes display features characteristic of a high degree of intermolecular association because of the self-assembling of polymer chains. The PT/CS ratio can be tuned to enhance the mechanical strength (σ = 39 MPa) of the membranes. These polysaccharide-based materials can demonstrate advantages over synthetic materials for technological applications. Copyright © 2018 Elsevier Ltd. All rights reserved.

Light-Driven Water Splitting by a Covalently Linked Ruthenium-Based Chromophore–Catalyst Assembly

DOE PAGES

Sherman, Benjamin D.; Xie, Yan; Sheridan, Matthew V.; ...

2016-12-09

The preparation and characterization of new Ru(II) polypyridyl-based chromophore–catalyst assemblies, [(4,4'-PO 3H 2-bpy) 2Ru(4-Mebpy-4'-epic)Ru(bda)(pic)] 2+ (1, bpy = 2,2'-bipyridine; 4-Mebpy-4'-epic = 4-(4-methylbipyridin-4'-yl-ethyl)-pyridine; bda = 2,2'-bipyridine-6,6'-dicarboxylate; pic = 4-picoline), and [(bpy) 2Ru(4-Mebpy-4'-epic)Ru(bda)(pic)] 2+ (1') are described, as is the application of 1 in a dye-sensitized photoelectrosynthesis cell (DSPEC) for solar water splitting. Furthermore, on SnO 2/TiO 2 core–shell electrodes in a DSPEC configuration with a Pt cathode, the chromophore–catalyst assembly undergoes light-driven water oxidation at pH 5.7 in a 0.1 M acetate buffer, 0.5 M in NaClO 4. We observed photocurrents of ~0.85 mA cm –2, with illumination by a 100more » mW cm –2 white light source, after 30 s under a 0.1 V vs Ag/AgCl applied bias with a faradaic efficiency for O 2 production of 74% measured over a 5 min illumination period.« less

Light-Driven Water Splitting by a Covalently Linked Ruthenium-Based Chromophore–Catalyst Assembly

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sherman, Benjamin D.; Xie, Yan; Sheridan, Matthew V.

The preparation and characterization of new Ru(II) polypyridyl-based chromophore–catalyst assemblies, [(4,4'-PO 3H 2-bpy) 2Ru(4-Mebpy-4'-epic)Ru(bda)(pic)] 2+ (1, bpy = 2,2'-bipyridine; 4-Mebpy-4'-epic = 4-(4-methylbipyridin-4'-yl-ethyl)-pyridine; bda = 2,2'-bipyridine-6,6'-dicarboxylate; pic = 4-picoline), and [(bpy) 2Ru(4-Mebpy-4'-epic)Ru(bda)(pic)] 2+ (1') are described, as is the application of 1 in a dye-sensitized photoelectrosynthesis cell (DSPEC) for solar water splitting. Furthermore, on SnO 2/TiO 2 core–shell electrodes in a DSPEC configuration with a Pt cathode, the chromophore–catalyst assembly undergoes light-driven water oxidation at pH 5.7 in a 0.1 M acetate buffer, 0.5 M in NaClO 4. We observed photocurrents of ~0.85 mA cm –2, with illumination by a 100more » mW cm –2 white light source, after 30 s under a 0.1 V vs Ag/AgCl applied bias with a faradaic efficiency for O 2 production of 74% measured over a 5 min illumination period.« less

Measurement of Trace Water Vapor in a Carbon Dioxide Removal Assembly Product Stream

NASA Technical Reports Server (NTRS)

Wormhoudt, Joda; Shorter, Joanne H.; McManus, J. Barry; Nelson, David D.; Zahniser, Mark S.; Freedman, Andrew; Campbell, Melissa; Chang, Clarence T.; Smith, Frederick D.

2004-01-01

The International Space Station Carbon Dioxide Removal Assembly (CDRA) uses regenerable adsorption technology to remove carbon dioxide (COP) from cabin air. Product water vapor measurements from a CDRA test bed at the NASA Marshall Space Flight Center were made using a tunable infrared diode laser differential absorption spectrometer (TILDAS) provided by NASA Glenn Research Center. The TILDAS instrument exceeded all the test specifications, including sensitivity, dynamic range, time response, and unattended operation. During the COP desorption phase, water vapor concentrations as low as 5 ppmv were observed near the peak of CO2 evolution, rising to levels of approx. 40 ppmv at the end of a cycle. Periods of high water concentration (>100 ppmv) were detected and shown to be caused by an experimental artifact. Measured values of total water vapor evolved during a single desorption cycle were as low as 1 mg.

Bottom-up construction of artificial molecules for superconducting quantum processors

NASA Astrophysics Data System (ADS)

Poletto, Stefano; Rigetti, Chad; Gambetta, Jay M.; Merkel, Seth; Chow, Jerry M.; Corcoles, Antonio D.; Smolin, John A.; Rozen, Jim R.; Keefe, George A.; Rothwell, Mary B.; Ketchen, Mark B.; Steffen, Matthias

2012-02-01

Recent experiments on transmon qubits capacitively coupled to superconducting 3-dimensional cavities have shown coherence times much longer than transmons coupled to more traditional planar resonators. For the implementation of a quantum processor this approach has clear advantages over traditional techniques but it poses the challenge of scalability. We are currently implementing multi-qubits experiments based on a bottom-up scaling approach. First, transmon qubits are fabricated on individual chips and are independently characterized. Second, an artificial molecule is assembled by selecting a particular set of previously characterized single-transmon chips. We present recent data on a two-qubit artificial molecule constructed in this way. The two qubits are chosen to generate a strong Z-Z interaction by matching the 0-1 transition energy of one qubit with the 1-2 transition of the other. Single qubit manipulations and state tomography cannot be done with ``traditional'' single tone microwave pulses but instead specifically shaped pulses have to be simultaneously applied on both qubits. Coherence times, coupling strength, and optimal pulses for decoupling the two qubits and perform state tomography are presented

Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

NASA Technical Reports Server (NTRS)

Moore, J. Strother

1992-01-01

Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.

The 3D laser radar vision processor system

NASA Astrophysics Data System (ADS)

Sebok, T. M.

1990-10-01

Loral Defense Systems (LDS) developed a 3D Laser Radar Vision Processor system capable of detecting, classifying, and identifying small mobile targets as well as larger fixed targets using three dimensional laser radar imagery for use with a robotic type system. This processor system is designed to interface with the NASA Johnson Space Center in-house Extra Vehicular Activity (EVA) Retriever robot program and provide to it needed information so it can fetch and grasp targets in a space-type scenario.

The 3D laser radar vision processor system

NASA Technical Reports Server (NTRS)

Sebok, T. M.

1990-01-01

Loral Defense Systems (LDS) developed a 3D Laser Radar Vision Processor system capable of detecting, classifying, and identifying small mobile targets as well as larger fixed targets using three dimensional laser radar imagery for use with a robotic type system. This processor system is designed to interface with the NASA Johnson Space Center in-house Extra Vehicular Activity (EVA) Retriever robot program and provide to it needed information so it can fetch and grasp targets in a space-type scenario.

ISS Expeditions 16 through 20: Chemical Analysis Results for Potable Water

NASA Technical Reports Server (NTRS)

Straub, John E., II; Plumlee, Debrah K.; Schultz, John R.

2010-01-01

During the 2-year span from Expedition 16 through Expedition 20, the chemical quality of the potable water onboard the International Space Station (ISS) was verified safe for crew consumption through the return and chemical analysis of archival water samples by the Water and Food Analytical Laboratory (WAFAL) at Johnson Space Center (JSC). Reclaimed cabin humidity condensate and Russian ground-supplied water were the principal sources of potable water for Expeditions 16 through 18. During Expedition 18 the U.S. water processor assembly was delivered, installed, and tested during a 90-day checkout period. Beginning with Expedition 19, U.S. potable water recovered from a combined waste stream of humidity condensate and pretreated urine was also available for ISS crew use. A total of 74 potable water samples were collected using U.S. sampling hardware during Expeditions 16 through 20 and returned on both Shuttle and Soyuz vehicles. The results of JSC chemical analyses of these ISS potable water samples are presented in this paper. Eight potable water samples collected in flight with Russian hardware were also received for analysis, as well as 5 preflight samples of Rodnik potable water delivered to ISS on Russian Progress vehicles 28 to 34. Analytical results for these additional potable water samples are also reported and discussed.

The ATLAS Level-1 Calorimeter Trigger: PreProcessor implementation and performance

NASA Astrophysics Data System (ADS)

Åsman, B.; Achenbach, R.; Allbrooke, B. M. M.; Anders, G.; Andrei, V.; Büscher, V.; Bansil, H. S.; Barnett, B. M.; Bauss, B.; Bendtz, K.; Bohm, C.; Bracinik, J.; Brawn, I. P.; Brock, R.; Buttinger, W.; Caputo, R.; Caughron, S.; Cerrito, L.; Charlton, D. G.; Childers, J. T.; Curtis, C. J.; Daniells, A. C.; Davis, A. O.; Davygora, Y.; Dorn, M.; Eckweiler, S.; Edmunds, D.; Edwards, J. P.; Eisenhandler, E.; Ellis, K.; Ermoline, Y.; Föhlisch, F.; Faulkner, P. J. W.; Fedorko, W.; Fleckner, J.; French, S. T.; Gee, C. N. P.; Gillman, A. R.; Goeringer, C.; Hülsing, T.; Hadley, D. R.; Hanke, P.; Hauser, R.; Heim, S.; Hellman, S.; Hickling, R. S.; Hidvégi, A.; Hillier, S. J.; Hofmann, J. I.; Hristova, I.; Ji, W.; Johansen, M.; Keller, M.; Khomich, A.; Kluge, E.-E.; Koll, J.; Laier, H.; Landon, M. P. J.; Lang, V. S.; Laurens, P.; Lepold, F.; Lilley, J. N.; Linnemann, J. T.; Müller, F.; Müller, T.; Mahboubi, K.; Martin, T. A.; Mass, A.; Meier, K.; Meyer, C.; Middleton, R. P.; Moa, T.; Moritz, S.; Morris, J. D.; Mudd, R. D.; Narayan, R.; zur Nedden, M.; Neusiedl, A.; Newman, P. R.; Nikiforov, A.; Ohm, C. C.; Perera, V. J. O.; Pfeiffer, U.; Plucinski, P.; Poddar, S.; Prieur, D. P. F.; Qian, W.; Rieck, P.; Rizvi, E.; Sankey, D. P. C.; Schäfer, U.; Scharf, V.; Schmitt, K.; Schröder, C.; Schultz-Coulon, H.-C.; Schumacher, C.; Schwienhorst, R.; Silverstein, S. B.; Simioni, E.; Snidero, G.; Staley, R. J.; Stamen, R.; Stock, P.; Stockton, M. C.; Tan, C. L. A.; Tapprogge, S.; Thomas, J. P.; Thompson, P. D.; Thomson, M.; True, P.; Watkins, P. M.; Watson, A. T.; Watson, M. F.; Weber, P.; Wessels, M.; Wiglesworth, C.; Williams, S. L.

2012-12-01

The PreProcessor system of the ATLAS Level-1 Calorimeter Trigger (L1Calo) receives about 7200 analogue signals from the electromagnetic and hadronic components of the calorimetric detector system. Lateral division results in cells which are pre-summed to so-called Trigger Towers of size 0.1 × 0.1 along azimuth (phi) and pseudorapidity (η). The received calorimeter signals represent deposits of transverse energy. The system consists of 124 individual PreProcessor modules that digitise the input signals for each LHC collision, and provide energy and timing information to the digital processors of the L1Calo system, which identify physics objects forming much of the basis for the full ATLAS first level trigger decision. This paper describes the architecture of the PreProcessor, its hardware realisation, functionality, and performance.

Treecode with a Special-Purpose Processor

NASA Astrophysics Data System (ADS)

Makino, Junichiro

1991-08-01

We describe an implementation of the modified Barnes-Hut tree algorithm for a gravitational N-body calculation on a GRAPE (GRAvity PipE) backend processor. GRAPE is a special-purpose computer for N-body calculations. It receives the positions and masses of particles from a host computer and then calculates the gravitational force at each coordinate specified by the host. To use this GRAPE processor with the hierarchical tree algorithm, the host computer must maintain a list of all nodes that exert force on a particle. If we create this list for each particle of the system at each timestep, the number of floating-point operations on the host and that on GRAPE would become comparable, and the increased speed obtained by using GRAPE would be small. In our modified algorithm, we create a list of nodes for many particles. Thus, the amount of the work required of the host is significantly reduced. This algorithm was originally developed by Barnes in order to vectorize the force calculation on a Cyber 205. With this algorithm, the computing time of the force calculation becomes comparable to that of the tree construction, if the GRAPE backend processor is sufficiently fast. The obtained speed-up factor is 30 to 50 for a RISC-based host computer and GRAPE-1A with a peak speed of 240 Mflops.

Power processor for a 20CM ion thruster

NASA Technical Reports Server (NTRS)

Biess, J. J.; Schoenfeld, A. D.; Cohen, E.

1973-01-01

A power processor breadboard for the JPL 20CM Ion Engine was designed, fabricated, and tested to determine compliance with the electrical specification. The power processor breadboard used the silicon-controlled rectifier (SCR) series resonant inverter as the basic power stage to process all the power to the ion engine. The breadboard power processor was integrated with the JPL 20CM ion engine and complete testing was performed. The integration tests were performed without any silicon-controlled rectifier failure. This demonstrated the ruggedness of the series resonant inverter in protecting the switching elements during arcing in the ion engine. A method of fault clearing the ion engine and returning back to normal operation without elaborate sequencing and timing control logic was evolved. In this method, the main vaporizer was turned off and the discharge current limit was reduced when an overload existed on the screen/accelerator supply. After the high voltage returned to normal, both the main vaporizer and the discharge were returned to normal.

Opportunities and Best Practices to Support Sustainable Production for Small Growers and Post-Harvest Processors in Southern California

ERIC Educational Resources Information Center

Fissore, Cinzia; Duran, Daniel F.; Russell, Robert

2015-01-01

This article describes current practices and needs associated with water and gas conservation among Southern California greenhouse growers, Post-Harvest Processors (PHPs), and agricultural associations. Two communication forums were held with the goal of educating the local gas company and small growers and PHPs on the most compelling needs and…

Merged ozone profiles from four MIPAS processors

NASA Astrophysics Data System (ADS)

Laeng, Alexandra; von Clarmann, Thomas; Stiller, Gabriele; Dinelli, Bianca Maria; Dudhia, Anu; Raspollini, Piera; Glatthor, Norbert; Grabowski, Udo; Sofieva, Viktoria; Froidevaux, Lucien; Walker, Kaley A.; Zehner, Claus

2017-04-01

The Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) was an infrared (IR) limb emission spectrometer on the Envisat platform. Currently, there are four MIPAS ozone data products, including the operational Level-2 ozone product processed at ESA, with the scientific prototype processor being operated at IFAC Florence, and three independent research products developed by the Istituto di Fisica Applicata Nello Carrara (ISAC-CNR)/University of Bologna, Oxford University, and the Karlsruhe Institute of Technology-Institute of Meteorology and Climate Research/Instituto de Astrofísica de Andalucía (KIT-IMK/IAA). Here we present a dataset of ozone vertical profiles obtained by merging ozone retrievals from four independent Level-2 MIPAS processors. We also discuss the advantages and the shortcomings of this merged product. As the four processors retrieve ozone in different parts of the spectra (microwindows), the source measurements can be considered as nearly independent with respect to measurement noise. Hence, the information content of the merged product is greater and the precision is better than those of any parent (source) dataset. The merging is performed on a profile per profile basis. Parent ozone profiles are weighted based on the corresponding error covariance matrices; the error correlations between different profile levels are taken into account. The intercorrelations between the processors' errors are evaluated statistically and are used in the merging. The height range of the merged product is 20-55 km, and error covariance matrices are provided as diagnostics. Validation of the merged dataset is performed by comparison with ozone profiles from ACE-FTS (Atmospheric Chemistry Experiment-Fourier Transform Spectrometer) and MLS (Microwave Limb Sounder). Even though the merging is not supposed to remove the biases of the parent datasets, around the ozone volume mixing ratio peak the merged product is found to have a smaller (up to 0.1 ppmv

33 CFR 154.500 - Hose assemblies.

Code of Federal Regulations, 2011 CFR

2011-07-01

... 33 Navigation and Navigable Waters 2 2011-07-01 2011-07-01 false Hose assemblies. 154.500 Section... assemblies. Each hose assembly used for transferring oil or hazardous material must meet the following requirements: (a) The minimum design burst pressure for each hose assembly must be at least four times the sum...

33 CFR 154.500 - Hose assemblies.

Code of Federal Regulations, 2014 CFR

2014-07-01

... 33 Navigation and Navigable Waters 2 2014-07-01 2014-07-01 false Hose assemblies. 154.500 Section... assemblies. Each hose assembly used for transferring oil or hazardous material must meet the following requirements: (a) The minimum design burst pressure for each hose assembly must be at least four times the sum...

33 CFR 154.500 - Hose assemblies.

Code of Federal Regulations, 2012 CFR

2012-07-01

... 33 Navigation and Navigable Waters 2 2012-07-01 2012-07-01 false Hose assemblies. 154.500 Section... assemblies. Each hose assembly used for transferring oil or hazardous material must meet the following requirements: (a) The minimum design burst pressure for each hose assembly must be at least four times the sum...

33 CFR 154.500 - Hose assemblies.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 33 Navigation and Navigable Waters 2 2010-07-01 2010-07-01 false Hose assemblies. 154.500 Section... assemblies. Each hose assembly used for transferring oil or hazardous material must meet the following requirements: (a) The minimum design burst pressure for each hose assembly must be at least four times the sum...

33 CFR 154.500 - Hose assemblies.

Code of Federal Regulations, 2013 CFR

2013-07-01

... 33 Navigation and Navigable Waters 2 2013-07-01 2013-07-01 false Hose assemblies. 154.500 Section... assemblies. Each hose assembly used for transferring oil or hazardous material must meet the following requirements: (a) The minimum design burst pressure for each hose assembly must be at least four times the sum...

Floating assembly of diatom Coscinodiscus sp. microshells.

PubMed

Wang, Yu; Pan, Junfeng; Cai, Jun; Zhang, Deyuan

2012-03-30

Diatoms have silica frustules with transparent and delicate micro/nano scale structures, two dimensional pore arrays, and large surface areas. Although, the diatom cells of Coscinodiscus sp. live underwater, we found that their valves can float on water and assemble together. Experiments show that the convex shape and the 40 nm sieve pores of the valves allow them to float on water, and that the buoyancy and the micro-range attractive forces cause the valves to assemble together at the highest point of water. As measured by AFM calibrated glass needles fixed in manipulator, the buoyancy force on a single floating valve may reach up to 10 μN in water. Turning the valves over, enlarging the sieve pores, reducing the surface tension of water, or vacuum pumping may cause the floating valves to sink. After the water has evaporated, the floating valves remained in their assembled state and formed a monolayer film. The bonded diatom monolayer may be valuable in studies on diatom based optical devices, biosensors, solar cells, and batteries, to better use the optical and adsorption properties of frustules. The floating assembly phenomenon can also be used as a self-assembly method for fabricating monolayer of circular plates. Copyright © 2012 Elsevier Inc. All rights reserved.

Demonstration of two-qubit algorithms with a superconducting quantum processor.

PubMed

DiCarlo, L; Chow, J M; Gambetta, J M; Bishop, Lev S; Johnson, B R; Schuster, D I; Majer, J; Blais, A; Frunzio, L; Girvin, S M; Schoelkopf, R J

2009-07-09

Quantum computers, which harness the superposition and entanglement of physical states, could outperform their classical counterparts in solving problems with technological impact-such as factoring large numbers and searching databases. A quantum processor executes algorithms by applying a programmable sequence of gates to an initialized register of qubits, which coherently evolves into a final state containing the result of the computation. Building a quantum processor is challenging because of the need to meet simultaneously requirements that are in conflict: state preparation, long coherence times, universal gate operations and qubit readout. Processors based on a few qubits have been demonstrated using nuclear magnetic resonance, cold ion trap and optical systems, but a solid-state realization has remained an outstanding challenge. Here we demonstrate a two-qubit superconducting processor and the implementation of the Grover search and Deutsch-Jozsa quantum algorithms. We use a two-qubit interaction, tunable in strength by two orders of magnitude on nanosecond timescales, which is mediated by a cavity bus in a circuit quantum electrodynamics architecture. This interaction allows the generation of highly entangled states with concurrence up to 94 per cent. Although this processor constitutes an important step in quantum computing with integrated circuits, continuing efforts to increase qubit coherence times, gate performance and register size will be required to fulfil the promise of a scalable technology.

Time Manager Software for a Flight Processor

NASA Technical Reports Server (NTRS)

Zoerne, Roger

2012-01-01

Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.

PATCH image processor user's manual

NASA Technical Reports Server (NTRS)

Nieves, M. J. (Principal Investigator)

1980-01-01

The patch image processor extracts patches in various size (32 x 32, 64 x 64, 128 x 128, and 256 x 256 pixels) from full frame LANDSAT imagery data. With the patches that are extracted, a patch image mosaic is created in the image processing system, IMDACS, format.

A Course on Reconfigurable Processors

ERIC Educational Resources Information Center

Shoufan, Abdulhadi; Huss, Sorin A.

2010-01-01

Reconfigurable computing is an established field in computer science. Teaching this field to computer science students demands special attention due to limited student experience in electronics and digital system design. This article presents a compact course on reconfigurable processors, which was offered at the Technische Universitat Darmstadt,…

Structural insights into the light-driven auto-assembly process of the water-oxidizing Mn4CaO5-cluster in photosystem II.

PubMed

Zhang, Miao; Bommer, Martin; Chatterjee, Ruchira; Hussein, Rana; Yano, Junko; Dau, Holger; Kern, Jan; Dobbek, Holger; Zouni, Athina

2017-07-18

In plants, algae and cyanobacteria, Photosystem II (PSII) catalyzes the light-driven splitting of water at a protein-bound Mn 4 CaO 5 -cluster, the water-oxidizing complex (WOC). In the photosynthetic organisms, the light-driven formation of the WOC from dissolved metal ions is a key process because it is essential in both initial activation and continuous repair of PSII. Structural information is required for understanding of this chaperone-free metal-cluster assembly. For the first time, we obtained a structure of PSII from Thermosynechococcus elongatus without the Mn 4 CaO 5 -cluster. Surprisingly, cluster-removal leaves the positions of all coordinating amino acid residues and most nearby water molecules largely unaffected, resulting in a pre-organized ligand shell for kinetically competent and error-free photo-assembly of the Mn 4 CaO 5 -cluster. First experiments initiating (i) partial disassembly and (ii) partial re-assembly after complete depletion of the Mn 4 CaO 5 -cluster agree with a specific bi-manganese cluster, likely a di-µ-oxo bridged pair of Mn(III) ions, as an assembly intermediate.

Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

2010-01-01

The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for

RISC Processors and High Performance Computing

NASA Technical Reports Server (NTRS)

Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)

1995-01-01

This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.

A site oriented supercomputer for theoretical physics: The Fermilab Advanced Computer Program Multi Array Processor System (ACMAPS)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nash, T.; Atac, R.; Cook, A.

1989-03-06

The ACPMAPS multipocessor is a highly cost effective, local memory parallel computer with a hypercube or compound hypercube architecture. Communication requires the attention of only the two communicating nodes. The design is aimed at floating point intensive, grid like problems, particularly those with extreme computing requirements. The processing nodes of the system are single board array processors, each with a peak power of 20 Mflops, supported by 8 Mbytes of data and 2 Mbytes of instruction memory. The system currently being assembled has a peak power of 5 Gflops. The nodes are based on the Weitek XL Chip set. Themore » system delivers performance at approximately $300/Mflop. 8 refs., 4 figs.« less

Watchdog activity monitor (WAM) for use wth high coverage processor self-test

NASA Technical Reports Server (NTRS)

Tulpule, Bhalchandra R. (Inventor); Crosset, III, Richard W. (Inventor); Versailles, Richard E. (Inventor)

1988-01-01

A high fault coverage, instruction modeled self-test for a signal processor in a user environment is disclosed. The self-test executes a sequence of sub-tests and issues a state transition signal upon the execution of each sub-test. The self-test may be combined with a watchdog activity monitor (WAM) which provides a test-failure signal in the presence of a counted number of state transitions not agreeing with an expected number. An independent measure of time may be provided in the WAM to increase fault coverage by checking the processor's clock. Additionally, redundant processor systems are protected from inadvertent unsevering of a severed processor using a unique unsever arming technique and apparatus.

Reduced power processor requirements for the 30-cm diameter HG ion thruster

NASA Technical Reports Server (NTRS)

Rawlin, V. K.

1979-01-01

The characteristics of power processors strongly impact the overall performance and cost of electric propulsion systems. A program was initiated to evaluate simplifications of the thruster-power processor interface requirements. The power processor requirements are mission dependent with major differences arising for those missions which require a nearly constant thruster operating point (typical of geocentric and some inbound planetary missions) and those requiring operation over a large range of input power (such as outbound planetary missions). This paper describes the results of tests which have indicated that as many as seven of the twelve power supplies may be eliminated from the present Functional Model Power Processor used with 30-cm diameter Hg ion thrusters.

Configurable Multi-Purpose Processor

NASA Technical Reports Server (NTRS)

Valencia, J. Emilio; Forney, Chirstopher; Morrison, Robert; Birr, Richard

2010-01-01

Advancements in technology have allowed the miniaturization of systems used in aerospace vehicles. This technology is driven by the need for next-generation systems that provide reliable, responsive, and cost-effective range operations while providing increased capabilities such as simultaneous mission support, increased launch trajectories, improved launch, and landing opportunities, etc. Leveraging the newest technologies, the command and telemetry processor (CTP) concept provides for a compact, flexible, and integrated solution for flight command and telemetry systems and range systems. The CTP is a relatively small circuit board that serves as a processing platform for high dynamic, high vibration environments. The CTP can be reconfigured and reprogrammed, allowing it to be adapted for many different applications. The design is centered around a configurable field-programmable gate array (FPGA) device that contains numerous logic cells that can be used to implement traditional integrated circuits. The FPGA contains two PowerPC processors running the Vx-Works real-time operating system and are used to execute software programs specific to each application. The CTP was designed and developed specifically to provide telemetry functions; namely, the command processing, telemetry processing, and GPS metric tracking of a flight vehicle. However, it can be used as a general-purpose processor board to perform numerous functions implemented in either hardware or software using the FPGA s processors and/or logic cells. Functionally, the CTP was designed for range safety applications where it would ultimately become part of a vehicle s flight termination system. Consequently, the major functions of the CTP are to perform the forward link command processing, GPS metric tracking, return link telemetry data processing, error detection and correction, data encryption/ decryption, and initiate flight termination action commands. Also, the CTP had to be designed to survive and

The Event Based Language and Its Multiple Processor Implementations.

DTIC Science & Technology

1980-01-01

10 6.1 "Recursive" Linear Fibonacci ................................................ 105 6.2 The Readers Writers Problem...kinds. Examples of such systems are: C.mmp [Wu-72], Pluribus [He-73], Data Flow [ De -75], the boolean n-cube parallel machine [Su-77], and the MuNet [Wa...concurrency within programs; therefore, we hate concentrated on two types of systems which seem suitable: a processor network, and a data flow processor [ De -77

Fabrication Security and Trust of Domain-Specific ASIC Processors

DTIC Science & Technology

2016-10-30

embedded in the design. For example , an ASIC processor potentially has a 10-1,000X performance advantage over its FPGA and GPP counterparts, but...paper by summarizing our lessons learned from this project and suggests a few research directions. II. DOMAIN-SPECIFIC ASIC PROCESSORS As Figure 1 has...sponsored by the Assistant Secretary of Defense for Research & Engineering under Air Force Contract #FA8721-05-C-0002. Opinions, interpretations

Rational calculation accuracy in acousto-optical matrix-vector processor

NASA Astrophysics Data System (ADS)

Oparin, V. V.; Tigin, Dmitry V.

1994-01-01

The high speed of parallel computations for a comparatively small-size processor and acceptable power consumption makes the usage of acousto-optic matrix-vector multiplier (AOMVM) attractive for processing of large amounts of information in real time. The limited accuracy of computations is an essential disadvantage of such a processor. The reduced accuracy requirements allow for considerable simplification of the AOMVM architecture and the reduction of the demands on its components.

Application of convolve-multiply-convolve SAW processor for satellite communications

NASA Technical Reports Server (NTRS)

Lie, Y. S.; Ching, M.

1991-01-01

There is a need for a satellite communications receiver than can perform simultaneous multi-channel processing of single channel per carrier (SCPC) signals originating from various small (mobile or fixed) earth stations. The number of ground users can be as many as 1000. Conventional techniques of simultaneously processing these signals is by employing as many RF-bandpass filters as the number of channels. Consequently, such an approach would result in a bulky receiver, which becomes impractical for satellite applications. A unique approach utilizing a realtime surface acoustic wave (SAW) chirp transform processor is presented. The application of a Convolve-Multiply-Convolve (CMC) chirp transform processor is described. The CMC processor transforms each input channel into a unique timeslot, while preserving its modulation content (in this case QPSK). Subsequently, each channel is individually demodulated without the need of input channel filters. Circuit complexity is significantly reduced, because the output frequency of the CMC processor is common for all input channel frequencies. The results of theoretical analysis and experimental results are in good agreement.

Reconfigurable lattice mesh designs for programmable photonic processors.

PubMed

Pérez, Daniel; Gasulla, Ivana; Capmany, José; Soref, Richard A

2016-05-30

We propose and analyse two novel mesh design geometries for the implementation of tunable optical cores in programmable photonic processors. These geometries are the hexagonal and the triangular lattice. They are compared here to a previously proposed square mesh topology in terms of a series of figures of merit that account for metrics that are relevant to on-chip integration of the mesh. We find that that the hexagonal mesh is the most suitable option of the three considered for the implementation of the reconfigurable optical core in the programmable processor.

Ring-array processor distribution topology for optical interconnects

NASA Technical Reports Server (NTRS)

Li, Yao; Ha, Berlin; Wang, Ting; Wang, Sunyu; Katz, A.; Lu, X. J.; Kanterakis, E.

1992-01-01

The existing linear and rectangular processor distribution topologies for optical interconnects, although promising in many respects, cannot solve problems such as clock skews, the lack of supporting elements for efficient optical implementation, etc. The use of a ring-array processor distribution topology, however, can overcome these problems. Here, a study of the ring-array topology is conducted with an aim of implementing various fast clock rate, high-performance, compact optical networks for digital electronic multiprocessor computers. Practical design issues are addressed. Some proof-of-principle experimental results are included.

Hypercluster Parallel Processor

NASA Technical Reports Server (NTRS)

Blech, Richard A.; Cole, Gary L.; Milner, Edward J.; Quealy, Angela

1992-01-01

Hypercluster computer system includes multiple digital processors, operation of which coordinated through specialized software. Configurable according to various parallel-computing architectures of shared-memory or distributed-memory class, including scalar computer, vector computer, reduced-instruction-set computer, and complex-instruction-set computer. Designed as flexible, relatively inexpensive system that provides single programming and operating environment within which one can investigate effects of various parallel-computing architectures and combinations on performance in solution of complicated problems like those of three-dimensional flows in turbomachines. Hypercluster software and architectural concepts are in public domain.

Interactive high-resolution isosurface ray casting on multicore processors.

PubMed

Wang, Qin; JaJa, Joseph

2008-01-01

We present a new method for the interactive rendering of isosurfaces using ray casting on multi-core processors. This method consists of a combination of an object-order traversal that coarsely identifies possible candidate 3D data blocks for each small set of contiguous pixels, and an isosurface ray casting strategy tailored for the resulting limited-size lists of candidate 3D data blocks. While static screen partitioning is widely used in the literature, our scheme performs dynamic allocation of groups of ray casting tasks to ensure almost equal loads among the different threads running on multi-cores while maintaining spatial locality. We also make careful use of memory management environment commonly present in multi-core processors. We test our system on a two-processor Clovertown platform, each consisting of a Quad-Core 1.86-GHz Intel Xeon Processor, for a number of widely different benchmarks. The detailed experimental results show that our system is efficient and scalable, and achieves high cache performance and excellent load balancing, resulting in an overall performance that is superior to any of the previous algorithms. In fact, we achieve an interactive isosurface rendering on a 1024(2) screen for all the datasets tested up to the maximum size of the main memory of our platform.

Analysis of the energy efficiency of an integrated ethanol processor for PEM fuel cell systems

NASA Astrophysics Data System (ADS)

Francesconi, Javier A.; Mussati, Miguel C.; Mato, Roberto O.; Aguirre, Pio A.

The aim of this work is to investigate the energy integration and to determine the maximum efficiency of an ethanol processor for hydrogen production and fuel cell operation. Ethanol, which can be produced from renewable feedstocks or agriculture residues, is an attractive option as feed to a fuel processor. The fuel processor investigated is based on steam reforming, followed by high- and low-temperature shift reactors and preferential oxidation, which are coupled to a polymeric fuel cell. Applying simulation techniques and using thermodynamic models the performance of the complete system has been evaluated for a variety of operating conditions and possible reforming reactions pathways. These models involve mass and energy balances, chemical equilibrium and feasible heat transfer conditions (Δ T min). The main operating variables were determined for those conditions. The endothermic nature of the reformer has a significant effect on the overall system efficiency. The highest energy consumption is demanded by the reforming reactor, the evaporator and re-heater operations. To obtain an efficient integration, the heat exchanged between the reformer outgoing streams of higher thermal level (reforming and combustion gases) and the feed stream should be maximized. Another process variable that affects the process efficiency is the water-to-fuel ratio fed to the reformer. Large amounts of water involve large heat exchangers and the associated heat losses. A net electric efficiency around 35% was calculated based on the ethanol HHV. The responsibilities for the remaining 65% are: dissipation as heat in the PEMFC cooling system (38%), energy in the flue gases (10%) and irreversibilities in compression and expansion of gases. In addition, it has been possible to determine the self-sufficient limit conditions, and to analyze the effect on the net efficiency of the input temperatures of the clean-up system reactors, combustion preheating, expander unit and crude ethanol as

Optically pure, water-stable metallo-helical ‘flexicate’ assemblies with antibiotic activity

NASA Astrophysics Data System (ADS)

Howson, Suzanne E.; Bolhuis, Albert; Brabec, Viktor; Clarkson, Guy J.; Malina, Jaroslav; Rodger, Alison; Scott, Peter

2012-01-01

The helicates—chiral assemblies of two or more metal atoms linked by short or relatively rigid multidentate organic ligands—may be regarded as non-peptide mimetics of α-helices because they are of comparable size and have shown some relevant biological activity. Unfortunately, these beautiful helical compounds have remained difficult to use in the medicinal arena because they contain mixtures of isomers, cannot be optimized for specific purposes, are insoluble, or are too difficult to synthesize. Instead, we have now prepared thermodynamically stable single enantiomers of monometallic units connected by organic linkers. Our highly adaptable self-assembly approach enables the rapid preparation of ranges of water-stable, helicate-like compounds with high stereochemical purity. One such iron(II) ‘flexicate’ system exhibits specific interactions with DNA, promising antimicrobial activity against a Gram-positive bacterium (methicillin-resistant Staphylococcus aureus, MRSA252), but also, unusually, a Gram-negative bacterium (Escherichia coli, MC4100), as well as low toxicity towards a non-mammalian model organism (Caenorhabditis elegans).

77 FR 124 - Biological Processors of Alabama; Decatur, Morgan County, AL; Notice of Settlement

Federal Register 2010, 2011, 2012, 2013, 2014

2012-01-03

... ENVIRONMENTAL PROTECTION AGENCY [FRL-9612-9] Biological Processors of Alabama; Decatur, Morgan... reimbursement of past response costs concerning the Biological Processors of Alabama Superfund Site located in... Ms. Paula V. Painter. Submit your comments by Site name Biological Processors of Alabama Superfund...

Performance of a Water Recirculation Loop Maintenance Device and Process for the Advanced Spacesuit Water Membrane Evaporator

NASA Technical Reports Server (NTRS)

Rector, Tony; Steele, John W.; Bue, Grant C.; Campbell, Colin; Makinen, Janice

2012-01-01

A water loop maintenance device and process to maintain the water quality of the Advanced Spacesuit Water Membrane Evaporation (SWME) water recirculation loop has been undergoing a performance evaluation. The SWME is a heat rejection device under development at the NASA Johnson Space Center to perform thermal control for advanced spacesuits. One advantage to this technology is the potential for a significantly greater degree of tolerance to contamination when compared to the existing Sublimator technology. The driver for the water recirculation maintenance device and process is to further enhance this advantage through the leveraging of fluid loop management lessons-learned from the International Space Station (ISS). A bed design that was developed for a Hamilton Sundstrand military application, and considered for a potential ISS application with the Urine Processor Assembly, provides a low pressure drop means for water maintenance in a recirculation loop. The bed design is coupled with high capacity ion exchange resins, organic adsorbents, and a cyclic methodology developed for the Extravehicular Mobility Unit (EMU) Transport Water loop. The maintenance process further leverages a sorbent developed for ISS that introduces a biocide in a microgravity-compatible manner for the Internal Active Thermal Control System (IATCS). The leveraging of these water maintenance technologies to the SWME recirculation loop is a unique demonstration of applying the valuable lessons learned on the ISS to the next generation of manned spaceflight Environmental Control and Life Support System (ECLSS) hardware. This

A hierarchical, automated target recognition algorithm for a parallel analog processor

NASA Technical Reports Server (NTRS)

Woodward, Gail; Padgett, Curtis

1997-01-01

A hierarchical approach is described for an automated target recognition (ATR) system, VIGILANTE, that uses a massively parallel, analog processor (3DANN). The 3DANN processor is capable of performing 64 concurrent inner products of size 1x4096 every 250 nanoseconds.

Phase coherence adaptive processor for automatic signal detection and identification

NASA Astrophysics Data System (ADS)

Wagstaff, Ronald A.

2006-05-01

A continuously adapting acoustic signal processor with an automatic detection/decision aid is presented. Its purpose is to preserve the signals of tactical interest, and filter out other signals and noise. It utilizes single sensor or beamformed spectral data and transforms the signal and noise phase angles into "aligned phase angles" (APA). The APA increase the phase temporal coherence of signals and leave the noise incoherent. Coherence thresholds are set, which are representative of the type of source "threat vehicle" and the geographic area or volume in which it is operating. These thresholds separate signals, based on the "quality" of their APA coherence. An example is presented in which signals from a submerged source in the ocean are preserved, while clutter signals from ships and noise are entirely eliminated. Furthermore, the "signals of interest" were identified by the processor's automatic detection aid. Similar performance is expected for air and ground vehicles. The processor's equations are formulated in such a manner that they can be tuned to eliminate noise and exploit signal, based on the "quality" of their APA temporal coherence. The mathematical formulation for this processor is presented, including the method by which the processor continuously self-adapts. Results show nearly complete elimination of noise, with only the selected category of signals remaining, and accompanying enhancements in spectral and spatial resolution. In most cases, the concept of signal-to-noise ratio looses significance, and "adaptive automated /decision aid" is more relevant.

The Assessment of Atmospheric Correction Processors for MERIS Based on In-Situ Measurements-Updates in OC-CCI Round Robin

NASA Astrophysics Data System (ADS)

Muller, Dagmar; Krasemann, Hajo; Zuhilke, Marco; Doerffer, Roland; Brockmann, Carsten; Steinmetz, Francois; Valente, Andre; Brotas, Vanda; Grant, kMicheal G.; Sathyendranath, Shubha; Melin, Frederic; Franz, Bryan A.; Mazeran, Constant; Regner, Peter

2016-08-01

The Ocean Colour Climate Change Initiative (OC- CCI) provides a long-term time series of ocean colour data and investigates the detectable climate impact. A reliable and stable atmospheric correction (AC) procedure is the basis for ocean colour products of the necessary high quality.The selection of atmospheric correction processors is repeated regularly based on a round robin exercise, at the latest when a revised production and release of the OC-CCI merged product is scheduled. Most of the AC processors are under constant development and changes are implemented to improve the quality of satellite-derived retrievals of remote sensing reflectances. The changes between versions of the inter-comparison are not restricted to the implementation of AC processors. There are activities to improve the quality flagging for some processors, and the system vicarious calibration for AC algorithms in their sensor specific behaviour are widely studied. Each inter-comparison starts with an updated in-situ database, as more spectra are included in order to broaden the temporal and spatial range of satellite match-ups. While the OC-CCI's focus has laid on case-1 waters in the past, it has expanded to the retrieval of case-2 products now. In light of this goal, new bidirectional correction procedures (normalisation) for the remote sensing spectra have been introduced. As in-situ measurements are not always available at the satellite sensor specific central wave- lengths, a band-shift algorithm has to be applied to the dataset.In order to guarantee an objective selection from a set of four atmospheric correction processors, the common validation strategy of comparisons between in-situ and satellite-derived water leaving reflectance spectra, is aided by a ranking system. In principal, the statistical parameters are transformed into relative scores, which evaluate the relationship of quality dependent on the algorithms under study. The sensitivity of these scores to the selected

Prototype Focal-Plane-Array Optoelectronic Image Processor

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Shaw, Timothy; Yu, Jeffrey

1995-01-01

Prototype very-large-scale integrated (VLSI) planar array of optoelectronic processing elements combines speed of optical input and output with flexibility of reconfiguration (programmability) of electronic processing medium. Basic concept of processor described in "Optical-Input, Optical-Output Morphological Processor" (NPO-18174). Performs binary operations on binary (black and white) images. Each processing element corresponds to one picture element of image and located at that picture element. Includes input-plane photodetector in form of parasitic phototransistor part of processing circuit. Output of each processing circuit used to modulate one picture element in output-plane liquid-crystal display device. Intended to implement morphological processing algorithms that transform image into set of features suitable for high-level processing; e.g., recognition.

ARTS III/Parallel Processor Design Study

DOT National Transportation Integrated Search

1975-04-01

It was the purpose of this design study to investigate the feasibility, suitability, and cost-effectiveness of augmenting the ARTS III failsafe/failsoft multiprocessor system with a form of parallel processor to accomodate a large growth in air traff...

Matching the Word Processor to the Job.

ERIC Educational Resources Information Center

Synder, Carin

1982-01-01

The intelligent purchase of school office equipment, specifically word processors, typewriters, calculators, and furniture, requires analysis of present needs and a realistic evaluation of future needs. (MLF)

Highly permeable artificial water channels that can self-assemble into two-dimensional arrays

PubMed Central

Shen, Yue-xiao; Si, Wen; Erbakan, Mustafa; Decker, Karl; De Zorzi, Rita; Saboe, Patrick O.; Kang, You Jung; Majd, Sheereen; Butler, Peter J.; Walz, Thomas; Aksimentiev, Aleksei; Hou, Jun-li; Kumar, Manish

2015-01-01

Bioinspired artificial water channels aim to combine the high permeability and selectivity of biological aquaporin (AQP) water channels with chemical stability. Here, we carefully characterized a class of artificial water channels, peptide-appended pillar[5]arenes (PAPs). The average single-channel osmotic water permeability for PAPs is 1.0(±0.3) × 10−14 cm3/s or 3.5(±1.0) × 108 water molecules per s, which is in the range of AQPs (3.4∼40.3 × 108 water molecules per s) and their current synthetic analogs, carbon nanotubes (CNTs, 9.0 × 108 water molecules per s). This permeability is an order of magnitude higher than first-generation artificial water channels (20 to ∼107 water molecules per s). Furthermore, within lipid bilayers, PAP channels can self-assemble into 2D arrays. Relevant to permeable membrane design, the pore density of PAP channel arrays (∼2.6 × 105 pores per μm2) is two orders of magnitude higher than that of CNT membranes (0.1∼2.5 × 103 pores per μm2). PAP channels thus combine the advantages of biological channels and CNTs and improve upon them through their relatively simple synthesis, chemical stability, and propensity to form arrays. PMID:26216964

17 CFR 242.609 - Registration of securities information processors: form of application and amendments.

Code of Federal Regulations, 2011 CFR

2011-04-01

... information processors: form of application and amendments. 242.609 Section 242.609 Commodity and Securities....609 Registration of securities information processors: form of application and amendments. (a) An application for the registration of a securities information processor shall be filed on Form SIP (§ 249.1001...

17 CFR 242.609 - Registration of securities information processors: form of application and amendments.

Code of Federal Regulations, 2010 CFR

2010-04-01

... information processors: form of application and amendments. 242.609 Section 242.609 Commodity and Securities....609 Registration of securities information processors: form of application and amendments. (a) An application for the registration of a securities information processor shall be filed on Form SIP (§ 249.1001...

IMPLEMENTATION OF THE SMOKE EMISSION DATA PROCESSOR AND SMOKE TOOL INPUT DATA PROCESSOR IN MODELS-3

EPA Science Inventory

The U.S. Environmental Protection Agency has implemented Version 1.3 of SMOKE (Sparse Matrix Object Kernel Emission) processor for preparation of area, mobile, point, and biogenic sources emission data within Version 4.1 of the Models-3 air quality modeling framework. The SMOK...

Processor Emulator with Benchmark Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lloyd, G. Scott; Pearce, Roger; Gokhale, Maya

2015-11-13

A processor emulator and a suite of benchmark applications have been developed to assist in characterizing the performance of data-centric workloads on current and future computer architectures. Some of the applications have been collected from other open source projects. For more details on the emulator and an example of its usage, see reference [1].

Fast, Massively Parallel Data Processors

NASA Technical Reports Server (NTRS)

Heaton, Robert A.; Blevins, Donald W.; Davis, ED

1994-01-01

Proposed fast, massively parallel data processor contains 8x16 array of processing elements with efficient interconnection scheme and options for flexible local control. Processing elements communicate with each other on "X" interconnection grid with external memory via high-capacity input/output bus. This approach to conditional operation nearly doubles speed of various arithmetic operations.

Ground Terminal Processor Interface Board for Skynet Uplink Synchronization Trials

DTIC Science & Technology

1997-11-01

I1 National DMfense Defence nationale GROUND TERMINAL PROCESSOR INTERFACE BOARD FOR SKYNET UPLINK SYNCHRONIZATION TRIALS by Caroline Tom 19980126...National D6fense Defence nationale GROUND TERMINAL PROCESSOR INTERFACE BOARD FOR SKYNET UPLINK SYNCHRONIZATION TRIALS by Caroline Tom MilSat...aspects of uplink synchronization for extremely-high-frequency (EHF) spread spectrum satellite communications (SATCOM). Requirements of the GT subsystem

Scan line graphics generation on the massively parallel processor

NASA Technical Reports Server (NTRS)

Dorband, John E.

1988-01-01

Described here is how researchers implemented a scan line graphics generation algorithm on the Massively Parallel Processor (MPP). Pixels are computed in parallel and their results are applied to the Z buffer in large groups. To perform pixel value calculations, facilitate load balancing across the processors and apply the results to the Z buffer efficiently in parallel requires special virtual routing (sort computation) techniques developed by the author especially for use on single-instruction multiple-data (SIMD) architectures.

PREMAQ: A NEW PRE-PROCESSOR TO CMAQ FOR AIR-QUALITY FORECASTING

EPA Science Inventory

A new pre-processor to CMAQ (PREMAQ) has been developed as part of the national air-quality forecasting system. PREMAQ combines the functionality of MCIP and parts of SMOKE in a single real-time processor. PREMAQ was specifically designed to link NCEP's Eta model with CMAQ, and...

Processor farming in two-level analysis of historical bridge

NASA Astrophysics Data System (ADS)

Krejčí, T.; Kruis, J.; Koudelka, T.; Šejnoha, M.

2017-11-01

This contribution presents a processor farming method in connection with a multi-scale analysis. In this method, each macro-scopic integration point or each finite element is connected with a certain meso-scopic problem represented by an appropriate representative volume element (RVE). The solution of a meso-scale problem provides then effective parameters needed on the macro-scale. Such an analysis is suitable for parallel computing because the meso-scale problems can be distributed among many processors. The application of the processor farming method to a real world masonry structure is illustrated by an analysis of Charles bridge in Prague. The three-dimensional numerical model simulates the coupled heat and moisture transfer of one half of arch No. 3. and it is a part of a complex hygro-thermo-mechanical analysis which has been developed to determine the influence of climatic loading on the current state of the bridge.

General Mechanism of Morphology Transition and Spreading Area-dependent Phase Diagram of Block Copolymer Self-assembly at the Air/Water Interface

NASA Astrophysics Data System (ADS)

Kim, Dong Hyup; Kim, So Youn

Block copolymers (BCPs) can be self-assembled forming periodic nanostructures, which have been employed in many applications. While general agreements exist for the phase diagrams of BCP self-assembly in bulk or thin films, a fundamental understanding of BCP structures at the air/water interface still remain elusive. The current study explains morphology transition of BCPs with relative fraction of each block at the air/water interface: block fraction is the only parameter to control the morphology. In this study, we show morphology transitions from spherical to cylindrical and planar structures with neat polystyrene-b-poly(2-vinylpyridine) (PS-b-P2VP) via reducing the spreading area of BCP solution at the air/water interface. For example, PS-b-P2VP in a fixed block fraction known to form only spheres can experience sphere to cylinder or lamellar transitions depending on the spreading area at the air/water interface. Suggesting a new parameter to control the interfacial assembly of BCPs, a complete phase diagram is drawn with two paramters: relative block fraction and spreading area. We also explain the morphology transition with the combinational description of dewetting mechanism and spring effect of hydrophilic block.

Structural insights into the light-driven auto-assembly process of the water-oxidizing Mn 4CaO 5-cluster in photosystem II

DOE PAGES

Zhang, Miao; Bommer, Martin; Chatterjee, Ruchira; ...

2017-07-18

In plants, algae and cyanobacteria, Photosystem II (PSII) catalyzes the light-driven splitting of water at a protein-bound Mn 4CaO 5-cluster, the water-oxidizing complex (WOC). In the photosynthetic organisms, the light-driven formation of the WOC from dissolved metal ions is a key process because it is essential in both initial activation and continuous repair of PSII. Structural information is required for understanding of this chaperone-free metal-cluster assembly. For the first time, we obtained a structure of PSII from Thermosynechococcus elongatus without the Mn 4CaO 5-cluster. Surprisingly, cluster-removal leaves the positions of all coordinating amino acid residues and most nearby water moleculesmore » largely unaffected, resulting in a pre-organized ligand shell for kinetically competent and error-free photo-assembly of the Mn 4CaO 5-cluster. First experiments initiating (i) partial disassembly and (ii) partial re-assembly after complete depletion of the Mn4CaO5-cluster agree with a specific bi-manganese cluster, likely a di-µ-oxo bridged pair of Mn(III) ions, as an assembly intermediate.« less

Structural insights into the light-driven auto-assembly process of the water-oxidizing Mn4CaO5-cluster in photosystem II

PubMed Central

Zhang, Miao; Bommer, Martin; Chatterjee, Ruchira; Hussein, Rana; Yano, Junko; Dau, Holger; Kern, Jan; Dobbek, Holger; Zouni, Athina

2017-01-01

In plants, algae and cyanobacteria, Photosystem II (PSII) catalyzes the light-driven splitting of water at a protein-bound Mn4CaO5-cluster, the water-oxidizing complex (WOC). In the photosynthetic organisms, the light-driven formation of the WOC from dissolved metal ions is a key process because it is essential in both initial activation and continuous repair of PSII. Structural information is required for understanding of this chaperone-free metal-cluster assembly. For the first time, we obtained a structure of PSII from Thermosynechococcus elongatus without the Mn4CaO5-cluster. Surprisingly, cluster-removal leaves the positions of all coordinating amino acid residues and most nearby water molecules largely unaffected, resulting in a pre-organized ligand shell for kinetically competent and error-free photo-assembly of the Mn4CaO5-cluster. First experiments initiating (i) partial disassembly and (ii) partial re-assembly after complete depletion of the Mn4CaO5-cluster agree with a specific bi-manganese cluster, likely a di-µ-oxo bridged pair of Mn(III) ions, as an assembly intermediate. DOI: http://dx.doi.org/10.7554/eLife.26933.001 PMID:28718766

Performance of a Water Recirculation Loop Maintenance Device and Process for the Advanced Spacesuit Water Membrane Evaporator

NASA Technical Reports Server (NTRS)

Steele, John W.; Rector, Tony; Bue, Grant C.; Campbell, Colin; Makinen, Janice

2013-01-01

A dual-bed device to maintain the water quality of the Advanced Spacesuit Water Membrane Evaporation (SWME) water recirculation loop has been designed and is undergoing testing. The SWME is a heat rejection device under development at the NASA Johnson Space Center to perform thermal control for advanced spacesuits. One advantage to this technology is the potential for a significantly greater degree of tolerance to contamination when compared to the existing Sublimator technology. The driver for the development of a water recirculation maintenance device is to further enhance this advantage through the leveraging of fluid loop management lessons-learned from the International Space Station (ISS). A bed design that was developed for a Hamilton Sundstrand military application, and considered for a potential ISS application with the Urine Processor Assembly, provides a low pressure drop means for water maintenance in a recirculation loop. The bed design is coupled with high capacity ion exchange resins, organic adsorbents, and a cyclic methodology developed for the Extravehicular Mobility Unit (EMU) Transport Water loop. The bed design further leverages a sorbent developed for ISS that introduces a biocide in a microgravity-compatible manner for the Internal Active Thermal Control System (IATCS). The leveraging of these water maintenance technologies to the SWME recirculation loop is a unique demonstration of applying the valuable lessons learned on the ISS to the next generation of manned spaceflight Environmental Control and Life Support System (ECLSS) hardware.

Design and Evaluation of a Water Recirculation Loop Maintenance Device for the Advanced Spacesuit Water Membrane Evaporator

NASA Technical Reports Server (NTRS)

Steele, John W.; Rector, Tony; Bue, Grant C.; Campbell, Colin; Makinen, Janice

2012-01-01

A dual-bed device to maintain the water quality of the Advanced Spacesuit Water Membrane Evaporation (SWME) water recirculation loop has been designed and is undergoing testing. The SWME is a heat rejection device under development at the NASA Johnson Space Center to perform thermal control for advanced spacesuits. One advantage to this technology is the potential for a significantly greater degree of tolerance to contamination when compared to the existing sublimator technology. The driver for the development of a water recirculation maintenance device is to further enhance this advantage through the leveraging of fluid loop management lessons learned from the International Space Station (ISS). A bed design that was developed for a Hamilton Sundstrand military application, and considered for a potential ISS application with the Urine Processor Assembly, provides a low pressure drop means for water maintenance in a recirculation loop. The bed design is coupled with high-capacity ion exchange resins, organic adsorbents, and a cyclic methodology developed for the Extravehicular Mobility Unit Transport Water Loop. The bed design further leverages a sorbent developed for the ISS that introduces a biocide in a microgravity-compatible manner for the Internal Active Thermal Control System. The leveraging of these water maintenance technologies to the SWME recirculation loop is a unique demonstration of applying the valuable lessons learned on the ISS to the next generation of crewed spaceflight Environmental Control and Life Support System hardware.

Design and Evaluation of a Water Recirculation Loop Maintenance Device for the Advanced Spacesuit Water Membrane Evaporator

NASA Technical Reports Server (NTRS)

Steele, John W.; Rector, Tony; Bue, Grant C.; Campbell, Colin; Makinen, Janice

2011-01-01

A dual-bed device to maintain the water quality of the Advanced Spacesuit Water Membrane Evaporation (SWME) water recirculation loop has been designed and is undergoing testing. The SWME is a heat rejection device under development at the NASA Johnson Space Center to perform thermal control for advanced spacesuits. One advantage to this technology is the potential for a significantly greater degree of tolerance to contamination when compared to the existing Sublimator technology. The driver for the development of a water recirculation maintenance device is to further enhance this advantage through the leveraging of fluid loop management lessons-learned from the International Space Station (ISS). A bed design that was developed for a Hamilton Sundstrand military application, and considered for a potential ISS application with the Urine Processor Assembly, provides a low pressure drop means for water maintenance in a recirculation loop. The bed design is coupled with high capacity ion exchange resins, organic adsorbents, and a cyclic methodology developed for the Extravehicular Mobility Unit (EMU) Transport Water loop. The bed design further leverages a sorbent developed for ISS that introduces a biocide in a microgravity-compatible manner for the Internal Active Thermal Control System (IATCS). The leveraging of these water maintenance technologies to the SWME recirculation loop is a clear demonstration of applying the valuable lessons learned on the ISS to the next generation of manned spaceflight Environmental Control and Life Support System (ECLSS) hardware.

Contextual classification on a CDC Flexible Processor system. [for photomapped remote sensing data

NASA Technical Reports Server (NTRS)

Smith, B. W.; Siegel, H. J.; Swain, P. H.

1981-01-01

A potential hardware organization for the Flexible Processor Array is presented. An algorithm that implements a contextual classifier for remote sensing data analysis is given, along with uniprocessor classification algorithms. The Flexible Processor algorithm is provided, as are simulated timings for contextual classifiers run on the Flexible Processor Array and another system. The timings are analyzed for context neighborhoods of sizes three and nine.

Algorithms and Application of Sparse Matrix Assembly and Equation Solvers for Aeroacoustics

NASA Technical Reports Server (NTRS)

Watson, W. R.; Nguyen, D. T.; Reddy, C. J.; Vatsa, V. N.; Tang, W. H.

2001-01-01

An algorithm for symmetric sparse equation solutions on an unstructured grid is described. Efficient, sequential sparse algorithms for degree-of-freedom reordering, supernodes, symbolic/numerical factorization, and forward backward solution phases are reviewed. Three sparse algorithms for the generation and assembly of symmetric systems of matrix equations are presented. The accuracy and numerical performance of the sequential version of the sparse algorithms are evaluated over the frequency range of interest in a three-dimensional aeroacoustics application. Results show that the solver solutions are accurate using a discretization of 12 points per wavelength. Results also show that the first assembly algorithm is impractical for high-frequency noise calculations. The second and third assembly algorithms have nearly equal performance at low values of source frequencies, but at higher values of source frequencies the third algorithm saves CPU time and RAM. The CPU time and the RAM required by the second and third assembly algorithms are two orders of magnitude smaller than that required by the sparse equation solver. A sequential version of these sparse algorithms can, therefore, be conveniently incorporated into a substructuring for domain decomposition formulation to achieve parallel computation, where different substructures are handles by different parallel processors.

30/20 GHz communications systems baseband processor development

NASA Astrophysics Data System (ADS)

Brown, L.; Sabourin, D.; Stilwell, J.; McCallister, R.; Borota, M.

The architecture and system design concepts for a commercial satellite communications system planned for the 1990's has been developed. The system provides data communications between the individual users via trunking and customer premise service terminals utilizing a central switching satellite operating in a time-division multiple-access mode. Baseband processing is employed to route and control traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband processor design are being verified in the baseband processor proof-of-concept model described herein.

Embedded Data Processor and Portable Computer Technology testbeds

NASA Technical Reports Server (NTRS)

Alena, Richard; Liu, Yuan-Kwei; Goforth, Andre; Fernquist, Alan R.

1993-01-01

Attention is given to current activities in the Embedded Data Processor and Portable Computer Technology testbed configurations that are part of the Advanced Data Systems Architectures Testbed at the Information Sciences Division at NASA Ames Research Center. The Embedded Data Processor Testbed evaluates advanced microprocessors for potential use in mission and payload applications within the Space Station Freedom Program. The Portable Computer Technology (PCT) Testbed integrates and demonstrates advanced portable computing devices and data system architectures. The PCT Testbed uses both commercial and custom-developed devices to demonstrate the feasibility of functional expansion and networking for portable computers in flight missions.

30/20 GHz communications systems baseband processor development

NASA Technical Reports Server (NTRS)

Brown, L.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

The architecture and system design concepts for a commercial satellite communications system planned for the 1990's has been developed. The system provides data communications between the individual users via trunking and customer premise service terminals utilizing a central switching satellite operating in a time-division multiple-access mode. Baseband processing is employed to route and control traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband processor design are being verified in the baseband processor proof-of-concept model described herein.

Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures

PubMed Central

Manolakos, Elias S.

2015-01-01

Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub. PMID:26605332

Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures.

PubMed

Sharma, Anuj; Manolakos, Elias S

2015-01-01

Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub.

Micromechanical Signal Processors

NASA Astrophysics Data System (ADS)

Nguyen, Clark Tu-Cuong

Completely monolithic high-Q micromechanical signal processors constructed of polycrystalline silicon and integrated with CMOS electronics are described. The signal processors implemented include an oscillator, a bandpass filter, and a mixer + filter--all of which are components commonly required for up- and down-conversion in communication transmitters and receivers, and all of which take full advantage of the high Q of micromechanical resonators. Each signal processor is designed, fabricated, then studied with particular attention to the performance consequences associated with miniaturization of the high-Q element. The fabrication technology which realizes these components merges planar integrated circuit CMOS technologies with those of polysilicon surface micromachining. The technologies are merged in a modular fashion, where the CMOS is processed in the first module, the microstructures in a following separate module, and at no point in the process sequence are steps from each module intermixed. Although the advantages of such modularity include flexibility in accommodating new module technologies, the developed process constrained the CMOS metallization to a high temperature refractory metal (tungsten metallization with TiSi _2 contact barriers) and constrained the micromachining process to long-term temperatures below 835^circC. Rapid-thermal annealing (RTA) was used to relieve residual stress in the mechanical structures. To reduce the complexity involved with developing this merged process, capacitively transduced resonators are utilized. High-Q single resonator and spring-coupled micromechanical resonator filters are also investigated, with particular attention to noise performance, bandwidth control, and termination design. The noise in micromechanical filters is found to be fairly high due to poor electromechanical coupling on the micro-scale with present-day technologies. Solutions to this high series resistance problem are suggested, including smaller

Development of a Novel, Two-Processor Architecture for a Small UAV Autopilot System,

DTIC Science & Technology

2006-07-26

is, and the control laws the user implements to control it. The flight control system board will contain the processor selected for this system...Unit (IMU). The IMU contains solid-state gyros and accelerometers and uses these to determine the attitude of the UAV within the three dimensions of...multiple-UAV swarming for combat support operations. The mission processor board will contain the processor selected to execute the mission

Application of Advanced Multi-Core Processor Technologies to Oceanographic Research

DTIC Science & Technology

2013-09-30

STM32 NXP LPC series No Proprietary Microchip PIC32/DSPIC No > 500 mW; < 5 W ARM Cortex TI OMAP TI Sitara Broadcom BCM2835 Varies FPGA...1 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. Application of Advanced Multi-Core Processor Technologies...state-of-the-art information processing architectures. OBJECTIVES Next-generation processor architectures (multi-core, multi-threaded) hold the

Space Station Environmental Control and Life Support Systems: An Update on Waste Water Reclamation

NASA Technical Reports Server (NTRS)

Ferner, Kathleen M.

1994-01-01

Since the mid-1980's, work has been ongoing In the development of the various environmental control and life support systems (ECLSS) for the space station. Part of this effort has been focused on the development of a new subsystem to reclaim waste water that had not been previously required for shuttle missions. Because of the extended manned missions proposed, reclamation of waste water becomes imperative to avoid the weight penalties associated with resupplying a crew's entire water needs for consumption and daily hygiene. Hamilton Standard, under contract to Boeing Aerospace and Electronics, has been designing the water reclamation system for space station use. Since June of 1991, Hamilton Standard has developed a combined water processor capable of reclaiming potable quality water from waste hygiene water, used laundry water, processed urine, Shuttle fuel cell water, humidity condensate and other minor waste water sources. The system was assembled and then tested with over 27,700 pounds of 'real' waste water. During the 1700 hours of system operation required to process this waste water, potable quality water meeting NASA and Boeing specifications was produced. This paper gives a schematic overview of the system, describes the test conditions and test results and outlines the next steps for system development.

Implementation of a robotic flexible assembly system

NASA Technical Reports Server (NTRS)

Benton, Ronald C.

1987-01-01

As part of the Intelligent Task Automation program, a team developed enabling technologies for programmable, sensory controlled manipulation in unstructured environments. These technologies include 2-D/3-D vision sensing and understanding, force sensing and high speed force control, 2.5-D vision alignment and control, and multiple processor architectures. The subsequent design of a flexible, programmable, sensor controlled robotic assembly system for small electromechanical devices is described using these technologies and ongoing implementation and integration efforts. Using vision, the system picks parts dumped randomly in a tray. Using vision and force control, it performs high speed part mating, in-process monitoring/verification of expected results and autonomous recovery from some errors. It is programmed off line with semiautomatic action planning.

Next Generation Security for the 10,240 Processor Columbia System

NASA Technical Reports Server (NTRS)

Hinke, Thomas; Kolano, Paul; Shaw, Derek; Keller, Chris; Tweton, Dave; Welch, Todd; Liu, Wen (Betty)

2005-01-01

This presentation includes a discussion of the Columbia 10,240-processor system located at the NASA Advanced Supercomputing (NAS) division at the NASA Ames Research Center which supports each of NASA's four missions: science, exploration systems, aeronautics, and space operations. It is comprised of 20 Silicon Graphics nodes, each consisting of 512 Itanium II processors. A 64 processor Columbia front-end system supports users as they prepare their jobs and then submits them to the PBS system. Columbia nodes and front-end systems use the Linux OS. Prior to SC04, the Columbia system was used to attain a processing speed of 51.87 TeraFlops, which made it number two on the Top 500 list of the world's supercomputers and the world's fastest "operational" supercomputer since it was fully engaged in supporting NASA users.

A concept for magazine Bimat processor

NASA Technical Reports Server (NTRS)

Park, C. E.

1969-01-01

Concept utilizes existing film magazines to process photographic film as the film is exposed. A standard magazine can be converted to a Bimat processor by adding three stainless steel rollers. All chemicals required for processing and fixing the negative are contained in the Bimat film.

Performance Evaluation of NWChem Ab-Initio Molecular Dynamics (AIMD) Simulations on the Intel® Xeon Phi™ Processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bylaska, Eric J.; Jacquelin, Mathias; De Jong, Wibe A.

2017-10-20

Ab-initio Molecular Dynamics (AIMD) methods are an important class of algorithms, as they enable scientists to understand the chemistry and dynamics of molecular and condensed phase systems while retaining a first-principles-based description of their interactions. Many-core architectures such as the Intel® Xeon Phi™ processor are an interesting and promising target for these algorithms, as they can provide the computational power that is needed to solve interesting problems in chemistry. In this paper, we describe the efforts of refactoring the existing AIMD plane-wave method of NWChem from an MPI-only implementation to a scalable, hybrid code that employs MPI and OpenMP tomore » exploit the capabilities of current and future many-core architectures. We describe the optimizations required to get close to optimal performance for the multiplication of the tall-and-skinny matrices that form the core of the computational algorithm. We present strong scaling results on the complete AIMD simulation for a test case that simulates 256 water molecules and that strong-scales well on a cluster of 1024 nodes of Intel Xeon Phi processors. We compare the performance obtained with a cluster of dual-socket Intel® Xeon® E5–2698v3 processors.« less

Broadband set-top box using MAP-CA processor

NASA Astrophysics Data System (ADS)

Bush, John E.; Lee, Woobin; Basoglu, Chris

2001-12-01

Advances in broadband access are expected to exert a profound impact in our everyday life. It will be the key to the digital convergence of communication, computer and consumer equipment. A common thread that facilitates this convergence comprises digital media and Internet. To address this market, Equator Technologies, Inc., is developing the Dolphin broadband set-top box reference platform using its MAP-CA Broadband Signal ProcessorT chip. The Dolphin reference platform is a universal media platform for display and presentation of digital contents on end-user entertainment systems. The objective of the Dolphin reference platform is to provide a complete set-top box system based on the MAP-CA processor. It includes all the necessary hardware and software components for the emerging broadcast and the broadband digital media market based on IP protocols. Such reference design requires a broadband Internet access and high-performance digital signal processing. By using the MAP-CA processor, the Dolphin reference platform is completely programmable, allowing various codecs to be implemented in software, such as MPEG-2, MPEG-4, H.263 and proprietary codecs. The software implementation also enables field upgrades to keep pace with evolving technology and industry demands.

Flight design system level C requirements. Solid rocket booster and external tank impact prediction processors. [space transportation system

NASA Technical Reports Server (NTRS)

Seale, R. H.

1979-01-01

The prediction of the SRB and ET impact areas requires six separate processors. The SRB impact prediction processor computes the impact areas and related trajectory data for each SRB element. Output from this processor is stored on a secure file accessible by the SRB impact plot processor which generates the required plots. Similarly the ET RTLS impact prediction processor and the ET RTLS impact plot processor generates the ET impact footprints for return-to-launch-site (RTLS) profiles. The ET nominal/AOA/ATO impact prediction processor and the ET nominal/AOA/ATO impact plot processor generate the ET impact footprints for non-RTLS profiles. The SRB and ET impact processors compute the size and shape of the impact footprints by tabular lookup in a stored footprint dispersion data base. The location of each footprint is determined by simulating a reference trajectory and computing the reference impact point location. To insure consistency among all flight design system (FDS) users, much input required by these processors will be obtained from the FDS master data base.

Digital signal processor and processing method for GPS receivers

NASA Technical Reports Server (NTRS)

Thomas, Jr., Jess B. (Inventor)

1989-01-01

A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P.sub.1, and P.sub.2 channels on the L.sub.1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.

Design of a dataway processor for a parallel image signal processing system

NASA Astrophysics Data System (ADS)

Nomura, Mitsuru; Fujii, Tetsuro; Ono, Sadayasu

1995-04-01

Recently, demands for high-speed signal processing have been increasing especially in the field of image data compression, computer graphics, and medical imaging. To achieve sufficient power for real-time image processing, we have been developing parallel signal-processing systems. This paper describes a communication processor called 'dataway processor' designed for a new scalable parallel signal-processing system. The processor has six high-speed communication links (Dataways), a data-packet routing controller, a RISC CORE, and a DMA controller. Each communication link operates at 8-bit parallel in a full duplex mode at 50 MHz. Moreover, data routing, DMA, and CORE operations are processed in parallel. Therefore, sufficient throughput is available for high-speed digital video signals. The processor is designed in a top- down fashion using a CAD system called 'PARTHENON.' The hardware is fabricated using 0.5-micrometers CMOS technology, and its hardware is about 200 K gates.

The AIS-5000 parallel processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schmitt, L.A.; Wilson, S.S.

1988-05-01

The AIS-5000 is a commercially available massively parallel processor which has been designed to operate in an industrial environment. It has fine-grained parallelism with up to 1024 processing elements arranged in a single-instruction multiple-data (SIMD) architecture. The processing elements are arranged in a one-dimensional chain that, for computer vision applications, can be as wide as the image itself. This architecture has superior cost/performance characteristics than two-dimensional mesh-connected systems. The design of the processing elements and their interconnections as well as the software used to program the system allow a wide variety of algorithms and applications to be implemented. In thismore » paper, the overall architecture of the system is described. Various components of the system are discussed, including details of the processing elements, data I/O pathways and parallel memory organization. A virtual two-dimensional model for programming image-based algorithms for the system is presented. This model is supported by the AIS-5000 hardware and software and allows the system to be treated as a full-image-size, two-dimensional, mesh-connected parallel processor. Performance bench marks are given for certain simple and complex functions.« less

Parallelising a molecular dynamics algorithm on a multi-processor workstation

NASA Astrophysics Data System (ADS)

Müller-Plathe, Florian

1990-12-01

The Verlet neighbour-list algorithm is parallelised for a multi-processor Hewlett-Packard/Apollo DN10000 workstation. The implementation makes use of memory shared between the processors. It is a genuine master-slave approach by which most of the computational tasks are kept in the master process and the slaves are only called to do part of the nonbonded forces calculation. The implementation features elements of both fine-grain and coarse-grain parallelism. Apart from three calls to library routines, two of which are standard UNIX calls, and two machine-specific language extensions, the whole code is written in standard Fortran 77. Hence, it may be expected that this parallelisation concept can be transfered in parts or as a whole to other multi-processor shared-memory computers. The parallel code is routinely used in production work.

A Bayesian sequential processor approach to spectroscopic portal system decisions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sale, K; Candy, J; Breitfeller, E

The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waitingmore » for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.« less

A diesel fuel processor for fuel-cell-based auxiliary power unit applications

NASA Astrophysics Data System (ADS)

Samsun, Remzi Can; Krekel, Daniel; Pasel, Joachim; Prawitz, Matthias; Peters, Ralf; Stolten, Detlef

2017-07-01

Producing a hydrogen-rich gas from diesel fuel enables the efficient generation of electricity in a fuel-cell-based auxiliary power unit. In recent years, significant progress has been achieved in diesel reforming. One issue encountered is the stable operation of water-gas shift reactors with real reformates. A new fuel processor is developed using a commercial shift catalyst. The system is operated using optimized start-up and shut-down strategies. Experiments with diesel and kerosene fuels show slight performance drops in the shift reactor during continuous operation for 100 h. CO concentrations much lower than the target value are achieved during system operation in auxiliary power unit mode at partial loads of up to 60%. The regeneration leads to full recovery of the shift activity. Finally, a new operation strategy is developed whereby the gas hourly space velocity of the shift stages is re-designed. This strategy is validated using different diesel and kerosene fuels, showing a maximum CO concentration of 1.5% at the fuel processor outlet under extreme conditions, which can be tolerated by a high-temperature PEFC. The proposed operation strategy solves the issue of strong performance drop in the shift reactor and makes this technology available for reducing emissions in the transportation sector.

Chemical Characterization and Identification of Organosilicon Contaminants in ISS Potable Water

NASA Technical Reports Server (NTRS)

Straub, John E., II; Plumlee, Debrah K.; Gazda, Daniel B.

2016-01-01

2015 marked the 15th anniversary of continuous human presence on board the International Space Station. During the past year crew members from Expeditions 42-46, including two participating in a one-year mission, continued to rely on reclaimed water as their primary source of potable water. This paper presents and discusses results from chemical analyses performed on ISS water samples returned in 2015. Since the U.S. water processor assembly (WPA) became operational in 2008, there have been 5 instances of organic contaminants breaking through the treatment process. On each occasion, the breakthrough was signaled by an increase in the total organic carbon (TOC) concentration in the product water measured by the onboard TOC analyzer (TOCA). Although the most recent TOC rise in 2015 was not unexpected, it was the first time where dimethylsilanediol (DMSD) was not the primary compound responsible for the increase. Results from ground analysis of a product water sample collected in June of 2015 and returned on Soyuz 41 showed that DMSD only accounted for 10% of the measured TOC. After considerable laboratory investigation, the compound responsible for the majority of the TOC was identified as monomethysilanetriol (MMST). MMST is a low-toxicity compound that is structurally similar to DMSD.

Word Processors and Invention in Technical Writing.

ERIC Educational Resources Information Center

Barker, Thomas T.

1989-01-01

Explores how word processing affects thinking and writing. Examines two myths surrounding word processors and invention in technical writing. Describes how word processing can enhance invention through collaborative writing, templates, and on-screen outlining. (MM)

Assembly of acid-functionalized single-walled carbon nanotubes at oil/water interfaces.

PubMed

Feng, Tao; Hoagland, David A; Russell, Thomas P

2014-02-04

The efficient segregation of water-soluble, acid-functionalized, single-walled carbon nanotubes (SWCNTs) at the oil/water interface was induced by dissolving low-molecular-weight amine-terminated polystyrene (PS-NH2) in the oil phase. Salt-bridge interactions between carboxylic acid groups of SWCNTs and amine groups of PS drove the assembly of SWCNTs at the interface, monitored by pendant drop tensiometry and laser scanning confocal microscopy. The impact of PS end-group functionality, PS and SWCNT concentrations, and the degree of SWCNT acid modification on the interfacial activity was assessed, and a sharp drop in interfacial tension was observed above a critical SWCNT concentration. Interfacial tensions were low enough to support stable oil/water emulsions. Further experiments, including potentiometric titrations and the replacement of SWCNTs by other carboxyl-containing species, demonstrated that the interfacial tension drop reflects the loss of SWCNT charge as the pH falls near/below the intrinsic carboxyl dissociation constant; species lacking multivalent carboxylic acid groups are inactive. The trapped SWCNTs appear to be neither ordered nor oriented.

Assembling substrate-less plasmonic metacrystals at the oil/water interface for multiplex ultratrace analyte detection.

PubMed

Lee, Yih Hong; Lee, Hiang Kwee; Ho, Jonathan Yong Chew; Yang, Yijie; Ling, Xing Yi

2016-08-15

Current substrate-less SERS platforms are limited to uncontrolled aggregation of plasmonic nanoparticles or quasi-crystalline arrays of spherical nanoparticles, with no study on how the lattice structures formed by nanoparticle self-assembly affect their detection capabilities. Here, we organize Ag octahedral building blocks into two large-area plasmonic metacrystals at the oil/water interface, and investigate their in situ SERS sensing capabilities. Amphiphilic octahedra assemble into a hexagonal close-packed metacrystal, while hydrophobic octahedra assemble into an open square metacrystal. The lower packing density square metacrystal gives rise to much stronger SERS enhancement than the denser packing hexagonal metacrystal, arising from the larger areas of plasmonic hotspots within the square metacrystal at the excitation wavelength. We further demonstrate the ability of the square metacrystal to achieve quantitative ultratrace detection of analytes from both the aqueous and organic phases. Detection limits are at the nano-molar levels, with analytical enhancement factors reaching 10(8). In addition, multiplex detection across both phases can be achieved in situ without any loss of signal quantitation.

The software system development for the TAMU real-time fan beam scatterometer data processors

NASA Technical Reports Server (NTRS)

Clark, B. V.; Jean, B. R.

1980-01-01

A software package was designed and written to process in real-time any one quadrature channel pair of radar scatterometer signals form the NASA L- or C-Band radar scatterometer systems. The software was successfully tested in the C-Band processor breadboard hardware using recorded radar and NERDAS (NASA Earth Resources Data Annotation System) signals as the input data sources. The processor development program and the overall processor theory of operation and design are described. The real-time processor software system is documented and the results of the laboratory software tests, and recommendations for the efficient application of the data processing capabilities are presented.

Region-specific role of water in collagen unwinding and assembly.

PubMed

Ravikumar, Krishnakumar M; Hwang, Wonmuk

2008-09-01

Conformational stability of the collagen triple helix affects its turnover and determines tissue homeostasis. Although it is known that the presence of imino acids (prolines or hydroxyprolines) confer stability to the molecule, little is known regarding the stability of the imino-poor region lacking imino acids, which plays a key role in collagen cleavage. In particular, there have been continuing debates about the role of water in collagen stability. We addressed these issues using molecular dynamics simulations on 30-residue long collagen triple helices, including a structure that has a biologically relevant 9-residue imino-poor region from type III collagen (PDB ID: 1BKV). A torsional map approach was used to characterize the conformational motion of the molecule that differ between imino-rich and imino-poor regions. At temperatures 300 K and above, unwinding initiates at a common cleavage site, the glycine-isoleucine bond in the imino-poor region. This provides a linkage between previous observations that unwinding of the imino-poor region is a requirement for collagenase cleavage, and that isolated collagen molecules are unstable at body temperature. We found that unwinding of the imino-poor region is controlled by dynamic water bridges between backbone atoms with average lifetimes on the order of a few picoseconds, as the degree of unwinding strongly correlated with the loss of water bridges, and unwinding could be either prevented or enhanced, respectively by enforcing or forbidding water bridge formation. While individual water bridges were short-lived in the imino-poor region, the hydration shell surrounding the entire molecule was stable even at 330 K. The diameter of the hydrated collagen including the first hydration shell was about 14 A, in good agreement with the experimentally measured inter-collagen distances. These results elucidate the general role of water in collagen turnover: water not only affects collagen cleavage by controlling its torsional

Evaluation of Natural Language Processors.

DTIC Science & Technology

1980-11-01

techniques described. Common practice in describing natural language processors is to describe the programs, then give about 20 examples of correctly...make a decision based on performance as to which approaches are most promising for further research and development. The lack of evaluation leaves...successively more difficult problems. This approach might be compared to children taking achievement tests in school. A 90% score on problems involving

Comparison of the CENTRM resonance processor to the NITAWL resonance processor in SCALE

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hollenbach, D.F.; Petrie, L.M.

1998-01-01

This report compares the MTAWL and CENTRM resonance processors in the SCALE code system. The cases examined consist of the International OECD/NEA Criticality Working Group Benchmark 20 problem. These cases represent fuel pellets partially dissolved in a borated solution. The assumptions inherent to the Nordheim Integral Treatment, used in MTAWL, are not valid for these problems. CENTRM resolves this limitation by explicitly calculating a problem dependent point flux from point cross sections, which is then used to create group cross sections.

Space and frequency-multiplexed optical linear algebra processor - Fabrication and initial tests

NASA Technical Reports Server (NTRS)

Casasent, D.; Jackson, J.

1986-01-01

A new optical linear algebra processor architecture is described. Space and frequency-multiplexing are used to accommodate bipolar and complex-valued data. A fabricated laboratory version of this processor is described, the electronic support system used is discussed, and initial test data obtained on it are presented.

Hierarchical nanoparticle assemblies formed by decorating breath figures.

PubMed

Böker, Alexander; Lin, Yao; Chiapperini, Kristen; Horowitz, Reina; Thompson, Mike; Carreon, Vincent; Xu, Ting; Abetz, Clarissa; Skaff, Habib; Dinsmore, A D; Emrick, Todd; Russell, Thomas P

2004-05-01

The combination of two self-assembly processes on different length scales leads to the formation of hierarchically structured nanoparticle arrays. Here, the formation of spherical cavities, or 'breath figures'-made by the condensation of micrometre-sized water droplets on the surface of a polymer solution-that self-assemble into a well-ordered hexagonal array, is combined with the self-assembly of CdSe nanoparticles at the polymer solution-water droplet interface. Complete evaporation of the solvent and water confines the particle assembly to an array of spherical cavities and allows for ex situ investigation. Fluorescence confocal, transmission electron and scanning electron microscope images show the preferential segregation of the CdSe nanoparticles to the polymer solution-water interface where they form a 5-7-nm-thick layer, thus functionalizing the walls of the holes. This process opens a new route to fabricating highly functionalized ordered microarrays of nanoparticles, potentially useful in sensory, separation membrane or catalytic applications.

An Efficient Solution Method for Multibody Systems with Loops Using Multiple Processors

NASA Technical Reports Server (NTRS)

Ghosh, Tushar K.; Nguyen, Luong A.; Quiocho, Leslie J.

2015-01-01

This paper describes a multibody dynamics algorithm formulated for parallel implementation on multiprocessor computing platforms using the divide-and-conquer approach. The system of interest is a general topology of rigid and elastic articulated bodies with or without loops. The algorithm divides the multibody system into a number of smaller sets of bodies in chain or tree structures, called "branches" at convenient joints called "connection points", and uses an Order-N (O (N)) approach to formulate the dynamics of each branch in terms of the unknown spatial connection forces. The equations of motion for the branches, leaving the connection forces as unknowns, are implemented in separate processors in parallel for computational efficiency, and the equations for all the unknown connection forces are synthesized and solved in one or several processors. The performances of two implementations of this divide-and-conquer algorithm in multiple processors are compared with an existing method implemented on a single processor.

Effect of water on self-assembled tubules in β-sitosterol + γ-oryzanol-based organogels

NASA Astrophysics Data System (ADS)

den Adel, Ruud; Heussen, Patricia C. M.; Bot, Arjen

2010-10-01

Mixtures of β-sitosterol and γ-oryzanol form a network in triglyceride oil that may serve as an alternative to the network of small crystallites of triglycerides occurring in regular oil structuring. The present x-ray diffraction study investigates the relation between the crystal forms of the individual compounds and the mixture in oil, water and emulsion. β-Sitosterol and γ-oryzanol form normal crystals in oil, in water, or in emulsions. The crystals are sensitive to the presence of water. The mixture of β-sitosterol + γ-oryzanol forms crystals in water and emulsions that can be traced back to the crystals of the pure compounds. Only in oil, a completely different structure emerges in the mixture of β-sitosterol + γ-oryzanol, which bears no relation to the structures that are formed by both individual compounds, and which can be identified as a self-assembled tubule (diameter 7.2±0.1 nm, wall thickness 0.8±0.2 nm).

An enhanced Ada run-time system for real-time embedded processors

NASA Technical Reports Server (NTRS)

Sims, J. T.

1991-01-01

An enhanced Ada run-time system has been developed to support real-time embedded processor applications. The primary focus of this development effort has been on the tasking system and the memory management facilities of the run-time system. The tasking system has been extended to support efficient and precise periodic task execution as required for control applications. Event-driven task execution providing a means of task-asynchronous control and communication among Ada tasks is supported in this system. Inter-task control is even provided among tasks distributed on separate physical processors. The memory management system has been enhanced to provide object allocation and protected access support for memory shared between disjoint processors, each of which is executing a distinct Ada program.

A programmable power processor for a 25-kW power module

NASA Technical Reports Server (NTRS)

Lanier, R., Jr.; Kapustka, R. E.; Bush, J. R., Jr.

1979-01-01

A discussion of the power processor for an electrical power system for a 25-kW Power Module that could support the Space Shuttle program during the 1980's and 1990's and which could be a stepping stone to future large space power systems is presented. Trades that led to the selection of a microprocessor-controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Efficiency data from a breadboard programmable power processor are presented, and component selection and design considerations are also discussed.

New Developments in the SCIAMACHY L2 Ground Processor

NASA Astrophysics Data System (ADS)

Gretschany, S.; Lichtenberg, G.; Meringer, M.; Theys, N.; Lerot, C.; Eichmann, K.-U.; Liebing, P.; Noel, S.; Dehn, A.; Fehr, T.

2016-08-01

SCIAMACHY (SCanning Imaging Absorption spectroMeter for Atmospheric ChartographY) aboard ESA's environmental satellite ENVISAT observed the Earth's atmosphere in limb, nadir, and solar/lunar occultation geometries covering the UV-Visible to NIR spectral range. It is a joint project of Germany, the Netherlands and Belgium and was launched in February 2002. SCIAMACHY doubled its originally planned in-orbit lifetime of five years before the communication to ENVISAT was severed in April 2012, and the mission entered its post- operational phase F.The SCIAMACHY Quality Working Group (SQWG) was established in 2007. The group coordinates evolution of algorithms and processors, aiming at improving the quality of the operational data products. University of Bremen (IUP), BIRA, DLR-IMF, SRON (Netherlands Institute for Space Research) and KNMI (The Royal Netherlands Meteorological Institute) are the members providing expertise in this group.In order to preserve the best quality of the outstanding data obtained by SCIAMACHY, data processors are still being updated. This presentation will highlight new developments that are currently being incorporated into the forthcoming Version 7 of ESA's operational Level 2 processor.

SPP: A data base processor data communications protocol

NASA Technical Reports Server (NTRS)

Fishwick, P. A.

1983-01-01

The design and implementation of a data communications protocol for the Intel Data Base Processor (DBP) is defined. The protocol is termed SPP (Service Port Protocol) since it enables data transfer between the host computer and the DBP service port. The protocol implementation is extensible in that it is explicitly layered and the protocol functionality is hierarchically organized. Extensive trace and performance capabilities have been supplied with the protocol software to permit optional efficient monitoring of the data transfer between the host and the Intel data base processor. Machine independence was considered to be an important attribute during the design and implementation of SPP. The protocol source is fully commented and is included in Appendix A of this report.

Novel processor architecture for onboard infrared sensors

NASA Astrophysics Data System (ADS)

Hihara, Hiroki; Iwasaki, Akira; Tamagawa, Nobuo; Kuribayashi, Mitsunobu; Hashimoto, Masanori; Mitsuyama, Yukio; Ochi, Hiroyuki; Onodera, Hidetoshi; Kanbara, Hiroyuki; Wakabayashi, Kazutoshi; Tada, Munehiro

2016-09-01

Infrared sensor system is a major concern for inter-planetary missions that investigate the nature and the formation processes of planets and asteroids. The infrared sensor system requires signal preprocessing functions that compensate for the intensity of infrared image sensors to get high quality data and high compression ratio through the limited capacity of transmission channels towards ground stations. For those implementations, combinations of Field Programmable Gate Arrays (FPGAs) and microprocessors are employed by AKATSUKI, the Venus Climate Orbiter, and HAYABUSA2, the asteroid probe. On the other hand, much smaller size and lower power consumption are demanded for future missions to accommodate more sensors. To fulfill this future demand, we developed a novel processor architecture which consists of reconfigurable cluster cores and programmable-logic cells with complementary atom switches. The complementary atom switches enable hardware programming without configuration memories, and thus soft-error on logic circuit connection is completely eliminated. This is a noteworthy advantage for space applications which cannot be found in conventional re-writable FPGAs. Almost one-tenth of lower power consumption is expected compared to conventional re-writable FPGAs because of the elimination of configuration memories. The proposed processor architecture can be reconfigured by behavioral synthesis with higher level language specification. Consequently, compensation functions are implemented in a single chip without accommodating program memories, which is accompanied with conventional microprocessors, while maintaining the comparable performance. This enables us to embed a processor element on each infrared signal detector output channel.

Single-Scale Retinex Using Digital Signal Processors

NASA Technical Reports Server (NTRS)

Hines, Glenn; Rahman, Zia-Ur; Jobson, Daniel; Woodell, Glenn

2005-01-01

The Retinex is an image enhancement algorithm that improves the brightness, contrast and sharpness of an image. It performs a non-linear spatial/spectral transform that provides simultaneous dynamic range compression and color constancy. It has been used for a wide variety of applications ranging from aviation safety to general purpose photography. Many potential applications require the use of Retinex processing at video frame rates. This is difficult to achieve with general purpose processors because the algorithm contains a large number of complex computations and data transfers. In addition, many of these applications also constrain the potential architectures to embedded processors to save power, weight and cost. Thus we have focused on digital signal processors (DSPs) and field programmable gate arrays (FPGAs) as potential solutions for real-time Retinex processing. In previous efforts we attained a 21 (full) frame per second (fps) processing rate for the single-scale monochromatic Retinex with a TMS320C6711 DSP operating at 150 MHz. This was achieved after several significant code improvements and optimizations. Since then we have migrated our design to the slightly more powerful TMS320C6713 DSP and the fixed point TMS320DM642 DSP. In this paper we briefly discuss the Retinex algorithm, the performance of the algorithm executing on the TMS320C6713 and the TMS320DM642, and compare the results with the TMS320C6711.

A GaAs vector processor based on parallel RISC microprocessors

NASA Astrophysics Data System (ADS)

Misko, Tim A.; Rasset, Terry L.

A vector processor architecture based on the development of a 32-bit microprocessor using gallium arsenide (GaAs) technology has been developed. The McDonnell Douglas vector processor (MVP) will be fabricated completely from GaAs digital integrated circuits. The MVP architecture includes a vector memory of 1 megabyte, a parallel bus architecture with eight processing elements connected in parallel, and a control processor. The processing elements consist of a reduced instruction set CPU (RISC) with four floating-point coprocessor units and necessary memory interface functions. This architecture has been simulated for several benchmark programs including complex fast Fourier transform (FFT), complex inner product, trigonometric functions, and sort-merge routine. The results of this study indicate that the MVP can process a 1024-point complex FFT at a speed of 112 microsec (389 megaflops) while consuming approximately 618 W of power in a volume of approximately 0.1 ft-cubed.

Preliminary study on the potential usefulness of array processor techniques for structural synthesis

NASA Technical Reports Server (NTRS)

Feeser, L. J.

1980-01-01

The effects of the use of array processor techniques within the structural analyzer program, SPAR, are simulated in order to evaluate the potential analysis speedups which may result. In particular the connection of a Floating Point System AP120 processor to the PRIME computer is discussed. Measurements of execution, input/output, and data transfer times are given. Using these data estimates are made as to the relative speedups that can be executed in a more complete implementation on an array processor maxi-mini computer system.

JIGSAW: Joint Inhomogeneity estimation via Global Segment Assembly for Water-fat separation.

PubMed

Lu, Wenmiao; Lu, Yi

2011-07-01

Water-fat separation in magnetic resonance imaging (MRI) is of great clinical importance, and the key to uniform water-fat separation lies in field map estimation. This work deals with three-point field map estimation, in which water and fat are modelled as two single-peak spectral lines, and field inhomogeneities shift the spectrum by an unknown amount. Due to the simplified spectrum modelling, there exists inherent ambiguity in forming field maps from multiple locally feasible field map values at each pixel. To resolve such ambiguity, spatial smoothness of field maps has been incorporated as a constraint of an optimization problem. However, there are two issues: the optimization problem is computationally intractable and even when it is solved exactly, it does not always separate water and fat images. Hence, robust field map estimation remains challenging in many clinically important imaging scenarios. This paper proposes a novel field map estimation technique called JIGSAW. It extends a loopy belief propagation (BP) algorithm to obtain an approximate solution to the optimization problem. The solution produces locally smooth segments and avoids error propagation associated with greedy methods. The locally smooth segments are then assembled into a globally consistent field map by exploiting the periodicity of the feasible field map values. In vivo results demonstrate that JIGSAW outperforms existing techniques and produces correct water-fat separation in challenging imaging scenarios.

Advanced development of a programmable power processor

NASA Technical Reports Server (NTRS)

Lukens, F. E.; Lanier, J. R., Jr.; Kapustka, R. E.; Graves, J.

1980-01-01

The need for the development of a multipurpose flexible programmable power processor (PPP) has increased significantly in recent years to reduce ever rising development costs. One of the program requirements the PPP specification will cover is the 25 kW power module power conversion needs. The 25 kW power module could support the Space Shuttle program during the 1980s and 1990s and could be the stepping stone to future large space programs. Trades that led to selection of a microprocessor controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Component selection and design considerations are also discussed.

Autonomous Telemetry Collection for Single-Processor Small Satellites

NASA Technical Reports Server (NTRS)