Optimized smith waterman processor design for breast cancer early diagnosis

NASA Astrophysics Data System (ADS)

Nurdin, D. S.; Isa, M. N.; Ismail, R. C.; Ahmad, M. I.

2017-09-01

This paper presents an optimized design of Processing Element (PE) of Systolic Array (SA) which implements affine gap penalty Smith Waterman (SW) algorithm on the Xilinx Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) for Deoxyribonucleic Acid (DNA) sequence alignment. The PE optimization aims to reduce PE logic resources to increase number of PEs in FPGA for higher degree of parallelism during alignment matrix computations. This is useful for aligning long DNA-based disease sequence such as Breast Cancer (BC) for early diagnosis. The optimized PE architecture has the smallest PE area with 15 slices in a PE and 776 PEs implemented in the Virtex - 6 FPGA.

Virtex-5 CN Package Daisy Chain Evaluation Test Report

NASA Technical Reports Server (NTRS)

Suh, Jong-ook

2016-01-01

The board-level temperature cycling reliability of Xilinx Virtex-5 (V5) CN package was investigated. V5s were temperature cycled under two conditions, 0 to +100 C (0/100) and -55 to +100 C (-55/100). During the 0/100 test, no part out of 8 parts failed up to 6586 cycles. During the -55/100 test, one part out of 8 parts failed at 1236 cycle, and there were no additional failures up to 1705 cycles. The failure mode of the part that failed at 1236 cycles indicated that most likely the failure was not a solder fatigue failure, and therefore no obvious solder fatigue failure was observed throughout the tests.

The SMS4 cryptographic system design based on dynamic partial self-reconfiguration technology

NASA Astrophysics Data System (ADS)

Wang, Jianxin; Gao, Xianwei; Li, Xiuying; Sui, Meili

2013-03-01

This paper describes SMS4 algorithm by using dynamic partial self-reconfiguration. The design is implemented on Xilinx VirtexII-Pro XC2VP30 FPGA devices. The partial self-reconfiguration encryption/decryption module data throughput is up to 50Mb/s, key expansion and encryption/decryption modules use 1606 and 1570 slices respectively, and the resource utilization ratio of the key expansion by using partial self-reconfiguration technology is less 32.03% and slices are less 757 than the non-reconfiguration technology. SMS4 implementation gets a good balance between high performance and low complexity in area. The theoretical and practical research of dynamic partial self-reconfiguration has a broad space for development and application prospect.

Scalable System Design for Covert MIMO Communications

DTIC Science & Technology

2014-06-01

Sample based resolution of the QRD and equalization processes in the MIMO receiver, for NQR = 11...55 5.1 NQR calculation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2 Resources available on Xilinx Virtex-7 FPGAs...carried out for Na ∈ [2 3 4]. Extrapolation is used to determine trends as a function of the number of QRD blocks instantiated NQR and Na. This section

Thermal Interface Materials Selection and Application Guidelines: In Perspective of Xilinx Virtex-5QV Thermal Management

NASA Technical Reports Server (NTRS)

Suh, Jong-ook; Dillon, R. Peter; Tseng, Stephen

2015-01-01

The heat from high-power microdevices for space, such as Xilinx Virtex 4 and 5 (V4 and V5), has to be removed mainly through conduction in the space vacuum environment. The class-Y type packages are designed to remove the heat from the top of the package, and the most effective method to remove heat from the class-Y type packages is to attach a heat transfer device on the lid of the package and to transfer the heat to frame or chassis. When a heat transfer device is attached to the package lid, the surfaces roughness of the package lid and the heat transfer device reduces the effective contact area between the two. The reduced contact area results in increased thermal contact resistance, and a thermal interface material is required to reduce the thermal contact resistance by filling in the gap between the surfaces of the package lid and the heat transfer device. The current report describes JPL's FY14 NEPP task study on property requirements of TIM and impact of TIM properties on the packaging reliability. The current task also developed appratuses to investigate the performances of TIMs in the actual mission environment.

Physics of Failure Analysis of Xilinx Flip Chip CCGA Packages: Effects of Mission Environments on Properties of LP2 Underfill and ATI Lid Adhesive Materials

NASA Technical Reports Server (NTRS)

Suh, Jong-ook

2013-01-01

The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

CoNNeCT Baseband Processor Module

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K; Jedrey, Thomas C.; Gutrich, Daniel G.; Goodpasture, Richard L.

2011-01-01

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit

NASA Technical Reports Server (NTRS)

French, Matthew; Graham, Paul; Wirthlin, Michael; Wang, Li; Larchev, Gregory

2005-01-01

The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power inefficiencies. For radiation, a single event Upset (SEU) emulator, persistence analysis tool, and a half-latch removal tool for Xilinx/Virtex-II devices have been created. Research is underway on a persistence mitigation tool and multiple bit upsets (MBU) studies. For power, synthesis level dynamic power visualization and analysis tools have been completed. Power optimization tools are under development and preliminary test results are positive.

An FPGA- Based General-Purpose Data Acquisition Controller

NASA Astrophysics Data System (ADS)

Robson, C. C. W.; Bousselham, A.; Bohm

2006-08-01

System development in advanced FPGAs allows considerable flexibility, both during development and in production use. A mixed firmware/software solution allows the developer to choose what shall be done in firmware or software, and to make that decision late in the process. However, this flexibility comes at the cost of increased complexity. We have designed a modular development framework to help to overcome these issues of increased complexity. This framework comprises a generic controller that can be adapted for different systems by simply changing the software or firmware parts. The controller can use both soft and hard processors, with or without an RTOS, based on the demands of the system to be developed. The resulting system uses the Internet for both control and data acquisition. In our studies we developed the embedded system in a Xilinx Virtex-II Pro FPGA, where we used both PowerPC and MicroBlaze cores, http, Java, and LabView for control and communication, together with the MicroC/OS-II and OSE operating systems

Image processing for a tactile/vision substitution system using digital CNN.

PubMed

Lin, Chien-Nan; Yu, Sung-Nien; Hu, Jin-Cheng

2006-01-01

In view of the parallel processing and easy implementation properties of CNN, we propose to use digital CNN as the image processor of a tactile/vision substitution system (TVSS). The digital CNN processor is used to execute the wavelet down-sampling filtering and the half-toning operations, aiming to extract important features from the images. A template combination method is used to embed the two image processing functions into a single CNN processor. The digital CNN processor is implemented on an intellectual property (IP) and is implemented on a XILINX VIRTEX II 2000 FPGA board. Experiments are designated to test the capability of the CNN processor in the recognition of characters and human subjects in different environments. The experiments demonstrates impressive results, which proves the proposed digital CNN processor a powerful component in the design of efficient tactile/vision substitution systems for the visually impaired people.

Multiple Embedded Processors for Fault-Tolerant Computing

NASA Technical Reports Server (NTRS)

Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

2005-01-01

A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

A Secure Content Delivery System Based on a Partially Reconfigurable FPGA

NASA Astrophysics Data System (ADS)

Hori, Yohei; Yokoyama, Hiroyuki; Sakane, Hirofumi; Toda, Kenji

We developed a content delivery system using a partially reconfigurable FPGA to securely distribute digital content on the Internet. With partial reconfigurability of a Xilinx Virtex-II Pro FPGA, the system provides an innovative single-chip solution for protecting digital content. In the system, a partial circuit must be downloaded from a server to the client terminal to play content. Content will be played only when the downloaded circuit is correctly combined (=interlocked) with the circuit built in the terminal. Since each circuit has a unique I/O configuration, the downloaded circuit interlocks with the corresponding built-in circuit designed for a particular terminal. Thus, the interface of the circuit itself provides a novel authentication mechanism. This paper describes the detailed architecture of the system and clarify the feasibility and effectiveness of the system. In addition, we discuss a fail-safe mechanism and future work necessary for the practical application of the system.

Mercury BLASTP: Accelerating Protein Sequence Alignment

PubMed Central

Jacob, Arpith; Lancaster, Joseph; Buhler, Jeremy; Harris, Brandon; Chamberlain, Roger D.

2008-01-01

Large-scale protein sequence comparison is an important but compute-intensive task in molecular biology. BLASTP is the most popular tool for comparative analysis of protein sequences. In recent years, an exponential increase in the size of protein sequence databases has required either exponentially more running time or a cluster of machines to keep pace. To address this problem, we have designed and built a high-performance FPGA-accelerated version of BLASTP, Mercury BLASTP. In this paper, we describe the architecture of the portions of the application that are accelerated in the FPGA, and we also describe the integration of these FPGA-accelerated portions with the existing BLASTP software. We have implemented Mercury BLASTP on a commodity workstation with two Xilinx Virtex-II 6000 FPGAs. We show that the new design runs 11-15 times faster than software BLASTP on a modern CPU while delivering close to 99% identical results. PMID:19492068

Technology Readiness Level (TRL) Advancement of the MSPI On-Board Processing Platform for the ACE Decadal Survey Mission

NASA Technical Reports Server (NTRS)

Pingree, Paula J.; Werne, Thomas A.; Bekker, Dmitriy L.; Wilson, Thor O.

2011-01-01

The Xilinx Virtex-5QV is a new Single-event Immune Reconfigurable FPGA (SIRF) device that is targeted as the spaceborne processor for the NASA Decadal Survey Aerosol-Cloud-Ecosystem (ACE) mission's Multiangle SpectroPolarimetric Imager (MSPI) instrument, currently under development at JPL. A key technology needed for MSPI is on-board processing (OBP) to calculate polarimetry data as imaged by each of the 9 cameras forming the instrument. With funding from NASA's ESTO1 AIST2 Program, JPL is demonstrating how signal data at 95 Mbytes/sec over 16 channels for each of the 9 multi-angle cameras can be reduced to 0.45 Mbytes/sec, thereby substantially reducing the image data volume for spacecraft downlink without loss of science information. This is done via a least-squares fitting algorithm implemented on the Virtex-5 FPGA operating in real-time on the raw video data stream.

A 128-channel Time-to-Digital Converter (TDC) inside a Virtex-5 FPGA on the GANDALF module

NASA Astrophysics Data System (ADS)

Büchele, M.; Fischer, H.; Gorzellik, M.; Herrmann, F.; Königsmann, K.; Schill, C.; Schopferer, S.

2012-03-01

The GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. To perform different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition and trigger generation, this module comes with exchangeable analog and digital mezzanine cards. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In contrast to common TDC concepts, the input signal is sampled by 16 equidistant phase-shifted clocks. A particular challenge of the design is the minimum skew routing of the input signals to the sampling flip-flops. We present measurement results for the differential nonlinearity and the time resolution of the TDC readout system.

Radiation Hardening by Software Techniques on FPGAs: Flight Experiment Evaluation and Results

NASA Technical Reports Server (NTRS)

Schmidt, Andrew G.; Flatley, Thomas

2017-01-01

We present our work on implementing Radiation Hardening by Software (RHBSW) techniques on the Xilinx Virtex5 FPGAs PowerPC 440 processors on the SpaceCube 2.0 platform. The techniques have been matured and tested through simulation modeling, fault emulation, laser fault injection and now in a flight experiment, as part of the Space Test Program- Houston 4-ISS SpaceCube Experiment 2.0 (STP-H4-ISE 2.0). This work leverages concepts such as heartbeat monitoring, control flow assertions, and checkpointing, commonly used in the High Performance Computing industry, and adapts them for use in remote sensing embedded systems. These techniques are extremely low overhead (typically <1.3%), enabling a 3.3x gain in processing performance as compared to the equivalent traditionally radiation hardened processor. The recently concluded STP-H4 flight experiment was an opportunity to upgrade the RHBSW techniques for the Virtex5 FPGA and demonstrate them on-board the ISS to achieve TRL 7. This work details the implementation of the RHBSW techniques, that were previously developed for the Virtex4-based SpaceCube 1.0 platform, on the Virtex5-based SpaceCube 2.0 flight platform. The evaluation spans the development and integration with flight software, remotely uploading the new experiment to the ISS SpaceCube 2.0 platform, and conducting the experiment continuously for 16 days before the platform was decommissioned. The experiment was conducted on two PowerPCs embedded within the Virtex5 FPGA devices and the experiment collected 19,400 checkpoints, processed 253,482 status messages, and incurred 0 faults. These results are highly encouraging and future work is looking into longer duration testing as part of the STP-H5 flight experiment.

Exploring Accelerating Science Applications with FPGAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Storaasli, Olaf O; Strenski, Dave

2007-01-01

FPGA hardware and tools (VHDL, Viva, MitrionC and CHiMPS) are described. FPGA performance is evaluated on two Cray XD1 systems (Virtex-II Pro 50 and Virtex-4 LX160) for human genome (DNA and protein) sequence comparisons for a computational biology code (FASTA). Scalable FPGA speedups of 50X (Virtex-II) and 100X (Virtex-4) over a 2.2 GHz Opteron were achieved. Coding and IO issues faced for human genome data are described.

Virtex-II Pro SEE Test Methods and Results

NASA Technical Reports Server (NTRS)

Petrick, David; Powell, Wesley; Howard, James W., Jr.; LaBel, Kenneth A.

2004-01-01

The objective of this coarse Single Event Effect (SEE) test is to determine the suitability of the commercial Virtex-II Pro family for use in spaceflight applications. To this end, this test is primarily intended to determine any Singe Event Latchup (SEL) susceptibilities for these devices. Secondly, this test is intended to measure the level of Single Event Upset (SEU) susceptibilities and in a general sense where they occur. The coarse SEE test was performed on a commercial XC2VP7 device, a relatively small single processor version of the Virtex-II Pro. As the XC2VP7 shares the same functional block design and fabrication process with the larger Virtex-II Pro devices, the results of this test should also be applicable to the larger devices. The XC2VP7 device was tested on a commercial Virtex-II Pro development board. The testing was performed at the Cyclotron laboratories at Texas A&M and Michigan State Universities using ions of varying energy levels and fluences.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Learn, Mark Walter

Sandia National Laboratories is currently developing new processing and data communication architectures for use in future satellite payloads. These architectures will leverage the flexibility and performance of state-of-the-art static-random-access-memory-based Field Programmable Gate Arrays (FPGAs). One such FPGA is the radiation-hardened version of the Virtex-5 being developed by Xilinx. However, not all features of this FPGA are being radiation-hardened by design and could still be susceptible to on-orbit upsets. One such feature is the embedded hard-core PPC440 processor. Since this processor is implemented in the FPGA as a hard-core, traditional mitigation approaches such as Triple Modular Redundancy (TMR) are not availablemore » to improve the processor's on-orbit reliability. The goal of this work is to investigate techniques that can help mitigate the embedded hard-core PPC440 processor within the Virtex-5 FPGA other than TMR. Implementing various mitigation schemes reliably within the PPC440 offers a powerful reconfigurable computing resource to these node-based processing architectures. This document summarizes the work done on the cache mitigation scheme for the embedded hard-core PPC440 processor within the Virtex-5 FPGAs, and describes in detail the design of the cache mitigation scheme and the testing conducted at the radiation effects facility on the Texas A&M campus.« less

A Hardware-Accelerated Quantum Monte Carlo framework (HAQMC) for N-body systems

NASA Astrophysics Data System (ADS)

Gothandaraman, Akila; Peterson, Gregory D.; Warren, G. Lee; Hinde, Robert J.; Harrison, Robert J.

2009-12-01

Interest in the study of structural and energetic properties of highly quantum clusters, such as inert gas clusters has motivated the development of a hardware-accelerated framework for Quantum Monte Carlo simulations. In the Quantum Monte Carlo method, the properties of a system of atoms, such as the ground-state energies, are averaged over a number of iterations. Our framework is aimed at accelerating the computations in each iteration of the QMC application by offloading the calculation of properties, namely energy and trial wave function, onto reconfigurable hardware. This gives a user the capability to run simulations for a large number of iterations, thereby reducing the statistical uncertainty in the properties, and for larger clusters. This framework is designed to run on the Cray XD1 high performance reconfigurable computing platform, which exploits the coarse-grained parallelism of the processor along with the fine-grained parallelism of the reconfigurable computing devices available in the form of field-programmable gate arrays. In this paper, we illustrate the functioning of the framework, which can be used to calculate the energies for a model cluster of helium atoms. In addition, we present the capabilities of the framework that allow the user to vary the chemical identities of the simulated atoms. Program summaryProgram title: Hardware Accelerated Quantum Monte Carlo (HAQMC) Catalogue identifier: AEEP_v1_0 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AEEP_v1_0.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: Standard CPC licence, http://cpc.cs.qub.ac.uk/licence/licence.html No. of lines in distributed program, including test data, etc.: 691 537 No. of bytes in distributed program, including test data, etc.: 5 031 226 Distribution format: tar.gz Programming language: C/C++ for the QMC application, VHDL and Xilinx 8.1 ISE/EDK tools for FPGA design and development Computer: Cray XD1 consisting of a dual-core, dualprocessor AMD Opteron 2.2 GHz with a Xilinx Virtex-4 (V4LX160) or Xilinx Virtex-II Pro (XC2VP50) FPGA per node. We use the compute node with the Xilinx Virtex-4 FPGA Operating system: Red Hat Enterprise Linux OS Has the code been vectorised or parallelized?: Yes Classification: 6.1 Nature of problem: Quantum Monte Carlo is a practical method to solve the Schrödinger equation for large many-body systems and obtain the ground-state properties of such systems. This method involves the sampling of a number of configurations of atoms and averaging the properties of the configurations over a number of iterations. We are interested in applying the QMC method to obtain the energy and other properties of highly quantum clusters, such as inert gas clusters. Solution method: The proposed framework provides a combined hardware-software approach, in which the QMC simulation is performed on the host processor, with the computationally intensive functions such as energy and trial wave function computations mapped onto the field-programmable gate array (FPGA) logic device attached as a co-processor to the host processor. We perform the QMC simulation for a number of iterations as in the case of our original software QMC approach, to reduce the statistical uncertainty of the results. However, our proposed HAQMC framework accelerates each iteration of the simulation, by significantly reducing the time taken to calculate the ground-state properties of the configurations of atoms, thereby accelerating the overall QMC simulation. We provide a generic interpolation framework that can be extended to study a variety of pure and doped atomic clusters, irrespective of the chemical identities of the atoms. For the FPGA implementation of the properties, we use a two-region approach for accurately computing the properties over the entire domain, employ deep pipelines and fixed-point for all our calculations guaranteeing the accuracy required for our simulation.

Hardware-Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-Architektur

NASA Astrophysics Data System (ADS)

Flatt, H.; Tarnowsky, A.; Blume, H.; Pirsch, P.

2010-10-01

Dieser Beitrag behandelt die Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-Architektur. Die Architektur besteht aus mehreren dedizierten Recheneinheiten zur parallelen Verarbeitung rechenintensiver Bildverarbeitungsverfahren und ist mit einem RISC-Prozessor verbunden. Eine konfigurierbare Architekturerweiterung um eine Recheneinheit zur Auswertung von Winkelhistogrammen von Objekten ermöglicht in Verbindung mit dem RISC eine echtzeitfähige Klassifikation. Je nach Konfiguration sind für die Architekturerweiterung auf einem Xilinx Virtex-5-FPGA zwischen 3300 und 12 000 Lookup-Tables erforderlich. Bei einer Taktfrequenz von 100 MHz können unabhängig von der Bildauflösung pro Einzelbild in einem 25-Hz-Videodatenstrom bis zu 100 Objekte der Größe 256×256 Pixel analysiert werden. This paper presents the mapping of a video-based approach for real-time evaluation of angular histograms on a modular coprocessor architecture. The architecture comprises several dedicated processing elements for parallel processing of computation-intensive image processing tasks and is coupled with a RISC processor. A configurable architecture extension, especially a processing element for evaluating angular histograms of objects in conjunction with a RISC processor, provides a real-time classification. Depending on the configuration of the architecture extension, 3 300 to 12 000 look-up tables are required for a Xilinx Virtex-5 FPGA implementation. Running at a clock frequency of 100 MHz and independently of the image resolution per frame, 100 objects of size 256×256 pixels are analyzed in a 25 Hz video stream by the architecture.

Novel intelligent real-time position tracking system using FPGA and fuzzy logic.

PubMed

Soares dos Santos, Marco P; Ferreira, J A F

2014-03-01

The main aim of this paper is to test if FPGAs are able to achieve better position tracking performance than software-based soft real-time platforms. For comparison purposes, the same controller design was implemented in these architectures. A Multi-state Fuzzy Logic controller (FLC) was implemented both in a Xilinx(®) Virtex-II FPGA (XC2v1000) and in a soft real-time platform NI CompactRIO(®)-9002. The same sampling time was used. The comparative tests were conducted using a servo-pneumatic actuation system. Steady-state errors lower than 4 μm were reached for an arbitrary vertical positioning of a 6.2 kg mass when the controller was embedded into the FPGA platform. Performance gains up to 16 times in the steady-state error, up to 27 times in the overshoot and up to 19.5 times in the settling time were achieved by using the FPGA-based controller over the software-based FLC controller. © 2013 ISA. Published by Elsevier Ltd. All rights reserved.

FPGA based hardware optimized implementation of signal processing system for LFM pulsed radar

NASA Astrophysics Data System (ADS)

Azim, Noor ul; Jun, Wang

2016-11-01

Signal processing is one of the main parts of any radar system. Different signal processing algorithms are used to extract information about different parameters like range, speed, direction etc, of a target in the field of radar communication. This paper presents LFM (Linear Frequency Modulation) pulsed radar signal processing algorithms which are used to improve target detection, range resolution and to estimate the speed of a target. Firstly, these algorithms are simulated in MATLAB to verify the concept and theory. After the conceptual verification in MATLAB, the simulation is converted into implementation on hardware using Xilinx FPGA. Chosen FPGA is Xilinx Virtex-6 (XC6LVX75T). For hardware implementation pipeline optimization is adopted and also other factors are considered for resources optimization in the process of implementation. Focusing algorithms in this work for improving target detection, range resolution and speed estimation are hardware optimized fast convolution processing based pulse compression and pulse Doppler processing.

A Re-programmable Platform for Dynamic Burn-in Test of Xilinx Virtexll 3000 FPGA for Military and Aerospace Applications

NASA Technical Reports Server (NTRS)

Roosta, Ramin; Wang, Xinchen; Sadigursky, Michael; Tracton, Phil

2004-01-01

Field Programmable Gate Arrays (FPGA) have played increasingly important roles in military and aerospace applications. Xilinx SRAM-based FPGAs have been extensively used in commercial applications. They have been used less frequently in space flight applications due to their susceptibility to single-event upsets. Reliability of these devices in space applications is a concern that has not been addressed. The objective of this project is to design a fully programmable hardware/software platform that allows (but is not limited to) comprehensive static/dynamic burn-in test of Virtex-II 3000 FPGAs, at speed test and SEU test. Conventional methods test very few discrete AC parameters (primarily switching) of a given integrated circuit. This approach will test any possible configuration of the FPGA and any associated performance parameters. It allows complete or partial re-programming of the FPGA and verification of the program by using read back followed by dynamic test. Designers have full control over which functional elements of the FPGA to stress. They can completely simulate all possible types of configurations/functions. Another benefit of this platform is that it allows collecting information on elevation of the junction temperature as a function of gate utilization, operating frequency and functionality. A software tool has been implemented to demonstrate the various features of the system. The software consists of three major parts: the parallel interface driver, main system procedure and a graphical user interface (GUI).

FPGA implemented testbed in 8-by-8 and 2-by-2 OFDM-MIMO channel estimation and design of baseband transceiver.

PubMed

Ramesh, S; Seshasayanan, R

2016-01-01

In this study, a baseband OFDM-MIMO framework with channel timing and estimation synchronization is composed and executed utilizing the FPGA innovation. The framework is prototyped in light of the IEEE 802.11a standard and the signals transmitted and received utilizing a data transmission of 20 MHz. With the assistance of the QPSK tweak, the framework can accomplish a throughput of 24 Mbps. Besides, the LS formula is executed and the estimation of a frequency-specific fading channel is illustrated. For the rough estimation of timing, MNC plan is examined and actualized. Above all else, the whole framework is demonstrated in MATLAB and a drifting point model is set up. At that point, the altered point model is made with the assistance of Simulink and Xilinx's System Generator for DSP. In this way, the framework is incorporated and actualized inside of Xilinx's ISE tools and focused to Xilinx Virtex 5 board. In addition, an equipment co-simulation is contrived to decrease the preparing time while figuring the BER of the fixed point model. The work concentrates on above all else venture for further examination of planning creative channel estimation strategies towards applications in the fourth era (4G) mobile correspondence frameworks.

High-Precision Pulse Generator

NASA Technical Reports Server (NTRS)

Katz, Richard; Kleyner, Igor

2011-01-01

A document discusses a pulse generator with subnanosecond resolution implemented with a low-cost field-programmable gate array (FPGA) at low power levels. The method used exploits the fast carry chains of certain FPGAs. Prototypes have been built and tested in both Actel AX and Xilinx Virtex 4 technologies. In-flight calibration or control can be performed by using a similar and related technique as a time interval measurement circuit by measuring a period of the stable oscillator, as the delays through the fast carry chains will vary as a result of manufacturing variances as well as the result of environmental conditions (voltage, aging, temperature, and radiation).

Embedded system of image storage based on fiber channel

NASA Astrophysics Data System (ADS)

Chen, Xiaodong; Su, Wanxin; Xing, Zhongbao; Wang, Hualong

2008-03-01

In domains of aerospace, aviation, aiming, and optic measure etc., the embedded system of imaging, processing and recording is absolutely necessary, which has small volume, high processing speed and high resolution. But the embedded storage technology becomes system bottleneck because of developing slowly. It is used to use RAID to promote storage speed, but it is unsuitable for the embedded system because of its big volume. Fiber channel (FC) technology offers a new method to develop the high-speed, portable storage system. In order to make storage subsystem meet the needs of high storage rate, make use of powerful Virtex-4 FPGA and high speed fiber channel, advance a project of embedded system of digital image storage based on Xilinx Fiber Channel Arbitrated Loop LogiCORE. This project utilizes Virtex- 4 RocketIO MGT transceivers to transmit the data serially, and connects many Fiber Channel hard drivers by using of Arbitrated Loop optionally. It can achieve 400MBps storage rate, breaks through the bottleneck of PCI interface, and has excellences of high-speed, real-time, portable and massive capacity.

Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA

PubMed Central

de Souza, Alisson C. D.; Fernandes, Marcelo A. C.

2014-01-01

This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA. PMID:25268918

Moving target detection for frequency agility radar by sparse reconstruction

NASA Astrophysics Data System (ADS)

Quan, Yinghui; Li, YaChao; Wu, Yaojun; Ran, Lei; Xing, Mengdao; Liu, Mengqi

2016-09-01

Frequency agility radar, with randomly varied carrier frequency from pulse to pulse, exhibits superior performance compared to the conventional fixed carrier frequency pulse-Doppler radar against the electromagnetic interference. A novel moving target detection (MTD) method is proposed for the estimation of the target's velocity of frequency agility radar based on pulses within a coherent processing interval by using sparse reconstruction. Hardware implementation of orthogonal matching pursuit algorithm is executed on Xilinx Virtex-7 Field Programmable Gata Array (FPGA) to perform sparse optimization. Finally, a series of experiments are performed to evaluate the performance of proposed MTD method for frequency agility radar systems.

Moving target detection for frequency agility radar by sparse reconstruction.

PubMed

Quan, Yinghui; Li, YaChao; Wu, Yaojun; Ran, Lei; Xing, Mengdao; Liu, Mengqi

2016-09-01

Frequency agility radar, with randomly varied carrier frequency from pulse to pulse, exhibits superior performance compared to the conventional fixed carrier frequency pulse-Doppler radar against the electromagnetic interference. A novel moving target detection (MTD) method is proposed for the estimation of the target's velocity of frequency agility radar based on pulses within a coherent processing interval by using sparse reconstruction. Hardware implementation of orthogonal matching pursuit algorithm is executed on Xilinx Virtex-7 Field Programmable Gata Array (FPGA) to perform sparse optimization. Finally, a series of experiments are performed to evaluate the performance of proposed MTD method for frequency agility radar systems.

NASA Accelerates SpaceCube Technology into Orbit

NASA Technical Reports Server (NTRS)

Petrick, David

2010-01-01

On May 11, 2009, STS-125 Space Shuttle Atlantis blasted off from Kennedy Space Center on a historic mission to service the Hubble Space Telescope (HST). In addition to sending up the hardware and tools required to repair the observatory, the servicing team at NASA's Goddard Space Flight Center also sent along a complex experimental payload called Relative Navigation Sensors (RNS). The main objective of the RNS payload was to provide real-time image tracking of HST during rendezvous and docking operations. RNS was a complete success, and was brought to life by four Xilinx FPGAs (Field Programmable Gate Arrays) tightly packed into one integrated computer called SpaceCube. SpaceCube is a compact, reconfigurable, multiprocessor computing platform for space applications demanding extreme processing capabilities based on Xilinx Virtex 4 FX60 FPGAs. In a matter of months, the concept quickly went from the white board to a fully funded flight project. The 4-inch by 4-inch SpaceCube processor card was prototyped by a group of Goddard engineers using internal research funding. Once engineers were able to demonstrate the processing power of SpaceCube to NASA, HST management stood behind the product and invested in a flight qualified version, inserting it into the heart of the RNS system. With the determination of putting Xilinx into space, the team strengthened to a small army and delivered a fully functional, space qualified system to the mission.

Design space exploration of high throughput finite field multipliers for channel coding on Xilinx FPGAs

NASA Astrophysics Data System (ADS)

de Schryver, C.; Weithoffer, S.; Wasenmüller, U.; Wehn, N.

2012-09-01

Channel coding is a standard technique in all wireless communication systems. In addition to the typically employed methods like convolutional coding, turbo coding or low density parity check (LDPC) coding, algebraic codes are used in many cases. For example, outer BCH coding is applied in the DVB-S2 standard for satellite TV broadcasting. A key operation for BCH and the related Reed-Solomon codes are multiplications in finite fields (Galois Fields), where extension fields of prime fields are used. A lot of architectures for multiplications in finite fields have been published over the last decades. This paper examines four different multiplier architectures in detail that offer the potential for very high throughputs. We investigate the implementation performance of these multipliers on FPGA technology in the context of channel coding. We study the efficiency of the multipliers with respect to area, frequency and throughput, as well as configurability and scalability. The implementation data of the fully verified circuits are provided for a Xilinx Virtex-4 device after place and route.

Hardware Implementation of Lossless Adaptive Compression of Data From a Hyperspectral Imager

NASA Technical Reports Server (NTRS)

Keymeulen, Didlier; Aranki, Nazeeh I.; Klimesh, Matthew A.; Bakhshi, Alireza

2012-01-01

Efficient onboard data compression can reduce the data volume from hyperspectral imagers on NASA and DoD spacecraft in order to return as much imagery as possible through constrained downlink channels. Lossless compression is important for signature extraction, object recognition, and feature classification capabilities. To provide onboard data compression, a hardware implementation of a lossless hyperspectral compression algorithm was developed using a field programmable gate array (FPGA). The underlying algorithm is the Fast Lossless (FL) compression algorithm reported in Fast Lossless Compression of Multispectral- Image Data (NPO-42517), NASA Tech Briefs, Vol. 30, No. 8 (August 2006), p. 26 with the modification reported in Lossless, Multi-Spectral Data Comressor for Improved Compression for Pushbroom-Type Instruments (NPO-45473), NASA Tech Briefs, Vol. 32, No. 7 (July 2008) p. 63, which provides improved compression performance for data from pushbroom-type imagers. An FPGA implementation of the unmodified FL algorithm was previously developed and reported in Fast and Adaptive Lossless Onboard Hyperspectral Data Compression System (NPO-46867), NASA Tech Briefs, Vol. 36, No. 5 (May 2012) p. 42. The essence of the FL algorithm is adaptive linear predictive compression using the sign algorithm for filter adaption. The FL compressor achieves a combination of low complexity and compression effectiveness that exceeds that of stateof- the-art techniques currently in use. The modification changes the predictor structure to tolerate differences in sensitivity of different detector elements, as occurs in pushbroom-type imagers, which are suitable for spacecraft use. The FPGA implementation offers a low-cost, flexible solution compared to traditional ASIC (application specific integrated circuit) and can be integrated as an intellectual property (IP) for part of, e.g., a design that manages the instrument interface. The FPGA implementation was benchmarked on the Xilinx Virtex IV LX25 device, and ported to a Xilinx prototype board. The current implementation has a critical path of 29.5 ns, which dictated a clock speed of 33 MHz. The critical path delay is end-to-end measurement between the uncompressed input data and the output compression data stream. The implementation compresses one sample every clock cycle, which results in a speed of 33 Msample/s. The implementation has a rather low device use of the Xilinx Virtex IV LX25, making the total power consumption of the implementation about 1.27 W.

Radiation tolerance of readout electronics for Belle II

NASA Astrophysics Data System (ADS)

Higuchi, T.; Nakao, M.; Nakano, E.

2012-02-01

We plan to start the Belle II experiment in 2015 and to continue data taking for more than ten years. Because some of the front-end electronics cards of Belle II are located inside the detector, radiation effects onto their components will be a severe problem. Using experimental exposure facilities of neutrons and γ rays, we study the radiation effects from these particles to the Virtex-5 FPGA, optical transceivers, and voltage regulators. The Virtex-5 FPGA is found to keep its operation after irradiation of more than 20-year-equivalent neutron flux of Belle II and 88-year-equivalent γ-ray dose. We observe single event upsets (SEUs) and multiple bit upsets (MBUs) in the Virtex-5 FPGA in the neutron irradiation. We also find almost doubled SEU counts in the Virtex-5 FPGA bombarded from its tail side than its head side. We extrapolate the observed SEU and MBU counts in the Virtex-5 FPGA to the entire readout system of the Belle II central drift chamber, and expect the SEU and MBU rates as one SEU per four minutes and one MBU per 11.5 hours, respectively. The optical transceivers are found to keep its operation after integration of 12-year-equivalent neutron flux, while they are killed by about 3-year-equivalent γ-ray dose, which should be solved in the future research. The voltage regulators are found to keep its operation for more than 10-year-equivalent γ-ray dose.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Batista, Antonio J. N.; Santos, Bruno; Fernandes, Ana

The data acquisition and control instrumentation cubicles room of the ITER tokamak will be irradiated with neutrons during the fusion reactor operation. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of I and C products - Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), functional data stored in dedicated Block RAM (BRAM) and functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons causes soft errors, unintended changes (bit-flips) to the values stored in statemore » elements of the FPGA. The SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA configuration memory. Novel SEU sensors with Error Correction Code (ECC) detect and repair the BRAM memories. Proper management of SEU can increase reliability and availability of control instrumentation hardware for nuclear applications. The results of the tests performed using the SEM controller and the BRAM SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU errors in the configuration and BRAM memories. (authors)« less

Hardware accelerator design for tracking in smart camera

NASA Astrophysics Data System (ADS)

Singh, Sanjay; Dunga, Srinivasa Murali; Saini, Ravi; Mandal, A. S.; Shekhar, Chandra; Vohra, Anil

2011-10-01

Smart Cameras are important components in video analysis. For video analysis, smart cameras needs to detect interesting moving objects, track such objects from frame to frame, and perform analysis of object track in real time. Therefore, the use of real-time tracking is prominent in smart cameras. The software implementation of tracking algorithm on a general purpose processor (like PowerPC) could achieve low frame rate far from real-time requirements. This paper presents the SIMD approach based hardware accelerator designed for real-time tracking of objects in a scene. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA. Resulted frame rate is 30 frames per second for 250x200 resolution video in gray scale.

HyspIRI Intelligent Payload Module(IPM) and Benchmarking Algorithms for Upload

NASA Technical Reports Server (NTRS)

Mandl, Daniel

2010-01-01

Features: Hardware: a) Xilinx Virtex-5 (GSFC Space Cube 2); b) 2 x 400MHz PPC; c) 100MHz Bus; d) 2 x 512MB SDRAM; e) Dual Gigabit Ethernet. Support Linux kernel 2.6.31 (gcc version 4.2.2). Support software running in stand alone mode for better performance. Can stream raw data up to 800 Mbps. Ready for operations. Software Application Examples: Band-stripping Algiotrhmsl:cloud, sulfur, flood, thermal, SWIL, NDVI, NDWI, SIWI, oil spills, algae blooms, etc. Corrections: geometric, radiometric, atmospheric. Core Flight System/dynamic software bus. CCSDS File Delivery Protocol. Delay Tolerant Network. CASPER /onboard planning. Fault monitoring/recovery software. S/C command and telemetry software. Data compression. Sensor Web for Autonomous Mission Operations.

Mitigating Upsets in SRAM Based FPGAs from the Xilinix Virtex 2 Family

NASA Technical Reports Server (NTRS)

Swift, Gary M.; Yui, Candice C.; Carmichael, Carl; Koga, Rocky; George, Jeffrey S.

2003-01-01

This slide presentation reviews the single event upset static testing of the Virtex II field programmable gate arrays (FPGA) that were tested in protons and heavy-ions. The test designs and static and dynamic test results are reviewed.

Hardware accelerator design for change detection in smart camera

NASA Astrophysics Data System (ADS)

Singh, Sanjay; Dunga, Srinivasa Murali; Saini, Ravi; Mandal, A. S.; Shekhar, Chandra; Chaudhury, Santanu; Vohra, Anil

2011-10-01

Smart Cameras are important components in Human Computer Interaction. In any remote surveillance scenario, smart cameras have to take intelligent decisions to select frames of significant changes to minimize communication and processing overhead. Among many of the algorithms for change detection, one based on clustering based scheme was proposed for smart camera systems. However, such an algorithm could achieve low frame rate far from real-time requirements on a general purpose processors (like PowerPC) available on FPGAs. This paper proposes the hardware accelerator capable of detecting real time changes in a scene, which uses clustering based change detection scheme. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA board. Resulted frame rate is 30 frames per second for QVGA resolution in gray scale.

A multi-rate DPSK modem for free-space laser communications

NASA Astrophysics Data System (ADS)

Spellmeyer, N. W.; Browne, C. A.; Caplan, D. O.; Carney, J. J.; Chavez, M. L.; Fletcher, A. S.; Fitzgerald, J. J.; Kaminsky, R. D.; Lund, G.; Hamilton, S. A.; Magliocco, R. J.; Mikulina, O. V.; Murphy, R. J.; Rao, H. G.; Scheinbart, M. S.; Seaver, M. M.; Wang, J. P.

2014-03-01

The multi-rate DPSK format, which enables efficient free-space laser communications over a wide range of data rates, is finding applications in NASA's Laser Communications Relay Demonstration. We discuss the design and testing of an efficient and robust multi-rate DPSK modem, including aspects of the electrical, mechanical, thermal, and optical design. The modem includes an optically preamplified receiver, an 0.5-W average power transmitter, a LEON3 rad-hard microcontroller that provides the command and telemetry interface and supervisory control, and a Xilinx Virtex-5 radhard reprogrammable FPGA that both supports the high-speed data flow to and from the modem and controls the modem's analog and digital subsystems. For additional flexibility, the transmitter and receiver can be configured to support operation with multi-rate PPM waveforms.

An Efficient VLSI Architecture of the Enhanced Three Step Search Algorithm

NASA Astrophysics Data System (ADS)

Biswas, Baishik; Mukherjee, Rohan; Saha, Priyabrata; Chakrabarti, Indrajit

2016-09-01

The intense computational complexity of any video codec is largely due to the motion estimation unit. The Enhanced Three Step Search is a popular technique that can be adopted for fast motion estimation. This paper proposes a novel VLSI architecture for the implementation of the Enhanced Three Step Search Technique. A new addressing mechanism has been introduced which enhances the speed of operation and reduces the area requirements. The proposed architecture when implemented in Verilog HDL on Virtex-5 Technology and synthesized using Xilinx ISE Design Suite 14.1 achieves a critical path delay of 4.8 ns while the area comes out to be 2.9K gate equivalent. It can be incorporated in commercial devices like smart-phones, camcorders, video conferencing systems etc.

High-performance reconfigurable hardware architecture for restricted Boltzmann machines.

PubMed

Ly, Daniel Le; Chow, Paul

2010-11-01

Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications has been limited. A primary cause for this lack of adoption is that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can exploit the inherent parallelism in neural networks is desired. This paper investigates how the restricted Boltzmann machine (RBM), which is a popular type of neural network, can be mapped to a high-performance hardware architecture on field-programmable gate array (FPGA) platforms. The proposed modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. A method to partition large RBMs into smaller congruent components is also presented, allowing the distribution of one RBM across multiple FPGA resources. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100 MHz through a variety of different configurations. The maximum performance was obtained by instantiating an RBM of 256 × 256 nodes distributed across four FPGAs, which resulted in a computational speed of 3.13 billion connection-updates-per-second and a speedup of 145-fold over an optimized C program running on a 2.8-GHz Intel processor.

FPGA implementation of neuro-fuzzy system with improved PSO learning.

PubMed

Karakuzu, Cihan; Karakaya, Fuat; Çavuşlu, Mehmet Ali

2016-07-01

This paper presents the first hardware implementation of neuro-fuzzy system (NFS) with its metaheuristic learning ability on field programmable gate array (FPGA). Metaheuristic learning of NFS for all of its parameters is accomplished by using the improved particle swarm optimization (iPSO). As a second novelty, a new functional approach, which does not require any memory and multiplier usage, is proposed for the Gaussian membership functions of NFS. NFS and its learning using iPSO are implemented on Xilinx Virtex5 xc5vlx110-3ff1153 and efficiency of the proposed implementation tested on two dynamic system identification problems and licence plate detection problem as a practical application. Results indicate that proposed NFS implementation and membership function approximation is as effective as the other approaches available in the literature but requires less hardware resources. Copyright © 2016 Elsevier Ltd. All rights reserved.

Field-programmable gate array implementation of an all-digital IEEE 802.15.4-compliant transceiver

NASA Astrophysics Data System (ADS)

Cornetta, Gianluca; Touhafi, Abdellah; Santos, David J.; Vázquez, José M.

2010-12-01

An architecture for a low-cost, low-complexity digital transceiver is presented in this article. The proposed architecture targets the IEEE 802.15.4 standard for short-range wireless personal area networks and has been implemented as a synthesisable VHDL register transfer level description. The system has been evaluated and tested using a Xilinx 90 nm Virtex-4 field-programmable gate array as the target technology. Bit error rate (BER) and error vector magnitude (EVM) have been used as the figures of merit for modem performance. Simulations show that the recommended minimum BER is achieved at E b/N 0 = 8.7 dB, whereas the EVM is 19.5%. The implemented device occupies 10% of the target FPGA and has a normalised maximum power consumption of 44 mW in transmit mode and 53 mW in receiver mode.

FPGA Online Tracking Algorithm for the PANDA Straw Tube Tracker

NASA Astrophysics Data System (ADS)

Liang, Yutie; Ye, Hua; Galuska, Martin J.; Gessler, Thomas; Kuhn, Wolfgang; Lange, Jens Soren; Wagner, Milan N.; Liu, Zhen'an; Zhao, Jingzhou

2017-06-01

A novel FPGA based online tracking algorithm for helix track reconstruction in a solenoidal field, developed for the PANDA spectrometer, is described. Employing the Straw Tube Tracker detector with 4636 straw tubes, the algorithm includes a complex track finder, and a track fitter. Implemented in VHDL, the algorithm is tested on a Xilinx Virtex-4 FX60 FPGA chip with different types of events, at different event rates. A processing time of 7 $\\mu$s per event for an average of 6 charged tracks is obtained. The momentum resolution is about 3\\% (4\\%) for $p_t$ ($p_z$) at 1 GeV/c. Comparing to the algorithm running on a CPU chip (single core Intel Xeon E5520 at 2.26 GHz), an improvement of 3 orders of magnitude in processing time is obtained. The algorithm can handle severe overlapping of events which are typical for interaction rates above 10 MHz.

A Practical, Hardware Friendly MMSE Detector for MIMO-OFDM-Based Systems

NASA Astrophysics Data System (ADS)

Kim, Hun Seok; Zhu, Weijun; Bhatia, Jatin; Mohammed, Karim; Shah, Anish; Daneshrad, Babak

2008-12-01

Design and implementation of a highly optimized MIMO (multiple-input multiple-output) detector requires cooptimization of the algorithm with the underlying hardware architecture. Special attention must be paid to application requirements such as throughput, latency, and resource constraints. In this work, we focus on a highly optimized matrix inversion free [InlineEquation not available: see fulltext.] MMSE (minimum mean square error) MIMO detector implementation. The work has resulted in a real-time field-programmable gate array-based implementation (FPGA-) on a Xilinx Virtex-2 6000 using only 9003 logic slices, 66 multipliers, and 24 Block RAMs (less than 33% of the overall resources of this part). The design delivers over 420 Mbps sustained throughput with a small 2.77-microsecond latency. The designed [InlineEquation not available: see fulltext.] linear MMSE MIMO detector is capable of complying with the proposed IEEE 802.11n standard.

Analyzing the effectiveness of a frame-level redundancy scrubbing technique for SRAM-based FPGAs

DOE PAGES

Tonfat, Jorge; Lima Kastensmidt, Fernanda; Rech, Paolo; ...

2015-12-17

Radiation effects such as soft errors are the major threat to the reliability of SRAM-based FPGAs. This work analyzes the effectiveness in correcting soft errors of a novel scrubbing technique using internal frame redundancy called Frame-level Redundancy Scrubbing (FLR-scrubbing). This correction technique can be implemented in a coarse grain TMR design. The FLR-scrubbing technique was implemented on a mid-size Xilinx Virtex-5 FPGA device used as a case study. The FLR-scrubbing technique was tested under neutron radiation and fault injection. Implementation results demonstrated minimum area and energy consumption overhead when compared to other techniques. The time to repair the fault ismore » also improved by using the Internal Configuration Access Port (ICAP). Lastly, neutron radiation test results demonstrated that the proposed technique is suitable for correcting accumulated SEUs and MBUs.« less

Research of x-ray nondestructive detector for high-speed running conveyor belt with steel wire ropes

NASA Astrophysics Data System (ADS)

Wang, Junfeng; Miao, Changyun; Wang, Wei; Lu, Xiaocui

2008-03-01

An X-ray nondestructive detector for high-speed running conveyor belt with steel wire ropes is researched in the paper. The principle of X-ray nondestructive testing (NDT) is analyzed, the general scheme of the X-ray nondestructive testing system is proposed, and the nondestructive detector for high-speed running conveyor belt with steel wire ropes is developed. The hardware of system is designed with Xilinx's VIRTEX-4 FPGA that embeds PowerPC and MAC IP core, and its network communication software based on TCP/IP protocol is programmed by loading LwIP to PowerPC. The nondestructive testing of high-speed conveyor belt with steel wire ropes and network transfer function are implemented. It is a strong real-time system with rapid scanning speed, high reliability and remotely nondestructive testing function. The nondestructive detector can be applied to the detection of product line in industry.

Analyzing the effectiveness of a frame-level redundancy scrubbing technique for SRAM-based FPGAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tonfat, Jorge; Lima Kastensmidt, Fernanda; Rech, Paolo

Radiation effects such as soft errors are the major threat to the reliability of SRAM-based FPGAs. This work analyzes the effectiveness in correcting soft errors of a novel scrubbing technique using internal frame redundancy called Frame-level Redundancy Scrubbing (FLR-scrubbing). This correction technique can be implemented in a coarse grain TMR design. The FLR-scrubbing technique was implemented on a mid-size Xilinx Virtex-5 FPGA device used as a case study. The FLR-scrubbing technique was tested under neutron radiation and fault injection. Implementation results demonstrated minimum area and energy consumption overhead when compared to other techniques. The time to repair the fault ismore » also improved by using the Internal Configuration Access Port (ICAP). Lastly, neutron radiation test results demonstrated that the proposed technique is suitable for correcting accumulated SEUs and MBUs.« less

Commodity cluster and hardware-based massively parallel implementations of hyperspectral imaging algorithms

NASA Astrophysics Data System (ADS)

Plaza, Antonio; Chang, Chein-I.; Plaza, Javier; Valencia, David

2006-05-01

The incorporation of hyperspectral sensors aboard airborne/satellite platforms is currently producing a nearly continual stream of multidimensional image data, and this high data volume has soon introduced new processing challenges. The price paid for the wealth spatial and spectral information available from hyperspectral sensors is the enormous amounts of data that they generate. Several applications exist, however, where having the desired information calculated quickly enough for practical use is highly desirable. High computing performance of algorithm analysis is particularly important in homeland defense and security applications, in which swift decisions often involve detection of (sub-pixel) military targets (including hostile weaponry, camouflage, concealment, and decoys) or chemical/biological agents. In order to speed-up computational performance of hyperspectral imaging algorithms, this paper develops several fast parallel data processing techniques. Techniques include four classes of algorithms: (1) unsupervised classification, (2) spectral unmixing, and (3) automatic target recognition, and (4) onboard data compression. A massively parallel Beowulf cluster (Thunderhead) at NASA's Goddard Space Flight Center in Maryland is used to measure parallel performance of the proposed algorithms. In order to explore the viability of developing onboard, real-time hyperspectral data compression algorithms, a Xilinx Virtex-II field programmable gate array (FPGA) is also used in experiments. Our quantitative and comparative assessment of parallel techniques and strategies may help image analysts in selection of parallel hyperspectral algorithms for specific applications.

FPGA-based RF spectrum merging and adaptive hopset selection

NASA Astrophysics Data System (ADS)

McLean, R. K.; Flatley, B. N.; Silvius, M. D.; Hopkinson, K. M.

The radio frequency (RF) spectrum is a limited resource. Spectrum allotment disputes stem from this scarcity as many radio devices are confined to a fixed frequency or frequency sequence. One alternative is to incorporate cognition within a reconfigurable radio platform, therefore enabling the radio to adapt to dynamic RF spectrum environments. In this way, the radio is able to actively sense the RF spectrum, decide, and act accordingly, thereby sharing the spectrum and operating in more flexible manner. In this paper, we present a novel solution for merging many distributed RF spectrum maps into one map and for subsequently creating an adaptive hopset. We also provide an example of our system in operation, the result of which is a pseudorandom adaptive hopset. The paper then presents a novel hardware design for the frequency merger and adaptive hopset selector, both of which are written in VHDL and implemented as a custom IP core on an FPGA-based embedded system using the Xilinx Embedded Development Kit (EDK) software tool. The design of the custom IP core is optimized for area, and it can process a high-volume digital input via a low-latency circuit architecture. The complete embedded system includes the Xilinx PowerPC microprocessor, UART serial connection, and compact flash memory card IP cores, and our custom map merging/hopset selection IP core, all of which are targeted to the Virtex IV FPGA. This system is then incorporated into a cognitive radio prototype on a Rice University Wireless Open Access Research Platform (WARP) reconfigurable radio.

An embedded vision system for an unmanned four-rotor helicopter

NASA Astrophysics Data System (ADS)

Lillywhite, Kirt; Lee, Dah-Jye; Tippetts, Beau; Fowers, Spencer; Dennis, Aaron; Nelson, Brent; Archibald, James

2006-10-01

In this paper an embedded vision system and control module is introduced that is capable of controlling an unmanned four-rotor helicopter and processing live video for various law enforcement, security, military, and civilian applications. The vision system is implemented on a newly designed compact FPGA board (Helios). The Helios board contains a Xilinx Virtex-4 FPGA chip and memory making it capable of implementing real time vision algorithms. A Smooth Automated Intelligent Leveling daughter board (SAIL), attached to the Helios board, collects attitude and heading information to be processed in order to control the unmanned helicopter. The SAIL board uses an electrolytic tilt sensor, compass, voltage level converters, and analog to digital converters to perform its operations. While level flight can be maintained, problems stemming from the characteristics of the tilt sensor limits maneuverability of the helicopter. The embedded vision system has proven to give very good results in its performance of a number of real-time robotic vision algorithms.

Spacecube: A Family of Reconfigurable Hybrid On-Board Science Data Processors

NASA Technical Reports Server (NTRS)

Flatley, Thomas P.

2015-01-01

SpaceCube is a family of Field Programmable Gate Array (FPGA) based on-board science data processing systems developed at the NASA Goddard Space Flight Center (GSFC). The goal of the SpaceCube program is to provide 10x to 100x improvements in on-board computing power while lowering relative power consumption and cost. SpaceCube is based on the Xilinx Virtex family of FPGAs, which include processor, FPGA logic and digital signal processing (DSP) resources. These processing elements are leveraged to produce a hybrid science data processing platform that accelerates the execution of algorithms by distributing computational functions to the most suitable elements. This approach enables the implementation of complex on-board functions that were previously limited to ground based systems, such as on-board product generation, data reduction, calibration, classification, eventfeature detection, data mining and real-time autonomous operations. The system is fully reconfigurable in flight, including data parameters, software and FPGA logic, through either ground commanding or autonomously in response to detected eventsfeatures in the instrument data stream.

Electronics design of a multi-rate DPSK modem for free-space optical communications

NASA Astrophysics Data System (ADS)

Rao, H. G.; Browne, C. A.; Caplan, D. O.; Carney, J. J.; Chavez, M. L.; Fletcher, A. S.; Fitzgerald, J. J.; Kaminsky, R. D.; Lund, G.; Hamilton, S. A.; Magliocco, R. J.; Mikulina, O. V.; Murphy, R. J.; Seaver, M. M.; Scheinbart, M. S.; Spellmeyer, N. W.; Wang, J. P.

2014-03-01

We have designed and experimentally demonstrated a radiation-hardened modem suitable for NASA's Laser Communications Relay Demonstration. The modem supports free-space DPSK communication over a wide range of channel rates, from 72 Mb/s up to 2.88 Gb/s. The modem transmitter electronics generate a bursty DPSK waveform, such that only one optical modulator is required. The receiver clock recovery is capable of operating over all channel rates at average optical signal levels below -70 dBm. The modem incorporates a radiation-hardened Xilinx Virtex 5 FPGA and a radiation-hardened Aeroflex UT699 CPU. The design leverages unique capabilities of each device, such as the FPGA's multi-gigabit transceivers. The modem scrubs itself against radiation events, but does not require pervasive triple-mode redundant logic. The modem electronics include automatic stabilization functions for its optical components, and software to control its initialization and operation. The design allows the modem to be put into a low-power standby mode.

S-Band POSIX Device Drivers for RTEMS

NASA Technical Reports Server (NTRS)

Lux, James P.; Lang, Minh; Peters, Kenneth J.; Taylor, Gregory H.

2011-01-01

This is a set of POSIX device driver level abstractions in the RTEMS RTOS (Real-Time Executive for Multiprocessor Systems real-time operating system) to SBand radio hardware devices that have been instantiated in an FPGA (field-programmable gate array). These include A/D (analog-to-digital) sample capture, D/A (digital-to-analog) sample playback, PLL (phase-locked-loop) tuning, and PWM (pulse-width-modulation)-controlled gain. This software interfaces to Sband radio hardware in an attached Xilinx Virtex-2 FPGA. It uses plug-and-play device discovery to map memory to device IDs. Instead of interacting with hardware devices directly, using direct-memory mapped access at the application level, this driver provides an application programming interface (API) offering that easily uses standard POSIX function calls. This simplifies application programming, enables portability, and offers an additional level of protection to the hardware. There are three separate device drivers included in this package: sband_device (ADC capture and DAC playback), pll_device (RF front end PLL tuning), and pwm_device (RF front end AGC control).

FPGA Implementation of the Coupled Filtering Method and the Affine Warping Method.

PubMed

Zhang, Chen; Liang, Tianzhu; Mok, Philip K T; Yu, Weichuan

2017-07-01

In ultrasound image analysis, the speckle tracking methods are widely applied to study the elasticity of body tissue. However, "feature-motion decorrelation" still remains as a challenge for the speckle tracking methods. Recently, a coupled filtering method and an affine warping method were proposed to accurately estimate strain values, when the tissue deformation is large. The major drawback of these methods is the high computational complexity. Even the graphics processing unit (GPU)-based program requires a long time to finish the analysis. In this paper, we propose field-programmable gate array (FPGA)-based implementations of both methods for further acceleration. The capability of FPGAs on handling different image processing components in these methods is discussed. A fast and memory-saving image warping approach is proposed. The algorithms are reformulated to build a highly efficient pipeline on FPGA. The final implementations on a Xilinx Virtex-7 FPGA are at least 13 times faster than the GPU implementation on the NVIDIA graphic card (GeForce GTX 580).

Hand veins feature extraction using DT-CNNS

NASA Astrophysics Data System (ADS)

Malki, Suleyman; Spaanenburg, Lambert

2007-05-01

As the identification process is based on the unique patterns of the users, biometrics technologies are expected to provide highly secure authentication systems. The existing systems using fingerprints or retina patterns are, however, very vulnerable. One's fingerprints are accessible as soon as the person touches a surface, while a high resolution camera easily captures the retina pattern. Thus, both patterns can easily be "stolen" and forged. Beside, technical considerations decrease the usability for these methods. Due to the direct contact with the finger, the sensor gets dirty, which decreases the authentication success ratio. Aligning the eye with a camera to capture the retina pattern gives uncomfortable feeling. On the other hand, vein patterns of either a palm of the hand or a single finger offer stable, unique and repeatable biometrics features. A fingerprint-based identification system using Cellular Neural Networks has already been proposed by Gao. His system covers all stages of a typical fingerprint verification procedure from Image Preprocessing to Feature Matching. This paper performs a critical review of the individual algorithmic steps. Notably, the operation of False Feature Elimination is applied only once instead of 3 times. Furthermore, the number of iterations is limited to 1 for all used templates. Hence, the computational need of the feedback contribution is removed. Consequently the computational effort is drastically reduced without a notable chance in quality. This allows a full integration of the detection mechanism. The system is prototyped on a Xilinx Virtex II Pro P30 FPGA.

FPGA implementation of sparse matrix algorithm for information retrieval

NASA Astrophysics Data System (ADS)

Bojanic, Slobodan; Jevtic, Ruzica; Nieto-Taladriz, Octavio

2005-06-01

Information text data retrieval requires a tremendous amount of processing time because of the size of the data and the complexity of information retrieval algorithms. In this paper the solution to this problem is proposed via hardware supported information retrieval algorithms. Reconfigurable computing may adopt frequent hardware modifications through its tailorable hardware and exploits parallelism for a given application through reconfigurable and flexible hardware units. The degree of the parallelism can be tuned for data. In this work we implemented standard BLAS (basic linear algebra subprogram) sparse matrix algorithm named Compressed Sparse Row (CSR) that is showed to be more efficient in terms of storage space requirement and query-processing timing over the other sparse matrix algorithms for information retrieval application. Although inverted index algorithm is treated as the de facto standard for information retrieval for years, an alternative approach to store the index of text collection in a sparse matrix structure gains more attention. This approach performs query processing using sparse matrix-vector multiplication and due to parallelization achieves a substantial efficiency over the sequential inverted index. The parallel implementations of information retrieval kernel are presented in this work targeting the Virtex II Field Programmable Gate Arrays (FPGAs) board from Xilinx. A recent development in scientific applications is the use of FPGA to achieve high performance results. Computational results are compared to implementations on other platforms. The design achieves a high level of parallelism for the overall function while retaining highly optimised hardware within processing unit.

A Method of Sky Ripple Residual Nonuniformity Reduction for a Cooled Infrared Imager and Hardware Implementation.

PubMed

Li, Yiyang; Jin, Weiqi; Li, Shuo; Zhang, Xu; Zhu, Jin

2017-05-08

Cooled infrared detector arrays always suffer from undesired ripple residual nonuniformity (RNU) in sky scene observations. The ripple residual nonuniformity seriously affects the imaging quality, especially for small target detection. It is difficult to eliminate it using the calibration-based techniques and the current scene-based nonuniformity algorithms. In this paper, we present a modified temporal high-pass nonuniformity correction algorithm using fuzzy scene classification. The fuzzy scene classification is designed to control the correction threshold so that the algorithm can remove ripple RNU without degrading the scene details. We test the algorithm on a real infrared sequence by comparing it to several well-established methods. The result shows that the algorithm has obvious advantages compared with the tested methods in terms of detail conservation and convergence speed for ripple RNU correction. Furthermore, we display our architecture with a prototype built on a Xilinx Virtex-5 XC5VLX50T field-programmable gate array (FPGA), which has two advantages: (1) low resources consumption; and (2) small hardware delay (less than 10 image rows). It has been successfully applied in an actual system.

Real-Time On-Board Processing Validation of MSPI Ground Camera Images

NASA Technical Reports Server (NTRS)

Pingree, Paula J.; Werne, Thomas A.; Bekker, Dmitriy L.

2010-01-01

The Earth Sciences Decadal Survey identifies a multiangle, multispectral, high-accuracy polarization imager as one requirement for the Aerosol-Cloud-Ecosystem (ACE) mission. JPL has been developing a Multiangle SpectroPolarimetric Imager (MSPI) as a candidate to fill this need. A key technology development needed for MSPI is on-board signal processing to calculate polarimetry data as imaged by each of the 9 cameras forming the instrument. With funding from NASA's Advanced Information Systems Technology (AIST) Program, JPL is solving the real-time data processing requirements to demonstrate, for the first time, how signal data at 95 Mbytes/sec over 16-channels for each of the 9 multiangle cameras in the spaceborne instrument can be reduced on-board to 0.45 Mbytes/sec. This will produce the intensity and polarization data needed to characterize aerosol and cloud microphysical properties. Using the Xilinx Virtex-5 FPGA including PowerPC440 processors we have implemented a least squares fitting algorithm that extracts intensity and polarimetric parameters in real-time, thereby substantially reducing the image data volume for spacecraft downlink without loss of science information.

DeepX: Deep Learning Accelerator for Restricted Boltzmann Machine Artificial Neural Networks.

PubMed

Kim, Lok-Won

2018-05-01

Although there have been many decades of research and commercial presence on high performance general purpose processors, there are still many applications that require fully customized hardware architectures for further computational acceleration. Recently, deep learning has been successfully used to learn in a wide variety of applications, but their heavy computation demand has considerably limited their practical applications. This paper proposes a fully pipelined acceleration architecture to alleviate high computational demand of an artificial neural network (ANN) which is restricted Boltzmann machine (RBM) ANNs. The implemented RBM ANN accelerator (integrating network size, using 128 input cases per batch, and running at a 303-MHz clock frequency) integrated in a state-of-the art field-programmable gate array (FPGA) (Xilinx Virtex 7 XC7V-2000T) provides a computational performance of 301-billion connection-updates-per-second and about 193 times higher performance than a software solution running on general purpose processors. Most importantly, the architecture enables over 4 times (12 times in batch learning) higher performance compared with a previous work when both are implemented in an FPGA device (XC2VP70).

Exploiting the chaotic behaviour of atmospheric models with reconfigurable architectures

NASA Astrophysics Data System (ADS)

Russell, Francis P.; Düben, Peter D.; Niu, Xinyu; Luk, Wayne; Palmer, T. N.

2017-12-01

Reconfigurable architectures are becoming mainstream: Amazon, Microsoft and IBM are supporting such architectures in their data centres. The computationally intensive nature of atmospheric modelling is an attractive target for hardware acceleration using reconfigurable computing. Performance of hardware designs can be improved through the use of reduced-precision arithmetic, but maintaining appropriate accuracy is essential. We explore reduced-precision optimisation for simulating chaotic systems, targeting atmospheric modelling, in which even minor changes in arithmetic behaviour will cause simulations to diverge quickly. The possibility of equally valid simulations having differing outcomes means that standard techniques for comparing numerical accuracy are inappropriate. We use the Hellinger distance to compare statistical behaviour between reduced-precision CPU implementations to guide reconfigurable designs of a chaotic system, then analyse accuracy, performance and power efficiency of the resulting implementations. Our results show that with only a limited loss in accuracy corresponding to less than 10% uncertainty in input parameters, the throughput and energy efficiency of a single-precision chaotic system implemented on a Xilinx Virtex-6 SX475T Field Programmable Gate Array (FPGA) can be more than doubled.

A high-throughput two channel discrete wavelet transform architecture for the JPEG2000 standard

NASA Astrophysics Data System (ADS)

Badakhshannoory, Hossein; Hashemi, Mahmoud R.; Aminlou, Alireza; Fatemi, Omid

2005-07-01

The Discrete Wavelet Transform (DWT) is increasingly recognized in image and video compression standards, as indicated by its use in JPEG2000. The lifting scheme algorithm is an alternative DWT implementation that has a lower computational complexity and reduced resource requirement. In the JPEG2000 standard two lifting scheme based filter banks are introduced: the 5/3 and 9/7. In this paper a high throughput, two channel DWT architecture for both of the JPEG2000 DWT filters is presented. The proposed pipelined architecture has two separate input channels that process the incoming samples simultaneously with minimum memory requirement for each channel. The architecture had been implemented in VHDL and synthesized on a Xilinx Virtex2 XCV1000. The proposed architecture applies DWT on a 2K by 1K image at 33 fps with a 75 MHZ clock frequency. This performance is achieved with 70% less resources than two independent single channel modules. The high throughput and reduced resource requirement has made this architecture the proper choice for real time applications such as Digital Cinema.

Active vibration control of a full scale aircraft wing using a reconfigurable controller

NASA Astrophysics Data System (ADS)

Prakash, Shashikala; Renjith Kumar, T. G.; Raja, S.; Dwarakanathan, D.; Subramani, H.; Karthikeyan, C.

2016-01-01

This work highlights the design of a Reconfigurable Active Vibration Control (AVC) System for aircraft structures using adaptive techniques. The AVC system with a multichannel capability is realized using Filtered-X Least Mean Square algorithm (FxLMS) on Xilinx Virtex-4 Field Programmable Gate Array (FPGA) platform in Very High Speed Integrated Circuits Hardware Description Language, (VHDL). The HDL design is made based on Finite State Machine (FSM) model with Floating point Intellectual Property (IP) cores for arithmetic operations. The use of FPGA facilitates to modify the system parameters even during runtime depending on the changes in user's requirements. The locations of the control actuators are optimized based on dynamic modal strain approach using genetic algorithm (GA). The developed system has been successfully deployed for the AVC testing of the full-scale wing of an all composite two seater transport aircraft. Several closed loop configurations like single channel and multi-channel control have been tested. The experimental results from the studies presented here are very encouraging. They demonstrate the usefulness of the system's reconfigurability for real time applications.

PCI bus content-addressable-memory (CAM) implementation on FPGA for pattern recognition/image retrieval in a distributed environment

NASA Astrophysics Data System (ADS)

Megherbi, Dalila B.; Yan, Yin; Tanmay, Parikh; Khoury, Jed; Woods, C. L.

2004-11-01

Recently surveillance and Automatic Target Recognition (ATR) applications are increasing as the cost of computing power needed to process the massive amount of information continues to fall. This computing power has been made possible partly by the latest advances in FPGAs and SOPCs. In particular, to design and implement state-of-the-Art electro-optical imaging systems to provide advanced surveillance capabilities, there is a need to integrate several technologies (e.g. telescope, precise optics, cameras, image/compute vision algorithms, which can be geographically distributed or sharing distributed resources) into a programmable system and DSP systems. Additionally, pattern recognition techniques and fast information retrieval, are often important components of intelligent systems. The aim of this work is using embedded FPGA as a fast, configurable and synthesizable search engine in fast image pattern recognition/retrieval in a distributed hardware/software co-design environment. In particular, we propose and show a low cost Content Addressable Memory (CAM)-based distributed embedded FPGA hardware architecture solution with real time recognition capabilities and computing for pattern look-up, pattern recognition, and image retrieval. We show how the distributed CAM-based architecture offers a performance advantage of an order-of-magnitude over RAM-based architecture (Random Access Memory) search for implementing high speed pattern recognition for image retrieval. The methods of designing, implementing, and analyzing the proposed CAM based embedded architecture are described here. Other SOPC solutions/design issues are covered. Finally, experimental results, hardware verification, and performance evaluations using both the Xilinx Virtex-II and the Altera Apex20k are provided to show the potential and power of the proposed method for low cost reconfigurable fast image pattern recognition/retrieval at the hardware/software co-design level.

Path planning on cellular nonlinear network using active wave computing technique

NASA Astrophysics Data System (ADS)

Yeniçeri, Ramazan; Yalçın, Müstak E.

2009-05-01

This paper introduces a simple algorithm to solve robot path finding problem using active wave computing techniques. A two-dimensional Cellular Neural/Nonlinear Network (CNN), consist of relaxation oscillators, has been used to generate active waves and to process the visual information. The network, which has been implemented on a Field Programmable Gate Array (FPGA) chip, has the feature of being programmed, controlled and observed by a host computer. The arena of the robot is modelled as the medium of the active waves on the network. Active waves are employed to cover the whole medium with their own dynamics, by starting from an initial point. The proposed algorithm is achieved by observing the motion of the wave-front of the active waves. Host program first loads the arena model onto the active wave generator network and command to start the generation. Then periodically pulls the network image from the generator hardware to analyze evolution of the active waves. When the algorithm is completed, vectorial data image is generated. The path from any of the pixel on this image to the active wave generating pixel is drawn by the vectors on this image. The robot arena may be a complicated labyrinth or may have a simple geometry. But, the arena surface always must be flat. Our Autowave Generator CNN implementation which is settled on the Xilinx University Program Virtex-II Pro Development System is operated by a MATLAB program running on the host computer. As the active wave generator hardware has 16, 384 neurons, an arena with 128 × 128 pixels can be modeled and solved by the algorithm. The system also has a monitor and network image is depicted on the monitor simultaneously.

The Application of Virtex-II Pro FPGA in High-Speed Image Processing Technology of Robot Vision Sensor

NASA Astrophysics Data System (ADS)

Ren, Y. J.; Zhu, J. G.; Yang, X. Y.; Ye, S. H.

2006-10-01

The Virtex-II Pro FPGA is applied to the vision sensor tracking system of IRB2400 robot. The hardware platform, which undertakes the task of improving SNR and compressing data, is constructed by using the high-speed image processing of FPGA. The lower level image-processing algorithm is realized by combining the FPGA frame and the embedded CPU. The velocity of image processing is accelerated due to the introduction of FPGA and CPU. The usage of the embedded CPU makes it easily to realize the logic design of interface. Some key techniques are presented in the text, such as read-write process, template matching, convolution, and some modules are simulated too. In the end, the compare among the modules using this design, using the PC computer and using the DSP, is carried out. Because the high-speed image processing system core is a chip of FPGA, the function of which can renew conveniently, therefore, to a degree, the measure system is intelligent.

A Method of Sky Ripple Residual Nonuniformity Reduction for a Cooled Infrared Imager and Hardware Implementation

PubMed Central

Li, Yiyang; Jin, Weiqi; Li, Shuo; Zhang, Xu; Zhu, Jin

2017-01-01

Cooled infrared detector arrays always suffer from undesired ripple residual nonuniformity (RNU) in sky scene observations. The ripple residual nonuniformity seriously affects the imaging quality, especially for small target detection. It is difficult to eliminate it using the calibration-based techniques and the current scene-based nonuniformity algorithms. In this paper, we present a modified temporal high-pass nonuniformity correction algorithm using fuzzy scene classification. The fuzzy scene classification is designed to control the correction threshold so that the algorithm can remove ripple RNU without degrading the scene details. We test the algorithm on a real infrared sequence by comparing it to several well-established methods. The result shows that the algorithm has obvious advantages compared with the tested methods in terms of detail conservation and convergence speed for ripple RNU correction. Furthermore, we display our architecture with a prototype built on a Xilinx Virtex-5 XC5VLX50T field-programmable gate array (FPGA), which has two advantages: (1) low resources consumption; and (2) small hardware delay (less than 10 image rows). It has been successfully applied in an actual system. PMID:28481320

The GANDALF 128-Channel Time-to-Digital Converter

NASA Astrophysics Data System (ADS)

Büchele, M.; Fischer, H.; Herrmann, F.; Königsmann, K.; Schill, C.; Schopferer, S.

The GANDALF 6U-VME64x/VXS module has been designed to cope with a variety of readout tasks in high energy and nuclear physics experiments, in particular the COMPASS experiment at CERN. The exchangeable mezzanine cards allow for an employment of the system in very different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition or fast trigger generation. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In this concept each input signal is continuously sampled by 16 flip-flops using equidistant phase-shifted clocks. Compared to previous FPGA designs, usually based on delay lines and comprising few TDC channels with resolutions in the order of 10 ps, our design permits the implementation of a large number of TDC channels with a resolution of 64 ps in a single FPGA. Predictable placement of logic components and uniform routing inside the FPGA fabric is a particular challenge of this design. We present measurement results for the time resolution and the nonlinearity of the TDC readout system.

Fast neuromimetic object recognition using FPGA outperforms GPU implementations.

PubMed

Orchard, Garrick; Martin, Jacob G; Vogelstein, R Jacob; Etienne-Cummings, Ralph

2013-08-01

Recognition of objects in still images has traditionally been regarded as a difficult computational problem. Although modern automated methods for visual object recognition have achieved steadily increasing recognition accuracy, even the most advanced computational vision approaches are unable to obtain performance equal to that of humans. This has led to the creation of many biologically inspired models of visual object recognition, among them the hierarchical model and X (HMAX) model. HMAX is traditionally known to achieve high accuracy in visual object recognition tasks at the expense of significant computational complexity. Increasing complexity, in turn, increases computation time, reducing the number of images that can be processed per unit time. In this paper we describe how the computationally intensive and biologically inspired HMAX model for visual object recognition can be modified for implementation on a commercial field-programmable aate Array, specifically the Xilinx Virtex 6 ML605 evaluation board with XC6VLX240T FPGA. We show that with minor modifications to the traditional HMAX model we can perform recognition on images of size 128 × 128 pixels at a rate of 190 images per second with a less than 1% loss in recognition accuracy in both binary and multiclass visual object recognition tasks.

Ripple FPN reduced algorithm based on temporal high-pass filter and hardware implementation

NASA Astrophysics Data System (ADS)

Li, Yiyang; Li, Shuo; Zhang, Zhipeng; Jin, Weiqi; Wu, Lei; Jin, Minglei

2016-11-01

Cooled infrared detector arrays always suffer from undesired Ripple Fixed-Pattern Noise (FPN) when observe the scene of sky. The Ripple Fixed-Pattern Noise seriously affect the imaging quality of thermal imager, especially for small target detection and tracking. It is hard to eliminate the FPN by the Calibration based techniques and the current scene-based nonuniformity algorithms. In this paper, we present a modified space low-pass and temporal high-pass nonuniformity correction algorithm using adaptive time domain threshold (THP&GM). The threshold is designed to significantly reduce ghosting artifacts. We test the algorithm on real infrared in comparison to several previously published methods. This algorithm not only can effectively correct common FPN such as Stripe, but also has obviously advantage compared with the current methods in terms of detail protection and convergence speed, especially for Ripple FPN correction. Furthermore, we display our architecture with a prototype built on a Xilinx Virtex-5 XC5VLX50T field-programmable gate array (FPGA). The hardware implementation of the algorithm based on FPGA has two advantages: (1) low resources consumption, and (2) small hardware delay (less than 20 lines). The hardware has been successfully applied in actual system.

FPGA Implementation of Metastability-Based True Random Number Generator

NASA Astrophysics Data System (ADS)

Hata, Hisashi; Ichikawa, Shuichi

True random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in free-running ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with full-custom LSI technology, this study presents an implementation based on common FPGA technology. Our TRNG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64-256 latches are XOR'ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5Mbps throughput.

DESDynI Quad First Stage Processor - A Four Channel Digitizer and Digital Beam Forming Processor

NASA Technical Reports Server (NTRS)

Chuang, Chung-Lun; Shaffer, Scott; Smythe, Robert; Niamsuwan, Noppasin; Li, Samuel; Liao, Eric; Lim, Chester; Morfopolous, Arin; Veilleux, Louise

2013-01-01

The proposed Deformation, Eco-Systems, and Dynamics of Ice Radar (DESDynI-R) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique. The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high precision and high-speed analog to digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam form the receive signals. Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynI instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6. This paper will detail the design and development of the prototype qFSP as well as the preliminary results from hardware tests.

An FPGA-Based Rapid Wheezing Detection System

PubMed Central

Lin, Bor-Shing; Yen, Tian-Shiue

2014-01-01

Wheezing is often treated as a crucial indicator in the diagnosis of obstructive pulmonary diseases. A rapid wheezing detection system may help physicians to monitor patients over the long-term. In this study, a portable wheezing detection system based on a field-programmable gate array (FPGA) is proposed. This system accelerates wheezing detection, and can be used as either a single-process system, or as an integrated part of another biomedical signal detection system. The system segments sound signals into 2-second units. A short-time Fourier transform was used to determine the relationship between the time and frequency components of wheezing sound data. A spectrogram was processed using 2D bilateral filtering, edge detection, multithreshold image segmentation, morphological image processing, and image labeling, to extract wheezing features according to computerized respiratory sound analysis (CORSA) standards. These features were then used to train the support vector machine (SVM) and build the classification models. The trained model was used to analyze sound data to detect wheezing. The system runs on a Xilinx Virtex-6 FPGA ML605 platform. The experimental results revealed that the system offered excellent wheezing recognition performance (0.912). The detection process can be used with a clock frequency of 51.97 MHz, and is able to perform rapid wheezing classification. PMID:24481034

Bitstream decoding processor for fast entropy decoding of variable length coding-based multiformat videos

NASA Astrophysics Data System (ADS)

Jo, Hyunho; Sim, Donggyu

2014-06-01

We present a bitstream decoding processor for entropy decoding of variable length coding-based multiformat videos. Since most of the computational complexity of entropy decoders comes from bitstream accesses and table look-up process, the developed bitstream processing unit (BsPU) has several designated instructions to access bitstreams and to minimize branch operations in the table look-up process. In addition, the instruction for bitstream access has the capability to remove emulation prevention bytes (EPBs) of H.264/AVC without initial delay, repeated memory accesses, and additional buffer. Experimental results show that the proposed method for EPB removal achieves a speed-up of 1.23 times compared to the conventional EPB removal method. In addition, the BsPU achieves speed-ups of 5.6 and 3.5 times in entropy decoding of H.264/AVC and MPEG-4 Visual bitstreams, respectively, compared to an existing processor without designated instructions and a new table mapping algorithm. The BsPU is implemented on a Xilinx Virtex5 LX330 field-programmable gate array. The MPEG-4 Visual (ASP, Level 5) and H.264/AVC (Main Profile, Level 4) are processed using the developed BsPU with a core clock speed of under 250 MHz in real time.

An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks

PubMed Central

Pani, Danilo; Meloni, Paolo; Tuveri, Giuseppe; Palumbo, Francesca; Massobrio, Paolo; Raffo, Luigi

2017-01-01

In the last years, the idea to dynamically interface biological neurons with artificial ones has become more and more urgent. The reason is essentially due to the design of innovative neuroprostheses where biological cell assemblies of the brain can be substituted by artificial ones. For closed-loop experiments with biological neuronal networks interfaced with in silico modeled networks, several technological challenges need to be faced, from the low-level interfacing between the living tissue and the computational model to the implementation of the latter in a suitable form for real-time processing. Field programmable gate arrays (FPGAs) can improve flexibility when simple neuronal models are required, obtaining good accuracy, real-time performance, and the possibility to create a hybrid system without any custom hardware, just programming the hardware to achieve the required functionality. In this paper, this possibility is explored presenting a modular and efficient FPGA design of an in silico spiking neural network exploiting the Izhikevich model. The proposed system, prototypically implemented on a Xilinx Virtex 6 device, is able to simulate a fully connected network counting up to 1,440 neurons, in real-time, at a sampling rate of 10 kHz, which is reasonable for small to medium scale extra-cellular closed-loop experiments. PMID:28293163

Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

NASA Astrophysics Data System (ADS)

Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

2014-05-01

With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

Reconfigurable Hardware for Compressing Hyperspectral Image Data

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh; Namkung, Jeffrey; Villapando, Carlos; Kiely, Aaron; Klimesh, Matthew; Xie, Hua

2010-01-01

High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of the FPGAs makes it possible to effectively alter the design to some extent to satisfy different requirements without adding hardware. The implementation could be easily propagated to future FPGA generations and/or to custom application-specific integrated circuits.

Electronics for CMS Endcap Muon Level-1 Trigger System Phase-1 and HL LHC upgrades

NASA Astrophysics Data System (ADS)

Madorsky, A.

2017-07-01

To accommodate high-luminosity LHC operation at a 13 TeV collision energy, the CMS Endcap Muon Level-1 Trigger system had to be significantly modified. To provide robust track reconstruction, the trigger system must now import all available trigger primitives generated by the Cathode Strip Chambers and by certain other subsystems, such as Resistive Plate Chambers (RPC). In addition to massive input bandwidth, this also required significant increase in logic and memory resources. To satisfy these requirements, a new Sector Processor unit has been designed. It consists of three modules. The Core Logic module houses the large FPGA that contains the track-finding logic and multi-gigabit serial links for data exchange. The Optical module contains optical receivers and transmitters; it communicates with the Core Logic module via a custom backplane section. The Pt Lookup table (PTLUT) module contains 1 GB of low-latency memory that is used to assign the final Pt to reconstructed muon tracks. The μ TCA architecture (adopted by CMS) was used for this design. The talk presents the details of the hardware and firmware design of the production system based on Xilinx Virtex-7 FPGA family. The next round of LHC and CMS upgrades starts in 2019, followed by a major High-Luminosity (HL) LHC upgrade starting in 2024. In the course of these upgrades, new Gas Electron Multiplier (GEM) detectors and more RPC chambers will be added to the Endcap Muon system. In order to keep up with all these changes, a new Advanced Processor unit is being designed. This device will be based on Xilinx UltraScale+ FPGAs. It will be able to accommodate up to 100 serial links with bit rates of up to 25 Gb/s, and provide up to 2.5 times more logic resources than the device used currently. The amount of PTLUT memory will be significantly increased to provide more flexibility for the Pt assignment algorithm. The talk presents preliminary details of the hardware design program.

Design for Security Workshop

DTIC Science & Technology

2014-09-30

fingerprint sensor etc.  Secure application execution  Trust established outwards  With normal world apps  With internet/cloud apps...Xilinx Zynq Security Components and Capabilities © Copyright 2014 Xilinx . Security Features Inherited from FPGAs Zynq Secure Boot TrustZone...2014 Xilinx . Security Features Inherited from FPGAs Zynq Secure Boot TrustZone Integration 4 Agenda © Copyright 2014 Xilinx . Device DNA and User

Optimizing latency in Xilinx FPGA implementations of the GBT

NASA Astrophysics Data System (ADS)

Muschter, S.; Baron, S.; Bohm, C.; Cachemiche, J.-P.; Soos, C.

2010-12-01

The GigaBit Transceiver (GBT) [1] system has been developed to replace the Timing, Trigger and Control (TTC) system [2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation [3]. This code was optimized for resource utilization [4], as the GBT protocol is very demanding. It was not, however, optimized for latency — which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board [5] equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

Area and power efficient DCT architecture for image compression

NASA Astrophysics Data System (ADS)

Dhandapani, Vaithiyanathan; Ramachandran, Seshasayanan

2014-12-01

The discrete cosine transform (DCT) is one of the major components in image and video compression systems. The final output of these systems is interpreted by the human visual system (HVS), which is not perfect. The limited perception of human visualization allows the algorithm to be numerically approximate rather than exact. In this paper, we propose a new matrix for discrete cosine transform. The proposed 8 × 8 transformation matrix contains only zeros and ones which requires only adders, thus avoiding the need for multiplication and shift operations. The new class of transform requires only 12 additions, which highly reduces the computational complexity and achieves a performance in image compression that is comparable to that of the existing approximated DCT. Another important aspect of the proposed transform is that it provides an efficient area and power optimization while implementing in hardware. To ensure the versatility of the proposal and to further evaluate the performance and correctness of the structure in terms of speed, area, and power consumption, the model is implemented on Xilinx Virtex 7 field programmable gate array (FPGA) device and synthesized with Cadence® RTL Compiler® using UMC 90 nm standard cell library. The analysis obtained from the implementation indicates that the proposed structure is superior to the existing approximation techniques with a 30% reduction in power and 12% reduction in area.

Waveform Developer's Guide for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio System (STRS) Radio

NASA Technical Reports Server (NTRS)

Shalkhauser, Mary Jo W.; Roche, Rigoberto

2017-01-01

The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS-compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx(Trademark) ML605 Virtex(Trademark)-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek(Trademark) eBox 620-110-FL) running the Ubuntu 12.4 operating system. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications. The purpose of this document is to describe how to develop a new waveform using the RIACS platform and the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) FPGA wrapper code and the STRS implementation on the Axiomtek processor.

Configurable Crossbar Switch for Deterministic, Low-latency Inter-blade Communications in a MicroTCA Platform

DOE Office of Scientific and Technical Information (OSTI.GOV)

Karamooz, Saeed; Breeding, John Eric; Justice, T Alan

As MicroTCA expands into applications beyond the telecommunications industry from which it originated, it faces new challenges in the area of inter-blade communications. The ability to achieve deterministic, low-latency communications between blades is critical to realizing a scalable architecture. In the past, legacy bus architectures accomplished inter-blade communications using dedicated parallel buses across the backplane. Because of limited fabric resources on its backplane, MicroTCA uses the carrier hub (MCH) for this purpose. Unfortunately, MCH products from commercial vendors are limited to standard bus protocols such as PCI Express, Serial Rapid IO and 10/40GbE. While these protocols have exceptional throughput capability,more » they are neither deterministic nor necessarily low-latency. To overcome this limitation, an MCH has been developed based on the Xilinx Virtex-7 690T FPGA. This MCH provides the system architect/developer complete flexibility in both the interface protocol and routing of information between blades. In this paper, we present the application of this configurable MCH concept to the Machine Protection System under development for the Spallation Neutron Sources's proton accelerator. Specifically, we demonstrate the use of the configurable MCH as a 12x4-lane crossbar switch using the Aurora protocol to achieve a deterministic, low-latency data link. In this configuration, the crossbar has an aggregate bandwidth of 48 GB/s.« less

Optimization of the Multi-Spectral Euclidean Distance Calculation for FPGA-based Spaceborne Systems

NASA Technical Reports Server (NTRS)

Cristo, Alejandro; Fisher, Kevin; Perez, Rosa M.; Martinez, Pablo; Gualtieri, Anthony J.

2012-01-01

Due to the high quantity of operations that spaceborne processing systems must carry out in space, new methodologies and techniques are being presented as good alternatives in order to free the main processor from work and improve the overall performance. These include the development of ancillary dedicated hardware circuits that carry out the more redundant and computationally expensive operations in a faster way, leaving the main processor free to carry out other tasks while waiting for the result. One of these devices is SpaceCube, a FPGA-based system designed by NASA. The opportunity to use FPGA reconfigurable architectures in space allows not only the optimization of the mission operations with hardware-level solutions, but also the ability to create new and improved versions of the circuits, including error corrections, once the satellite is already in orbit. In this work, we propose the optimization of a common operation in remote sensing: the Multi-Spectral Euclidean Distance calculation. For that, two different hardware architectures have been designed and implemented in a Xilinx Virtex-5 FPGA, the same model of FPGAs used by SpaceCube. Previous results have shown that the communications between the embedded processor and the circuit create a bottleneck that affects the overall performance in a negative way. In order to avoid this, advanced methods including memory sharing, Native Port Interface (NPI) connections and Data Burst Transfers have been used.

FPGA in-the-loop simulations of cardiac excitation model under voltage clamp conditions

NASA Astrophysics Data System (ADS)

Othman, Norliza; Adon, Nur Atiqah; Mahmud, Farhanahani

2017-01-01

Voltage clamp technique allows the detection of single channel currents in biological membranes in identifying variety of electrophysiological problems in the cellular level. In this paper, a simulation study of the voltage clamp technique has been presented to analyse current-voltage (I-V) characteristics of ion currents based on Luo-Rudy Phase-I (LR-I) cardiac model by using a Field Programmable Gate Array (FPGA). Nowadays, cardiac models are becoming increasingly complex which can cause a vast amount of time to run the simulation. Thus, a real-time hardware implementation using FPGA could be one of the best solutions for high-performance real-time systems as it provides high configurability and performance, and able to executes in parallel mode operation. For shorter time development while retaining high confidence results, FPGA-based rapid prototyping through HDL Coder from MATLAB software has been used to construct the algorithm for the simulation system. Basically, the HDL Coder is capable to convert the designed MATLAB Simulink blocks into hardware description language (HDL) for the FPGA implementation. As a result, the voltage-clamp fixed-point design of LR-I model has been successfully conducted in MATLAB Simulink and the simulation of the I-V characteristics of the ionic currents has been verified on Xilinx FPGA Virtex-6 XC6VLX240T development board through an FPGA-in-the-loop (FIL) simulation.

VIRTEX-5 Fpga Implementation of Advanced Encryption Standard Algorithm

NASA Astrophysics Data System (ADS)

Rais, Muhammad H.; Qasim, Syed M.

2010-06-01

In this paper, we present an implementation of Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Virtex-5 Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a maximum throughput of 4.34 Gbps utilizing a total of 399 slices.

High-speed, multi-channel detector readout electronics for fast radiation detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hennig, Wolfgang

2012-06-22

In this project, we are developing a high speed digital spectrometer that a) captures detector waveforms at rates up to 500 MSPS b) has upgraded event data acquisition with additional data buffers for zero dead time operation c) moves energy calculations to the FPGA to increase spectrometer throughput in fast scintillator applications d) uses a streamlined architecture and high speed data interface for even faster readout to the host PC These features are in addition to the standard functions in our existing spectrometers such as digitization, programmable trigger and energy filters, pileup inspection, data acquisition with energy and time stamps,more » MCA histograms, and run statistics. In Phase I, we upgraded one of our existing spectrometer designs to demonstrate the key principle of fast waveform capture using a 500 MSPS, 12 bit ADC and a Xilinx Virtex-4 FPGA. This upgraded spectrometer, named P500, performed well in initial tests of energy resolution, pulse shape analysis, and timing measurements, thus achieving item (a) above. In Phase II, we are revising the P500 to build a commercial prototype with the improvements listed in items (b)-(d). As described in the previous report, two devices were built to pursue this goal, named the Pixie-500 and the Pixie-500 Express. The Pixie-500 has only minor improvements from the Phase I prototype and is intended as an early commercial product (its production and part of its development were funded outside the SBIR). It also allows testing of the ADC performance in real applications.The Pixie-500 Express (or Pixie-500e) includes all of the improvements (b)-(d). At the end of Phase II of the project, we have tested and debugged the hardware, firmware and software of the Pixie-500 Express prototype boards delivered 12/3/2010. This proved substantially more complex than anticipated. At the time of writing, all hardware bugs have been fixed, the PCI Express interface is working, the SDRAM has been successfully tested and the SHARC DSP has been booted with preliminary code. All new ICs and circuitry on the prototype are working properly, however some of the planned firmware and software functions have not yet been completely implemented and debugged. Overall, due to the unanticipated complexity of the PCI Express interface, some aspects of the project could not be completed with the time and funds available in Phase II. These aspects will be completed in self-funded Phase III.« less

Aeroflex Technology as Class-Y Demonstrator

NASA Technical Reports Server (NTRS)

Suh, Jong-ook; Agarwal, Shri; Popelar, Scott

2014-01-01

Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.

Fpga based L-band pulse doppler radar design and implementation

NASA Astrophysics Data System (ADS)

Savci, Kubilay

As its name implies RADAR (Radio Detection and Ranging) is an electromagnetic sensor used for detection and locating targets from their return signals. Radar systems propagate electromagnetic energy, from the antenna which is in part intercepted by an object. Objects reradiate a portion of energy which is captured by the radar receiver. The received signal is then processed for information extraction. Radar systems are widely used for surveillance, air security, navigation, weather hazard detection, as well as remote sensing applications. In this work, an FPGA based L-band Pulse Doppler radar prototype, which is used for target detection, localization and velocity calculation has been built and a general-purpose Pulse Doppler radar processor has been developed. This radar is a ground based stationary monopulse radar, which transmits a short pulse with a certain pulse repetition frequency (PRF). Return signals from the target are processed and information about their location and velocity is extracted. Discrete components are used for the transmitter and receiver chain. The hardware solution is based on Xilinx Virtex-6 ML605 FPGA board, responsible for the control of the radar system and the digital signal processing of the received signal, which involves Constant False Alarm Rate (CFAR) detection and Pulse Doppler processing. The algorithm is implemented in MATLAB/SIMULINK using the Xilinx System Generator for DSP tool. The field programmable gate arrays (FPGA) implementation of the radar system provides the flexibility of changing parameters such as the PRF and pulse length therefore it can be used with different radar configurations as well. A VHDL design has been developed for 1Gbit Ethernet connection to transfer digitized return signal and detection results to PC. An A-Scope software has been developed with C# programming language to display time domain radar signals and detection results on PC. Data are processed both in FPGA chip and on PC. FPGA uses fixed point arithmetic operations as it is fast and facilitates source requirement as it consumes less hardware than floating point arithmetic operations. The software uses floating point arithmetic operations, which ensure precision in processing at the expense of speed. The functionality of the radar system has been tested for experimental validation in the field with a moving car and the validation of submodules are tested with synthetic data simulated on MATLAB.

NASA Tech Briefs, February 2012

NASA Technical Reports Server (NTRS)

2012-01-01

This issue contains the following briefs: (1) Optical Comb from a Whispering Gallery Mode Resonator for Spectroscopy and Astronomy Instruments Calibration (2) Real-Time Flight Envelope Monitoring System (3) Nemesis Autonomous Test System (4) Mirror Metrology Using Nano-Probe Supports (5) Automated Lab-on-a-Chip Electrophoresis System (6) Techniques for Down-Sampling a Measured Surface Height Map for Model Validation (7) Multi-Component, Multi-Point Interferometric Rayleigh/Mie Doppler Velocimeter (8) Frequency to Voltage Converter Analog Front-End Prototype (9) Dust-Tolerant Intelligent Electrical Connection System (10) Gigabit Ethernet Asynchronous Clock Compensation FIFO (11) High-Speed, Multi-Channel Serial ADC LVDS Interface for Xilinx Virtex-5 FPGA (12) Glovebox for GeoLab Subsystem in HDU1-PEM (13) Modified Process Reduces Porosity when Soldering in Reduced Gravity Environments (14) Use of Functionalized Carbon Nanotubes for Covalent Attachment of Nanotubes to Silicon (15) Flexible Plug Repair for Shuttle Wing Leading Edge (16) Three Dimensionally Interlinked, Dense, Solid Form of Single-Walled CNT Ropes (17) Axel Robotic Platform for Crater and Extreme Terrain Exploration (18) Site Tamper and Material Plow Tool - STAMP (19) Magnetic Interface for Segmented Mirror Assembly (20) Transpiration-Cooled Spacecraft-Insulation-Repair Fasteners (21) Fluorescence-Based Sensor for Monitoring Activation of Lunar Dust (22) Aperture Ion Source (23) Virtual Ultrasound Guidance for Inexperienced Operators (24) Model-Based Fault Diagnosis: Performing Root Cause and Impact Analyses in Real Time (25) Interactive Schematic Integration Within the Propellant System Modeling Environment (26) Magnetic and Electric Field Polarizations of Oblique Magnetospheric Chorus Waves (27) Variable Sampling Mapping.

RFI Risk Reduction Activities Using New Goddard Digital Radiometry Capabilities

NASA Technical Reports Server (NTRS)

Bradley, Damon; Kim, Ed; Young, Peter; Miles, Lynn; Wong, Mark; Morris, Joel

2012-01-01

The Goddard Radio-Frequency Explorer (GREX) is the latest fast-sampling radiometer digital back-end processor that will be used for radiometry and radio-frequency interference (RFI) surveying at Goddard Space Flight Center. The system is compact and deployable, with a mass of about 40 kilograms. It is intended to be flown on aircraft. GREX is compatible with almost any aircraft, including P-3, twin otter, C-23, C-130, G3, and G5 types. At a minimum, the system can function as a clone of the Soil Moisture Active Passive (SMAP) ground-based development unit [1], or can be a completely independent system that is interfaced to any radiometer, provided that frequency shifting to GREX's intermediate frequency is performed prior to sampling. If the radiometer RF is less than 200MHz, then the band can be sampled and acquired directly by the system. A key feature of GREX is its ability to simultaneously sample two polarization channels simultaneously at up to 400MSPS, 14-bit resolution each. The sampled signals can be recorded continuously to a 23 TB solid-state RAID storage array. Data captures can be analyzed offline using the supercomputing facilities at Goddard Space Flight Center. In addition, various Field Programmable Gate Array (FPGA) - amenable radiometer signal processing and RFI detection algorithms can be implemented directly on the GREX system because it includes a high-capacity Xilinx Virtex-5 FPGA prototyping system that is user customizable.

The KLOE-2 high energy taggers

NASA Astrophysics Data System (ADS)

Curciarello, F.

2017-06-01

The precision measurement of the π0 → γγ width allows to gain insights into the low-energy QCD dynamics. A way to achieve the precision needed (1%) in order to test theory predictions is to study the π0 production through γγ fusion in the e+e- → e+e-γ*γ* → e+e-π0 reaction. The KLOE-2 experiment, currently running at the DAΦNE facility in Frascati, aims to perform this measurement. For this reason, new detectors, which allow to tag final state leptons, have been installed along the DAΦNE beam line in order to reduce the background coming from phi-meson decays. The High Energy Tagger (HET) detector measures the deviation of leptons from their main orbit by determining their position and timing. The HET detectors are placed in roman pots just at the exit of the DAΦNE dipole magnets, 11 m away from the IP, both on positron and electron sides. The HET sensitive area is made up of a set of 28 plastic scintillators. A dedicated DAQ electronic board, based on a Xilinx Virtex-5 FPGA, has been developed for this detector. It provides a MultiHit TDC with a time resolution of 550(1) ps and the possibility to clearly identify the correct bunch crossing (ΔTbunch ~ 2.7 ns). The most relevant features of the KLOE-2 tagging system operation as time performance, stability and the techniques used to determine the time overlap between the KLOE and HET asynchronous DAQs will be presented.

The Unified Floating Point Vector Coprocessor for Reconfigurable Hardware

NASA Astrophysics Data System (ADS)

Kathiara, Jainik

There has been an increased interest recently in using embedded cores on FPGAs. Many of the applications that make use of these cores have floating point operations. Due to the complexity and expense of floating point hardware, these algorithms are usually converted to fixed point operations or implemented using floating-point emulation in software. As the technology advances, more and more homogeneous computational resources and fixed function embedded blocks are added to FPGAs and hence implementation of floating point hardware becomes a feasible option. In this research we have implemented a high performance, autonomous floating point vector Coprocessor (FPVC) that works independently within an embedded processor system. We have presented a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. The Hybrid vector/SIMD computational model of FPVC results in greater overall performance for most applications along with improved peak performance compared to other approaches. By parameterizing vector length and the number of vector lanes, we can design an application specific FPVC and take optimal advantage of the FPGA fabric. For this research we have also initiated designing a software library for various computational kernels, each of which adapts FPVC's configuration and provide maximal performance. The kernels implemented are from the area of linear algebra and include matrix multiplication and QR and Cholesky decomposition. We have demonstrated the operation of FPVC on a Xilinx Virtex 5 using the embedded PowerPC.

Fast and Adaptive Lossless On-Board Hyperspectral Data Compression System for Space Applications

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh; Bakhshi, Alireza; Keymeulen, Didier; Klimesh, Matthew

2009-01-01

Efficient on-board lossless hyperspectral data compression reduces the data volume necessary to meet NASA and DoD limited downlink capabilities. The techniques also improves signature extraction, object recognition and feature classification capabilities by providing exact reconstructed data on constrained downlink resources. At JPL a novel, adaptive and predictive technique for lossless compression of hyperspectral data was recently developed. This technique uses an adaptive filtering method and achieves a combination of low complexity and compression effectiveness that far exceeds state-of-the-art techniques currently in use. The JPL-developed 'Fast Lossless' algorithm requires no training data or other specific information about the nature of the spectral bands for a fixed instrument dynamic range. It is of low computational complexity and thus well-suited for implementation in hardware, which makes it practical for flight implementations of pushbroom instruments. A prototype of the compressor (and decompressor) of the algorithm is available in software, but this implementation may not meet speed and real-time requirements of some space applications. Hardware acceleration provides performance improvements of 10x-100x vs. the software implementation (about 1M samples/sec on a Pentium IV machine). This paper describes a hardware implementation of the JPL-developed 'Fast Lossless' compression algorithm on a Field Programmable Gate Array (FPGA). The FPGA implementation targets the current state of the art FPGAs (Xilinx Virtex IV and V families) and compresses one sample every clock cycle to provide a fast and practical real-time solution for Space applications.

Hardware Implementation of Lossless Adaptive and Scalable Hyperspectral Data Compression for Space

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh; Keymeulen, Didier; Bakhshi, Alireza; Klimesh, Matthew

2009-01-01

On-board lossless hyperspectral data compression reduces data volume in order to meet NASA and DoD limited downlink capabilities. The technique also improves signature extraction, object recognition and feature classification capabilities by providing exact reconstructed data on constrained downlink resources. At JPL a novel, adaptive and predictive technique for lossless compression of hyperspectral data was recently developed. This technique uses an adaptive filtering method and achieves a combination of low complexity and compression effectiveness that far exceeds state-of-the-art techniques currently in use. The JPL-developed 'Fast Lossless' algorithm requires no training data or other specific information about the nature of the spectral bands for a fixed instrument dynamic range. It is of low computational complexity and thus well-suited for implementation in hardware. A modified form of the algorithm that is better suited for data from pushbroom instruments is generally appropriate for flight implementation. A scalable field programmable gate array (FPGA) hardware implementation was developed. The FPGA implementation achieves a throughput performance of 58 Msamples/sec, which can be increased to over 100 Msamples/sec in a parallel implementation that uses twice the hardware resources This paper describes the hardware implementation of the 'Modified Fast Lossless' compression algorithm on an FPGA. The FPGA implementation targets the current state-of-the-art FPGAs (Xilinx Virtex IV and V families) and compresses one sample every clock cycle to provide a fast and practical real-time solution for space applications.

Hardware Interface Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio Ssystem (STRS) Radio

NASA Technical Reports Server (NTRS)

Shalkhauser, Mary Jo W.; Roche, Rigoberto

2017-01-01

The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS-compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe how to develop a new waveform using the RIACS platform and the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) FPGA wrapper code and the STRS implementation on the Axiomtek processor.

Research and design of portable photoelectric rotary table data-acquisition and analysis system

NASA Astrophysics Data System (ADS)

Yang, Dawei; Yang, Xiufang; Han, Junfeng; Yan, Xiaoxu

2015-02-01

Photoelectric rotary table as the main test tracking measurement platform, widely use in shooting range and aerospace fields. In the range of photoelectric tracking measurement system, in order to meet the photoelectric testing instruments and equipment of laboratory and field application demand, research and design the portable photoelectric rotary table data acquisition and analysis system, and introduces the FPGA device based on Xilinx company Virtex-4 series and its peripheral module of the system hardware design, and the software design of host computer in VC++ 6.0 programming platform and MFC package based on class libraries. The data acquisition and analysis system for data acquisition, display and storage, commission control, analysis, laboratory wave playback, transmission and fault diagnosis, and other functions into an organic whole, has the advantages of small volume, can be embedded, high speed, portable, simple operation, etc. By photoelectric tracking turntable as experimental object, carries on the system software and hardware alignment, the experimental results show that the system can realize the data acquisition, analysis and processing of photoelectric tracking equipment and control of turntable debugging good, and measurement results are accurate, reliable and good maintainability and extensibility. The research design for advancing the photoelectric tracking measurement equipment debugging for diagnosis and condition monitoring and fault analysis as well as the standardization and normalization of the interface and improve the maintainability of equipment is of great significance, and has certain innovative and practical value.

The characterization and application of a low resource FPGA-based time to digital converter

NASA Astrophysics Data System (ADS)

Balla, Alessandro; Mario Beretta, Matteo; Ciambrone, Paolo; Gatta, Maurizio; Gonnella, Francesco; Iafolla, Lorenzo; Mascolo, Matteo; Messi, Roberto; Moricciani, Dario; Riondino, Domenico

2014-03-01

Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of "off-the-shelf" TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4×Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured.

Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs

NASA Astrophysics Data System (ADS)

Dias, Tiago; Roma, Nuno; Sousa, Leonel

2014-12-01

A unified architecture for fast and efficient computation of the set of two-dimensional (2-D) transforms adopted by the most recent state-of-the-art digital video standards is presented in this paper. Contrasting to other designs with similar functionality, the presented architecture is supported on a scalable, modular and completely configurable processing structure. This flexible structure not only allows to easily reconfigure the architecture to support different transform kernels, but it also permits its resizing to efficiently support transforms of different orders (e.g. order-4, order-8, order-16 and order-32). Consequently, not only is it highly suitable to realize high-performance multi-standard transform cores, but it also offers highly efficient implementations of specialized processing structures addressing only a reduced subset of transforms that are used by a specific video standard. The experimental results that were obtained by prototyping several configurations of this processing structure in a Xilinx Virtex-7 FPGA show the superior performance and hardware efficiency levels provided by the proposed unified architecture for the implementation of transform cores for the Advanced Video Coding (AVC), Audio Video coding Standard (AVS), VC-1 and High Efficiency Video Coding (HEVC) standards. In addition, such results also demonstrate the ability of this processing structure to realize multi-standard transform cores supporting all the standards mentioned above and that are capable of processing the 8k Ultra High Definition Television (UHDTV) video format (7,680 × 4,320 at 30 fps) in real time.

Electronic readout system for the Belle II imaging Time-Of-Propagation detector

NASA Astrophysics Data System (ADS)

Kotchetkov, Dmitri

2017-07-01

The imaging Time-Of-Propagation (iTOP) detector, constructed for the Belle II experiment at the SuperKEKB e+e- collider, is an 8192-channel high precision Cherenkov particle identification detector with timing resolution below 50 ps. To acquire data from the iTOP, a novel front-end electronic readout system was designed, built, and integrated. Switched-capacitor array application-specific integrated circuits are used to sample analog signals. Triggering, digitization, readout, and data transfer are controlled by Xilinx Zynq-7000 system on a chip devices.

Upgrading the Digital Electronics of the PEP-II Bunch Current Monitors at the Stanford Linear Accelerator Center

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kline, Josh; /SLAC

2006-08-28

The testing of the upgrade prototype for the bunch current monitors (BCMs) in the PEP-II storage rings at the Stanford Linear Accelerator Center (SLAC) is the topic of this paper. Bunch current monitors are used to measure the charge in the electron/positron bunches traveling in particle storage rings. The BCMs in the PEP-II storage rings need to be upgraded because components of the current system have failed and are known to be failure prone with age, and several of the integrated chips are no longer produced making repairs difficult if not impossible. The main upgrade is replacing twelve old (1995)more » field programmable gate arrays (FPGAs) with a single Virtex II FPGA. The prototype was tested using computer synthesis tools, a commercial signal generator, and a fast pulse generator.« less

Implementation of a Loosely-Coupled Lockstep Approach in the Xilinx Zynq-7000 All Programmable SoC for High Consequence Applications

DTIC Science & Technology

2017-03-01

Implementation of a Loosely-Coupled Lockstep Approach in the Xilinx Zynq-7000 All Programmable SoC™ for High Consequence Applications Ryan D...sandia.gov Abstract: For high consequence applications requiring information assurance, the architecture of the Xilinx Zynq- 7000 All Programmable ...transaction checker residing in the Programmable Logic portion of the Zynq device will be discussed along with implementation results and latency

Parallel point-multiplication architecture using combined group operations for high-speed cryptographic applications

PubMed Central

Saeedi, Ehsan; Kong, Yinan

2017-01-01

In this paper, we propose a novel parallel architecture for fast hardware implementation of elliptic curve point multiplication (ECPM), which is the key operation of an elliptic curve cryptography processor. The point multiplication over binary fields is synthesized on both FPGA and ASIC technology by designing fast elliptic curve group operations in Jacobian projective coordinates. A novel combined point doubling and point addition (PDPA) architecture is proposed for group operations to achieve high speed and low hardware requirements for ECPM. It has been implemented over the binary field which is recommended by the National Institute of Standards and Technology (NIST). The proposed ECPM supports two Koblitz and random curves for the key sizes 233 and 163 bits. For group operations, a finite-field arithmetic operation, e.g. multiplication, is designed on a polynomial basis. The delay of a 233-bit point multiplication is only 3.05 and 3.56 μs, in a Xilinx Virtex-7 FPGA, for Koblitz and random curves, respectively, and 0.81 μs in an ASIC 65-nm technology, which are the fastest hardware implementation results reported in the literature to date. In addition, a 163-bit point multiplication is also implemented in FPGA and ASIC for fair comparison which takes around 0.33 and 0.46 μs, respectively. The area-time product of the proposed point multiplication is very low compared to similar designs. The performance (1Area×Time=1AT) and Area × Time × Energy (ATE) product of the proposed design are far better than the most significant studies found in the literature. PMID:28459831

STAR: FPGA-based software defined satellite transponder

NASA Astrophysics Data System (ADS)

Davalle, Daniele; Cassettari, Riccardo; Saponara, Sergio; Fanucci, Luca; Cucchi, Luca; Bigongiari, Franco; Errico, Walter

2013-05-01

This paper presents STAR, a flexible Telemetry, Tracking & Command (TT&C) transponder for Earth Observation (EO) small satellites, developed in collaboration with INTECS and SITAEL companies. With respect to state-of-the-art EO transponders, STAR includes the possibility of scientific data transfer thanks to the 40 Mbps downlink data-rate. This feature represents an important optimization in terms of hardware mass, which is important for EO small satellites. Furthermore, in-flight re-configurability of communication parameters via telecommand is important for in-orbit link optimization, which is especially useful for low orbit satellites where visibility can be as short as few hundreds of seconds. STAR exploits the principles of digital radio to minimize the analog section of the transceiver. 70MHz intermediate frequency (IF) is the interface with an external S/X band radio-frequency front-end. The system is composed of a dedicated configurable high-speed digital signal processing part, the Signal Processor (SP), described in technology-independent VHDL working with a clock frequency of 184.32MHz and a low speed control part, the Control Processor (CP), based on the 32-bit Gaisler LEON3 processor clocked at 32 MHz, with SpaceWire and CAN interfaces. The quantization parameters were fine-tailored to reach a trade-off between hardware complexity and implementation loss which is less than 0.5 dB at BER = 10-5 for the RX chain. The IF ports require 8-bit precision. The system prototype is fitted on the Xilinx Virtex 6 VLX75T-FF484 FPGA of which a space-qualified version has been announced. The total device occupation is 82 %.

TOT measurement implemented in FPGA TDC

NASA Astrophysics Data System (ADS)

Fan, Huan-Huan; Cao, Ping; Liu, Shu-Bin; An, Qi

2015-11-01

Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays (FPGAs), FPGA time-to-digital converters (TDCs) have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold (TOT) measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC's integrity. This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method, TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates. Supported by National Natural Science Foundation of China (11079003, 10979003)

Parallel point-multiplication architecture using combined group operations for high-speed cryptographic applications.

PubMed

Hossain, Md Selim; Saeedi, Ehsan; Kong, Yinan

2017-01-01

In this paper, we propose a novel parallel architecture for fast hardware implementation of elliptic curve point multiplication (ECPM), which is the key operation of an elliptic curve cryptography processor. The point multiplication over binary fields is synthesized on both FPGA and ASIC technology by designing fast elliptic curve group operations in Jacobian projective coordinates. A novel combined point doubling and point addition (PDPA) architecture is proposed for group operations to achieve high speed and low hardware requirements for ECPM. It has been implemented over the binary field which is recommended by the National Institute of Standards and Technology (NIST). The proposed ECPM supports two Koblitz and random curves for the key sizes 233 and 163 bits. For group operations, a finite-field arithmetic operation, e.g. multiplication, is designed on a polynomial basis. The delay of a 233-bit point multiplication is only 3.05 and 3.56 μs, in a Xilinx Virtex-7 FPGA, for Koblitz and random curves, respectively, and 0.81 μs in an ASIC 65-nm technology, which are the fastest hardware implementation results reported in the literature to date. In addition, a 163-bit point multiplication is also implemented in FPGA and ASIC for fair comparison which takes around 0.33 and 0.46 μs, respectively. The area-time product of the proposed point multiplication is very low compared to similar designs. The performance ([Formula: see text]) and Area × Time × Energy (ATE) product of the proposed design are far better than the most significant studies found in the literature.

Evaluation of FPGA to PC feedback loop

NASA Astrophysics Data System (ADS)

Linczuk, Pawel; Zabolotny, Wojciech M.; Wojenski, Andrzej; Krawczyk, Rafal D.; Pozniak, Krzysztof T.; Chernyshova, Maryna; Czarski, Tomasz; Gaska, Michal; Kasprowicz, Grzegorz; Kowalska-Strzeciwilk, Ewa; Malinowski, Karol

2017-08-01

The paper presents the evaluation study of the performance of the data transmission subsystem which can be used in High Energy Physics (HEP) and other High-Performance Computing (HPC) systems. The test environment consisted of Xilinx Artix-7 FPGA and server-grade PC connected via the PCIe 4xGen2 bus. The DMA engine was based on the Xilinx DMA for PCI Express Subsystem1 controlled by the modified Xilinx XDMA kernel driver.2 The research is focused on the influence of the system configuration on achievable throughput and latency of data transfer.

Multiplier less high-speed squaring circuit for binary numbers

NASA Astrophysics Data System (ADS)

Sethi, Kabiraj; Panda, Rutuparna

2015-03-01

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth's algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

SpaceCube v2.0 Space Flight Hybrid Reconfigurable Data Processing System

NASA Technical Reports Server (NTRS)

Petrick, Dave

2014-01-01

This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications. The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences. This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of an Engineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x 100mm in size The typical power draw of the processor card is 8 to 10W and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection.Finally, this paper will describe how this system is being used to solve the extreme challenges of a robotic satellite servicing mission where typical space-rated processors are not sufficient enough to meet the intensive data processing requirements. The SpaceCube v2.0 is the main payload control computer and is required to control critical subsystems such as autonomous rendezvous and docking using a suite of vision sensors and object avoidance when controlling two robotic arms.

Pixel Perfect

DOE Office of Scientific and Technical Information (OSTI.GOV)

Perrine, Kenneth A.; Hopkins, Derek F.; Lamarche, Brian L.

2005-09-01

Biologists and computer engineers at Pacific Northwest National Laboratory have specified, designed, and implemented a hardware/software system for performing real-time, multispectral image processing on a confocal microscope. This solution is intended to extend the capabilities of the microscope, enabling scientists to conduct advanced experiments on cell signaling and other kinds of protein interactions. FRET (fluorescence resonance energy transfer) techniques are used to locate and monitor protein activity. In FRET, it is critical that spectral images be precisely aligned with each other despite disturbances in the physical imaging path caused by imperfections in lenses and cameras, and expansion and contraction ofmore » materials due to temperature changes. The central importance of this work is therefore automatic image registration. This runs in a framework that guarantees real-time performance (processing pairs of 1024x1024, 8-bit images at 15 frames per second) and enables the addition of other types of advanced image processing algorithms such as image feature characterization. The supporting system architecture consists of a Visual Basic front-end containing a series of on-screen interfaces for controlling various aspects of the microscope and a script engine for automation. One of the controls is an ActiveX component written in C++ for handling the control and transfer of images. This component interfaces with a pair of LVDS image capture boards and a PCI board containing a 6-million gate Xilinx Virtex-II FPGA. Several types of image processing are performed on the FPGA in a pipelined fashion, including the image registration. The FPGA offloads work that would otherwise need to be performed by the main CPU and has a guaranteed real-time throughput. Image registration is performed in the FPGA by applying a cubic warp on one image to precisely align it with the other image. Before each experiment, an automated calibration procedure is run in order to set up the cubic warp. During image acquisitions, the cubic warp is evaluated by way of forward differencing. Unwanted pixelation artifacts are minimized by bilinear sampling. The resulting system is state-of-the-art for biological imaging. Precisely registered images enable the reliable use of FRET techniques. In addition, real-time image processing performance allows computed images to be fed back and displayed to scientists immediately, and the pipelined nature of the FPGA allows additional image processing algorithms to be incorporated into the system without slowing throughput.« less

Experiences on developing digital down conversion algorithms using Xilinx system generator

NASA Astrophysics Data System (ADS)

Xu, Chengfa; Yuan, Yuan; Zhao, Lizhi

2013-07-01

The Digital Down Conversion (DDC) algorithm is a classical signal processing method which is widely used in radar and communication systems. In this paper, the DDC function is implemented by Xilinx System Generator tool on FPGA. System Generator is an FPGA design tool provided by Xilinx Inc and MathWorks Inc. It is very convenient for programmers to manipulate the design and debug the function, especially for the complex algorithm. Through the developing process of DDC function based on System Generator, the results show that System Generator is a very fast and efficient tool for FPGA design.

Reconfigurable Processing Module

NASA Technical Reports Server (NTRS)

Somervill, Kevin; Hodson, Robert; Jones, Robert; Williams, John

2005-01-01

To accommodate a wide spectrum of applications and technologies, NASA s Exploration System's Missions Directorate has called for reconfigurable and modular technologies to support future missions to the moon and Mars. In response, Langley Research Center is leading a program entitled Reconfigurable Scaleable Computing (RSC) that is centered on the development of FPGA-based computing resources in a stackable form factor. This paper details the architecture and implementation of the Reconfigurable Processing Module (RPM), which is the key element of the RSC system. The RPM is an FPGA-based, space-qualified printed circuit assembly leveraging terrestrial/commercial design standards into the space applications domain. The form factor is similar to, and backwards compatible with, the PCI-104 standard utilizing only the PCI interface. The size is expanded to accommodate the required functionality while still better than 30% smaller than a 3U CompactPCI(TradeMark)card and without the overhead of the backplane. The architecture is built around two FPGA devices, one hosting PCI and memory interfaces, and another hosting mission application resources; both of which are connected with a high-speed data bus. The PCI interface FPGA provides access via the PCI bus to onboard SDRAM, flash PROM, and the application resources; both configuration management as well as runtime interaction. The reconfigurable FPGA, referred to as the Application FPGA - or simply "the application" - is a radiation-tolerant Xilinx Virtex-4 FX60 hosting custom application specific logic or soft microprocessor IP. The RPM implements various SEE mitigation techniques including TMR, EDAC, and configuration scrubbing of the reconfigurable FPGA. Prototype hardware and formal modeling techniques are used to explore the performability trade space. These models provide a novel way to calculate quality-of-service performance measures while simultaneously considering fault-related behavior due to SEE soft errors.

Programmable Logic Device (PLD) Design Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio System (STRS) Radio

NASA Technical Reports Server (NTRS)

Shalkhauser, Mary Jo W.

2017-01-01

The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. At the conclusion of the development, the software and hardware description language (HDL) code was delivered to JSC for their use in their iPAS test bed to get hands-on experience with the STRS standard, and for development of their own STRS Waveforms on the now STRS compliant platform.The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe the design of the HDL code for the FPGA portion of the iPAS STRS Radio particularly the design of the FPGA wrapper and the test waveform.

Parallel heterogeneous architectures for efficient OMP compressive sensing reconstruction

NASA Astrophysics Data System (ADS)

Kulkarni, Amey; Stanislaus, Jerome L.; Mohsenin, Tinoosh

2014-05-01

Compressive Sensing (CS) is a novel scheme, in which a signal that is sparse in a known transform domain can be reconstructed using fewer samples. The signal reconstruction techniques are computationally intensive and have sluggish performance, which make them impractical for real-time processing applications . The paper presents novel architectures for Orthogonal Matching Pursuit algorithm, one of the popular CS reconstruction algorithms. We show the implementation results of proposed architectures on FPGA, ASIC and on a custom many-core platform. For FPGA and ASIC implementation, a novel thresholding method is used to reduce the processing time for the optimization problem by at least 25%. Whereas, for the custom many-core platform, efficient parallelization techniques are applied, to reconstruct signals with variant signal lengths of N and sparsity of m. The algorithm is divided into three kernels. Each kernel is parallelized to reduce execution time, whereas efficient reuse of the matrix operators allows us to reduce area. Matrix operations are efficiently paralellized by taking advantage of blocked algorithms. For demonstration purpose, all architectures reconstruct a 256-length signal with maximum sparsity of 8 using 64 measurements. Implementation on Xilinx Virtex-5 FPGA, requires 27.14 μs to reconstruct the signal using basic OMP. Whereas, with thresholding method it requires 18 μs. ASIC implementation reconstructs the signal in 13 μs. However, our custom many-core, operating at 1.18 GHz, takes 18.28 μs to complete. Our results show that compared to the previous published work of the same algorithm and matrix size, proposed architectures for FPGA and ASIC implementations perform 1.3x and 1.8x respectively faster. Also, the proposed many-core implementation performs 3000x faster than the CPU and 2000x faster than the GPU.

Dual Active Bridge based DC Transformer LabVIEW FPGA Control Code

DOE Office of Scientific and Technical Information (OSTI.GOV)

In the area of power electronics control, Field Programmable Gate Arrays (FPGAs) have the capability to outperform their Digital Signal Processor (DSP) counterparts due to the FPGA’s ability to implement true parallel processing and therefore facilitate higher switching frequencies, higher control bandwidth, and/or enhanced functionality. National Instruments (NI) has developed two platforms, Compact RIO (cRIO) and Single Board RIO (sbRIO), which combine a real-time processor with an FPGA. The FPGA can be programmed with a subset of the well-known LabVIEW graphical programming language. The candidate software implements complete control algorithms in LabVIEW FPGA for a DC Transformer (DCX) based onmore » a dual active bridge (DAB). A DCX is an isolated bi-directional DC-DC converter designed to operate at unity conversion ratio, M, defined by where Vin is the primary-side DC bus voltage, Vout is the secondary-side DC bus voltage, and n is the turns ratio of the embedded high frequency transformer (HFX). The DCX based on a DAB incorporates two H-bridges, a resonant inductor, and an HFX to provide this functionality. The candidate software employs phase-shift modulation of the two H-bridges and a feedback loop to regulate the conversion ratio at unity. The software also includes alarm-handling capabilities as well as debugging and tuning tools. The software fits on the Xilinx Virtex V LX110 FPGA embedded in the NI cRIO-9118 FPGA chassis, and with a 40 MHz base clock, supports a modulation update rate of 40 MHz, and user-settable switching frequencies and synchronized control loop update rates of tens of kHz.« less

Fast and Adaptive Lossless Onboard Hyperspectral Data Compression System

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh I.; Keymeulen, Didier; Kimesh, Matthew A.

2012-01-01

Modern hyperspectral imaging systems are able to acquire far more data than can be downlinked from a spacecraft. Onboard data compression helps to alleviate this problem, but requires a system capable of power efficiency and high throughput. Software solutions have limited throughput performance and are power-hungry. Dedicated hardware solutions can provide both high throughput and power efficiency, while taking the load off of the main processor. Thus a hardware compression system was developed. The implementation uses a field-programmable gate array (FPGA). The implementation is based on the fast lossless (FL) compression algorithm reported in Fast Lossless Compression of Multispectral-Image Data (NPO-42517), NASA Tech Briefs, Vol. 30, No. 8 (August 2006), page 26, which achieves excellent compression performance and has low complexity. This algorithm performs predictive compression using an adaptive filtering method, and uses adaptive Golomb coding. The implementation also packetizes the coded data. The FL algorithm is well suited for implementation in hardware. In the FPGA implementation, one sample is compressed every clock cycle, which makes for a fast and practical realtime solution for space applications. Benefits of this implementation are: 1) The underlying algorithm achieves a combination of low complexity and compression effectiveness that exceeds that of techniques currently in use. 2) The algorithm requires no training data or other specific information about the nature of the spectral bands for a fixed instrument dynamic range. 3) Hardware acceleration provides a throughput improvement of 10 to 100 times vs. the software implementation. A prototype of the compressor is available in software, but it runs at a speed that does not meet spacecraft requirements. The hardware implementation targets the Xilinx Virtex IV FPGAs, and makes the use of this compressor practical for Earth satellites as well as beyond-Earth missions with hyperspectral instruments.

Design of a reversible single precision floating point subtractor.

PubMed

Anantha Lakshmi, Av; Sudha, Gf

2014-01-04

In recent years, Reversible logic has emerged as a major area of research due to its ability to reduce the power dissipation which is the main requirement in the low power digital circuit design. It has wide applications like low power CMOS design, Nano-technology, Digital signal processing, Communication, DNA computing and Optical computing. Floating-point operations are needed very frequently in nearly all computing disciplines, and studies have shown floating-point addition/subtraction to be the most used floating-point operation. However, few designs exist on efficient reversible BCD subtractors but no work on reversible floating point subtractor. In this paper, it is proposed to present an efficient reversible single precision floating-point subtractor. The proposed design requires reversible designs of an 8-bit and a 24-bit comparator unit, an 8-bit and a 24-bit subtractor, and a normalization unit. For normalization, a 24-bit Reversible Leading Zero Detector and a 24-bit reversible shift register is implemented to shift the mantissas. To realize a reversible 1-bit comparator, in this paper, two new 3x3 reversible gates are proposed The proposed reversible 1-bit comparator is better and optimized in terms of the number of reversible gates used, the number of transistor count and the number of garbage outputs. The proposed work is analysed in terms of number of reversible gates, garbage outputs, constant inputs and quantum costs. Using these modules, an efficient design of a reversible single precision floating point subtractor is proposed. Proposed circuits have been simulated using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3. The total on-chip power consumed by the proposed 32-bit reversible floating point subtractor is 0.410 W.

Reconfigurable fault tolerant avionics system

NASA Astrophysics Data System (ADS)

Ibrahim, M. M.; Asami, K.; Cho, Mengu

This paper presents the design of a reconfigurable avionics system based on modern Static Random Access Memory (SRAM)-based Field Programmable Gate Array (FPGA) to be used in future generations of nano satellites. A major concern in satellite systems and especially nano satellites is to build robust systems with low-power consumption profiles. The system is designed to be flexible by providing the capability of reconfiguring itself based on its orbital position. As Single Event Upsets (SEU) do not have the same severity and intensity in all orbital locations, having the maximum at the South Atlantic Anomaly (SAA) and the polar cusps, the system does not have to be fully protected all the time in its orbit. An acceptable level of protection against high-energy cosmic rays and charged particles roaming in space is provided within the majority of the orbit through software fault tolerance. Check pointing and roll back, besides control flow assertions, is used for that level of protection. In the minority part of the orbit where severe SEUs are expected to exist, a reconfiguration for the system FPGA is initiated where the processor systems are triplicated and protection through Triple Modular Redundancy (TMR) with feedback is provided. This technique of reconfiguring the system as per the level of the threat expected from SEU-induced faults helps in reducing the average dynamic power consumption of the system to one-third of its maximum. This technique can be viewed as a smart protection through system reconfiguration. The system is built on the commercial version of the (XC5VLX50) Xilinx Virtex5 FPGA on bulk silicon with 324 IO. Simulations of orbit SEU rates were carried out using the SPENVIS web-based software package.

High-performance hardware implementation of a parallel database search engine for real-time peptide mass fingerprinting

PubMed Central

Bogdán, István A.; Rivers, Jenny; Beynon, Robert J.; Coca, Daniel

2008-01-01

Motivation: Peptide mass fingerprinting (PMF) is a method for protein identification in which a protein is fragmented by a defined cleavage protocol (usually proteolysis with trypsin), and the masses of these products constitute a ‘fingerprint’ that can be searched against theoretical fingerprints of all known proteins. In the first stage of PMF, the raw mass spectrometric data are processed to generate a peptide mass list. In the second stage this protein fingerprint is used to search a database of known proteins for the best protein match. Although current software solutions can typically deliver a match in a relatively short time, a system that can find a match in real time could change the way in which PMF is deployed and presented. In a paper published earlier we presented a hardware design of a raw mass spectra processor that, when implemented in Field Programmable Gate Array (FPGA) hardware, achieves almost 170-fold speed gain relative to a conventional software implementation running on a dual processor server. In this article we present a complementary hardware realization of a parallel database search engine that, when running on a Xilinx Virtex 2 FPGA at 100 MHz, delivers 1800-fold speed-up compared with an equivalent C software routine, running on a 3.06 GHz Xeon workstation. The inherent scalability of the design means that processing speed can be multiplied by deploying the design on multiple FPGAs. The database search processor and the mass spectra processor, running on a reconfigurable computing platform, provide a complete real-time PMF protein identification solution. Contact: d.coca@sheffield.ac.uk PMID:18453553

Effectiveness of Internal vs. External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis

NASA Technical Reports Server (NTRS)

Berg, Melanie; Poivey C.; Petrick, D.; Espinosa, D.; Lesea, Austin; LaBel, K. A.; Friendlich, M; Kim, H; Phan, A.

2008-01-01

We compare two scrubbing mitigation schemes for Xilinx FPGA devices. The design of the scrubbers is briefly discussed along with an examination of mitigation limitations. Proton and Heavy Ion data are then presented and analyzed.

Single Event Effects in FPGA Devices 2015-2016

NASA Technical Reports Server (NTRS)

Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

2016-01-01

This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

Single Event Effects in FPGA Devices 2014-2015

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth A.; Pellish, Jonathan

2015-01-01

This presentation provides an overview of single event effects in FPGA devices 2014-2015 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

Single Event Effects in FPGA Devices 2015-2016

NASA Technical Reports Server (NTRS)

Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

2016-01-01

This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

75 FR 7031 - Xilinx, Inc., Albuquerque, NM; Notice of Affirmative Determination Regarding Application for...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-02-16

... DEPARTMENT OF LABOR Employment and Training Administration [TA-W-71,608] Xilinx, Inc., Albuquerque, NM; Notice of Affirmative Determination Regarding Application for Reconsideration By application... After careful review of the application, I conclude that the claim is of sufficient weight to justify...

Porting of an FPGA Based High Data Rate DVB-S2 Modulator

DTIC Science & Technology

2011-06-13

broadcast satellite market. The physical layer is detailed in the ETSI EN 302 307 V 1.1.2 (2006-06) standard. The waveform has seen broad adoption and...independent u IRRC Atar fi I I ii I .• DDS l; OAC Interface ~ (opCIontJ) " " 7 a RRC Filler V; ~ implementation, and one from Xilinx, which is...at 37- 38 is shown in Fignre 6. Additionally, the HDR DVB-S2 waveform running on the BDR-I was tested for interoperability at the physical layer

Open Component Portability Infrastructure (OPENCPI)

DTIC Science & Technology

2009-11-01

Disk Drive 7 1 www.antec.com P182 $120. ATX Mid Tower Computer Case 8 1 www.xilinx.com HW-V5-ML555-G $2200. Xilinx ML555 V5 Dev Kit Notes: Cost...s/ GEORGE RAMSEYER EDWARD J. JONES, Deputy Chief Work Unit Manager Advanced Computing ...uniquely positioned to meet the goals of the Software Systems Stockroom (S3) since in some sense component-based systems are computer -science’s

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

NASA Technical Reports Server (NTRS)

Berg, Melanie; Label, Kenneth; Campola, Michael; Pellish, Jonathan

2017-01-01

This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

NASA Astrophysics Data System (ADS)

Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-03-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

Data Acquisition System for Silicon Ultra Fast Cameras for Electron and Gamma Sources in Medical Applications (sucima Imager)

NASA Astrophysics Data System (ADS)

Czermak, A.; Zalewska, A.; Dulny, B.; Sowicki, B.; Jastrząb, M.; Nowak, L.

2004-07-01

The needs for real time monitoring of the hadrontherapy beam intensity and profile as well as requirements for the fast dosimetry using Monolithic Active Pixel Sensors (MAPS) forced the SUCIMA collaboration to the design of the unique Data Acquisition System (DAQ SUCIMA Imager). The DAQ system has been developed on one of the most advanced XILINX Field Programmable Gate Array chip - VERTEX II. The dedicated multifunctional electronic board for the detector's analogue signals capture, their parallel digital processing and final data compression as well as transmission through the high speed USB 2.0 port has been prototyped and tested.

Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform.

PubMed

Minho Won; Albalawi, Hassan; Xin Li; Thomas, Donald E

2014-01-01

This paper describes a low-power hardware implementation for movement decoding of brain computer interface. Our proposed hardware design is facilitated by two novel ideas: (i) an efficient feature extraction method based on reduced-resolution discrete cosine transform (DCT), and (ii) a new hardware architecture of dual look-up table to perform discrete cosine transform without explicit multiplication. The proposed hardware implementation has been validated for movement decoding of electrocorticography (ECoG) signal by using a Xilinx FPGA Zynq-7000 board. It achieves more than 56× energy reduction over a reference design using band-pass filters for feature extraction.

UW VLSI chip tester

NASA Astrophysics Data System (ADS)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

Generation of Custom DSP Transform IP Cores: Case Study Walsh-Hadamard Transform

DTIC Science & Technology

2002-09-01

mathematics and hardware design What I know: Finite state machine Pipelining Systolic array … What I know: Linear algebra Digital signal processing...state machine Pipelining Systolic array … What I know: Linear algebra Digital signal processing Adaptive filter theory … A math guy A hardware engineer...Synthesis Technology Libary Bit-width (8) HF factor (1,2,3,6) VF factor (1,2,4, ... 32) Xilinx FPGA Place&Route Xilinx FPGA Place&Route Performance

In-situ FPGA debug driven by on-board microcontroller

DOE Office of Scientific and Technical Information (OSTI.GOV)

Baker, Zachary Kent

2009-01-01

Often we are faced with the situation that the behavior of a circuit changes in an unpredictable way when chassis cover is attached or the system is not easily accessible. For instance, in a deployed environment, such as space, hardware can malfunction in unpredictable ways. What can a designer do to ascertain the cause of the problem? Register interrogations only go so far, and sometimes the problem being debugged is register transactions themselves, or the problem lies in FPGA programming. This work provides a solution to this; namely, the ability to drive a JTAG chain via an on-board microcontroller andmore » use a simple clone of the Xilinx Chipscope core without a Xilinx JTAG cable or any external interfaces required. We have demonstrated the functionality of the prototype system using a Xilinx Spartan 3E FPGA and a Microchip PIC18j2550 microcontroller. This paper will discuss the implementation details as well as present case studies describing how the tools have aided satellite hardware development.« less

Evaluation of the FIR Example using Xilinx Vivado High-Level Synthesis Compiler

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Zheming; Finkel, Hal; Yoshii, Kazutomo

Compared to central processing units (CPUs) and graphics processing units (GPUs), field programmable gate arrays (FPGAs) have major advantages in reconfigurability and performance achieved per watt. This development flow has been augmented with high-level synthesis (HLS) flow that can convert programs written in a high-level programming language to Hardware Description Language (HDL). Using high-level programming languages such as C, C++, and OpenCL for FPGA-based development could allow software developers, who have little FPGA knowledge, to take advantage of the FPGA-based application acceleration. This improves developer productivity and makes the FPGA-based acceleration accessible to hardware and software developers. Xilinx Vivado HLSmore » compiler is a high-level synthesis tool that enables C, C++ and System C specification to be directly targeted into Xilinx FPGAs without the need to create RTL manually. The white paper [1] published recently by Xilinx uses a finite impulse response (FIR) example to demonstrate the variable-precision features in the Vivado HLS compiler and the resource and power benefits of converting floating point to fixed point for a design. To get a better understanding of variable-precision features in terms of resource usage and performance, this report presents the experimental results of evaluating the FIR example using Vivado HLS 2017.1 and a Kintex Ultrascale FPGA. In addition, we evaluated the half-precision floating-point data type against the double-precision and single-precision data type and present the detailed results.« less

Design and implementation of projects with Xilinx Zynq FPGA: a practical case

NASA Astrophysics Data System (ADS)

Travaglini, R.; D'Antone, I.; Meneghini, S.; Rignanese, L.; Zuffa, M.

The main advantage when using FPGAs with embedded processors is the availability of additional several high-performance resources in the same physical device. Moreover, the FPGA programmability allows for connect custom peripherals. Xilinx have designed a programmable device named Zynq-7000 (simply called Zynq in the following), which integrates programmable logic (identical to the other Xilinx "serie 7" devices) with a System on Chip (SOC) based on two embedded ARM processors. Since both parts are deeply connected, the designers benefit from performance of hardware SOC and flexibility of programmability as well. In this paper a design developed by the Electronic Design Department at the Bologna Division of INFN will be presented as a practical case of project based on Zynq device. It is developed by using a commercial board called ZedBoard hosting a FMC mezzanine with a 12-bit 500 MS/s ADC. The Zynq FPGA on the ZedBoard receives digital outputs from the ADC and send them to the acquisition PC, after proper formatting, through a Gigabit Ethernet link. The major focus of the paper will be about the methodology to develop a Zynq-based design with the Xilinx Vivado software, enlightening how to configure the SOC and connect it with the programmable logic. Firmware design techniques will be presented: in particular both VHDL and IP core based strategies will be discussed. Further, the procedure to develop software for the embedded processor will be presented. Finally, some debugging tools, like the embedded Logic Analyzer, will be shown. Advantages and disadvantages with respect to adopting FPGA without embedded processors will be discussed.

Fast semivariogram computation using FPGA architectures

NASA Astrophysics Data System (ADS)

Lagadapati, Yamuna; Shirvaikar, Mukul; Dong, Xuanliang

2015-02-01

The semivariogram is a statistical measure of the spatial distribution of data and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. The semivariogram is a plot of semivariances for different lag distances between pixels. A semi-variance, γ(h), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h. Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O(n2). Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz, but they can perform tens of thousands of calculations per clock cycle while operating in the low range of power. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. The design consists of several modules dedicated to the constituent computational tasks. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current implementation is focused on isotropic semivariogram computations only. Anisotropic semivariogram implementation is anticipated to be an extension of the current architecture, ostensibly based on refinements to the current modules. The algorithm is benchmarked using VHDL on a Xilinx XUPV5-LX110T development Kit, which utilizes the Virtex5 FPGA. Medical image data from MRI scans are utilized for the experiments. Computational speedup is measured with respect to Matlab implementation on a personal computer with an Intel i7 multi-core processor. Preliminary simulation results indicate that a significant advantage in speed can be attained by the architectures, making the algorithm viable for implementation in medical devices

FPGA implementation of adaptive beamforming in hearing aids.

PubMed

Samtani, Kartik; Thomas, Jobin; Varma, G Abhinav; Sumam, David S; Deepu, S P

2017-07-01

Beamforming is a spatial filtering technique used in hearing aids to improve target sound reception by reducing interference from other directions. In this paper we propose improvements in an existing architecture present for two omnidirectional microphone array based adaptive beamforming for hearing aid applications and implement the same on Xilinx Artix 7 FPGA using VHDL coding and Xilinx Vivado ® 2015.2. The nulls are introduced in particular directions by combination of two fixed polar patterns. This combination can be adaptively controlled to steer the null in the direction of noise. The beamform patterns and improvements in SNR values obtained from experiments in a conference room environment are analyzed.

Risk Reduction for Use of Complex Devices in Space Projects

NASA Technical Reports Server (NTRS)

Berg, Melanie; Poivey, Christian; Friendlich, Mark; Petrick, Dave; LaBel, Kenneth; Stansberry, Scott

2007-01-01

We present guidel!nes to reduce risk to an acceptable level when using complex devices in space applications. Application to Virtex 4 Field Programmable Gate Array (FPGA) on Express Logistic Carrier (ELC) project is presented.

Application of Reconfigurable Computing Technology to Multi-KiloHertz Micro-Laser Altimeter (MMLA) Data Processing

NASA Technical Reports Server (NTRS)

Powell, Wesley; Dabney, Philip; Hicks, Edward; Pinchinat, Maxime; Day, John H. (Technical Monitor)

2002-01-01

The Multi-KiloHertz Micro-Laser Altimeter (MMLA) is an aircraft based instrument developed by NASA Goddard Space Flight Center with several potential spaceflight applications. This presentation describes how reconfigurable computing technology was employed to perform MMLA signal extraction in real-time under realistic operating constraints. The MMLA is a "single-photon-counting" airborne laser altimeter that is used to measure land surface features such as topography and vegetation canopy height. This instrument has to date flown a number of times aboard the NASA P3 aircraft acquiring data at a number of sites in the Mid-Atlantic region. This instrument pulses a relatively low-powered laser at a very high rate (10 kHz) and then measures the time-of-flight of discrete returns from the target surface. The instrument then bins these measurements into a two-dimensional array (vertical height vs. horizontal ground track) and selects the most likely signal path through the array. Return data that does not correspond to the selected signal path are classified as noise returns and are then discarded. The MMLA signal extraction algorithm is very compute intensive in that a score must be computed for every possible path through the two dimensional array in order to select the most likely signal path. Given a typical array size with 50 x 6, up to 33 arrays must be processed per second. And for each of these arrays, roughly 12,000 individual paths must be scored. Furthermore, the number of paths increases exponentially with the horizontal size of the array, and linearly with the vertical size. Yet, increasing the horizontal and vertical sizes of the array offer science advantages such as improved range, resolution, and noise rejection. Due to the volume of return data and the compute intensive signal extraction algorithm, the existing PC-based MMLA data system has been unable to perform signal extraction in real-time unless the array is limited in size to one column, This limits the ability of the MMLA to operate in environments with sparse signal returns and a high number of noise return. However, under an IR&D project, an FPGA-based, reconfigurable computing data system has been developed that has been demonstrated to perform real-time signal extraction under realistic operating constraints. This reconfigurable data system is based on the commercially available Firebird Board from Annapolis Microsystems. This PCI board consists of a Xilinx Virtex 2000E FPGA along with 36 MB of SRAM arranged in five separately addressable banks. This board is housed in a rackmount PC with dual 850MHz Pentium processors running the Windows 2000 operating system. This data system performs all signal extraction in hardware on the Firebird, but also runs the existing "software based" signal extraction in tandem for comparison purposes. Using a relatively small amount of the Virtex XCV2000E resources, the reconfigurable data system has demonstrated to improve performance improvement over the existing software based data system by an order of magnitude. Performance could be further improved by employing parallelism. Ground testing and a preliminary engineering test flight aboard the NASA P3 has been performed, during which the reconfigurable data system has been demonstrated to match the results of the existing data system.

Digital Interface Board to Control Phase and Amplitude of Four Channels

NASA Technical Reports Server (NTRS)

Smith, Amy E.; Cook, Brian M.; Khan, Abdur R.; Lux, James P.

2011-01-01

An increasing number of parts are designed with digital control interfaces, including phase shifters and variable attenuators. When designing an antenna array in which each antenna has independent amplitude and phase control, the number of digital control lines that must be set simultaneously can grow very large. Use of a parallel interface would require separate line drivers, more parts, and thus additional failure points. A convenient form of control where single-phase shifters or attenuators could be set or the whole set could be programmed with an update rate of 100 Hz is needed to solve this problem. A digital interface board with a field-programmable gate array (FPGA) can simultaneously control an essentially arbitrary number of digital control lines with a serial command interface requiring only three wires. A small set of short, high-level commands provides a simple programming interface for an external controller. Parity bits are used to validate the control commands. Output timing is controlled within the FPGA to allow for rapid update rates of the phase shifters and attenuators. This technology has been used to set and monitor eight 5-bit control signals via a serial UART (universal asynchronous receiver/transmitter) interface. The digital interface board controls the phase and amplitude of the signals for each element in the array. A host computer running Agilent VEE sends commands via serial UART connection to a Xilinx VirtexII FPGA. The commands are decoded, and either outputs are set or telemetry data is sent back to the host computer describing the status and the current phase and amplitude settings. This technology is an integral part of a closed-loop system in which the angle of arrival of an X-band uplink signal is detected and the appropriate phase shifts are applied to the Ka-band downlink signal to electronically steer the array back in the direction of the uplink signal. It will also be used in the non-beam-steering case to compensate for phase shift variations through power amplifiers. The digital interface board can be used to set four 5-bit phase shifters and four 5-bit attenuators and monitor their current settings. Additionally, it is useful outside of the closed-loop system for beamsteering alone. When the VEE program is started, it prompts the user to initialize variables (to zero) or skip initialization. After that, the program enters into a continuous loop waiting for the telemetry period to elapse or a button to be pushed. A telemetry request is sent when the telemetry period is elapsed (every five seconds). Pushing one of the set or reset buttons will send the appropriate command. When a command is sent, the interface status is returned, and the user will be notified by a pop-up window if any error has occurred. The program runs until the End Program button is depressed.

Splash 2

NASA Technical Reports Server (NTRS)

Arnold, Jeffrey M.; Buell, Duncan A.; Kleinfelder, Walter J.

1993-01-01

Splash 2 is an attached processor system for Sun SPARC 2 workstations that uses Xilinx 4010 Field Programmable Gate Arrays (FPGA's) as its processing elements. The purpose of this paper is to describe Splash 2. The predecessor system, Splash 1, was designed to be used as a systolic processing system. Although it was very successful in that mode, there were many other applications that were not systolic, but which were successful, nonetheless, on Splash 1, or that were not implemented successfully due to one or more architectural limitations, most notably I/O bandwidth and interprocessor communication. Although other uses to increase computational performance have been found for the Xilinx FPGA's that are Splash's processing elements. Splash is unique in its goal to be programmable in a general sense.

Soft error evaluation and vulnerability analysis in Xilinx Zynq-7010 system-on chip

NASA Astrophysics Data System (ADS)

Du, Xuecheng; He, Chaohui; Liu, Shuhuan; Zhang, Yao; Li, Yonghong; Xiong, Ceng; Tan, Pengkang

2016-09-01

Radiation-induced soft errors are an increasingly important threat to the reliability of modern electronic systems. In order to evaluate system-on chip's reliability and soft error, the fault tree analysis method was used in this work. The system fault tree was constructed based on Xilinx Zynq-7010 All Programmable SoC. Moreover, the soft error rates of different components in Zynq-7010 SoC were tested by americium-241 alpha radiation source. Furthermore, some parameters that used to evaluate the system's reliability and safety were calculated using Isograph Reliability Workbench 11.0, such as failure rate, unavailability and mean time to failure (MTTF). According to fault tree analysis for system-on chip, the critical blocks and system reliability were evaluated through the qualitative and quantitative analysis.

Semivariogram Analysis of Bone Images Implemented on FPGA Architectures.

PubMed

Shirvaikar, Mukul; Lagadapati, Yamuna; Dong, Xuanliang

2017-03-01

Osteoporotic fractures are a major concern for the healthcare of elderly and female populations. Early diagnosis of patients with a high risk of osteoporotic fractures can be enhanced by introducing second-order statistical analysis of bone image data using techniques such as variogram analysis. Such analysis is computationally intensive thereby creating an impediment for introduction into imaging machines found in common clinical settings. This paper investigates the fast implementation of the semivariogram algorithm, which has been proven to be effective in modeling bone strength, and should be of interest to readers in the areas of computer-aided diagnosis and quantitative image analysis. The semivariogram is a statistical measure of the spatial distribution of data, and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. A semi-variance, γ ( h ), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h . Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O ( n 2 ) Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current implementation is focused on isotropic semivariogram computations only. The algorithm is benchmarked using VHDL on a Xilinx XUPV5-LX110T development Kit, which utilizes the Virtex5 FPGA. Medical image data from DXA scans are utilized for the experiments. Implementation results show that a significant advantage in computational speed is attained by the architectures with respect to implementation on a personal computer with an Intel i7 multi-core processor.

Semivariogram Analysis of Bone Images Implemented on FPGA Architectures

PubMed Central

Shirvaikar, Mukul; Lagadapati, Yamuna; Dong, Xuanliang

2016-01-01

Osteoporotic fractures are a major concern for the healthcare of elderly and female populations. Early diagnosis of patients with a high risk of osteoporotic fractures can be enhanced by introducing second-order statistical analysis of bone image data using techniques such as variogram analysis. Such analysis is computationally intensive thereby creating an impediment for introduction into imaging machines found in common clinical settings. This paper investigates the fast implementation of the semivariogram algorithm, which has been proven to be effective in modeling bone strength, and should be of interest to readers in the areas of computer-aided diagnosis and quantitative image analysis. The semivariogram is a statistical measure of the spatial distribution of data, and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. A semi-variance, γ(h), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h. Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O (n2) Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current implementation is focused on isotropic semivariogram computations only. The algorithm is benchmarked using VHDL on a Xilinx XUPV5-LX110T development Kit, which utilizes the Virtex5 FPGA. Medical image data from DXA scans are utilized for the experiments. Implementation results show that a significant advantage in computational speed is attained by the architectures with respect to implementation on a personal computer with an Intel i7 multi-core processor. PMID:28428829

A Frequency Agile, Self-Adaptive Serial Link on Xilinx FPGAs

NASA Astrophysics Data System (ADS)

Aloisio, A.; Giordano, R.; Izzo, V.; Perrella, S.

2015-06-01

In this paper, we focused on the GTX transceiver modules of Xilinx Kintex 7 field-programmable gate arrays (FPGAs), which provide high bandwidth, low jitter on the recovered clock, and an equalization system on the transmitter and the receiver. We present a frequency agile, auto-adaptive serial link. The link is able to take care of the reconfiguration of the GTX parameters in order to fully benefit from the available link bandwidth, by setting the highest line rate. It is designed around an FPGA-embedded microprocessor, which drives the programmable ports of the GTX in order to control the quality of the received data and to easily calculate the bit-error rate in each sampling point of the eye diagram. We present the self-adaptive link project, the description of the test system, and the main results.

CoNNeCT Baseband Processor Module Boot Code SoftWare (BCSW)

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K.; Orozco, David S.; Byrne, D. J.; Allen, Steven J.; Sahasrabudhe, Adit; Lang, Minh

2012-01-01

This software provides essential startup and initialization routines for the CoNNeCT baseband processor module (BPM) hardware upon power-up. A command and data handling (C&DH) interface is provided via 1553 and diagnostic serial interfaces to invoke operational, reconfiguration, and test commands within the code. The BCSW has features unique to the hardware it is responsible for managing. In this case, the CoNNeCT BPM is configured with an updated CPU (Atmel AT697 SPARC processor) and a unique set of memory and I/O peripherals that require customized software to operate. These features include configuration of new AT697 registers, interfacing to a new HouseKeeper with a flash controller interface, a new dual Xilinx configuration/scrub interface, and an updated 1553 remote terminal (RT) core. The BCSW is intended to provide a "safe" mode for the BPM when initially powered on or when an unexpected trap occurs, causing the processor to reset. The BCSW allows the 1553 bus controller in the spacecraft or payload controller to operate the BPM over 1553 to upload code; upload Xilinx bit files; perform rudimentary tests; read, write, and copy the non-volatile flash memory; and configure the Xilinx interface. Commands also exist over 1553 to cause the CPU to jump or call a specified address to begin execution of user-supplied code. This may be in the form of a real-time operating system, test routine, or specific application code to run on the BPM.

Implementation of a Multichannel Serial Data Streaming Algorithm using the Xilinx Serial RapidIO Solution

NASA Technical Reports Server (NTRS)

Doxley, Charles A.

2016-01-01

In the current world of applications that use reconfigurable technology implemented on field programmable gate arrays (FPGAs), there is a need for flexible architectures that can grow as the systems evolve. A project has limited resources and a fixed set of requirements that development efforts are tasked to meet. Designers must develop robust solutions that practically meet the current customer demands and also have the ability to grow for future performance. This paper describes the development of a high speed serial data streaming algorithm that allows for transmission of multiple data channels over a single serial link. The technique has the ability to change to meet new applications developed for future design considerations. This approach uses the Xilinx Serial RapidIO LOGICORE Solution to implement a flexible infrastructure to meet the current project requirements with the ability to adapt future system designs.

An FPGA-Based People Detection System

NASA Astrophysics Data System (ADS)

Nair, Vinod; Laprise, Pierre-Olivier; Clark, James J.

2005-12-01

This paper presents an FPGA-based system for detecting people from video. The system is designed to use JPEG-compressed frames from a network camera. Unlike previous approaches that use techniques such as background subtraction and motion detection, we use a machine-learning-based approach to train an accurate detector. We address the hardware design challenges involved in implementing such a detector, along with JPEG decompression, on an FPGA. We also present an algorithm that efficiently combines JPEG decompression with the detection process. This algorithm carries out the inverse DCT step of JPEG decompression only partially. Therefore, it is computationally more efficient and simpler to implement, and it takes up less space on the chip than the full inverse DCT algorithm. The system is demonstrated on an automated video surveillance application and the performance of both hardware and software implementations is analyzed. The results show that the system can detect people accurately at a rate of about[InlineEquation not available: see fulltext.] frames per second on a Virtex-II 2V1000 using a MicroBlaze processor running at[InlineEquation not available: see fulltext.], communicating with dedicated hardware over FSL links.

Fabless company mask technology approach: fabless but not fab-careless

NASA Astrophysics Data System (ADS)

Hisamura, Toshiyuki; Wu, Xin

2009-10-01

There are two different foundry-fabless working models in the aspect of mask. Some foundries have in-house mask facility while others contract with merchant mask vendors. Significant progress has been made in both kinds of situations. Xilinx as one of the pioneers of fabless semiconductor companies has been continually working very closely with both merchant mask vendors and mask facilities of foundries in past many years, contributed well in both technology development and benefited from corporations. Our involvement in manufacturing is driven by the following three elements: The first element is to understand the new fabrication and mask technologies and then find a suitable design / layout style to better utilize these new technologies and avoid potential risks. Because Xilinx has always been involved in early stage of advanced technology nodes, this early understanding and adoption is especially important. The second element is time to market. Reduction in mask and wafer manufacturing cycle-time can ensure faster time to market. The third element is quality. Commitment to quality is our highest priority for our customers. We have enough visibility on any manufacturing issues affecting the device functionality. Good correlation has consistently been observed between FPGA speed uniformity and the poly mask Critical Dimension (CD) uniformity performance. To achieve FPGA speed uniformity requirement, the manufacturing process as well as the mask and wafer CD uniformity has to be monitored. Xilinx works closely with the wafer foundries and mask suppliers to improve productivity and the yield from initial development stage of mask making operations. As an example, defect density reduction is one of the biggest challenges for mask supplier in development stage to meet the yield target satisfying the mask cost and mask turn-around-time (TAT) requirement. Historically, masks were considered to be defect free but at these advanced process nodes, that assumption no longer holds true. There is a need to be flexible enough on unrepairable defect at early stage but also a need for efficient risk management system on mask defect waivers. Mask defects are often waived in low design criticality area in favor of scrapping the mask and delaying the mask and wafer schedule. Xilinx's involvement in mask manufacturing has contributed significantly to our success in past many nodes and will continue.

The prototype cameras for trans-Neptunian automatic occultation survey

NASA Astrophysics Data System (ADS)

Wang, Shiang-Yu; Ling, Hung-Hsu; Hu, Yen-Sang; Geary, John C.; Chang, Yin-Chang; Chen, Hsin-Yo; Amato, Stephen M.; Huang, Pin-Jie; Pratlong, Jerome; Szentgyorgyi, Andrew; Lehner, Matthew; Norton, Timothy; Jorden, Paul

2016-08-01

The Transneptunian Automated Occultation Survey (TAOS II) is a three robotic telescope project to detect the stellar occultation events generated by TransNeptunian Objects (TNOs). TAOS II project aims to monitor about 10000 stars simultaneously at 20Hz to enable statistically significant event rate. The TAOS II camera is designed to cover the 1.7 degrees diameter field of view of the 1.3m telescope with 10 mosaic 4.5k×2k CMOS sensors. The new CMOS sensor (CIS 113) has a back illumination thinned structure and high sensitivity to provide similar performance to that of the back-illumination thinned CCDs. Due to the requirements of high performance and high speed, the development of the new CMOS sensor is still in progress. Before the science arrays are delivered, a prototype camera is developed to help on the commissioning of the robotic telescope system. The prototype camera uses the small format e2v CIS 107 device but with the same dewar and also the similar control electronics as the TAOS II science camera. The sensors, mounted on a single Invar plate, are cooled to the operation temperature of about 200K as the science array by a cryogenic cooler. The Invar plate is connected to the dewar body through a supporting ring with three G10 bipods. The control electronics consists of analog part and a Xilinx FPGA based digital circuit. One FPGA is needed to control and process the signal from a CMOS sensor for 20Hz region of interests (ROI) readout.

Modeling and Analysis of a Constant Power Series-Loaded Resonant Converter

DTIC Science & Technology

2011-06-01

Paperwork Reduction Project (0704-0188) Washington DC 20503. 1 . AGENCY USE ONLY (Leave blank) 2 . REPORT DATE June 2011 3. REPORT TYPE AND DATES...CONVERTER THEORY .......................8 1 . Converter Topology .............................................................................8 2 . Modes of...25 1 . Fixed-Point Numbers. ........................................................................25 2 . Xilinx

Design and implementation of power efficient 10-bit dual port SRAM on 28 nm technology

NASA Astrophysics Data System (ADS)

Gulati, Anmol; Gupta, Ashutosh; Murgai, Shruti; Bhaskar, Lala

2016-03-01

In this paper, 10 bit synchronous clock gated Dual port RAM has been designed. The negative latch based clock gating technique has been employed to optimize the power of the design. The design has been implemented on XV7K70T device, -3 speed grade, and kintex 7 FPGA family on Xilinx ISE Design Suite 14.7 using 28 nm technology. The design has been synthesized using Verilog HDL. We have been successful in achieving approximately 55 % reduction in total clock power, 81.55% reduction in BRAM power, 82.65%, 0.07%, 1.04% and 11.31% reduction in static power, 72.32%, 38.60%, 68.74% and 71.97%, reduction in dynamic power and 72.44%, 16.96%, 60.88% and 71.06% reduction in total supply power at 1 THz, 1GHz, 100 GHz and 1000 GHz frequency respectively. The power of the device has been calculated using XPower Analyzer tool of Xilinx ISE Design Suite 14.7.

Power efficient, clock gated multiplexer based full adder cell using 28 nm technology

NASA Astrophysics Data System (ADS)

Gupta, Ashutosh; Murgai, Shruti; Gulati, Anmol; Kumar, Pradeep

2016-03-01

Clock gating is a leading technique used for power saving. Full adders is one of the basic circuit that can be found in maximum VLSI circuits. In this paper clock gated multiplexer based full adder cell is implemented on 28 nm technology. We have designed a full adder cell using a multiplexer with a gated clock without degrading its performance of the cell. We have negative latch circuit for generating gated clock. This gated clock is used to control the multiplexer based full adder cell. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. The circuit has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment. The total power of the circuit has been reduced by 7.41% without degrading the performance of original circuit. The power has been calculated using XPower Analyzer tool of XILINX ISE DESIGN SUITE 14.3.

A z-Vertex Trigger for Belle II

NASA Astrophysics Data System (ADS)

Skambraks, S.; Abudinén, F.; Chen, Y.; Feindt, M.; Frühwirth, R.; Heck, M.; Kiesling, C.; Knoll, A.; Neuhaus, S.; Paul, S.; Schieck, J.

2015-08-01

The Belle II experiment will go into operation at the upgraded SuperKEKB collider in 2016. SuperKEKB is designed to deliver an instantaneous luminosity L = 8 ×1035 cm - 2 s - 1. The experiment will therefore have to cope with a much larger machine background than its predecessor Belle, in particular from events outside of the interaction region. We present the concept of a track trigger, based on a neural network approach, that is able to suppress a large fraction of this background by reconstructing the z (longitudinal) position of the event vertex within the latency of the first level trigger. The trigger uses the hit information from the Central Drift Chamber (CDC) of Belle II within narrow cones in polar and azimuthal angle as well as in transverse momentum (“sectors”), and estimates the z-vertex without explicit track reconstruction. The preprocessing for the track trigger is based on the track information provided by the standard CDC trigger. It takes input from the 2D track finder, adds information from the stereo wires of the CDC, and finds the appropriate sectors in the CDC for each track. Within the sector, the z-vertex is estimated by a specialized neural network, with the drift times from the CDC as input and a continuous output corresponding to the scaled z-vertex. The neural algorithm will be implemented in programmable hardware. To this end a Virtex 7 FPGA board will be used, which provides at present the most promising solution for a fully parallelized implementation of neural networks or alternative multivariate methods. A high speed interface for external memory will be integrated into the platform, to be able to store the O(109) parameters required. The contribution presents the results of our feasibility studies and discusses the details of the envisaged hardware solution.

Measuring Input Thresholds on an Existing Board

NASA Technical Reports Server (NTRS)

Kuperman, Igor; Gutrich, Daniel G.; Berkun, Andrew C.

2011-01-01

A critical PECL (positive emitter-coupled logic) interface to Xilinx interface needed to be changed on an existing flight board. The new Xilinx input interface used a CMOS (complementary metal-oxide semiconductor) type of input, and the driver could meet its thresholds typically, but not in worst-case, according to the data sheet. The previous interface had been based on comparison with an external reference, but the CMOS input is based on comparison with an internal divider from the power supply. A way to measure what the exact input threshold was for this device for 64 inputs on a flight board was needed. The measurement technique allowed an accurate measurement of the voltage required to switch a Xilinx input from high to low for each of the 64 lines, while only probing two of them. Directly driving an external voltage was considered too risky, and tests done on any other unit could not be used to qualify the flight board. The two lines directly probed gave an absolute voltage threshold calibration, while data collected on the remaining 62 lines without probing gave relative measurements that could be used to identify any outliers. The PECL interface was forced to a long-period square wave by driving a saturated square wave into the ADC (analog to digital converter). The active pull-down circuit was turned off, causing each line to rise rapidly and fall slowly according to the input s weak pull-down circuitry. The fall time shows up as a change in the pulse width of the signal ready by the Xilinx. This change in pulse width is a function of capacitance, pulldown current, and input threshold. Capacitance was known from the different trace lengths, plus a gate input capacitance, which is the same for all inputs. The pull-down current is the same for all inputs including the two that are probed directly. The data was combined, and the Excel solver tool was used to find input thresholds for the 62 lines. This was repeated over different supply voltages and temperatures to show that the interface had voltage margin under all worst case conditions. Gate input thresholds are normally measured at the manufacturer when the device is on a chip tester. A key function of this machine was duplicated on an existing flight board with no modifications to the nets to be tested, with the exception of changes in the FPGA program.

Multicasting mesh AER: a scalable assembly approach for reconfigurable neuromorphic structured AER systems. Application to ConvNets.

PubMed

Zamarreno-Ramos, C; Linares-Barranco, A; Serrano-Gotarredona, T; Linares-Barranco, B

2013-02-01

This paper presents a modular, scalable approach to assembling hierarchically structured neuromorphic Address Event Representation (AER) systems. The method consists of arranging modules in a 2D mesh, each communicating bidirectionally with all four neighbors. Address events include a module label. Each module includes an AER router which decides how to route address events. Two routing approaches have been proposed, analyzed and tested, using either destination or source module labels. Our analyses reveal that depending on traffic conditions and network topologies either one or the other approach may result in better performance. Experimental results are given after testing the approach using high-end Virtex-6 FPGAs. The approach is proposed for both single and multiple FPGAs, in which case a special bidirectional parallel-serial AER link with flow control is exploited, using the FPGA Rocket-I/O interfaces. Extensive test results are provided exploiting convolution modules of 64 × 64 pixels with kernels with sizes up to 11 × 11, which process real sensory data from a Dynamic Vision Sensor (DVS) retina. One single Virtex-6 FPGA can hold up to 64 of these convolution modules, which is equivalent to a neural network with 262 × 10(3) neurons and almost 32 million synapses.

The DCU: the detector control unit for SPICA-SAFARI

NASA Astrophysics Data System (ADS)

Clénet, Antoine; Ravera, Laurent; Bertrand, Bernard; den Hartog, Roland H.; Jackson, Brian D.; van Leeuven, Bert-Joost; van Loon, Dennis; Parot, Yann; Pointecouteau, Etienne; Sournac, Anthony

2014-08-01

IRAP is developing the warm electronic, so called Detector Control Unit" (DCU), in charge of the readout of the SPICA-SAFARI's TES type detectors. The architecture of the electronics used to readout the 3 500 sensors of the 3 focal plane arrays is based on the frequency domain multiplexing technique (FDM). In each of the 24 detection channels the data of up to 160 pixels are multiplexed in frequency domain between 1 and 3:3 MHz. The DCU provides the AC signals to voltage-bias the detectors; it demodulates the detectors data which are readout in the cold by a SQUID; and it computes a feedback signal for the SQUID to linearize the detection chain in order to optimize its dynamic range. The feedback is computed with a specific technique, so called baseband feedback (BBFB) which ensures that the loop is stable even with long propagation and processing delays (i.e. several µs) and with fast signals (i.e. frequency carriers at 3:3 MHz). This digital signal processing is complex and has to be done at the same time for the 3 500 pixels. It thus requires an optimisation of the power consumption. We took the advantage of the relatively reduced science signal bandwidth (i.e. 20 - 40 Hz) to decouple the signal sampling frequency (10 MHz) and the data processing rate. Thanks to this method we managed to reduce the total number of operations per second and thus the power consumption of the digital processing circuit by a factor of 10. Moreover we used time multiplexing techniques to share the resources of the circuit (e.g. a single BBFB module processes 32 pixels). The current version of the firmware is under validation in a Xilinx Virtex 5 FPGA, the final version will be developed in a space qualified digital ASIC. Beyond the firmware architecture the optimization of the instrument concerns the characterization routines and the definition of the optimal parameters. Indeed the operation of the detection and readout chains requires to properly define more than 17 500 parameters (about 5 parameters per pixel). Thus it is mandatory to work out an automatic procedure to set up these optimal values. We defined a fast algorithm which characterizes the phase correction to be applied by the BBFB firmware and the pixel resonance frequencies. We also defined a technique to define the AC-carrier initial phases in such a way that the amplitude of their sum is minimized (for a better use of the DAC dynamic range).

77 FR 26045 - Notice Pursuant to the National Cooperative Research and Production Act of 1993-Accellera Systems...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-02

..., IRELAND; Freescale Semiconductor, Austin, TX; IBM, Hopewell Junction, NY; Jasper Design Automation..., San Jose, CA; Vayavya Labs, Belguam, INDIA; Verilab, Austin, TX; and Xilinx, Inc., San Jose, CA, have... DEPARTMENT OF JUSTICE Antitrust Division Notice Pursuant to the National Cooperative Research and...

Implementation of a Parameterized Interacting Multiple Model Filter on an FPGA for Satellite Communications

NASA Technical Reports Server (NTRS)

Hackett, Timothy M.; Bilen, Sven G.; Ferreira, Paulo Victor R.; Wyglinski, Alexander M.; Reinhart, Richard C.

2016-01-01

In a communications channel, the space environment between a spacecraft and an Earth ground station can potentially cause the loss of a data link or at least degrade its performance due to atmospheric effects, shadowing, multipath, or other impairments. In adaptive and coded modulation, the signal power level at the receiver can be used in order to choose a modulation-coding technique that maximizes throughput while meeting bit error rate (BER) and other performance requirements. It is the goal of this research to implement a generalized interacting multiple model (IMM) filter based on Kalman filters for improved received power estimation on software-dened radio (SDR) technology for satellite communications applications. The IMM filter has been implemented in Verilog consisting of a customizable bank of Kalman filters for choosing between performance and resource utilization. Each Kalman filter can be implemented using either solely a Schur complement module (for high area efficiency) or with Schur complement, matrix multiplication, and matrix addition modules (for high performance). These modules were simulated and synthesized for the Virtex II platform on the JPL Radio Experimenter Development System (EDS) at NASA Glenn Research Center. The results for simulation, synthesis, and hardware testing are presented.

76 FR 2148 - Xilinx, Inc. Including On-Site Leased Workers of TEKsystems, Albuquerque, NM; Notice of Revised...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-01-12

..., for integrated circuit test engineers and test equipment engineers for a Product and Test Engineering... engineering services. In the request for reconsideration, workers alleged that the subject firm has shifted abroad the supply of services like and directly competitive with the internal-use engineering services...

75 FR 65526 - Xilinx, Inc., Including On-Site Leased Workers of TEKsystems, Albuquerque, NM; Notice of Revised...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-10-25

..., for integrated circuit test engineers and test equipment engineers for a Product and Test Engineering... engineering services. In the request for reconsideration, workers alleged that the subject firm has shifted abroad the supply of services like and directly competitive with the internal-use engineering services...

Efficient FIR Filter Implementations for Multichannel BCIs Using Xilinx System Generator.

PubMed

Ghani, Usman; Wasim, Muhammad; Khan, Umar Shahbaz; Mubasher Saleem, Muhammad; Hassan, Ali; Rashid, Nasir; Islam Tiwana, Mohsin; Hamza, Amir; Kashif, Amir

2018-01-01

Background . Brain computer interface (BCI) is a combination of software and hardware communication protocols that allow brain to control external devices. Main purpose of BCI controlled external devices is to provide communication medium for disabled persons. Now these devices are considered as a new way to rehabilitate patients with impunities. There are certain potentials present in electroencephalogram (EEG) that correspond to specific event. Main issue is to detect such event related potentials online in such a low signal to noise ratio (SNR). In this paper we propose a method that will facilitate the concept of online processing by providing an efficient filtering implementation in a hardware friendly environment by switching to finite impulse response (FIR). Main focus of this research is to minimize latency and computational delay of preprocessing related to any BCI application. Four different finite impulse response (FIR) implementations along with large Laplacian filter are implemented in Xilinx System Generator. Efficiency of 25% is achieved in terms of reduced number of coefficients and multiplications which in turn reduce computational delays accordingly.

Development of ROACH firmware for microwave multiplexed X-ray TES microcalorimeters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Madden, T. J.; Cecil, T. W.; Gades, L. M.

We are developing room temperature electronics based upon the ROACH platform for reading out microwave multiplexed X-ray TES. ROACH is an open-source hardware and software platform featuring a large Xilinx Field Programmable Gate Array (FPGA), Power PC processor, several 10GB Ethernet SFP+ interfaces, and a collection of daughter boards for analog signal generation and acquisition. The combination of a ROACH board, ADC/DAC conversion daughter boards, and hardware for RF mixing allows for the generation and capture of multiple RF tones for reading out microwave multiplexed x-ray TES microcalorimeters. The FPGA is used to generate multiple tones in base band, frommore » 10MHz to 250MHz, which are subsequently mixed to RF in the multiple GHz range and sent through the microwave multiplexer. The tones are generated in the FPGA by storing a large lookup table in Quad Data Rate (QDR) SRAM modules and playing out the waveform to a DAC board. Once the signal has been modulated to RF, passed through the microwave multiplexer, and has been modulated back to base band, the signal is digitized by an ADC board. The tones are modulated to 0Hz by using a FPGA circuit consisting of a polyphase filter bank, several Xilinx FFT blocks, Xilinx CORDIC blocks (for converting to magnitude and phase), and special phase accumulator circuit for mixing to exactly 0Hz. Upwards of 256 channels can be simultaneously captured and written into a bank of 256 First-In-First-Out (FIFO) memories, with each FIFO corresponding to a channel. Individual channel data can be further processed in the FPGA before being streamed through a 10GB Ethernet fiber-optic interface to a Linux system. The Linux system runs software written in Python and QT C++ for controlling the ROACH system, capturing data, and processing data.« less

Global Educational Ecosystem: Case Study of a Partnership with K-12 Schools, Community Organizations, and Business

ERIC Educational Resources Information Center

Lewis, Donna S.

2010-01-01

The purpose of this study was to describe a collaborative partnership model known as the Global Educational Ecosystem, which involves three K-12 schools in Northern California, community organizations (representing science, technology, health, and arts), and Xilinx, Inc. from the perspectives of the leaders of the involved partner organizations in…

FASEA: A FPGA Acquisition System and Software Event Analysis for liquid scintillation counting

NASA Astrophysics Data System (ADS)

Steele, T.; Mo, L.; Bignell, L.; Smith, M.; Alexiev, D.

2009-10-01

The FASEA (FPGA based Acquisition and Software Event Analysis) system has been developed to replace the MAC3 for coincidence pulse processing. The system uses a National Instruments Virtex 5 FPGA card (PXI-7842R) for data acquisition and a purpose developed data analysis software for data analysis. Initial comparisons to the MAC3 unit are included based on measurements of 89Sr and 3H, confirming that the system is able to accurately emulate the behaviour of the MAC3 unit.

High speed wide field CMOS camera for Transneptunian Automatic Occultation Survey

NASA Astrophysics Data System (ADS)

Wang, Shiang-Yu; Geary, John C.; Amato, Stephen M.; Hu, Yen-Sang; Ling, Hung-Hsu; Huang, Pin-Jie; Furesz, Gabor; Chen, Hsin-Yo; Chang, Yin-Chang; Szentgyorgyi, Andrew; Lehner, Matthew; Norton, Timothy

2014-08-01

The Transneptunian Automated Occultation Survey (TAOS II) is a three robotic telescope project to detect the stellar occultation events generated by Trans Neptunian Objects (TNOs). TAOS II project aims to monitor about 10000 stars simultaneously at 20Hz to enable statistically significant event rate. The TAOS II camera is designed to cover the 1.7 degree diameter field of view (FoV) of the 1.3m telescope with 10 mosaic 4.5kx2k CMOS sensors. The new CMOS sensor has a back illumination thinned structure and high sensitivity to provide similar performance to that of the backillumination thinned CCDs. The sensor provides two parallel and eight serial decoders so the region of interests can be addressed and read out separately through different output channels efficiently. The pixel scale is about 0.6"/pix with the 16μm pixels. The sensors, mounted on a single Invar plate, are cooled to the operation temperature of about 200K by a cryogenic cooler. The Invar plate is connected to the dewar body through a supporting ring with three G10 bipods. The deformation of the cold plate is less than 10μm to ensure the sensor surface is always within ±40μm of focus range. The control electronics consists of analog part and a Xilinx FPGA based digital circuit. For each field star, 8×8 pixels box will be readout. The pixel rate for each channel is about 1Mpix/s and the total pixel rate for each camera is about 80Mpix/s. The FPGA module will calculate the total flux and also the centroid coordinates for every field star in each exposure.

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

PubMed Central

Pérez Suárez, Santiago T.; Travieso González, Carlos M.; Alonso Hernández, Jesús B.

2013-01-01

This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE) and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

Design and implementation of low power clock gated 64-bit ALU on ultra scale FPGA

NASA Astrophysics Data System (ADS)

Gupta, Ashutosh; Murgai, Shruti; Gulati, Anmol; Kumar, Pradeep

2016-03-01

64-bit energy efficient Arithmetic and Logic Unit using negative latch based clock gating technique is designed in this paper. The 64-bit ALU is designed using multiplexer based full adder cell. We have designed a 64-bit ALU with a gated clock. We have used negative latch based circuit for generating gated clock. This gated clock is used to control the multiplexer based 64-bit ALU. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. The circuit has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment. We have achieved 74.07%, 92. 93% and 95.53% reduction in total clock power, 89.73%, 91.35% and 92.85% reduction in I/Os power, 67.14%, 62.84% and 74.34% reduction in dynamic power and 25.47%, 29.05% and 46.13% reduction in total supply power at 20 MHz, 200 MHz and 2 GHz frequency respectively. The power has been calculated using XPower Analyzer tool of Xilinx ISE Design Suite 14.3.

FPGA Boot Loader and Scrubber

NASA Technical Reports Server (NTRS)

Wade, Randall S.; Jones, Bailey

2009-01-01

A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation. The program consists mainly of a set of VHDL files (wherein "VHDL" signifies "VHSIC Hardware Description Language" and "VHSIC" signifies "very-high-speed integrated circuit").

Design and Implementation of Viterbi Decoder Using VHDL

NASA Astrophysics Data System (ADS)

Thakur, Akash; Chattopadhyay, Manju K.

2018-03-01

A digital design conversion of Viterbi decoder for ½ rate convolutional encoder with constraint length k = 3 is presented in this paper. The design is coded with the help of VHDL, simulated and synthesized using XILINX ISE 14.7. Synthesis results show a maximum frequency of operation for the design is 100.725 MHz. The requirement of memory is less as compared to conventional method.

MicroShell Minimalist Shell for Xilinx Microprocessors

NASA Technical Reports Server (NTRS)

Werne, Thomas A.

2011-01-01

MicroShell is a lightweight shell environment for engineers and software developers working with embedded microprocessors in Xilinx FPGAs. (MicroShell has also been successfully ported to run on ARM Cortex-M1 microprocessors in Actel ProASIC3 FPGAs, but without project-integration support.) Micro Shell decreases the time spent performing initial tests of field-programmable gate array (FPGA) designs, simplifies running customizable one-time-only experiments, and provides a familiar-feeling command-line interface. The program comes with a collection of useful functions and enables the designer to add an unlimited number of custom commands, which are callable from the command-line. The commands are parameterizable (using the C-based command-line parameter idiom), so the designer can use one function to exercise hardware with different values. Also, since many hardware peripherals instantiated in FPGAs have reasonably simple register-mapped I/O interfaces, the engineer can edit and view hardware parameter settings at any time without stopping the processor. MicroShell comes with a set of support scripts that interface seamlessly with Xilinx's EDK tool. Adding an instance of MicroShell to a project is as simple as marking a check box in a library configuration dialog box and specifying a software project directory. The support scripts then examine the hardware design, build design-specific functions, conditionally include processor-specific functions, and complete the compilation process. For code-size constrained designs, most of the stock functionality can be excluded from the compiled library. When all of the configurable options are removed from the binary, MicroShell has an unoptimized memory footprint of about 4.8 kB and a size-optimized footprint of about 2.3 kB. Since MicroShell allows unfettered access to all processor-accessible memory locations, it is possible to perform live patching on a running system. This can be useful, for instance, if a bug is discovered in a routine but the system cannot be rebooted: Shell allows a skilled operator to directly edit the binary executable in memory. With some forethought, MicroShell code can be located in a different memory location from custom code, permitting the custom functionality to be overwritten at any time without stopping the controlling shell.

Clock and carrier recovery in high-speed coherent optical communication systems

NASA Astrophysics Data System (ADS)

Amado, Sofia B.; Ferreira, Ricardo; Costa, Pedro S.; Guiomar, Fernando P.; Ziaie, Somayeh; Teixeira, António L.; Muga, Nelson J.; Pinto, Armando N.

2014-08-01

In this paper, the implementations of clock and carrier recovery in digital domain are analyzed. Hardware implementation details, resources estimation and real-time results are presented. Analog-to-Digital Converters (ADC), operating at 1.25Gsa/s, and a Virtex-6 Field-Programmable Gate Array (FPGA), have been used, allowing the implementation of a real-time Quadrature Phase Shift Keying (QPSK) system operating at 1.25Gb/s. The real-time mode operation is successfully demonstrated over 80 km of Standard Single Mode Fiber (SSMF).

An Architecture for Coexistence with Multiple Users in Frequency Hopping Cognitive Radio Networks

DTIC Science & Technology

2013-03-01

the base WARP system, a custom IP core written in VHDL , and the Virtex IV’s embedded PowerPC core with C code to implement the radio and hopset...shown in Appendix C as Figure C.2. All VHDL code necessary to implement this IP core is included in Appendix G. 69 Figure 3.19: FPGA bus structure...subsystem functionality. A total of 1,430 lines of VHDL code were implemented for this research. 1 library ieee; 2 use ieee.std logic 1164.all; 3 use

A hybrid intelligent controller for a twin rotor MIMO system and its hardware implementation.

PubMed

Juang, Jih-Gau; Liu, Wen-Kai; Lin, Ren-Wei

2011-10-01

This paper presents a fuzzy PID control scheme with a real-valued genetic algorithm (RGA) to a setpoint control problem. The objective of this paper is to control a twin rotor MIMO system (TRMS) to move quickly and accurately to the desired attitudes, both the pitch angle and the azimuth angle in a cross-coupled condition. A fuzzy compensator is applied to the PID controller. The proposed control structure includes four PID controllers with independent inputs in 2-DOF. In order to reduce total error and control energy, all parameters of the controller are obtained by a RGA with the system performance index as a fitness function. The system performance index utilized the integral of time multiplied by the square error criterion (ITSE) to build a suitable fitness function in the RGA. A new method for RGA to solve more than 10 parameters in the control scheme is investigated. For real-time control, Xilinx Spartan II SP200 FPGA (Field Programmable Gate Array) is employed to construct a hardware-in-the-loop system through writing VHDL on this FPGA. Copyright © 2011 ISA. Published by Elsevier Ltd. All rights reserved.

Logic design and implementation of FPGA for a high frame rate ultrasound imaging system

NASA Astrophysics Data System (ADS)

Liu, Anjun; Wang, Jing; Lu, Jian-Yu

2002-05-01

Recently, a method has been developed for high frame rate medical imaging [Jian-yu Lu, ``2D and 3D high frame rate imaging with limited diffraction beams,'' IEEE Trans. Ultrason. Ferroelectr. Freq. Control 44(4), 839-856 (1997)]. To realize this method, a complicated system [multiple-channel simultaneous data acquisition, large memory in each channel for storing up to 16 seconds of data at 40 MHz and 12-bit resolution, time-variable-gain (TGC) control, Doppler imaging, harmonic imaging, as well as coded transmissions] is designed. Due to the complexity of the system, field programmable gate array (FPGA) (Xilinx Spartn II) is used. In this presentation, the design and implementation of the FPGA for the system will be reported. This includes the synchronous dynamic random access memory (SDRAM) controller and other system controllers, time sharing for auto-refresh of SDRAMs to reduce peak power, transmission and imaging modality selections, ECG data acquisition and synchronization, 160 MHz delay locked loop (DLL) for accurate timing, and data transfer via either a parallel port or a PCI bus for post image processing. [Work supported in part by Grant 5RO1 HL60301 from NIH.

Moving Horizon Estimation on a Chip

DTIC Science & Technology

2014-06-26

description, e.g. VHDL or Verilog, for FPGA implementation . Especially for those whose main expertise is in control system design, writing algorithms in C...ditional Kalman Filter(KF) where recursive solution is available. We devel- oped various MHE designs and implemented them on the Xilinx Zynq ZC702 FPGA...practical deployment of the MHE technology. 2.2 Implementation of MHE on FPGA The next paper demonstrated the feasibility of implementing MHE algo

Advanced Wireless Integrated Navy Network - AWINN

DTIC Science & Technology

2005-09-30

progress report No. 3 on AWINN hardware and software configurations of smart , wideband, multi-function antennas, secure configurable platform, close-in...results to the host PC via a UART soft core. The UART core used is a proprietary Xilinx core which incorporates features described in National...current software uses wheel odometry and visual landmarks to create a map and estimate position on an internal x, y grid . The wheel odometry provides a

Hardware realization of an SVM algorithm implemented in FPGAs

NASA Astrophysics Data System (ADS)

Wiśniewski, Remigiusz; Bazydło, Grzegorz; Szcześniak, Paweł

2017-08-01

The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC the SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which consumes the large number of power transistors (18 transistors and 18 independent PWM outputs) and "non-standard positions of control pulses" during the switching sequence. Recently, hardware implementations become popular since computed operations may be executed much faster and efficient due to nature of the digital devices (especially concurrency). In the paper, we propose a hardware algorithm of SVM computation. In opposite to the existing techniques, the presented solution applies COordinate Rotation DIgital Computer (CORDIC) method to solve the trigonometric operations. Furthermore, adequate arithmetic modules (that is, sub-devices) used for intermediate calculations, such as code converters or proper sectors selectors (for output voltages and input current) are presented in detail. The proposed technique has been implemented as a design described with the use of Verilog hardware description language. The preliminary results of logic implementation oriented on the Xilinx FPGA (particularly, low-cost device from Artix-7 family from Xilinx was used) are also presented.

FPGA Coprocessor for Accelerated Classification of Images

NASA Technical Reports Server (NTRS)

Pingree, Paula J.; Scharenbroich, Lucas J.; Werne, Thomas A.

2008-01-01

An effort related to that described in the preceding article focuses on developing a spaceborne processing platform for fast and accurate onboard classification of image data, a critical part of modern satellite image processing. The approach again has been to exploit the versatility of recently developed hybrid Virtex-4FX field-programmable gate array (FPGA) to run diverse science applications on embedded processors while taking advantage of the reconfigurable hardware resources of the FPGAs. In this case, the FPGA serves as a coprocessor that implements legacy C-language support-vector-machine (SVM) image-classification algorithms to detect and identify natural phenomena such as flooding, volcanic eruptions, and sea-ice break-up. The FPGA provides hardware acceleration for increased onboard processing capability than previously demonstrated in software. The original C-language program demonstrated on an imaging instrument aboard the Earth Observing-1 (EO-1) satellite implements a linear-kernel SVM algorithm for classifying parts of the images as snow, water, ice, land, or cloud or unclassified. Current onboard processors, such as on EO-1, have limited computing power, extremely limited active storage capability and are no longer considered state-of-the-art. Using commercially available software that translates C-language programs into hardware description language (HDL) files, the legacy C-language program, and two newly formulated programs for a more capable expanded-linear-kernel and a more accurate polynomial-kernel SVM algorithm, have been implemented in the Virtex-4FX FPGA. In tests, the FPGA implementations have exhibited significant speedups over conventional software implementations running on general-purpose hardware.

Field programmable gate array-assigned complex-valued computation and its limits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bernard-Schwarz, Maria, E-mail: maria.bernardschwarz@ni.com; Institute of Applied Physics, TU Wien, Wiedner Hauptstrasse 8, 1040 Wien; Zwick, Wolfgang

We discuss how leveraging Field Programmable Gate Array (FPGA) technology as part of a high performance computing platform reduces latency to meet the demanding real time constraints of a quantum optics simulation. Implementations of complex-valued operations using fixed point numeric on a Virtex-5 FPGA compare favorably to more conventional solutions on a central processing unit. Our investigation explores the performance of multiple fixed point options along with a traditional 64 bits floating point version. With this information, the lowest execution times can be estimated. Relative error is examined to ensure simulation accuracy is maintained.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kapusta, P.; Kisielewski, B.

In this paper the overvoltage protection modules (OVP) for the power supply (PS) system of the Belle II pixel detector (PXD) are described. The aim of the OVP is to protect the detector and associated electronics against overvoltage conditions. Most critical in the system are voltages supplying the front-end ASICs. The PXD detector consists of the DEPFET sensor modules with integrated chips like the Drain Current Digitizer, the Switcher and the Data Handling Processor. These chips, implemented in modern sub-micron technologies, are quite vulnerable to variations in the supply voltages. The PXD will be placed in the Belle II experimentmore » as close as possible to the interaction point, where access during experiment is very limited or even impossible, thus the PS and OVP systems exploit the remote-sensing method. Overvoltage conditions are due to failures of the PS itself, wrong setting of the output voltages or transient voltages coming out of hard noisy environment of the experiment. The OVP modules are parts of the PS modules. For powering the PXD 40 PS modules are placed 15 m outside the Belle II spectrometer. Each one is equipped with the OVP board. All voltages (22) are grouped in 4 domains: Analog, Digital, Steering and Gate which have independent grounds. The OVP boards are designed from integrated circuits from Linear Technology. All configurations were simulated with the Spice program. The control electronics is designed in a Xilinx CPLD. Two types of integrated circuits were used. LT4356 surge stopper protects loads from high voltage transients. The output voltages are limited to a safe value and also protect loads against over current faults. For less critical voltages, the LTC2912 voltage monitors are used that detect under-voltage and overvoltage events. It has to be noted that the OVP system is working independently of any other protection of the PS system, which increases its overall reliability. (authors)« less

FPGA Implementation of Reed-Solomon Decoder for IEEE 802.16 WiMAX Systems using Simulink-Sysgen Design Environment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bobrek, Miljko; Albright, Austin P

This paper presents FPGA implementation of the Reed-Solomon decoder for use in IEEE 802.16 WiMAX systems. The decoder is based on RS(255,239) code, and is additionally shortened and punctured according to the WiMAX specifications. Simulink model based on Sysgen library of Xilinx blocks was used for simulation and hardware implementation. At the end, simulation results and hardware implementation performances are presented.

FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG

DTIC Science & Technology

2014-06-01

is normalized to π. The proposed burst-mode architecture is written in VHDL and verified using Modelsim. The VHDL design is implemented on a Xilinx...Document Number: SET 2014-0043 412TW-PA-14298 FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG June 2014 Final Report Test...To) 9/11 -- 8/14 4. TITLE AND SUBTITLE FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG 5a. CONTRACT NUMBER: W900KK-11-C-0032 5b

Serial data acquisition for GEM-2D detector

NASA Astrophysics Data System (ADS)

Kolasinski, Piotr; Pozniak, Krzysztof T.; Czarski, Tomasz; Linczuk, Maciej; Byszuk, Adrian; Chernyshova, Maryna; Juszczyk, Bartlomiej; Kasprowicz, Grzegorz; Wojenski, Andrzej; Zabolotny, Wojciech; Zienkiewicz, Pawel; Mazon, Didier; Malard, Philippe; Herrmann, Albrecht; Vezinet, Didier

2014-11-01

This article debates about data fast acquisition and histogramming method for the X-ray GEM detector. The whole process of histogramming is performed by FPGA chips (Spartan-6 series from Xilinx). The results of the histogramming process are stored in an internal FPGA memory and then sent to PC. In PC data is merged and processed by MATLAB. The structure of firmware functionality implemented in the FPGAs is described. Examples of test measurements and results are presented.

Single-Event Effect (SEE) Survey of Advanced Reconfigurable Field Programmable Gate Arrays: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

NASA Technical Reports Server (NTRS)

Allen, Gregory

2011-01-01

The NEPP Reconfigurable Field-Programmable Gate Array (FPGA) task has been charged to evaluate reconfigurable FPGA technologies for use in space. Under this task, the Xilinx single-event-immune, reconfigurable FPGA (SIRF) XQR5VFX130 device was evaluated for SEE. Additionally, the Altera Stratix-IV and SiliconBlue iCE65 were screened for single-event latchup (SEL).

Neuro-Inspired Spike-Based Motion: From Dynamic Vision Sensor to Robot Motor Open-Loop Control through Spike-VITE

PubMed Central

Perez-Peña, Fernando; Morgado-Estevez, Arturo; Linares-Barranco, Alejandro; Jimenez-Fernandez, Angel; Gomez-Rodriguez, Francisco; Jimenez-Moreno, Gabriel; Lopez-Coronado, Juan

2013-01-01

In this paper we present a complete spike-based architecture: from a Dynamic Vision Sensor (retina) to a stereo head robotic platform. The aim of this research is to reproduce intended movements performed by humans taking into account as many features as possible from the biological point of view. This paper fills the gap between current spike silicon sensors and robotic actuators by applying a spike processing strategy to the data flows in real time. The architecture is divided into layers: the retina, visual information processing, the trajectory generator layer which uses a neuroinspired algorithm (SVITE) that can be replicated into as many times as DoF the robot has; and finally the actuation layer to supply the spikes to the robot (using PFM). All the layers do their tasks in a spike-processing mode, and they communicate each other through the neuro-inspired AER protocol. The open-loop controller is implemented on FPGA using AER interfaces developed by RTC Lab. Experimental results reveal the viability of this spike-based controller. Two main advantages are: low hardware resources (2% of a Xilinx Spartan 6) and power requirements (3.4 W) to control a robot with a high number of DoF (up to 100 for a Xilinx Spartan 6). It also evidences the suitable use of AER as a communication protocol between processing and actuation. PMID:24264330

Neuro-inspired spike-based motion: from dynamic vision sensor to robot motor open-loop control through spike-VITE.

PubMed

Perez-Peña, Fernando; Morgado-Estevez, Arturo; Linares-Barranco, Alejandro; Jimenez-Fernandez, Angel; Gomez-Rodriguez, Francisco; Jimenez-Moreno, Gabriel; Lopez-Coronado, Juan

2013-11-20

In this paper we present a complete spike-based architecture: from a Dynamic Vision Sensor (retina) to a stereo head robotic platform. The aim of this research is to reproduce intended movements performed by humans taking into account as many features as possible from the biological point of view. This paper fills the gap between current spike silicon sensors and robotic actuators by applying a spike processing strategy to the data flows in real time. The architecture is divided into layers: the retina, visual information processing, the trajectory generator layer which uses a neuroinspired algorithm (SVITE) that can be replicated into as many times as DoF the robot has; and finally the actuation layer to supply the spikes to the robot (using PFM). All the layers do their tasks in a spike-processing mode, and they communicate each other through the neuro-inspired AER protocol. The open-loop controller is implemented on FPGA using AER interfaces developed by RTC Lab. Experimental results reveal the viability of this spike-based controller. Two main advantages are: low hardware resources (2% of a Xilinx Spartan 6) and power requirements (3.4 W) to control a robot with a high number of DoF (up to 100 for a Xilinx Spartan 6). It also evidences the suitable use of AER as a communication protocol between processing and actuation.

FPGA implementation of image dehazing algorithm for real time applications

NASA Astrophysics Data System (ADS)

Kumar, Rahul; Kaushik, Brajesh Kumar; Balasubramanian, R.

2017-09-01

Weather degradation such as haze, fog, mist, etc. severely reduces the effective range of visual surveillance. This degradation is a spatially varying phenomena, which makes this problem non trivial. Dehazing is an essential preprocessing stage in applications such as long range imaging, border security, intelligent transportation system, etc. However, these applications require low latency of the preprocessing block. In this work, single image dark channel prior algorithm is modified and implemented for fast processing with comparable visual quality of the restored image/video. Although conventional single image dark channel prior algorithm is computationally expensive, it yields impressive results. Moreover, a two stage image dehazing architecture is introduced, wherein, dark channel and airlight are estimated in the first stage. Whereas, transmission map and intensity restoration are computed in the next stages. The algorithm is implemented using Xilinx Vivado software and validated by using Xilinx zc702 development board, which contains an Artix7 equivalent Field Programmable Gate Array (FPGA) and ARM Cortex A9 dual core processor. Additionally, high definition multimedia interface (HDMI) has been incorporated for video feed and display purposes. The results show that the dehazing algorithm attains 29 frames per second for the image resolution of 1920x1080 which is suitable of real time applications. The design utilizes 9 18K_BRAM, 97 DSP_48, 6508 FFs and 8159 LUTs.

Three-phase Four-leg Inverter LabVIEW FPGA Control Code

DOE Office of Scientific and Technical Information (OSTI.GOV)

In the area of power electronics control, Field Programmable Gate Arrays (FPGAs) have the capability to outperform their Digital Signal Processor (DSP) counterparts due to the FPGA’s ability to implement true parallel processing and therefore facilitate higher switching frequencies, higher control bandwidth, and/or enhanced functionality. National Instruments (NI) has developed two platforms, Compact RIO (cRIO) and Single Board RIO (sbRIO), which combine a real-time processor with an FPGA. The FPGA can be programmed with a subset of the well-known LabVIEW graphical programming language. The use of cRIO and sbRIO for power electronics control has developed over the last few yearsmore » to include control of three-phase inverters. Most three-phase inverter topologies include three switching legs. The addition of a fourth-leg to natively generate the neutral connection allows the inverter to serve single-phase loads in a microgrid or stand-alone power system and to balance the three-phase voltages in the presence of significant load imbalance. However, the control of a four-leg inverter is much more complex. In particular, instead of standard two-dimensional space vector modulation (SVM), the inverter requires three-dimensional space vector modulation (3D-SVM). The candidate software implements complete control algorithms in LabVIEW FPGA for a three-phase four-leg inverter. The software includes feedback control loops, three-dimensional space vector modulation gate-drive algorithms, advanced alarm handling capabilities, contactor control, power measurements, and debugging and tuning tools. The feedback control loops allow inverter operation in AC voltage control, AC current control, or DC bus voltage control modes based on external mode selection by a user or supervisory controller. The software includes the ability to synchronize its AC output to the grid or other voltage-source before connection. The software also includes provisions to allow inverter operation in parallel with other voltage regulating devices on the AC or DC buses. This flexibility allows the Inverter to operate as a stand-alone voltage source, connected to the grid, or in parallel with other controllable voltage sources as part of a microgrid or remote power system. In addition, as the inverter is expected to operate under severe unbalanced conditions, the software includes algorithms to accurately compute real and reactive power for each phase based on definitions provided in the IEEE Standard 1459: IEEE Standard Definitions for the Measurement of Electric Power Quantities Under Sinusoidal, Nonsinusoidal, Balanced, or Unbalanced Conditions. Finally, the software includes code to output analog signals for debugging and for tuning of control loops. The software fits on the Xilinx Virtex V LX110 FPGA embedded in the NI cRIO-9118 FPGA chassis, and with a 40 MHz base clock, supports a modulation update rate of 40 MHz, user-settable switching frequencies and synchronized control loop update rates of tens of kHz, and reference waveform generation, including Phase Lock Loop (PLL), update rate of 100 kHz.« less

Design Considerations for a Computationally-Lightweight Authentication Mechanism for Passive RFID Tags

DTIC Science & Technology

2009-09-01

suffer the power and complexity requirements of a public key system. 28 In [18], a simulation of the SHA –1 algorithm is performed on a Xilinx FPGA ... 256 bits. Thus, the construction of a hash table would need 2512 independent comparisons. It is known that hash collisions of the SHA –1 algorithm... SHA –1 algorithm for small-core FPGA design. Small-core FPGA design is the process by which a circuit is adapted to use the minimal amount of logic

FPGA based charge fast histogramming for GEM detector

NASA Astrophysics Data System (ADS)

Poźniak, Krzysztof T.; Byszuk, A.; Chernyshova, M.; Cieszewski, R.; Czarski, T.; Dominik, W.; Jakubowska, K.; Kasprowicz, G.; Rzadkiewicz, J.; Scholz, M.; Zabolotny, W.

2013-10-01

This article presents a fast charge histogramming method for the position sensitive X-ray GEM detector. The energy resolved measurements are carried out simultaneously for 256 channels of the GEM detector. The whole process of histogramming is performed in 21 FPGA chips (Spartan-6 series from Xilinx) . The results of the histogramming process are stored in an external DDR3 memory. The structure of an electronic measuring equipment and a firmware functionality implemented in the FPGAs is described. Examples of test measurements are presented.

Fast data transmission from serial data acquisition for the GEM detector system

NASA Astrophysics Data System (ADS)

Kolasinski, Piotr; Pozniak, Krzysztof T.; Czarski, Tomasz; Byszuk, Adrian; Chernyshova, Maryna; Kasprowicz, Grzegorz; Krawczyk, Rafal D.; Wojenski, Andrzej; Zabolotny, Wojciech

2015-09-01

This article proposes new method of storing data and transferring it to PC in the X-ray GEM detector system. The whole process is performed by FPGA chips (Spartan-6 series from Xilinx). Comparing to previous methods, new approach allows to store much more data in the system. New, improved implementation of the communication algorithm significantly increases transfer rate between system and PC. In PC data is merged and processed by MATLAB. The structure of firmware implemented in the FPGAs is described.

FPGA for Power Control of MSL Avionics

NASA Technical Reports Server (NTRS)

Wang, Duo; Burke, Gary R.

2011-01-01

A PLGT FPGA (Field Programmable Gate Array) is included in the LCC (Load Control Card), GID (Guidance Interface & Drivers), TMC (Telemetry Multiplexer Card), and PFC (Pyro Firing Card) boards of the Mars Science Laboratory (MSL) spacecraft. (PLGT stands for PFC, LCC, GID, and TMC.) It provides the interface between the backside bus and the power drivers on these boards. The LCC drives power switches to switch power loads, and also relays. The GID drives the thrusters and latch valves, as well as having the star-tracker and Sun-sensor interface. The PFC drives pyros, and the TMC receives digital and analog telemetry. The FPGA is implemented both in Xilinx (Spartan 3- 400) and in Actel (RTSX72SU, ASX72S). The Xilinx Spartan 3 part is used for the breadboard, the Actel ASX part is used for the EM (Engineer Module), and the pin-compatible, radiation-hardened RTSX part is used for final EM and flight. The MSL spacecraft uses a FC (Flight Computer) to control power loads, relays, thrusters, latch valves, Sun-sensor, and star-tracker, and to read telemetry such as temperature. Commands are sent over a 1553 bus to the MREU (Multi-Mission System Architecture Platform Remote Engineering Unit). The MREU resends over a remote serial command bus c-bus to the LCC, GID TMC, and PFC. The MREU also sends out telemetry addresses via a remote serial telemetry address bus to the LCC, GID, TMC, and PFC, and the status is returned over the remote serial telemetry data bus.

Electronics for a highly segmented electromagnetic calorimeter prototype

NASA Astrophysics Data System (ADS)

Fehlker, D.; Alme, J.; van den Brink, A.; de Haas, A. P.; Nooren, G.-J.; Reicher, M.; Röhrich, D.; Rossewij, M.; Ullaland, K.; Yang, S.

2013-03-01

A prototype of a highly segmented electromagnetic calorimeter has been developed. The detector tower is made of 24 layers of PHASE2/MIMOSA23 silicon sensors sandwiched between tungsten plates, with 4 sensors per layer, a total of 96 MIMOSA sensors, resulting in 39 MPixels for the complete prototype detector tower. The paper focuses on the electronics of this calorimeter prototype. Two detector readout and control systems are used, each containing two Spartan 6 and one Virtex 6 FPGA, running embedded Linux, each system serving 12 detector layers. In 550 ms a total of 4 Gbytes of data is read from the detector, stored in memory on the electronics and then shipped to the DAQ system via Gigabit ethernet.

SpaceCube 2.0: An Advanced Hybrid Onboard Data Processor

NASA Technical Reports Server (NTRS)

Lin, Michael; Flatley, Thomas; Godfrey, John; Geist, Alessandro; Espinosa, Daniel; Petrick, David

2011-01-01

The SpaceCube 2.0 is a compact, high performance, low-power onboard processing system that takes advantage of cutting-edge hybrid (CPU/FPGA/DSP) processing elements. The SpaceCube 2.0 design concept includes two commercial Virtex-5 field-programmable gate array (FPGA) parts protected by gradiation hardened by software" technology, and possesses exceptional size, weight, and power characteristics [5x5x7 in., 3.5 lb (approximately equal to 12.7 x 12.7 x 17.8 cm, 1.6 kg) 5-25 W, depending on the application fs required clock rate]. The two Virtex-5 FPGA parts are implemented in a unique back-toback configuration to maximize data transfer and computing performance. Draft computing power specifications for the SpaceCube 2.0 unit include four PowerPC 440s (1100 DMIPS each), 500+ DSP48Es (2x580 GMACS), 100+ LVDS high-speed serial I/Os (1.25 Gbps each), and 2x190 GFLOPS single-precision (65 GFLOPS double-precision) floating point performance. The SpaceCube 2.0 includes PROM memory for CPU boot, health and safety, and basic command and telemetry functionality; RAM memory for program execution; and FLASH/EEPROM memory to store algorithms and application code for the CPU, FPGA, and DSP processing elements. Program execution can be reconfigured in real time and algorithms can be updated, modified, and/or replaced at any point during the mission. Gigabit Ethernet, Spacewire, SATA and highspeed LVDS serial/parallel I/O channels are available for instrument/sensor data ingest, and mission-unique instrument interfaces can be accommodated using a compact PCI (cPCI) expansion card interface. The SpaceCube 2.0 can be utilized in NASA Earth Science, Helio/Astrophysics and Exploration missions, and Department of Defense satellites for onboard data processing. It can also be used in commercial communication and mapping satellites.

A Nonlinearity Minimization-Oriented Resource-Saving Time-to-Digital Converter Implemented in a 28 nm Xilinx FPGA

NASA Astrophysics Data System (ADS)

Wang, Yonggang; Liu, Chong

2015-10-01

Because large nonlinearity errors exist in the current tapped-delay line (TDL) style field programmable gate array (FPGA)-based time-to-digital converters (TDC), bin-by-bin calibration techniques have to be resorted for gaining a high measurement resolution. If the TDL in selected FPGAs is significantly affected by changes in ambient temperature, the bin-by-bin calibration table has to be updated as frequently as possible. The on-line calibration and calibration table updating increase the TDC design complexity and limit the system performance to some extent. This paper proposes a method to minimize the nonlinearity errors of TDC bins, so that the bin-by-bin calibration may not be needed while maintaining a reasonably high time resolution. The method is a two pass approach: By a bin realignment, the large number of wasted zero-width bins in the original TDL is reused and the granularity of the bins is improved; by a bin decimation, the bin size and its uniformity is traded-off, and the time interpolation by the delay line turns more precise so that the bin-by-bin calibration is not necessary. Using Xilinx 28 nm FPGAs, in which the TDL property is not very sensitive to ambient temperature, the proposed TDC achieves approximately 15 ps root-mean-square (RMS) time resolution by dual-channel measurements of time-intervals over the range of operating temperature. Because of removing the calibration and less logic resources required for the data post-processing, the method has bigger multi-channel capability.

Synthesis of blind source separation algorithms on reconfigurable FPGA platforms

NASA Astrophysics Data System (ADS)

Du, Hongtao; Qi, Hairong; Szu, Harold H.

2005-03-01

Recent advances in intelligence technology have boosted the development of micro- Unmanned Air Vehicles (UAVs) including Sliver Fox, Shadow, and Scan Eagle for various surveillance and reconnaissance applications. These affordable and reusable devices have to fit a series of size, weight, and power constraints. Cameras used on such micro-UAVs are therefore mounted directly at a fixed angle without any motion-compensated gimbals. This mounting scheme has resulted in the so-called jitter effect in which jitter is defined as sub-pixel or small amplitude vibrations. The jitter blur caused by the jitter effect needs to be corrected before any other processing algorithms can be practically applied. Jitter restoration has been solved by various optimization techniques, including Wiener approximation, maximum a-posteriori probability (MAP), etc. However, these algorithms normally assume a spatial-invariant blur model that is not the case with jitter blur. Szu et al. developed a smart real-time algorithm based on auto-regression (AR) with its natural generalization of unsupervised artificial neural network (ANN) learning to achieve restoration accuracy at the sub-pixel level. This algorithm resembles the capability of the human visual system, in which an agreement between the pair of eyes indicates "signal", otherwise, the jitter noise. Using this non-statistical method, for each single pixel, a deterministic blind sources separation (BSS) process can then be carried out independently based on a deterministic minimum of the Helmholtz free energy with a generalization of Shannon's information theory applied to open dynamic systems. From a hardware implementation point of view, the process of jitter restoration of an image using Szu's algorithm can be optimized by pixel-based parallelization. In our previous work, a parallelly structured independent component analysis (ICA) algorithm has been implemented on both Field Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) using standard-height cells. ICA is an algorithm that can solve BSS problems by carrying out the all-order statistical, decorrelation-based transforms, in which an assumption that neighborhood pixels share the same but unknown mixing matrix A is made. In this paper, we continue our investigation on the design challenges of firmware approaches to smart algorithms. We think two levels of parallelization can be explored, including pixel-based parallelization and the parallelization of the restoration algorithm performed at each pixel. This paper focuses on the latter and we use ICA as an example to explain the design and implementation methods. It is well known that the capacity constraints of single FPGA have limited the implementation of many complex algorithms including ICA. Using the reconfigurability of FPGA, we show, in this paper, how to manipulate the FPGA-based system to provide extra computing power for the parallelized ICA algorithm with limited FPGA resources. The synthesis aiming at the pilchard re-configurable FPGA platform is reported. The pilchard board is embedded with single Xilinx VIRTEX 1000E FPGA and transfers data directly to CPU on the 64-bit memory bus at the maximum frequency of 133MHz. Both the feasibility performance evaluations and experimental results validate the effectiveness and practicality of this synthesis, which can be extended to the spatial-variant jitter restoration for micro-UAV deployment.

Software Defined GPS Receiver for International Space Station

NASA Technical Reports Server (NTRS)

Duncan, Courtney B.; Robison, David E.; Koelewyn, Cynthia Lee

2011-01-01

JPL is providing a software defined radio (SDR) that will fly on the International Space Station (ISS) as part of the CoNNeCT project under NASA's SCaN program. The SDR consists of several modules including a Baseband Processor Module (BPM) and a GPS Module (GPSM). The BPM executes applications (waveforms) consisting of software components for the embedded SPARC processor and logic for two Virtex II Field Programmable Gate Arrays (FPGAs) that operate on data received from the GPSM. GPS waveforms on the SDR are enabled by an L-Band antenna, low noise amplifier (LNA), and the GPSM that performs quadrature downconversion at L1, L2, and L5. The GPS waveform for the JPL SDR will acquire and track L1 C/A, L2C, and L5 GPS signals from a CoNNeCT platform on ISS, providing the best GPS-based positioning of ISS achieved to date, the first use of multiple frequency GPS on ISS, and potentially the first L5 signal tracking from space. The system will also enable various radiometric investigations on ISS such as local multipath or ISS dynamic behavior characterization. In following the software-defined model, this work will create a highly portable GPS software and firmware package that can be adapted to another platform with the necessary processor and FPGA capability. This paper also describes ISS applications for the JPL CoNNeCT SDR GPS waveform, possibilities for future global navigation satellite system (GNSS) tracking development, and the applicability of the waveform components to other space navigation applications.

Particle identification algorithms for the PANDA Endcap Disc DIRC

NASA Astrophysics Data System (ADS)

Schmidt, M.; Ali, A.; Belias, A.; Dzhygadlo, R.; Gerhardt, A.; Götzen, K.; Kalicy, G.; Krebs, M.; Lehmann, D.; Nerling, F.; Patsyuk, M.; Peters, K.; Schepers, G.; Schmitt, L.; Schwarz, C.; Schwiening, J.; Traxler, M.; Böhm, M.; Eyrich, W.; Lehmann, A.; Pfaffinger, M.; Uhlig, F.; Düren, M.; Etzelmüller, E.; Föhl, K.; Hayrapetyan, A.; Kreutzfeld, K.; Merle, O.; Rieke, J.; Wasem, T.; Achenbach, P.; Cardinali, M.; Hoek, M.; Lauth, W.; Schlimme, S.; Sfienti, C.; Thiel, M.

2017-12-01

The Endcap Disc DIRC has been developed to provide an excellent particle identification for the future PANDA experiment by separating pions and kaons up to a momentum of 4 GeV/c with a separation power of 3 standard deviations in the polar angle region from 5o to 22o. This goal will be achieved using dedicated particle identification algorithms based on likelihood methods and will be applied in an offline analysis and online event filtering. This paper evaluates the resulting PID performance using Monte-Carlo simulations to study basic single track PID as well as the analysis of complex physics channels. The online reconstruction algorithm has been tested with a Virtex4 FGPA card and optimized regarding the resulting constraints.

Solder Joint Health Monitoring Testbed

NASA Technical Reports Server (NTRS)

Delaney, Michael M.; Flynn, James; Browder, Mark

2009-01-01

A method of monitoring the health of selected solder joints, called SJ-BIST, has been developed by Ridgetop Group Inc. under a Small Business Innovative Research (SBIR) contract. The primary goal of this research program is to test and validate this method in a flight environment using realistically seeded faults in selected solder joints. An additional objective is to gather environmental data for future development of physics-based and data-driven prognostics algorithms. A test board is being designed using a Xilinx FPGA. These boards will be tested both in flight and on the ground using a shaker table and an altitude chamber.

A MOdular System for Acquisition, Interface and Control (MOSAIC) of detectors and their related electronics for high energy physics experiment

NASA Astrophysics Data System (ADS)

Robertis, G. De; Fanizzi, G.; Loddo, F.; Manzari, V.; Rizzi, M.

2018-02-01

In this work the MOSAIC ("MOdular System for Acquisition, Interface and Control") board, designed for the readout and testing of the pixel modules for the silicon tracker upgrade of the ALICE (A Large Ion Collider Experiment) experiment at teh CERN LHC, is described. It is based on an Artix7 Field Programmable Gate Array device by Xilinx and is compliant with the six unit "Versa Modular Eurocard" standard (6U-VME) for easy housing in a standard VMEbus crate from which it takes only power supplies and cooling.

Controller for the Electronically Scanned Thinned Array Radiometer (ESTAR) instrument

NASA Technical Reports Server (NTRS)

Zomberg, Brian G.; Chren, William A., Jr.

1994-01-01

A prototype controller for the ESTAR (electronically scanned thinned array radiometer) instrument has been designed and tested. It manages the operation of the digital data subsystem (DDS) and its communication with the Small Explorer data system (SEDS). Among the data processing tasks that it coordinates are FEM data acquisition, noise removal, phase alignment and correlation. Its control functions include instrument calibration and testing of two critical subsystems, the output data formatter and Walsh function generator. It is implemented in a Xilinx XC3064PC84-100 field programmable gate array (FPGA) and has a maximum clocking frequency of 10 MHz.

A FPGA-based Measurement System for Nonvolatile Semiconductor Memory Characterization

NASA Astrophysics Data System (ADS)

Bu, Jiankang; White, Marvin

2002-03-01

Low voltage, long retention, high density SONOS nonvolatile semiconductor memory (NVSM) devices are ideally suited for PCMCIA, FLASH and 'smart' cards. The SONOS memory transistor requires characterization with an accurate, rapid measurement system with minimum disturbance to the device. The FPGA-based measurement system includes three parts: 1) a pattern generator implemented with XILINX FPGAs and corresponding software, 2) a high-speed, constant-current, threshold voltage detection circuit, 3) and a data evaluation program, implemented with a LABVIEW program. Fig. 1 shows the general block diagram of the FPGA-based measurement system. The function generator is designed and simulated with XILINX Foundation Software. Under the control of the specific erase/write/read pulses, the analog detect circuit applies operational modes to the SONOS device under test (DUT) and determines the change of the memory-state of the SONOS nonvolatile memory transistor. The TEK460 digitizes the analog threshold voltage output and sends to the PC computer. The data is filtered and averaged with a LABVIEWTM program running on the PC computer and displayed on the monitor in real time. We have implemented the pattern generator with XILINX FPGAs. Fig. 2 shows the block diagram of the pattern generator. We realized the logic control by a method of state machine design. Fig. 3 shows a small part of the state machine. The flexibility of the FPGAs enhances the capabilities of this system and allows measurement variations without hardware changes. The characterization of the nonvolatile memory transistor device under test (DUT), as function of programming voltage and time, is achieved by a high-speed, constant-current threshold voltage detection circuit. The analog detection circuit incorporating fast analog switches controlled digitally with the FPGAs. The schematic circuit diagram is shown in Fig. 4. The various operational modes for the DUT are realized with control signals applied to the analog switches (SW) as shown in Fig. 5. A LABVIEWTM program, on a PC platform, collects and processes the data. The data is displayed on the monitor in real time. This time-domain filtering reduces the digitizing error. Fig. 6 shows the data processing. SONOS nonvolatile semiconductor memories are characterized by erase/write, retention and endurance measurements. Fig. 7 shows the erase/write characteristics of an n-Channel, 5V prog-rammable SONOS memory transistor. Fig.8 shows the retention characteristic of the same SONOS transistor. We have used this system to characterize SONOS nonvolatile semiconductor memory transistors. The attractive features of the test system design lies in the cost-effectiveness and flexibility of the test pattern implementation, fast read-out of memory state, low power, high precision determination of the device threshold voltage, and perhaps most importantly, minimum disturbance, which is indispensable for nonvolatile memory characterization.

A hierarchical scheduling and management solution for dynamic reconfiguration in FPGA-based embedded systems

NASA Astrophysics Data System (ADS)

Cervero, T.; Gómez, A.; López, S.; Sarmiento, R.; Dondo, J.; Rincón, F.; López, J. C.

2013-05-01

One of the limiting factors that have prevented a widely dissemination of the reconfigurable technology is the absence of an appropriate model for certain target applications capable of offering a reliable control. Moreover, the lack of flexible and easy-to-use scheduling and management systems are also relevant drawbacks to be considered. Under static scenarios, it is relatively easy to schedule and manage the reconfiguration process since all the variations corresponding to predetermined and well-known tasks. However, the difficulty increases when the adaptation needs of the overall system change semi-randomly according to the environmental fluctuations. In this context, this work proposes a change in the paradigm of dynamically reconfigurable systems, by attending to the dynamically reconfigurable control problematic as a whole, in which the scheduling and the placement issues are packed together as a hierarchical management structure, interacting together as one entity from the system point of view, but performing their tasks with certain degree of independence each other. In this sense, the top hierarchical level corresponds with a dynamic scheduler in charge of planning and adjusting all the reconfigurable modules according to the variations of the external stimulus. The lower level interacts with the physical layer of the device by means of instantiating, relocating, removing a reconfigurable module following the scheduler's instructions. In regards to how fast is the proposed solution, the total partial reconfiguration time achieved with this proposal has been measured and compared with other two approaches: 1) using traditional Xilinx's tools; 2) using an optimized version of the Xilinx's drivers. The collected numbers demonstrate that our solution reaches a gain up to 10 times faster than the other approaches.

Primary investigation the impacts of the external memory (DDR3) failures on the performance of Xilinx Zynq-7010 SoC based system (MicroZed) using laser irradiation

NASA Astrophysics Data System (ADS)

Liu, Shuhuan; Du, Xuecheng; Du, Xiaozhi; Zhang, Yao; Mubashiru, Lawal Olarewaju; Luo, Dongyang; yuan, Yuan; Deng, Tianxiang; Li, Zhuoqi; Zang, Hang; Li, Yonghong; He, Chaohui; Ma, Yingqi; Shangguan, Shipeng

2017-09-01

The impacts of the external dynamic memory (DDR3) failures on the performance of 28 nm Xilinx Zynq-7010 SoC based system (MicroZed) were investigated with two sets of 1064 nm laser platforms. The failure sensitive area distributionsons on the back surface of the test DDR3 were primarily localized with a CW laser irradiation platform. During the CW laser scanning on the back surface of the DDR3 of the test board system, various failure modes except SEU and SEL (MBU, SEFI, data storage address error, rebooting, etc) were found in the testing embedded modules (ALU, PL, Register, Cache and DMA, etc) of SoC. Moreover, the experimental results demonstrated that there were 16 failure sensitive blocks symmetrically distributed on the back surface of the DDR3 with every sensitive block area measured was about 1 mm × 0.5 mm. The influence factors on the failure modes of the embedded modules were primarily analyzed and the SEE characteristics of DDR3 induced by the picoseconds pulsed laser were tested. The failure modes of DDR3 found were SEU, SEFI, SEL, test board rebooting by itself, unknown data, etc. Furthermore, the time interval distributions of failure occurrence in DDR3 changes with the pulsed laser irradiation energy and the CPU operating frequency were measured and compared. Meanwhile, the failure characteristics of DDR3 induced by pulsed laser irradiation were primarily explored. The measured results and the testing techniques designed in this paper provide some reference information for evaluating the reliability of the test system or other similar electronic system in harsh environment.

A real-time hybrid neuron network for highly parallel cognitive systems.

PubMed

Christiaanse, Gerrit Jan; Zjajo, Amir; Galuzzi, Carlo; van Leuken, Rene

2016-08-01

For comprehensive understanding of how neurons communicate with each other, new tools need to be developed that can accurately mimic the behaviour of such neurons and neuron networks under `real-time' constraints. In this paper, we propose an easily customisable, highly pipelined, neuron network design, which executes optimally scheduled floating-point operations for maximal amount of biophysically plausible neurons per FPGA family type. To reduce the required amount of resources without adverse effect on the calculation latency, a single exponent instance is used for multiple neuron calculation operations. Experimental results indicate that the proposed network design allows the simulation of up to 1188 neurons on Virtex7 (XC7VX550T) device in brain real-time yielding a speed-up of x12.4 compared to the state-of-the art.

Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems

NASA Astrophysics Data System (ADS)

Zhai, Xiaojun; Bensaali, Faycal; Sotudeh, Reza

2013-01-01

Number plate (NP) binarization and adjustment are important preprocessing stages in automatic number plate recognition (ANPR) systems and are used to link the number plate localization (NPL) and character segmentation stages. Successfully linking these two stages will improve the performance of the entire ANPR system. We present two optimized low-complexity NP binarization and adjustment algorithms. Efficient area/speed architectures based on the proposed algorithms are also presented and have been successfully implemented and tested using the Mentor Graphics RC240 FPGA development board, which together require only 9% of the available on-chip resources of a Virtex-4 FPGA, run with a maximum frequency of 95.8 MHz and are capable of processing one image in 0.07 to 0.17 ms.

Hardware Design and Implementation of Fixed-Width Standard and Truncated 4×4, 6×6, 8×8 and 12×12-BIT Multipliers Using Fpga

NASA Astrophysics Data System (ADS)

Rais, Muhammad H.

2010-06-01

This paper presents Field Programmable Gate Array (FPGA) implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT). Remarkable reduction in FPGA resources, delay, and power can be achieved using truncated multipliers instead of standard parallel multipliers when the full precision of the standard multiplier is not required. The truncated multipliers show significant improvement as compared to standard multipliers. Results show that the anomaly in Spartan-3 AN average connection and maximum pin delay have been efficiently reduced in Virtex-4 device.

On the design of a radix-10 online floating-point multiplier

NASA Astrophysics Data System (ADS)

McIlhenny, Robert D.; Ercegovac, Milos D.

2009-08-01

This paper describes an approach to design and implement a radix-10 online floating-point multiplier. An online approach is considered because it offers computational flexibility not available with conventional arithmetic. The design was coded in VHDL and compiled, synthesized, and mapped onto a Virtex 5 FPGA to measure cost in terms of LUTs (look-up-tables) as well as the cycle time and total latency. The routing delay which was not optimized is the major component in the cycle time. For a rough estimate of the cost/latency characteristics, our design was compared to a standard radix-2 floating-point multiplier of equivalent precision. The results demonstrate that even an unoptimized radix-10 online design is an attractive implementation alternative for FPGA floating-point multiplication.

Monitoring system for testing the radiation hardness of a KINTEX-7 FPGA

NASA Astrophysics Data System (ADS)

Cojocariu, L. N.; Placinta, V. M.; Dumitru, L.

2016-03-01

A much more efficient Ring Imaging Cherenkov sub-detector system will be rebuilt in the second long shutdown of Large Hadron Collider for the LHCb experiment. Radiation-hard electronic components together with Commercial Off-The-Shelf ones will be used in the new Cherenkov photon detection system architecture. An irradiation program was foreseen to determine the radiation tolerance for the new electronic devices, including a Field Programmable Gate Array from KINTEX-7 family of XILINX. An automated test bench for online monitoring of the XC7K70T KINTEX-7 device operation in radiation conditions was designed and implemented by the LHCb Romanian group.

Implementation of the 2-D Wavelet Transform into FPGA for Image

NASA Astrophysics Data System (ADS)

León, M.; Barba, L.; Vargas, L.; Torres, C. O.

2011-01-01

This paper presents a hardware system implementation of the of discrete wavelet transform algoritm in two dimensions for FPGA, using the Daubechies filter family of order 2 (db2). The decomposition algorithm of this transform is designed and simulated with the Hardware Description Language VHDL and is implemented in a programmable logic device (FPGA) XC3S1200E reference, Spartan IIIE family, by Xilinx, take advantage the parallels properties of these gives us and speeds processing that can reach them. The architecture is evaluated using images input of different sizes. This implementation is done with the aim of developing a future images encryption hardware system using wavelet transform for security information.

NULL Convention Floating Point Multiplier

PubMed Central

Ramachandran, Seshasayanan

2015-01-01

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation. PMID:25879069

NULL convention floating point multiplier.

PubMed

Albert, Anitha Juliette; Ramachandran, Seshasayanan

2015-01-01

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.

A high data rate universal lattice decoder on FPGA

NASA Astrophysics Data System (ADS)

Ma, Jing; Huang, Xinming; Kura, Swapna

2005-06-01

This paper presents the architecture design of a high data rate universal lattice decoder for MIMO channels on FPGA platform. A phost strategy based lattice decoding algorithm is modified in this paper to reduce the complexity of the closest lattice point search. The data dependency of the improved algorithm is examined and a parallel and pipeline architecture is developed with the iterative decoding function on FPGA and the division intensive channel matrix preprocessing on DSP. Simulation results demonstrate that the improved lattice decoding algorithm provides better bit error rate and less iteration number compared with the original algorithm. The system prototype of the decoder shows that it supports data rate up to 7Mbit/s on a Virtex2-1000 FPGA, which is about 8 times faster than the original algorithm on FPGA platform and two-orders of magnitude better than its implementation on a DSP platform.

An FPGA Implementation of a Polychronous Spiking Neural Network with Delay Adaptation.

PubMed

Wang, Runchun; Cohen, Gregory; Stiefel, Klaus M; Hamilton, Tara Julia; Tapson, Jonathan; van Schaik, André

2013-01-01

We present an FPGA implementation of a re-configurable, polychronous spiking neural network with a large capacity for spatial-temporal patterns. The proposed neural network generates delay paths de novo, so that only connections that actually appear in the training patterns will be created. This allows the proposed network to use all the axons (variables) to store information. Spike Timing Dependent Delay Plasticity is used to fine-tune and add dynamics to the network. We use a time multiplexing approach allowing us to achieve 4096 (4k) neurons and up to 1.15 million programmable delay axons on a Virtex 6 FPGA. Test results show that the proposed neural network is capable of successfully recalling more than 95% of all spikes for 96% of the stored patterns. The tests also show that the neural network is robust to noise from random input spikes.

VLSI implementation of RSA encryption system using ancient Indian Vedic mathematics

NASA Astrophysics Data System (ADS)

Thapliyal, Himanshu; Srinivas, M. B.

2005-06-01

This paper proposes the hardware implementation of RSA encryption/decryption algorithm using the algorithms of Ancient Indian Vedic Mathematics that have been modified to improve performance. The recently proposed hierarchical overlay multiplier architecture is used in the RSA circuitry for multiplication operation. The most significant aspect of the paper is the development of a division architecture based on Straight Division algorithm of Ancient Indian Vedic Mathematics and embedding it in RSA encryption/decryption circuitry for improved efficiency. The coding is done in Verilog HDL and the FPGA synthesis is done using Xilinx Spartan library. The results show that RSA circuitry implemented using Vedic division and multiplication is efficient in terms of area/speed compared to its implementation using conventional multiplication and division architectures.

SAD5 Stereo Correlation Line-Striping in an FPGA

NASA Technical Reports Server (NTRS)

Villalpando, Carlos Y.; Morfopoulos, Arin C.

2011-01-01

High precision SAD5 stereo computations can be performed in an FPGA (field-programmable gate array) at much higher speeds than possible in a conventional CPU (central processing unit), but this uses large amounts of FPGA resources that scale with image size. Of the two key resources in an FPGA, Slices and BRAM (block RAM), Slices scale linearly in the new algorithm with image size, and BRAM scales quadratically with image size. An approach was developed to trade latency for BRAM by sub-windowing the image vertically into overlapping strips and stitching the outputs together to create a single continuous disparity output. In stereo, the general rule of thumb is that the disparity search range must be 1/10 the image size. In the new algorithm, BRAM usage scales linearly with disparity search range and scales again linearly with line width. So a doubling of image size, say from 640 to 1,280, would in the previous design be an effective 4 of BRAM usage: 2 for line width, 2 again for disparity search range. The minimum strip size is twice the search range, and will produce an output strip width equal to the disparity search range. So assuming a disparity search range of 1/10 image width, 10 sequential runs of the minimum strip size would produce a full output image. This approach allowed the innovators to fit 1280 960 wide SAD5 stereo disparity in less than 80 BRAM, 52k Slices on a Virtex 5LX330T, 25% and 24% of resources, respectively. Using a 100-MHz clock, this build would perform stereo at 39 Hz. Of particular interest to JPL is that there is a flight qualified version of the Virtex 5: this could produce stereo results even for very large image sizes at 3 orders of magnitude faster than could be computed on the PowerPC 750 flight computer. The work covered in the report allows the stereo algorithm to run on much larger images than before, and using much less BRAM. This opens up choices for a smaller flight FPGA (which saves power and space), or for other algorithms in addition to SAD5 to be run on the same FPGA.

Rapid prototyping of SoC-based real-time vision system: application to image preprocessing and face detection

NASA Astrophysics Data System (ADS)

Jridi, Maher; Alfalou, Ayman

2017-05-01

By this paper, the major goal is to investigate the Multi-CPU/FPGA SoC (System on Chip) design flow and to transfer a know-how and skills to rapidly design embedded real-time vision system. Our aim is to show how the use of these devices can be benefit for system level integration since they make possible simultaneous hardware and software development. We take the facial detection and pretreatments as case study since they have a great potential to be used in several applications such as video surveillance, building access control and criminal identification. The designed system use the Xilinx Zedboard platform. The last is the central element of the developed vision system. The video acquisition is performed using either standard webcam connected to the Zedboard via USB interface or several camera IP devices. The visualization of video content and intermediate results are possible with HDMI interface connected to HD display. The treatments embedded in the system are as follow: (i) pre-processing such as edge detection implemented in the ARM and in the reconfigurable logic, (ii) software implementation of motion detection and face detection using either ViolaJones or LBP (Local Binary Pattern), and (iii) application layer to select processing application and to display results in a web page. One uniquely interesting feature of the proposed system is that two functions have been developed to transmit data from and to the VDMA port. With the proposed optimization, the hardware implementation of the Sobel filter takes 27 ms and 76 ms for 640x480, and 720p resolutions, respectively. Hence, with the FPGA implementation, an acceleration of 5 times is obtained which allow the processing of 37 fps and 13 fps for 640x480, and 720p resolutions, respectively.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lovell, Jack, E-mail: jack.lovell@durham.ac.uk; Culham Centre for Fusion Energy, Culham Science Centre, Abingdon, Oxon OX14 3DB; Naylor, Graham

A new resistive bolometer system has been developed for MAST-Upgrade. It will measure radiated power in the new Super-X divertor, with millisecond time resolution, along 16 vertical and 16 horizontal lines of sight. The system uses a Xilinx Zynq-7000 series Field-Programmable Gate Array (FPGA) in the D-TACQ ACQ2106 carrier to perform real time data acquisition and signal processing. The FPGA enables AC-synchronous detection using high performance digital filtering to achieve a high signal-to-noise ratio and will be able to output processed data in real time with millisecond latency. The system has been installed on 8 previously unused channels of themore » JET vertical bolometer system. Initial results suggest good agreement with data from existing vertical channels but with higher bandwidth and signal-to-noise ratio.« less

Programmable logic controller performance enhancement by field programmable gate array based design.

PubMed

Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

2015-01-01

PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported. Copyright © 2014 ISA. Published by Elsevier Ltd. All rights reserved.

Irradiation setup at the U-120M cyclotron facility

NASA Astrophysics Data System (ADS)

Křížek, F.; Ferencei, J.; Matlocha, T.; Pospíšil, J.; Príbeli, P.; Raskina, V.; Isakov, A.; Štursa, J.; Vaňát, T.; Vysoká, K.

2018-06-01

This paper describes parameters of the proton beams provided by the U-120M cyclotron and the related irradiation setup at the open access irradiation facility at the Nuclear Physics Institute of the Czech Academy of Sciences. The facility is suitable for testing radiation hardness of various electronic components. The use of the setup is illustrated by a measurement of an error rate for errors caused by Single Event Transients in an SRAM-based Xilinx XC3S200 FPGA. This measurement provides an estimate of a possible occurrence of Single Event Transients. Data suggest that the variation of error rate of the Single Event Effects for different clock phase shifts is not significant enough to use clock phase alignment with the beam as a fault mitigation technique.

Data transmission optical link for RF-GUN project

NASA Astrophysics Data System (ADS)

Olowski, Krzysztof; Zielinski, Jerzy; Jalmuzna, Wojciech; Pozniak, Krzysztof; Romaniuk, Ryszard

2005-09-01

Today, the fast optical data transmission is one of the fundamentals of modern distributed control systems. The fibers are widely use as multi-gigabit data stream medium. For a short range transmission, the multimode fibers are in common use. The data rate for this kind of transmission exceeds 10 Gbps for 10 Gigabit Ethernet and 10G Fibre Channel protocols. The Field Programmable Gate Arrays are one of the opportunities of managing the optical transmission. This article is concerning a synchronous optical transmission system via a multimode fiber. The transmission is controlled by the FPGA of two manufacturers: Xilinx and Altera. This paper contains the newest technology overview and market device parameters. It also describes a board for the optical transmission, technical details of the transmission and optical transmission results.

High speed fault tolerant secure communication for muon chamber using FPGA based GBTx emulator

NASA Astrophysics Data System (ADS)

Sau, Suman; Mandal, Swagata; Saini, Jogender; Chakrabarti, Amlan; Chattopadhyay, Subhasis

2015-12-01

The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at the GSI. The CBM experiment will investigate the highly compressed nuclear matter using nucleus-nucleus collisions. This experiment will examine lieavy-ion collisions in fixed target geometry and will be able to measure hadrons, electrons and muons. CBM requires precise time synchronization, compact hardware, radiation tolerance, self-triggered front-end electronics, efficient data aggregation schemes and capability to handle high data rate (up to several TB/s). As a part of the implementation of read out chain of Muon Cliamber(MUCH) [1] in India, we have tried to implement FPGA based emulator of GBTx in India. GBTx is a radiation tolerant ASIC that can be used to implement multipurpose high speed bidirectional optical links for high-energy physics (HEP) experiments and is developed by CERN. GBTx will be used in highly irradiated area and more prone to be affected by multi bit error. To mitigate this effect instead of single bit error correcting RS code we have used two bit error correcting (15, 7) BCH code. It will increase the redundancy which in turn increases the reliability of the coded data. So the coded data will be less prone to be affected by noise due to radiation. The data will go from detector to PC through multiple nodes through the communication channel. The computing resources are connected to a network which can be accessed by authorized person to prevent unauthorized data access which might happen by compromising the network security. Thus data encryption is essential. In order to make the data communication secure, advanced encryption standard [2] (AES - a symmetric key cryptography) and RSA [3], [4] (asymmetric key cryptography) are used after the channel coding. We have implemented GBTx emulator on two Xilinx Kintex-7 boards (KC705). One will act as transmitter and other will act as receiver and they are connected through optical fiber through small form-factor pluggable (SFP) port. We have tested the setup in the runtime environment using Xilinx Cliipscope Pro Analyzer. We also measure the resource utilization, throughput., power optimization of implemented design.

SPIDR, a general-purpose readout system for pixel ASICs

NASA Astrophysics Data System (ADS)

van der Heijden, B.; Visser, J.; van Beuzekom, M.; Boterenbrood, H.; Kulis, S.; Munneke, B.; Schreuder, F.

2017-02-01

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a "soft core" CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit Ethernet links, and in addition provides the slow and fast control for the chip.

Hardware-software face detection system based on multi-block local binary patterns

NASA Astrophysics Data System (ADS)

Acasandrei, Laurentiu; Barriga, Angel

2015-03-01

Face detection is an important aspect for biometrics, video surveillance and human computer interaction. Due to the complexity of the detection algorithms any face detection system requires a huge amount of computational and memory resources. In this communication an accelerated implementation of MB LBP face detection algorithm targeting low frequency, low memory and low power embedded system is presented. The resulted implementation is time deterministic and uses a customizable AMBA IP hardware accelerator. The IP implements the kernel operations of the MB-LBP algorithm and can be used as universal accelerator for MB LBP based applications. The IP employs 8 parallel MB-LBP feature evaluators cores, uses a deterministic bandwidth, has a low area profile and the power consumption is ~95 mW on a Virtex5 XC5VLX50T. The resulted implementation acceleration gain is between 5 to 8 times, while the hardware MB-LBP feature evaluation gain is between 69 and 139 times.

A new simple technique for improving the random properties of chaos-based cryptosystems

NASA Astrophysics Data System (ADS)

Garcia-Bosque, M.; Pérez-Resa, A.; Sánchez-Azqueta, C.; Celma, S.

2018-03-01

A new technique for improving the security of chaos-based stream ciphers has been proposed and tested experimentally. This technique manages to improve the randomness properties of the generated keystream by preventing the system to fall into short period cycles due to digitation. In order to test this technique, a stream cipher based on a Skew Tent Map algorithm has been implemented on a Virtex 7 FPGA. The randomness of the keystream generated by this system has been compared to the randomness of the keystream generated by the same system with the proposed randomness-enhancement technique. By subjecting both keystreams to the National Institute of Standards and Technology (NIST) tests, we have proved that our method can considerably improve the randomness of the generated keystreams. In order to incorporate our randomness-enhancement technique, only 41 extra slices have been needed, proving that, apart from effective, this method is also efficient in terms of area and hardware resources.

Implementation in an FPGA circuit of Edge detection algorithm based on the Discrete Wavelet Transforms

NASA Astrophysics Data System (ADS)

Bouganssa, Issam; Sbihi, Mohamed; Zaim, Mounia

2017-07-01

The 2D Discrete Wavelet Transform (DWT) is a computationally intensive task that is usually implemented on specific architectures in many imaging systems in real time. In this paper, a high throughput edge or contour detection algorithm is proposed based on the discrete wavelet transform. A technique for applying the filters on the three directions (Horizontal, Vertical and Diagonal) of the image is used to present the maximum of the existing contours. The proposed architectures were designed in VHDL and mapped to a Xilinx Sparten6 FPGA. The results of the synthesis show that the proposed architecture has a low area cost and can operate up to 100 MHz, which can perform 2D wavelet analysis for a sequence of images while maintaining the flexibility of the system to support an adaptive algorithm.

A minimal SATA III Host Controller based on FPGA

NASA Astrophysics Data System (ADS)

Liu, Hailiang

2018-03-01

SATA (Serial Advanced Technology Attachment) is an advanced serial bus which has a outstanding performance in transmitting high speed real-time data applied in Personal Computers, Financial Industry, astronautics and aeronautics, etc. In this express, a minimal SATA III Host Controller based on Xilinx Kintex 7 serial FPGA is designed and implemented. Compared to the state-of-art, registers utilization are reduced 25.3% and LUTs utilization are reduced 65.9%. According to the experimental results, the controller works precisely and steady with the reading bandwidth of up to 536 MB per second and the writing bandwidth of up to 512 MB per second, both of which are close to the maximum bandwidth of the SSD(Solid State Disk) device. The host controller is very suitable for high speed data transmission and mass data storage.

A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications.

PubMed

Revathy, M; Saravanan, R

2015-01-01

Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.

A radiation tolerant Data link board for the ATLAS Tile Cal upgrade

NASA Astrophysics Data System (ADS)

Åkerstedt, H.; Bohm, C.; Muschter, S.; Silverstein, S.; Valdes, E.

2016-01-01

This paper describes the latest, full-functionality revision of the high-speed data link board developed for the Phase-2 upgrade of ATLAS hadronic Tile Calorimeter. The link board design is highly redundant, with digital functionality implemented in two Xilinx Kintex-7 FPGAs, and two Molex QSFP+ electro-optic modules with uplinks run at 10 Gbps. The FPGAs are remotely configured through two radiation-hard CERN GBTx deserialisers (GBTx), which also provide the LHC-synchronous system clock. The redundant design eliminates virtually all single-point error modes, and a combination of triple-mode redundancy (TMR), internal and external scrubbing will provide adequate protection against radiation-induced errors. The small portion of the FPGA design that cannot be protected by TMR will be the dominant source of radiation-induced errors, even if that area is small.

An FPGA-based bolometer for the MAST-U Super-X divertor.

PubMed

Lovell, Jack; Naylor, Graham; Field, Anthony; Drewelow, Peter; Sharples, Ray

2016-11-01

A new resistive bolometer system has been developed for MAST-Upgrade. It will measure radiated power in the new Super-X divertor, with millisecond time resolution, along 16 vertical and 16 horizontal lines of sight. The system uses a Xilinx Zynq-7000 series Field-Programmable Gate Array (FPGA) in the D-TACQ ACQ2106 carrier to perform real time data acquisition and signal processing. The FPGA enables AC-synchronous detection using high performance digital filtering to achieve a high signal-to-noise ratio and will be able to output processed data in real time with millisecond latency. The system has been installed on 8 previously unused channels of the JET vertical bolometer system. Initial results suggest good agreement with data from existing vertical channels but with higher bandwidth and signal-to-noise ratio.

A new MicroTCA-based waveform digitizer for the Muon g-2 experiment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sweigart, David A.

We present the design of a newmore » $$\\mu$$TCA-based waveform digitizer, which will be deployed in the Muon g-2 experiment at Fermilab and will allow our pileup identification requirement to be met. This digitizer features five independent channels, each with 12-bit, 800-MSPS digitization and a 1-Gbit memory buffer. The data storage and readout along with configuration are handled by six Xilinx Kintex-7 FPGAs. In addition, the digitizer is equipped with a mezzanine card for analog signal conditioning prior to digitization, further widening its range of possible applications. The performance results of this design are also presented, highlighting its $$0.51 \\pm 0.13$$ mV intrinsic noise level and $< 22$ ps intrinsic timing resolution between channels. We believe that its performance, together with its flexible design, could be of interest to future experiments in search of a cost-effective waveform digitizer.« less

Design of CMOS imaging system based on FPGA

NASA Astrophysics Data System (ADS)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems.

PubMed

Park, Jongkil; Yu, Theodore; Joshi, Siddharth; Maier, Christoph; Cauwenberghs, Gert

2017-10-01

We present a hierarchical address-event routing (HiAER) architecture for scalable communication of neural and synaptic spike events between neuromorphic processors, implemented with five Xilinx Spartan-6 field-programmable gate arrays and four custom analog neuromophic integrated circuits serving 262k neurons and 262M synapses. The architecture extends the single-bus address-event representation protocol to a hierarchy of multiple nested buses, routing events across increasing scales of spatial distance. The HiAER protocol provides individually programmable axonal delay in addition to strength for each synapse, lending itself toward biologically plausible neural network architectures, and scales across a range of hierarchies suitable for multichip and multiboard systems in reconfigurable large-scale neuromorphic systems. We show approximately linear scaling of net global synaptic event throughput with number of routing nodes in the network, at 3.6×10 7 synaptic events per second per 16k-neuron node in the hierarchy.

A compact, smart Langmuir Probe control module for MAST-Upgrade

NASA Astrophysics Data System (ADS)

Lovell, J.; Stephen, R.; Bray, S.; Naylor, G.; Elmore, S.; Willett, H.; Peterka, M.; Dimitrova, M.; Havranek, A.; Hron, M.; Sharples, R.

2017-11-01

A new control module for the MAST-Upgrade Langmuir Probe system has been developed. It is based on a Xilinx Zynq FPGA, which allows for excellent configurability and ease of retrieving data. The module is capable of arbitrary bias voltage waveform generation, and digitises current and voltage readings from 16 probes. The probes are biased and measured one at a time in a time multiplexed fashion, with the multiplexing sequence completely configurable. In addition, simultaneous digitisation of the floating potential of all unbiased probes is possible. A suite of these modules, each coupled with a high voltage amplifier, enables biasing and digitisation of 640 Langmuir Probes in the MAST-Upgrade Super-X divertor. The system has been successfully tested on the York Linear Plasma Device and on the COMPASS tokamak. It will be installed on MAST-Upgrade ready for operations in 2018.

VLSI Technology for Cognitive Radio

NASA Astrophysics Data System (ADS)

VIJAYALAKSHMI, B.; SIDDAIAH, P.

2017-08-01

One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

An Embedded Reconfigurable Logic Module

NASA Technical Reports Server (NTRS)

Tucker, Jerry H.; Klenke, Robert H.; Shams, Qamar A. (Technical Monitor)

2002-01-01

A Miniature Embedded Reconfigurable Computer and Logic (MERCAL) module has been developed and verified. MERCAL was designed to be a general-purpose, universal module that that can provide significant hardware and software resources to meet the requirements of many of today's complex embedded applications. This is accomplished in the MERCAL module by combining a sub credit card size PC in a DIMM form factor with a XILINX Spartan I1 FPGA. The PC has the ability to download program files to the FPGA to configure it for different hardware functions and to transfer data to and from the FPGA via the PC's ISA bus during run time. The MERCAL module combines, in a compact package, the computational power of a 133 MHz PC with up to 150,000 gate equivalents of digital logic that can be reconfigured by software. The general architecture and functionality of the MERCAL hardware and system software are described.

A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications

PubMed Central

Revathy, M.; Saravanan, R.

2015-01-01

Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures. PMID:26065017

A low power, area efficient fpga based beamforming technique for 1-D CMUT arrays.

PubMed

Joseph, Bastin; Joseph, Jose; Vanjari, Siva Rama Krishna

2015-08-01

A low power area efficient digital beamformer targeting low frequency (2MHz) 1-D linear Capacitive Micromachined Ultrasonic Transducer (CMUT) array is developed. While designing the beamforming logic, the symmetry of the CMUT array is well exploited to reduce the area and power consumption. The proposed method is verified in Matlab by clocking an Arbitrary Waveform Generator(AWG). The architecture is successfully implemented in Xilinx Spartan 3E FPGA kit to check its functionality. The beamforming logic is implemented for 8, 16, 32, and 64 element CMUTs targeting Application Specific Integrated Circuit (ASIC) platform at Vdd 1.62V for UMC 90nm technology. It is observed that the proposed architecture consumes significantly lesser power and area (1.2895 mW power and 47134.4 μm(2) area for a 64 element digital beamforming circuit) compared to the conventional square root based algorithm.

Lifting Scheme DWT Implementation in a Wireless Vision Sensor Network

NASA Astrophysics Data System (ADS)

Ong, Jia Jan; Ang, L.-M.; Seng, K. P.

This paper presents the practical implementation of a Wireless Visual Sensor Network (WVSN) with DWT processing on the visual nodes. WVSN consists of visual nodes that capture video and transmit to the base-station without processing. Limitation of network bandwidth restrains the implementation of real time video streaming from remote visual nodes through wireless communication. Three layers of DWT filters are implemented to process the captured image from the camera. With having all the wavelet coefficients produced, it is possible just to transmit the low frequency band coefficients and obtain an approximate image at the base-station. This will reduce the amount of power required in transmission. When necessary, transmitting all the wavelet coefficients will produce the full detail of image, which is similar to the image captured at the visual nodes. The visual node combines the CMOS camera, Xilinx Spartan-3L FPGA and wireless ZigBee® network that uses the Ember EM250 chip.

Influence of radiation on metastability-based TRNG

NASA Astrophysics Data System (ADS)

Wieczorek, Piotr Z.; Wieczorek, Zbigniew

2017-08-01

This paper presents a True Random Number Generator (TRNG) based on Flip-Flops with violated timing constraints. The proposed circuit has been implemented in a Xilinx Spartan 6 device. The TRNG circuit utilizes the metastability phenomenon as a source of randomness. Therefore, in the paper the influence of timing constraints on the flip-flop metastability proximity is discussed. The metastable range of operation enhances the noise influence on a Flip-Flop behavior. Therefore, the influence of an external stochastic source on the flip-flop operation is also investigated. For this purpose a radioactive source of radiation was used. According to the results shown in the paper the radiation increases the unpredictability of the metastable process of flip-flops operating as the randomness source in the TRNG. The statistical properties of TRNG operating in an increased radiation conditions were verified with the NIST battery of statistical tests.

High-channel-count, high-density microelectrode array for closed-loop investigation of neuronal networks.

PubMed

Tsai, David; John, Esha; Chari, Tarun; Yuste, Rafael; Shepard, Kenneth

2015-01-01

We present a system for large-scale electrophysiological recording and stimulation of neural tissue with a planar topology. The recording system has 65,536 electrodes arranged in a 256 × 256 grid, with 25.5 μm pitch, and covering an area approximately 42.6 mm(2). The recording chain has 8.66 μV rms input-referred noise over a 100 ~ 10k Hz bandwidth while providing up to 66 dB of voltage gain. When recording from all electrodes in the array, it is capable of 10-kHz sampling per electrode. All electrodes can also perform patterned electrical microstimulation. The system produces ~ 1 GB/s of data when recording from the full array. To handle, store, and perform nearly real-time analyses of this large data stream, we developed a framework based around Xilinx FPGAs, Intel x86 CPUs and the NVIDIA Streaming Multiprocessors to interface with the electrode array.

FPGA Techniques Based New Hybrid Modulation Strategies for Voltage Source Inverters

PubMed Central

Sudha, L. U.; Baskaran, J.; Elankurisil, S. A.

2015-01-01

This paper corroborates three different hybrid modulation strategies suitable for single-phase voltage source inverter. The proposed method is formulated using fundamental switching and carrier based pulse width modulation methods. The main tale of this proposed method is to optimize a specific performance criterion, such as minimization of the total harmonic distortion (THD), lower order harmonics, switching losses, and heat losses. The proposed method is articulated using fundamental switching and carrier based pulse width modulation methods. Thus, the harmonic pollution in the power system will be reduced and the power quality will be augmented with better harmonic profile for a target fundamental output voltage. The proposed modulation strategies are simulated in MATLAB r2010a and implemented in a Xilinx spartan 3E-500 FG 320 FPGA processor. The feasibility of these modulation strategies is authenticated through simulation and experimental results. PMID:25821852

Facial emotion recognition system for autistic children: a feasible study based on FPGA implementation.

PubMed

Smitha, K G; Vinod, A P

2015-11-01

Children with autism spectrum disorder have difficulty in understanding the emotional and mental states from the facial expressions of the people they interact. The inability to understand other people's emotions will hinder their interpersonal communication. Though many facial emotion recognition algorithms have been proposed in the literature, they are mainly intended for processing by a personal computer, which limits their usability in on-the-move applications where portability is desired. The portability of the system will ensure ease of use and real-time emotion recognition and that will aid for immediate feedback while communicating with caretakers. Principal component analysis (PCA) has been identified as the least complex feature extraction algorithm to be implemented in hardware. In this paper, we present a detailed study of the implementation of serial and parallel implementation of PCA in order to identify the most feasible method for realization of a portable emotion detector for autistic children. The proposed emotion recognizer architectures are implemented on Virtex 7 XC7VX330T FFG1761-3 FPGA. We achieved 82.3% detection accuracy for a word length of 8 bits.

Smart Payload Development for High Data Rate Instrument Systems

NASA Technical Reports Server (NTRS)

Pingree, Paula J.; Norton, Charles D.

2007-01-01

This slide presentation reviews the development of smart payloads instruments systems with high data rates. On-board computation has become a bottleneck for advanced science instrument and engineering capabilities. In order to improve the computation capability on board, smart payloads have been proposed. A smart payload is a Localized instrument, that can offload the flight processor of extensive computing cycles, simplify the interfaces, and minimize the dependency of the instrument on the flight system. This has been proposed for the Mars mission, Mars Atmospheric Trace Molecule Spectroscopy (MATMOS). The design of this system is discussed; the features of the Virtex-4, are discussed, and the technical approach is reviewed. The proposed Hybrid Field Programmable Gate Array (FPGA) technology has been shown to deliver breakthrough performance by tightly coupling hardware and software. Smart Payload designs for instruments such as MATMOS can meet science data return requirements with more competitive use of available on-board resources and can provide algorithm acceleration in hardware leading to implementation of better (more advanced) algorithms in on-board systems for improved science data return

FPGA-based architecture for motion recovering in real-time

NASA Astrophysics Data System (ADS)

Arias-Estrada, Miguel; Maya-Rueda, Selene E.; Torres-Huitzil, Cesar

2002-03-01

A key problem in the computer vision field is the measurement of object motion in a scene. The main goal is to compute an approximation of the 3D motion from the analysis of an image sequence. Once computed, this information can be used as a basis to reach higher level goals in different applications. Motion estimation algorithms pose a significant computational load for the sequential processors limiting its use in practical applications. In this work we propose a hardware architecture for motion estimation in real time based on FPGA technology. The technique used for motion estimation is Optical Flow due to its accuracy, and the density of velocity estimation, however other techniques are being explored. The architecture is composed of parallel modules working in a pipeline scheme to reach high throughput rates near gigaflops. The modules are organized in a regular structure to provide a high degree of flexibility to cover different applications. Some results will be presented and the real-time performance will be discussed and analyzed. The architecture is prototyped in an FPGA board with a Virtex device interfaced to a digital imager.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge

The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memoriesmore » for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)« less

Design and implementation in VHDL code of the two-dimensional fast Fourier transform for frequency filtering, convolution and correlation operations

NASA Astrophysics Data System (ADS)

Vilardy, Juan M.; Giacometto, F.; Torres, C. O.; Mattos, L.

2011-01-01

The two-dimensional Fast Fourier Transform (FFT 2D) is an essential tool in the two-dimensional discrete signals analysis and processing, which allows developing a large number of applications. This article shows the description and synthesis in VHDL code of the FFT 2D with fixed point binary representation using the programming tool Simulink HDL Coder of Matlab; showing a quick and easy way to handle overflow, underflow and the creation registers, adders and multipliers of complex data in VHDL and as well as the generation of test bench for verification of the codes generated in the ModelSim tool. The main objective of development of the hardware architecture of the FFT 2D focuses on the subsequent completion of the following operations applied to images: frequency filtering, convolution and correlation. The description and synthesis of the hardware architecture uses the XC3S1200E family Spartan 3E FPGA from Xilinx Manufacturer.

Proposed hardware architectures of particle filter for object tracking

NASA Astrophysics Data System (ADS)

Abd El-Halym, Howida A.; Mahmoud, Imbaby Ismail; Habib, SED

2012-12-01

In this article, efficient hardware architectures for particle filter (PF) are presented. We propose three different architectures for Sequential Importance Resampling Filter (SIRF) implementation. The first architecture is a two-step sequential PF machine, where particle sampling, weight, and output calculations are carried out in parallel during the first step followed by sequential resampling in the second step. For the weight computation step, a piecewise linear function is used instead of the classical exponential function. This decreases the complexity of the architecture without degrading the results. The second architecture speeds up the resampling step via a parallel, rather than a serial, architecture. This second architecture targets a balance between hardware resources and the speed of operation. The third architecture implements the SIRF as a distributed PF composed of several processing elements and central unit. All the proposed architectures are captured using VHDL synthesized using Xilinx environment, and verified using the ModelSim simulator. Synthesis results confirmed the resource reduction and speed up advantages of our architectures.

Design of low noise imaging system

NASA Astrophysics Data System (ADS)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for low noise imaging system under the mode of global shutter, a complete imaging system is designed based on the SCMOS (Scientific CMOS) image sensor CIS2521F. The paper introduces hardware circuit and software system design. Based on the analysis of key indexes and technologies about the imaging system, the paper makes chips selection and decides SCMOS + FPGA+ DDRII+ Camera Link as processing architecture. Then it introduces the entire system workflow and power supply and distribution unit design. As for the software system, which consists of the SCMOS control module, image acquisition module, data cache control module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The imaging experimental results show that the imaging system exhibits a 2560*2160 pixel resolution, has a maximum frame frequency of 50 fps. The imaging quality of the system satisfies the requirement of the index.

Design and evaluation of online arithmetic for signal processing applications on FPGAs

NASA Astrophysics Data System (ADS)

Galli, Reto; Tenca, Alexandre F.

2001-11-01

This paper shows the design and the evaluation of on-line arithmetic modules for the most common operators used in DSP applications, using FPGAs as the target technology. The designs are highly optimized for the target technology and the common range of precision in DSP. The results are based on experimental data collected using CAD tools. All designs are synthesized for the same type of devices (Xilinx XC4000) for comparison, avoiding rough estimates of the system performance, and generating a more reliable and detailed comparison of on-line signal processing solutions with other state of the art approaches, such as distributed arithmetic. We show that on-line designs have a hard stand for basic DSP applications that use only addition and multiplication. However, we also show that on-line designs are able to overtake other approaches as the applications become more sophisticated, e.g. when data dependencies exist, or when non constant multiplicands restrict the use of other approaches.

Hardware Implementation of a MIMO Decoder Using Matrix Factorization Based Channel Estimation

NASA Astrophysics Data System (ADS)

Islam, Mohammad Tariqul; Numan, Mostafa Wasiuddin; Misran, Norbahiah; Ali, Mohd Alauddin Mohd; Singh, Mandeep

2011-05-01

This paper presents an efficient hardware realization of multiple-input multiple-output (MIMO) wireless communication decoder that utilizes the available resources by adopting the technique of parallelism. The hardware is designed and implemented on Xilinx Virtex™-4 XC4VLX60 field programmable gate arrays (FPGA) device in a modular approach which simplifies and eases hardware update, and facilitates testing of the various modules independently. The decoder involves a proficient channel estimation module that employs matrix factorization on least squares (LS) estimation to reduce a full rank matrix into a simpler form in order to eliminate matrix inversion. This results in performance improvement and complexity reduction of the MIMO system. Performance evaluation of the proposed method is validated through MATLAB simulations which indicate 2 dB improvement in terms of SNR compared to LS estimation. Moreover complexity comparison is performed in terms of mathematical operations, which shows that the proposed approach appreciably outperforms LS estimation at a lower complexity and represents a good solution for channel estimation technique.

Development of a modular test system for the silicon sensor R&D of the ATLAS Upgrade

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, H.; Benoit, M.; Chen, H.

High Voltage CMOS sensors are a promising technology for tracking detectors in collider experiments. Extensive R&D studies are being carried out by the ATLAS Collaboration for a possible use of HV-CMOS in the High Luminosity LHC upgrade of the Inner Tracker detector. CaRIBOu (Control and Readout Itk BOard) is a modular test system developed to test Silicon based detectors. It currently includes five custom designed boards, a Xilinx ZC706 development board, FELIX (Front-End LInk eXchange) PCIe card and a host computer. A software program has been developed in Python to control the CaRIBOu hardware. CaRIBOu has been used in themore » testbeam of the HV-CMOS sensor AMS180v4 at CERN. Preliminary results have shown that the test system is very versatile. In conclusion, further development is ongoing to adapt to different sensors, and to make it available to various lab test stands.« less

Development of a modular test system for the silicon sensor R&D of the ATLAS Upgrade

DOE PAGES

Liu, H.; Benoit, M.; Chen, H.; ...

2017-01-11

High Voltage CMOS sensors are a promising technology for tracking detectors in collider experiments. Extensive R&D studies are being carried out by the ATLAS Collaboration for a possible use of HV-CMOS in the High Luminosity LHC upgrade of the Inner Tracker detector. CaRIBOu (Control and Readout Itk BOard) is a modular test system developed to test Silicon based detectors. It currently includes five custom designed boards, a Xilinx ZC706 development board, FELIX (Front-End LInk eXchange) PCIe card and a host computer. A software program has been developed in Python to control the CaRIBOu hardware. CaRIBOu has been used in themore » testbeam of the HV-CMOS sensor AMS180v4 at CERN. Preliminary results have shown that the test system is very versatile. In conclusion, further development is ongoing to adapt to different sensors, and to make it available to various lab test stands.« less

Diversification of Processors Based on Redundancy in Instruction Set

NASA Astrophysics Data System (ADS)

Ichikawa, Shuichi; Sawada, Takashi; Hata, Hisashi

By diversifying processor architecture, computer software is expected to be more resistant to plagiarism, analysis, and attacks. This study presents a new method to diversify instruction set architecture (ISA) by utilizing the redundancy in the instruction set. Our method is particularly suited for embedded systems implemented with FPGA technology, and realizes a genuine instruction set randomization, which has not been provided by the preceding studies. The evaluation results on four typical ISAs indicate that our scheme can provide a far larger degree of freedom than the preceding studies. Diversified processors based on MIPS architecture were actually implemented and evaluated with Xilinx Spartan-3 FPGA. The increase of logic scale was modest: 5.1% in Specialized design and 3.6% in RAM-mapped design. The performance overhead was also modest: 3.4% in Specialized design and 11.6% in RAM-mapped design. From these results, our scheme is regarded as a practical and promising way to secure FPGA-based embedded systems.

Design of RISC Processor Using VHDL and Cadence

NASA Astrophysics Data System (ADS)

Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram

The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.

JPL Space Telecommunications Radio System Operating Environment

NASA Technical Reports Server (NTRS)

Lux, James P.; Lang, Minh; Peters, Kenneth J.; Taylor, Gregory H.; Duncan, Courtney B.; Orozco, David S.; Stern, Ryan A.; Ahten, Earl R.; Girard, Mike

2013-01-01

A flight-qualified implementation of a Software Defined Radio (SDR) Operating Environment for the JPL-SDR built for the CoNNeCT Project has been developed. It is compliant with the NASA Space Telecommunications Radio System (STRS) Architecture Standard, and provides the software infrastructure for STRS compliant waveform applications. This software provides a standards-compliant abstracted view of the JPL-SDR hardware platform. It uses industry standard POSIX interfaces for most functions, as well as exposing the STRS API (Application Programming In terface) required by the standard. This software includes a standardized interface for IP components instantiated within a Xilinx FPGA (Field Programmable Gate Array). The software provides a standardized abstracted interface to platform resources such as data converters, file system, etc., which can be used by STRS standards conformant waveform applications. It provides a generic SDR operating environment with a much smaller resource footprint than similar products such as SCA (Software Communications Architecture) compliant implementations, or the DoD Joint Tactical Radio Systems (JTRS).

Space and Time Partitioning with Hardware Support for Space Applications

NASA Astrophysics Data System (ADS)

Pinto, S.; Tavares, A.; Montenegro, S.

2016-08-01

Complex and critical systems like airplanes and spacecraft implement a very fast growing amount of functions. Typically, those systems were implemented with fully federated architectures, but the number and complexity of desired functions of todays systems led aerospace industry to follow another strategy. Integrated Modular Avionics (IMA) arose as an attractive approach for consolidation, by combining several applications into one single generic computing resource. Current approach goes towards higher integration provided by space and time partitioning (STP) of system virtualization. The problem is existent virtualization solutions are not ready to fully provide what the future of aerospace are demanding: performance, flexibility, safety, security while simultaneously containing Size, Weight, Power and Cost (SWaP-C).This work describes a real time hypervisor for space applications assisted by commercial off-the-shell (COTS) hardware. ARM TrustZone technology is exploited to implement a secure virtualization solution with low overhead and low memory footprint. This is demonstrated by running multiple guest partitions of RODOS operating system on a Xilinx Zynq platform.

A VLSI Implementation of Four-Phase Lift Controller Using Verilog HDL

NASA Astrophysics Data System (ADS)

Kumar, Manish; Singh, Priyanka; Singh, Shesha

2017-08-01

With the advent of an era of staggering range of new technologies to provide ease of mobility and transportation elevators have become an essential component of all high rise buildings. An elevator is a type of vertical transportation that moves people between the floors of a high rise building. A four-Phase lift controller modeled on Verilog HDL code using Finite State Machine (FSM) has been presented in this paper. Verilog HDL helps in automated analysis and simulation of lift controller circuit. This design is based on synchronous input that operates on a fixed frequency. The Lift motion is controlled by means of accepting the destination floor level as input and generate control signal as output. In the proposed design a Verilog RTL code is developed and verified. Project Navigator of XILINX has been used as a code writing platform and results were simulated using Modelsim 5.4a simulator. This paper discusses the overall evolution of design and also discusses simulated results.

AER synthetic generation in hardware for bio-inspired spiking systems

NASA Astrophysics Data System (ADS)

Linares-Barranco, Alejandro; Linares-Barranco, Bernabe; Jimenez-Moreno, Gabriel; Civit-Balcells, Anton

2005-06-01

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate 'events' according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems it is absolutely necessary to have a computer interface that allows (a) to read AER interchip traffic into the computer and visualize it on screen, and (b) convert conventional frame-based video stream in the computer into AER and inject it at some point of the AER structure. This is necessary for test and debugging of complex AER systems. This paper addresses the problem of converting, in a computer, a conventional frame-based video stream into the spike event based representation AER. There exist several proposed software methods for synthetic generation of AER for bio-inspired systems. This paper presents a hardware implementation for one method, which is based on Linear-Feedback-Shift-Register (LFSR) pseudo-random number generation. The sequence of events generated by this hardware, which follows a Poisson distribution like a biological neuron, has been reconstructed using two AER integrator cells. The error of reconstruction for a set of images that produces different traffic loads of event in the AER bus is used as evaluation criteria. A VHDL description of the method, that includes the Xilinx PCI Core, has been implemented and tested using a general purpose PCI-AER board. This PCI-AER board has been developed by authors, and uses a Spartan II 200 FPGA. This system for AER Synthetic Generation is capable of transforming frames of 64x64 pixels, received through a standard computer PCI bus, at a frame rate of 25 frames per second, producing spike events at a peak rate of 107 events per second.

FPGA implementation for real-time background subtraction based on Horprasert model.

PubMed

Rodriguez-Gomez, Rafael; Fernandez-Sanchez, Enrique J; Diaz, Javier; Ros, Eduardo

2012-01-01

Background subtraction is considered the first processing stage in video surveillance systems, and consists of determining objects in movement in a scene captured by a static camera. It is an intensive task with a high computational cost. This work proposes an embedded novel architecture on FPGA which is able to extract the background on resource-limited environments and offers low degradation (produced because of the hardware-friendly model modification). In addition, the original model is extended in order to detect shadows and improve the quality of the segmentation of the moving objects. We have analyzed the resource consumption and performance in Spartan3 Xilinx FPGAs and compared to others works available on the literature, showing that the current architecture is a good trade-off in terms of accuracy, performance and resources utilization. With less than a 65% of the resources utilization of a XC3SD3400 Spartan-3A low-cost family FPGA, the system achieves a frequency of 66.5 MHz reaching 32.8 fps with resolution 1,024 × 1,024 pixels, and an estimated power consumption of 5.76 W.

Efficient Implementation of a Symbol Timing Estimator for Broadband PLC.

PubMed

Nombela, Francisco; García, Enrique; Mateos, Raúl; Hernández, Álvaro

2015-08-21

Broadband Power Line Communications (PLC) have taken advantage of the research advances in multi-carrier modulations to mitigate frequency selective fading, and their adoption opens up a myriad of applications in the field of sensory and automation systems, multimedia connectivity or smart spaces. Nonetheless, the use of these multi-carrier modulations, such as Wavelet-OFDM, requires a highly accurate symbol timing estimation for reliably recovering of transmitted data. Furthermore, the PLC channel presents some particularities that prevent the direct use of previous synchronization algorithms proposed in wireless communication systems. Therefore more research effort should be involved in the design and implementation of novel and robust synchronization algorithms for PLC, thus enabling real-time synchronization. This paper proposes a symbol timing estimator for broadband PLC based on cross-correlation with multilevel complementary sequences or Zadoff-Chu sequences and its efficient implementation in a FPGA; the obtained results show a 90% of success rate in symbol timing estimation for a certain PLC channel model and a reduced resource consumption for its implementation in a Xilinx Kyntex FPGA.

Timing generator of scientific grade CCD camera and its implementation based on FPGA technology

NASA Astrophysics Data System (ADS)

Si, Guoliang; Li, Yunfei; Guo, Yongfei

2010-10-01

The Timing Generator's functions of Scientific Grade CCD Camera is briefly presented: it generates various kinds of impulse sequence for the TDI-CCD, video processor and imaging data output, acting as the synchronous coordinator for time in the CCD imaging unit. The IL-E2TDI-CCD sensor produced by DALSA Co.Ltd. use in the Scientific Grade CCD Camera. Driving schedules of IL-E2 TDI-CCD sensor has been examined in detail, the timing generator has been designed for Scientific Grade CCD Camera. FPGA is chosen as the hardware design platform, schedule generator is described with VHDL. The designed generator has been successfully fulfilled function simulation with EDA software and fitted into XC2VP20-FF1152 (a kind of FPGA products made by XILINX). The experiments indicate that the new method improves the integrated level of the system. The Scientific Grade CCD camera system's high reliability, stability and low power supply are achieved. At the same time, the period of design and experiment is sharply shorted.

A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather M; Graham, Paul S; Morgan, Keith S

2008-01-01

Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA usermore » designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.« less

The RTE inversion on FPGA aboard the solar orbiter PHI instrument

NASA Astrophysics Data System (ADS)

Cobos Carrascosa, J. P.; Aparicio del Moral, B.; Ramos Mas, J. L.; Balaguer, M.; López Jiménez, A. C.; del Toro Iniesta, J. C.

2016-07-01

In this work we propose a multiprocessor architecture to reach high performance in floating point operations by using radiation tolerant FPGA devices, and under narrow time and power constraints. This architecture is used in the PHI instrument that carries out the scientific analysis aboard the ESA's Solar Orbiter mission. The proposed architecture, in a SIMD flavor, is aimed to be an accelerator within the Data Processing Unit (it is composed by a main Leon processor and two FPGAs) for carrying out the RTE inversion on board the spacecraft using a relatively slow FPGA device - Xilinx XQR4VSX55-. The proposed architecture squeezes the FPGA resources in order to reach the computational requirements and improves the ground-based system performance based on commercial CPUs regarding time and power consumption. In this work we demonstrate the feasibility of using this FPGA devices embedded in the SO/PHI instrument. With that goal in mind, we perform tests to evaluate the scientific results and to measure the processing time and power consumption for carrying out the RTE inversion.

Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks

PubMed Central

Castillo, Encarnación; López-Ramos, Juan A.; Morales, Diego P.

2018-01-01

Security is a critical challenge for the effective expansion of all new emerging applications in the Internet of Things paradigm. Therefore, it is necessary to define and implement different mechanisms for guaranteeing security and privacy of data interchanged within the multiple wireless sensor networks being part of the Internet of Things. However, in this context, low power and low area are required, limiting the resources available for security and thus hindering the implementation of adequate security protocols. Group keys can save resources and communications bandwidth, but should be combined with public key cryptography to be really secure. In this paper, a compact and unified co-processor for enabling Elliptic Curve Cryptography along to Advanced Encryption Standard with low area requirements and Group-Key support is presented. The designed co-processor allows securing wireless sensor networks with independence of the communications protocols used. With an area occupancy of only 2101 LUTs over Spartan 6 devices from Xilinx, it requires 15% less area while achieving near 490% better performance when compared to cryptoprocessors with similar features in the literature. PMID:29337921

Intelligent FPGA Data Acquisition Framework

NASA Astrophysics Data System (ADS)

Bai, Yunpeng; Gaisbauer, Dominic; Huber, Stefan; Konorov, Igor; Levit, Dmytro; Steffen, Dominik; Paul, Stephan

2017-06-01

In this paper, we present the field programmable gate arrays (FPGA)-based framework intelligent FPGA data acquisition (IFDAQ), which is used for the development of DAQ systems for detectors in high-energy physics. The framework supports Xilinx FPGA and provides a collection of IP cores written in very high speed integrated circuit hardware description language, which use the common interconnect interface. The IP core library offers functionality required for the development of the full DAQ chain. The library consists of Serializer/Deserializer (SERDES)-based time-to-digital conversion channels, an interface to a multichannel 80-MS/s 10-b analog-digital conversion, data transmission, and synchronization protocol between FPGAs, event builder, and slow control. The functionality is distributed among FPGA modules built in the AMC form factor: front end and data concentrator. This modular design also helps to scale and adapt the DAQ system to the needs of the particular experiment. The first application of the IFDAQ framework is the upgrade of the read-out electronics for the drift chambers and the electromagnetic calorimeters (ECALs) of the COMPASS experiment at CERN. The framework will be presented and discussed in the context of this paper.

Implementation of a high precision multi-measurement time-to-digital convertor on a Kintex-7 FPGA

NASA Astrophysics Data System (ADS)

Kuang, Jie; Wang, Yonggang; Cao, Qiang; Liu, Chong

2018-05-01

Time-to-digital convertors (TDCs) based on field programmable gate array (FPGA) are becoming more and more popular. Multi-measurement is an effective method to improve TDC precision beyond the cell delay limitation. However, the implementation of TDC with multi-measurement on FPGAs manufactured with 28 nm and more advanced process is facing new challenges. Benefiting from the ones-counter encoding scheme, which was developed in our previous work, we implement a ring oscillator multi-measurement TDC on a Xilinx Kintex-7 FPGA. Using the two TDC channels to measure time-intervals in the range (0 ns-30 ns), the average RMS precision can be improved to 5.76 ps, meanwhile the logic resource usage remains the same with the one-measurement TDC, and the TDC dead time is only 22 ns. The investigation demonstrates that the multi-measurement methods are still available for current main-stream FPGAs. Furthermore, the new implementation in this paper could make the trade-off among the time precision, resource usage and TDC dead time better than ever before.

A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

NASA Astrophysics Data System (ADS)

Chen, Yuan-Ho

2017-05-01

In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [-0.54, 0.24] and [-0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks.

PubMed

Parrilla, Luis; Castillo, Encarnación; López-Ramos, Juan A; Álvarez-Bermejo, José A; García, Antonio; Morales, Diego P

2018-01-16

Security is a critical challenge for the effective expansion of all new emerging applications in the Internet of Things paradigm. Therefore, it is necessary to define and implement different mechanisms for guaranteeing security and privacy of data interchanged within the multiple wireless sensor networks being part of the Internet of Things. However, in this context, low power and low area are required, limiting the resources available for security and thus hindering the implementation of adequate security protocols. Group keys can save resources and communications bandwidth, but should be combined with public key cryptography to be really secure. In this paper, a compact and unified co-processor for enabling Elliptic Curve Cryptography along to Advanced Encryption Standard with low area requirements and Group-Key support is presented. The designed co-processor allows securing wireless sensor networks with independence of the communications protocols used. With an area occupancy of only 2101 LUTs over Spartan 6 devices from Xilinx, it requires 15% less area while achieving near 490% better performance when compared to cryptoprocessors with similar features in the literature.

Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems

PubMed Central

Atoche, Alejandro Castillo; Castillo, Javier Vázquez

2012-01-01

A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also conceptualized as another SA in a bit-level fashion. In this study, we addressed the design of a high-speed dual super-systolic array (SSA) core for the enhancement/reconstruction of remote sensing (RS) imaging of radar/synthetic aperture radar (SAR) sensor systems. The selected reconstructive SP algorithms are efficiently transformed in their parallel representation and then, they are mapped into an efficient high performance embedded computing (HPEC) architecture in reconfigurable Xilinx field programmable gate array (FPGA) platforms. As an implementation test case, the proposed approach was aggregated in a HW/SW co-design scheme in order to solve the nonlinear ill-posed inverse problem of nonparametric estimation of the power spatial spectrum pattern (SSP) from a remotely sensed scene. We show how such dual SSA core, drastically reduces the computational load of complex RS regularization techniques achieving the required real-time operational mode. PMID:22736964

Development of an embedded atmospheric turbulence mitigation engine

NASA Astrophysics Data System (ADS)

Paolini, Aaron; Bonnett, James; Kozacik, Stephen; Kelmelis, Eric

2017-05-01

Methods to reconstruct pictures from imagery degraded by atmospheric turbulence have been under development for decades. The techniques were initially developed for observing astronomical phenomena from the Earth's surface, but have more recently been modified for ground and air surveillance scenarios. Such applications can impose significant constraints on deployment options because they both increase the computational complexity of the algorithms themselves and often dictate a requirement for low size, weight, and power (SWaP) form factors. Consequently, embedded implementations must be developed that can perform the necessary computations on low-SWaP platforms. Fortunately, there is an emerging class of embedded processors driven by the mobile and ubiquitous computing industries. We have leveraged these processors to develop embedded versions of the core atmospheric correction engine found in our ATCOM software. In this paper, we will present our experience adapting our algorithms for embedded systems on a chip (SoCs), namely the NVIDIA Tegra that couples general-purpose ARM cores with their graphics processing unit (GPU) technology and the Xilinx Zynq which pairs similar ARM cores with their field-programmable gate array (FPGA) fabric.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hayes, T.; Smith, K.S.; Severino, F.

A critical capability of the new RHIC low level rf (LLRF) system is the ability to synchronize signals across multiple locations. The 'Update Link' provides this functionality. The 'Update Link' is a deterministic serial data link based on the Xilinx RocketIO protocol that is broadcast over fiber optic cable at 1 gigabit per second (Gbps). The link provides timing events and data packets as well as time stamp information for synchronizing diagnostic data from multiple sources. The new RHIC LLRF was designed to be a flexible, modular system. The system is constructed of numerous independent RF Controller chassis. To providemore » synchronization among all of these chassis, the Update Link system was designed. The Update Link system provides a low latency, deterministic data path to broadcast information to all receivers in the system. The Update Link system is based on a central hub, the Update Link Master (ULM), which generates the data stream that is distributed via fiber optic links. Downstream chassis have non-deterministic connections back to the ULM that allow any chassis to provide data that is broadcast globally.« less

Modular design and implementation of field-programmable-gate-array-based Gaussian noise generator

NASA Astrophysics Data System (ADS)

Li, Yuan-Ping; Lee, Ta-Sung; Hwang, Jeng-Kuang

2016-05-01

The modular design of a Gaussian noise generator (GNG) based on field-programmable gate array (FPGA) technology was studied. A new range reduction architecture was included in a series of elementary function evaluation modules and was integrated into the GNG system. The approximation and quantisation errors for the square root module with a first polynomial approximation were high; therefore, we used the central limit theorem (CLT) to improve the noise quality. This resulted in an output rate of one sample per clock cycle. We subsequently applied Newton's method for the square root module, thus eliminating the need for the use of the CLT because applying the CLT resulted in an output rate of two samples per clock cycle (>200 million samples per second). Two statistical tests confirmed that our GNG is of high quality. Furthermore, the range reduction, which is used to solve a limited interval of the function approximation algorithms of the System Generator platform using Xilinx FPGAs, appeared to have a higher numerical accuracy, was operated at >350 MHz, and can be suitably applied for any function evaluation.

FPGA Implementation for Real-Time Background Subtraction Based on Horprasert Model

PubMed Central

Rodriguez-Gomez, Rafael; Fernandez-Sanchez, Enrique J.; Diaz, Javier; Ros, Eduardo

2012-01-01

Background subtraction is considered the first processing stage in video surveillance systems, and consists of determining objects in movement in a scene captured by a static camera. It is an intensive task with a high computational cost. This work proposes an embedded novel architecture on FPGA which is able to extract the background on resource-limited environments and offers low degradation (produced because of the hardware-friendly model modification). In addition, the original model is extended in order to detect shadows and improve the quality of the segmentation of the moving objects. We have analyzed the resource consumption and performance in Spartan3 Xilinx FPGAs and compared to others works available on the literature, showing that the current architecture is a good trade-off in terms of accuracy, performance and resources utilization. With less than a 65% of the resources utilization of a XC3SD3400 Spartan-3A low-cost family FPGA, the system achieves a frequency of 66.5 MHz reaching 32.8 fps with resolution 1,024 × 1,024 pixels, and an estimated power consumption of 5.76 W. PMID:22368487

Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm

NASA Astrophysics Data System (ADS)

Azimi, Ehsan; Behrad, Alireza; Ghaznavi-Ghoushchi, Mohammad Bagher; Shanbehzadeh, Jamshid

2016-11-01

The projective model is an important mapping function for the calculation of global transformation between two images. However, its hardware implementation is challenging because of a large number of coefficients with different required precisions for fixed point representation. A VLSI hardware architecture is proposed for the calculation of a global projective model between input and reference images and refining false matches using random sample consensus (RANSAC) algorithm. To make the hardware implementation feasible, it is proved that the calculation of the projective model can be divided into four submodels comprising two translations, an affine model and a simpler projective mapping. This approach makes the hardware implementation feasible and considerably reduces the required number of bits for fixed point representation of model coefficients and intermediate variables. The proposed hardware architecture for the calculation of a global projective model using the RANSAC algorithm was implemented using Verilog hardware description language and the functionality of the design was validated through several experiments. The proposed architecture was synthesized by using an application-specific integrated circuit digital design flow utilizing 180-nm CMOS technology as well as a Virtex-6 field programmable gate array. Experimental results confirm the efficiency of the proposed hardware architecture in comparison with software implementation.

FPGA Implementation of Stereo Disparity with High Throughput for Mobility Applications

NASA Technical Reports Server (NTRS)

Villalpando, Carlos Y.; Morfopolous, Arin; Matthies, Larry; Goldberg, Steven

2011-01-01

High speed stereo vision can allow unmanned robotic systems to navigate safely in unstructured terrain, but the computational cost can exceed the capacity of typical embedded CPUs. In this paper, we describe an end-to-end stereo computation co-processing system optimized for fast throughput that has been implemented on a single Virtex 4 LX160 FPGA. This system is capable of operating on images from a 1024 x 768 3CCD (true RGB) camera pair at 15 Hz. Data enters the FPGA directly from the cameras via Camera Link and is rectified, pre-filtered and converted into a disparity image all within the FPGA, incurring no CPU load. Once complete, a rectified image and the final disparity image are read out over the PCI bus, for a bandwidth cost of 68 MB/sec. Within the FPGA there are 4 distinct algorithms: Camera Link capture, Bilinear rectification, Bilateral subtraction pre-filtering and the Sum of Absolute Difference (SAD) disparity. Each module will be described in brief along with the data flow and control logic for the system. The system has been successfully fielded upon the Carnegie Mellon University's National Robotics Engineering Center (NREC) Crusher system during extensive field trials in 2007 and 2008 and is being implemented for other surface mobility systems at JPL.

Multi-DSP and FPGA based Multi-channel Direct IF/RF Digital receiver for atmospheric radar

NASA Astrophysics Data System (ADS)

Yasodha, Polisetti; Jayaraman, Achuthan; Kamaraj, Pandian; Durga rao, Meka; Thriveni, A.

2016-07-01

Modern phased array radars depend highly on digital signal processing (DSP) to extract the echo signal information and to accomplish reliability along with programmability and flexibility. The advent of ASIC technology has made various digital signal processing steps to be realized in one DSP chip, which can be programmed as per the application and can handle high data rates, to be used in the radar receiver to process the received signal. Further, recent days field programmable gate array (FPGA) chips, which can be re-programmed, also present an opportunity to utilize them to process the radar signal. A multi-channel direct IF/RF digital receiver (MCDRx) is developed at NARL, taking the advantage of high speed ADCs and high performance DSP chips/FPGAs, to be used for atmospheric radars working in HF/VHF bands. Multiple channels facilitate the radar t be operated in multi-receiver modes and also to obtain the wind vector with improved time resolution, without switching the antenna beam. MCDRx has six channels, implemented on a custom built digital board, which is realized using six numbers of ADCs for simultaneous processing of the six input signals, Xilinx vertex5 FPGA and Spartan6 FPGA, and two ADSPTS201 DSP chips, each of which performs one phase of processing. MCDRx unit interfaces with the data storage/display computer via two gigabit ethernet (GbE) links. One of the six channels is used for Doppler beam swinging (DBS) mode and the other five channels are used for multi-receiver mode operations, dedicatedly. Each channel has (i) ADC block, to digitize RF/IF signal, (ii) DDC block for digital down conversion of the digitized signal, (iii) decoding block to decode the phase coded signal, and (iv) coherent integration block for integrating the data preserving phase intact. ADC block consists of Analog devices make AD9467 16-bit ADCs, to digitize the input signal at 80 MSPS. The output of ADC is centered around (80 MHz - input frequency). The digitized data is fed to DDC block, which down converts the data to base-band. The DDC block has NCO, mixer and two chains of Bessel filters (fifth order cascaded integration comb filter, two FIR filters, two half band filters and programmable FIR filters) for in-phase (I) and Quadrature phase (Q) channels. The NCO has 32 bits and is set to match the output frequency of ADC. Further, DDC down samples (decimation) the data and reduces the data rate to 16 MSPS. This data is further decimated and the data rate is reduced down to 4/2/1/0.5/0.25/0.125/0.0625 MSPS for baud lengths 0.25/0.5/1/2/4/8/16 μs respectively. The down sampled data is then fed to decoding block, which performs cross correlation to achieve pulse compression of the binary-phase coded data to obtain better range resolution with maximum possible height coverage. This step improves the signal power by a factor equal to the length of the code. Coherent integration block integrates the decoded data coherently for successive pulses, which improves the signal to noise ratio and reduces the data volume. DDC, decoding and coherent integration blocks are implemented in Xilinx vertex5 FPGA. Till this point, function of all six channels is same for DBS mode and multi-receiver modes. Data from vertex5 FPGA is transferred to PC via GbE-1 interface for multi-modes or to two Analog devices make ADSP-TS201 DSP chips (A and B), via link port for DBS mode. ADSP-TS201 chips perform the normalization, DC removal, windowing, FFT computation and spectral averaging on the data, which is transferred to storage/display PC via GbE-2 interface for real-time data display and data storing. Physical layer of GbE interface is implemented in an external chip (Marvel 88E1111) and MAC layer is implemented internal to vertex5 FPGA. The MCDRx has total 4 GB of DDR2 memory for data storage. Spartan6 FPGA is used for generating timing signals, required for basic operation of the radar and testing of the MCDRx.

Code generator for implementing dual tree complex wavelet transform on reconfigurable architectures for mobile applications

PubMed Central

Canbay, Ferhat; Levent, Vecdi Emre; Serbes, Gorkem; Ugurdag, H. Fatih; Goren, Sezer

2016-01-01

The authors aimed to develop an application for producing different architectures to implement dual tree complex wavelet transform (DTCWT) having near shift-invariance property. To obtain a low-cost and portable solution for implementing the DTCWT in multi-channel real-time applications, various embedded-system approaches are realised. For comparison, the DTCWT was implemented in C language on a personal computer and on a PIC microcontroller. However, in the former approach portability and in the latter desired speed performance properties cannot be achieved. Hence, implementation of the DTCWT on a reconfigurable platform such as field programmable gate array, which provides portable, low-cost, low-power, and high-performance computing, is considered as the most feasible solution. At first, they used the system generator DSP design tool of Xilinx for algorithm design. However, the design implemented by using such tools is not optimised in terms of area and power. To overcome all these drawbacks mentioned above, they implemented the DTCWT algorithm by using Verilog Hardware Description Language, which has its own difficulties. To overcome these difficulties, simplify the usage of proposed algorithms and the adaptation procedures, a code generator program that can produce different architectures is proposed. PMID:27733925

Design and implementation of a high performance network security processor

NASA Astrophysics Data System (ADS)

Wang, Haixin; Bai, Guoqiang; Chen, Hongyi

2010-03-01

The last few years have seen many significant progresses in the field of application-specific processors. One example is network security processors (NSPs) that perform various cryptographic operations specified by network security protocols and help to offload the computation intensive burdens from network processors (NPs). This article presents a high performance NSP system architecture implementation intended for both internet protocol security (IPSec) and secure socket layer (SSL) protocol acceleration, which are widely employed in virtual private network (VPN) and e-commerce applications. The efficient dual one-way pipelined data transfer skeleton and optimised integration scheme of the heterogenous parallel crypto engine arrays lead to a Gbps rate NSP, which is programmable with domain specific descriptor-based instructions. The descriptor-based control flow fragments large data packets and distributes them to the crypto engine arrays, which fully utilises the parallel computation resources and improves the overall system data throughput. A prototyping platform for this NSP design is implemented with a Xilinx XC3S5000 based FPGA chip set. Results show that the design gives a peak throughput for the IPSec ESP tunnel mode of 2.85 Gbps with over 2100 full SSL handshakes per second at a clock rate of 95 MHz.

Theory and implementation of a very high throughput true random number generator in field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Yonggang, E-mail: wangyg@ustc.edu.cn; Hui, Cong; Liu, Chong

The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving,more » so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.« less

Theory and implementation of a very high throughput true random number generator in field programmable gate array.

PubMed

Wang, Yonggang; Hui, Cong; Liu, Chong; Xu, Chao

2016-04-01

The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.

Code generator for implementing dual tree complex wavelet transform on reconfigurable architectures for mobile applications.

PubMed

Canbay, Ferhat; Levent, Vecdi Emre; Serbes, Gorkem; Ugurdag, H Fatih; Goren, Sezer; Aydin, Nizamettin

2016-09-01

The authors aimed to develop an application for producing different architectures to implement dual tree complex wavelet transform (DTCWT) having near shift-invariance property. To obtain a low-cost and portable solution for implementing the DTCWT in multi-channel real-time applications, various embedded-system approaches are realised. For comparison, the DTCWT was implemented in C language on a personal computer and on a PIC microcontroller. However, in the former approach portability and in the latter desired speed performance properties cannot be achieved. Hence, implementation of the DTCWT on a reconfigurable platform such as field programmable gate array, which provides portable, low-cost, low-power, and high-performance computing, is considered as the most feasible solution. At first, they used the system generator DSP design tool of Xilinx for algorithm design. However, the design implemented by using such tools is not optimised in terms of area and power. To overcome all these drawbacks mentioned above, they implemented the DTCWT algorithm by using Verilog Hardware Description Language, which has its own difficulties. To overcome these difficulties, simplify the usage of proposed algorithms and the adaptation procedures, a code generator program that can produce different architectures is proposed.

Embedded Streaming Deep Neural Networks Accelerator With Applications.

PubMed

Dundar, Aysegul; Jin, Jonghoon; Martini, Berin; Culurciello, Eugenio

2017-07-01

Deep convolutional neural networks (DCNNs) have become a very powerful tool in visual perception. DCNNs have applications in autonomous robots, security systems, mobile phones, and automobiles, where high throughput of the feedforward evaluation phase and power efficiency are important. Because of this increased usage, many field-programmable gate array (FPGA)-based accelerators have been proposed. In this paper, we present an optimized streaming method for DCNNs' hardware accelerator on an embedded platform. The streaming method acts as a compiler, transforming a high-level representation of DCNNs into operation codes to execute applications in a hardware accelerator. The proposed method utilizes maximum computational resources available based on a novel-scheduled routing topology that combines data reuse and data concatenation. It is tested with a hardware accelerator implemented on the Xilinx Kintex-7 XC7K325T FPGA. The system fully explores weight-level and node-level parallelizations of DCNNs and achieves a peak performance of 247 G-ops while consuming less than 4 W of power. We test our system with applications on object classification and object detection in real-world scenarios. Our results indicate high-performance efficiency, outperforming all other presented platforms while running these applications.

An FPGA-Based Silicon Neuronal Network with Selectable Excitability Silicon Neurons

PubMed Central

Li, Jing; Katori, Yuichi; Kohno, Takashi

2012-01-01

This paper presents a digital silicon neuronal network which simulates the nerve system in creatures and has the ability to execute intelligent tasks, such as associative memory. Two essential elements, the mathematical-structure-based digital spiking silicon neuron (DSSN) and the transmitter release based silicon synapse, allow us to tune the excitability of silicon neurons and are computationally efficient for hardware implementation. We adopt mixed pipeline and parallel structure and shift operations to design a sufficient large and complex network without excessive hardware resource cost. The network with 256 full-connected neurons is built on a Digilent Atlys board equipped with a Xilinx Spartan-6 LX45 FPGA. Besides, a memory control block and USB control block are designed to accomplish the task of data communication between the network and the host PC. This paper also describes the mechanism of associative memory performed in the silicon neuronal network. The network is capable of retrieving stored patterns if the inputs contain enough information of them. The retrieving probability increases with the similarity between the input and the stored pattern increasing. Synchronization of neurons is observed when the successful stored pattern retrieval occurs. PMID:23269911

LDPC decoder with a limited-precision FPGA-based floating-point multiplication coprocessor

NASA Astrophysics Data System (ADS)

Moberly, Raymond; O'Sullivan, Michael; Waheed, Khurram

2007-09-01

Implementing the sum-product algorithm, in an FPGA with an embedded processor, invites us to consider a tradeoff between computational precision and computational speed. The algorithm, known outside of the signal processing community as Pearl's belief propagation, is used for iterative soft-decision decoding of LDPC codes. We determined the feasibility of a coprocessor that will perform product computations. Our FPGA-based coprocessor (design) performs computer algebra with significantly less precision than the standard (e.g. integer, floating-point) operations of general purpose processors. Using synthesis, targeting a 3,168 LUT Xilinx FPGA, we show that key components of a decoder are feasible and that the full single-precision decoder could be constructed using a larger part. Soft-decision decoding by the iterative belief propagation algorithm is impacted both positively and negatively by a reduction in the precision of the computation. Reducing precision reduces the coding gain, but the limited-precision computation can operate faster. A proposed solution offers custom logic to perform computations with less precision, yet uses the floating-point format to interface with the software. Simulation results show the achievable coding gain. Synthesis results help theorize the the full capacity and performance of an FPGA-based coprocessor.

Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing

PubMed Central

Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L.; Espinosa, Felipe; García, Jorge

2011-01-01

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

Subnanosecond time-to-digital converter implemented in a Kintex-7 FPGA

NASA Astrophysics Data System (ADS)

Sano, Y.; Horii, Y.; Ikeno, M.; Sasaki, O.; Tomoto, M.; Uchida, T.

2017-12-01

Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful to cope with the changes in the experimental conditions. Recent FPGAs make it possible to implement TDCs with a time resolution less than 10 ps. On the other hand, various drift chambers require a time resolution of O(0.1) ns, and a simple and easy-to-implement TDC is useful for a robust operation. Herein an eight-channel TDC with a variable bin size down to 0.28 ns is implemented in a Xilinx Kintex-7 FPGA and tested. The TDC is based on a multisampling scheme with quad phase clocks synchronised with an external reference clock. Calibration of the bin size is unnecessary if a stable reference clock is available, which is common in high-energy physics experiments. Depending on the channel, the standard deviation of the differential nonlinearity for a 0.28 ns bin size is 0.13-0.31. The performance has a negligible dependence on the temperature. The power consumption and the potential to extend the number of channels are also discussed.

A 256-channel, high throughput and precision time-to-digital converter with a decomposition encoding scheme in a Kintex-7 FPGA

NASA Astrophysics Data System (ADS)

Song, Z.; Wang, Y.; Kuang, J.

2018-05-01

Field Programmable Gate Arrays (FPGAs) made with 28 nm and more advanced process technology have great potentials for implementation of high precision time-to-digital convertors (TDC), because the delay cells in the tapped delay line (TDL) used for time interpolation are getting smaller and smaller. However, the bubble problems in the TDL status are becoming more complicated, which make it difficult to achieve TDCs on these chips with a high time precision. In this paper, we are proposing a novel decomposition encoding scheme, which not only can solve the bubble problem easily, but also has a high encoding efficiency. The potential of these chips to realize TDC can be fully released with the scheme. In a Xilinx Kintex-7 FPGA chip, we implemented a TDC system with 256 TDC channels, which doubles the number of TDC channels that our previous technique could achieve. Performances of all these TDC channels are evaluated. The average RMS time precision among them is 10.23 ps in the time-interval measurement range of (0–10 ns), and their measurement throughput reaches 277 M measures per second.

System-on-chip architecture and validation for real-time transceiver optimization: APC implementation on FPGA

NASA Astrophysics Data System (ADS)

Suarez, Hernan; Zhang, Yan R.

2015-05-01

New radar applications need to perform complex algorithms and process large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression for real-time transceiver optimization are presented, they are based on a System-on-Chip architecture for Xilinx devices. This study also evaluates the performance of dedicated coprocessor as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through the high performance AXI buses, to perform floating-point operations, control the processing blocks, and communicate with external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band tested together with a low-cost channel emulator for different types of waveforms.

Implementation of four layer automatic elevator controller

NASA Astrophysics Data System (ADS)

Prasad, B. K. V.; Kumar, P. Satish; Charles, B. S.; Srilakshmi, G.

2017-07-01

In this modern era, elevators have become an integral part of any commercial or public complex. It facilitates the faster movement of people and luggage between floors. The lift control system is one among the keenest aspects in electronics controlling module that are used in auto motive filed. Usually elevators are designed for a specific building taking into account the main factors like the measure of the building, the count of persons travelling to each floor and the expected periods of large usage. The lift system was designed with different control strategies. This implementation is based on FPGA, which could be used for any building with any number of floors, with the necessary inputs and outputs. This controller can be implemented based on the required number of floors by merely changing a control variable from the HDL code. This approach is based on an algorithm which reduces the number of computation necessary, on concentrating only on the relevant principles that improves the score and ability of the club of elevator structure. The elevator controller is developed using Verilog HDL and is perfectly executed on a Xilinx ISE 12.4 and Spartan -3E FPGA.

L1 track trigger for the CMS HL-LHC upgrade using AM chips and FPGAs

NASA Astrophysics Data System (ADS)

Fedi, Giacomo

2017-08-01

The increase of luminosity at the HL-LHC will require the introduction of tracker information in CMS's Level-1 trigger system to maintain an acceptable trigger rate when selecting interesting events, despite the order of magnitude increase in minimum bias interactions. To meet the latency requirements, dedicated hardware has to be used. This paper presents the results of tests of a prototype system (pattern recognition ezzanine) as core of pattern recognition and track fitting for the CMS experiment, combining the power of both associative memory custom ASICs and modern Field Programmable Gate Array (FPGA) devices. The mezzanine uses the latest available associative memory devices (AM06) and the most modern Xilinx Ultrascale FPGAs. The results of the test for a complete tower comprising about 0.5 million patterns is presented, using as simulated input events traversing the upgraded CMS detector. The paper shows the performance of the pattern matching, track finding and track fitting, along with the latency and processing time needed. The pT resolution over pT of the muons measured using the reconstruction algorithm is at the order of 1% in the range 3-100 GeV/c.

Full image-processing pipeline in field-programmable gate array for a small endoscopic camera

NASA Astrophysics Data System (ADS)

Mostafa, Sheikh Shanawaz; Sousa, L. Natércia; Ferreira, Nuno Fábio; Sousa, Ricardo M.; Santos, Joao; Wäny, Martin; Morgado-Dias, F.

2017-01-01

Endoscopy is an imaging procedure used for diagnosis as well as for some surgical purposes. The camera used for the endoscopy should be small and able to produce a good quality image or video, to reduce discomfort of the patients, and to increase the efficiency of the medical team. To achieve these fundamental goals, a small endoscopy camera with a footprint of 1 mm×1 mm×1.65 mm is used. Due to the physical properties of the sensors and human vision system limitations, different image-processing algorithms, such as noise reduction, demosaicking, and gamma correction, among others, are needed to faithfully reproduce the image or video. A full image-processing pipeline is implemented using a field-programmable gate array (FPGA) to accomplish a high frame rate of 60 fps with minimum processing delay. Along with this, a viewer has also been developed to display and control the image-processing pipeline. The control and data transfer are done by a USB 3.0 end point in the computer. The full developed system achieves real-time processing of the image and fits in a Xilinx Spartan-6LX150 FPGA.

Real time mitigation of atmospheric turbulence in long distance imaging using the lucky region fusion algorithm with FPGA and GPU hardware acceleration

NASA Astrophysics Data System (ADS)

Jackson, Christopher Robert

"Lucky-region" fusion (LRF) is a synthetic imaging technique that has proven successful in enhancing the quality of images distorted by atmospheric turbulence. The LRF algorithm selects sharp regions of an image obtained from a series of short exposure frames, and fuses the sharp regions into a final, improved image. In previous research, the LRF algorithm had been implemented on a PC using the C programming language. However, the PC did not have sufficient sequential processing power to handle real-time extraction, processing and reduction required when the LRF algorithm was applied to real-time video from fast, high-resolution image sensors. This thesis describes two hardware implementations of the LRF algorithm to achieve real-time image processing. The first was created with a VIRTEX-7 field programmable gate array (FPGA). The other developed using the graphics processing unit (GPU) of a NVIDIA GeForce GTX 690 video card. The novelty in the FPGA approach is the creation of a "black box" LRF video processing system with a general camera link input, a user controller interface, and a camera link video output. We also describe a custom hardware simulation environment we have built to test the FPGA LRF implementation. The advantage of the GPU approach is significantly improved development time, integration of image stabilization into the system, and comparable atmospheric turbulence mitigation.

Single DMD time-multiplexed 64-views autostereoscopic 3D display

NASA Astrophysics Data System (ADS)

Loreti, Luigi

2013-03-01

Based on previous prototype of the Real time 3D holographic display developed last year, we developed a new concept of auto-stereoscopic multiview display (64 views), wide angle (90°) 3D full color display. The display is based on a RGB laser light source illuminating a DMD (Discovery 4100 0,7") at 24.000 fps, an image deflection system made with an AOD (Acoustic Optic Deflector) driven by a piezo-electric transducer generating a variable standing acoustic wave on the crystal that acts as a phase grating. The DMD projects in fast sequence 64 point of view of the image on the crystal cube. Depending on the frequency of the standing wave, the input picture sent by the DMD is deflected in different angle of view. An holographic screen at a proper distance diffuse the rays in vertical direction (60°) and horizontally select (1°) only the rays directed to the observer. A telescope optical system will enlarge the image to the right dimension. A VHDL firmware to render in real-time (16 ms) 64 views (16 bit 4:2:2) of a CAD model (obj, dxf or 3Ds) and depth-map encoded video images was developed into the resident Virtex5 FPGA of the Discovery 4100 SDK, thus eliminating the needs of image transfer and high speed links

Controller and data acquisition system for SIDECAR ASIC driven HAWAII detectors

NASA Astrophysics Data System (ADS)

Ramaprakash, Anamparambu; Burse, Mahesh; Chordia, Pravin; Chillal, Kalpesh; Kohok, Abhay; Mestry, Vilas; Punnadi, Sujit; Sinha, Sakya

2010-07-01

SIDECAR is an Application Specific Integrated Circuit (ASIC), which can be used for control and data acquisition from near-IR HAWAII detectors offered by Teledyne Imaging Sensors (TIS), USA. The standard interfaces provided by Teledyne are COM API and socket servers running under MS Windows platform. These interfaces communicate to the ASIC (and the detector) through an intermediate card called JWST ASIC Drive Electronics (JADE2). As part of an ongoing programme of several years, for developing astronomical focal plane array (CCDs, CMOS and Hybrid) controllers and data acquisition systems (CDAQs), IUCAA is currently developing the next generation controllers employing Virtex-5 family FPGA devices. We present here the capabilities which are built into these new CDAQs for handling HAWAII detectors. In our system, the computer which hosts the application programme, user interface and device drivers runs on a Linux platform. It communicates through a hot-pluggable USB interface (with an optional optical fibre extender) to the FPGA-based card which replaces the JADE2. The FPGA board in turn, controls the SIDECAR ASIC and through it a HAWAII-2RG detector, both of which are located in a cryogenic test Dewar set up which is liquid nitrogen cooled. The system can acquire data over 1, 4, or 32 readout channels, with or without binning, at different speeds, can define sub-regions for readout, offers various readout schemes like Fowler sampling, up-theramp etc. In this paper, we present the performance results obtained from a prototype system.

A high-speed, reconfigurable, channel- and time-tagged photon arrival recording system for intensity-interferometry and quantum optics experiments

NASA Astrophysics Data System (ADS)

Girish, B. S.; Pandey, Deepak; Ramachandran, Hema

2017-08-01

We present a compact, inexpensive multichannel module, APODAS (Avalanche Photodiode Output Data Acquisition System), capable of detecting 0.8 billion photons per second and providing real-time recording on a computer hard-disk, of channel- and time-tagged information of the arrival of upto 0.4 billion photons per second. Built around a Virtex-5 Field Programmable Gate Array (FPGA) unit, APODAS offers a temporal resolution of 5 nanoseconds with zero deadtime in data acquisition, utilising an efficient scheme for time and channel tagging and employing Gigabit ethernet for the transfer of data. Analysis tools have been developed on a Linux platform for multi-fold coincidence studies and time-delayed intensity interferometry. As illustrative examples, the second-order intensity correlation function ( g 2) of light from two commonly used sources in quantum optics —a coherent laser source and a dilute atomic vapour emitting spontaneously, constituting a thermal source— are presented. With easy reconfigurability and with no restriction on the total record length, APODAS can be readily used for studies over various time scales. This is demonstrated by using APODAS to reveal Rabi oscillations on nanosecond time scales in the emission of ultracold atoms, on the one hand, and, on the other hand, to measure the second-order correlation function on the millisecond time scales from tailored light sources. The efficient and versatile performance of APODAS promises its utility in diverse fields, like quantum optics, quantum communication, nuclear physics, astrophysics and biology.

Frequency Based Design Partitioning to Achieve Higher Throughput in Digital Cross Correlator for Aperture Synthesis Passive MMW Imager.

PubMed

Asif, Muhammad; Guo, Xiangzhou; Zhang, Jing; Miao, Jungang

2018-04-17

Digital cross-correlation is central to many applications including but not limited to Digital Image Processing, Satellite Navigation and Remote Sensing. With recent advancements in digital technology, the computational demands of such applications have increased enormously. In this paper we are presenting a high throughput digital cross correlator, capable of processing 1-bit digitized stream, at the rate of up to 2 GHz, simultaneously on 64 channels i.e., approximately 4 Trillion correlation and accumulation operations per second. In order to achieve higher throughput, we have focused on frequency based partitioning of our design and tried to minimize and localize high frequency operations. This correlator is designed for a Passive Millimeter Wave Imager intended for the detection of contraband items concealed on human body. The goals are to increase the system bandwidth, achieve video rate imaging, improve sensitivity and reduce the size. Design methodology is detailed in subsequent sections, elaborating the techniques enabling high throughput. The design is verified for Xilinx Kintex UltraScale device in simulation and the implementation results are given in terms of device utilization and power consumption estimates. Our results show considerable improvements in throughput as compared to our baseline design, while the correlator successfully meets the functional requirements.

Towards a Generic and Adaptive System-On-Chip Controller for Space Exploration Instrumentation

NASA Technical Reports Server (NTRS)

Iturbe, Xabier; Keymeulen, Didier; Yiu, Patrick; Berisford, Dan; Hand, Kevin; Carlson, Robert; Ozer, Emre

2015-01-01

This paper introduces one of the first efforts conducted at NASA’s Jet Propulsion Laboratory (JPL) to develop a generic System-on-Chip (SoC) platform to control science instruments that are proposed for future NASA missions. The SoC platform is named APEX-SoC, where APEX stands for Advanced Processor for space Exploration, and is based on a hybrid Xilinx Zynq that combines an FPGA and an ARM Cortex-A9 dual-core processor on a single chip. The Zynq implements a generic and customizable on-chip infrastructure that can be reused with a variety of instruments, and it has been coupled with a set of off-chip components that are necessary to deal with the different instruments. We have taken JPL’s Compositional InfraRed Imaging Spectrometer (CIRIS), which is proposed for NASA icy moons missions, as a use-case scenario to demonstrate that the entire data processing, control and interface of an instrument can be implemented on a single device using the on-chip infrastructure described in this paper. We show that the performance results achieved in this preliminary version of the instrumentation controller are sufficient to fulfill the science requirements demanded to the CIRIS instrument in future NASA missions, such as Europa.

High performance embedded system for real-time pattern matching

NASA Astrophysics Data System (ADS)

Sotiropoulou, C.-L.; Luciano, P.; Gkaitatzis, S.; Citraro, S.; Giannetti, P.; Dell'Orso, M.

2017-02-01

In this paper we present an innovative and high performance embedded system for real-time pattern matching. This system is based on the evolution of hardware and algorithms developed for the field of High Energy Physics and more specifically for the execution of extremely fast pattern matching for tracking of particles produced by proton-proton collisions in hadron collider experiments. A miniaturized version of this complex system is being developed for pattern matching in generic image processing applications. The system works as a contour identifier able to extract the salient features of an image. It is based on the principles of cognitive image processing, which means that it executes fast pattern matching and data reduction mimicking the operation of the human brain. The pattern matching can be executed by a custom designed Associative Memory chip. The reference patterns are chosen by a complex training algorithm implemented on an FPGA device. Post processing algorithms (e.g. pixel clustering) are also implemented on the FPGA. The pattern matching can be executed on a 2D or 3D space, on black and white or grayscale images, depending on the application and thus increasing exponentially the processing requirements of the system. We present the firmware implementation of the training and pattern matching algorithm, performance and results on a latest generation Xilinx Kintex Ultrascale FPGA device.

Design of a real-time system of moving ship tracking on-board based on FPGA in remote sensing images

NASA Astrophysics Data System (ADS)

Yang, Tie-jun; Zhang, Shen; Zhou, Guo-qing; Jiang, Chuan-xian

2015-12-01

With the broad attention of countries in the areas of sea transportation and trade safety, the requirements of efficiency and accuracy of moving ship tracking are becoming higher. Therefore, a systematic design of moving ship tracking onboard based on FPGA is proposed, which uses the Adaptive Inter Frame Difference (AIFD) method to track a ship with different speed. For the Frame Difference method (FD) is simple but the amount of computation is very large, it is suitable for the use of FPGA to implement in parallel. But Frame Intervals (FIs) of the traditional FD method are fixed, and in remote sensing images, a ship looks very small (depicted by only dozens of pixels) and moves slowly. By applying invariant FIs, the accuracy of FD for moving ship tracking is not satisfactory and the calculation is highly redundant. So we use the adaptation of FD based on adaptive extraction of key frames for moving ship tracking. A FPGA development board of Xilinx Kintex-7 series is used for simulation. The experiments show that compared with the traditional FD method, the proposed one can achieve higher accuracy of moving ship tracking, and can meet the requirement of real-time tracking in high image resolution.

Malleable architecture generator for FPGA computing

NASA Astrophysics Data System (ADS)

Gokhale, Maya; Kaba, James; Marks, Aaron; Kim, Jang

1996-10-01

The malleable architecture generator (MARGE) is a tool set that translates high-level parallel C to configuration bit streams for field-programmable logic based computing systems. MARGE creates an application-specific instruction set and generates the custom hardware components required to perform exactly those computations specified by the C program. In contrast to traditional fixed-instruction processors, MARGE's dynamic instruction set creation provides for efficient use of hardware resources. MARGE processes intermediate code in which each operation is annotated by the bit lengths of the operands. Each basic block (sequence of straight line code) is mapped into a single custom instruction which contains all the operations and logic inherent in the block. A synthesis phase maps the operations comprising the instructions into register transfer level structural components and control logic which have been optimized to exploit functional parallelism and function unit reuse. As a final stage, commercial technology-specific tools are used to generate configuration bit streams for the desired target hardware. Technology- specific pre-placed, pre-routed macro blocks are utilized to implement as much of the hardware as possible. MARGE currently supports the Xilinx-based Splash-2 reconfigurable accelerator and National Semiconductor's CLAy-based parallel accelerator, MAPA. The MARGE approach has been demonstrated on systolic applications such as DNA sequence comparison.

Reconfigurable signal processor designs for advanced digital array radar systems

NASA Astrophysics Data System (ADS)

Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

2017-05-01

The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

Radiation effects and mitigation strategies for modern FPGAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stettler, M. W.; Caffrey, M. P.; Graham, P. S.

2004-01-01

Field Programmable Gate Array devices have become the technology of choice in small volume modern instrumentation and control systems. These devices have always offered significant advantages in flexibility, and recent advances in fabrication have greatly increased logic capacity, substantially increasing the number of applications for this technology. Unfortunately, the increased density (and corresponding shrinkage of process geometry), has made these devices more susceptible to failure due to external radiation. This has been an issue for space based systems for some time, but is now becoming an issue for terrestrial systems in elevated radiation environments and commercial avionics as well. Characterizingmore » the failure modes of Xilinx FPGAs, and developing mitigation strategies is the subject of ongoing research by a consortium of academic, industrial, and governmental laboratories. This paper presents background information of radiation effects and failure modes, as well as current and future mitigation techniques. In particular, the availability of very large FPGA devices, complete with generous amounts of RAM and embedded processor(s), has led to the implementation of complete digital systems on a single device, bringing issues of system reliability and redundancy management to the chip level. Radiation effects on a single FPGA are increasingly likely to have system level consequences, and will need to be addressed in current and future designs.« less

FPGA implementation of low complexity LDPC iterative decoder

NASA Astrophysics Data System (ADS)

Verma, Shivani; Sharma, Sanjay

2016-07-01

Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property and excellent performance in the noisy channel. Belief propagation (BP) algorithm and its approximations, most notably min-sum, are popular iterative decoding algorithms used for LDPC and turbo codes. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. This article presents introduction to LDPC codes and its various decoding algorithms followed by realisation of LDPC decoder by using simplified message passing algorithm and partially parallel decoder architecture. Simplified message passing algorithm has been proposed for trade-off between low decoding complexity and decoder performance. It greatly reduces the routing and check node complexity of the decoder. Partially parallel decoder architecture possesses high speed and reduced complexity. The improved design of the decoder possesses a maximum symbol throughput of 92.95 Mbps and a maximum of 18 decoding iterations. The article presents implementation of 9216 bits, rate-1/2, (3, 6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family.

Palmprint and face score level fusion: hardware implementation of a contactless small sample biometric system

NASA Astrophysics Data System (ADS)

Poinsot, Audrey; Yang, Fan; Brost, Vincent

2011-02-01

Including multiple sources of information in personal identity recognition and verification gives the opportunity to greatly improve performance. We propose a contactless biometric system that combines two modalities: palmprint and face. Hardware implementations are proposed on the Texas Instrument Digital Signal Processor and Xilinx Field-Programmable Gate Array (FPGA) platforms. The algorithmic chain consists of a preprocessing (which includes palm extraction from hand images), Gabor feature extraction, comparison by Hamming distance, and score fusion. Fusion possibilities are discussed and tested first using a bimodal database of 130 subjects that we designed (uB database), and then two common public biometric databases (AR for face and PolyU for palmprint). High performance has been obtained for recognition and verification purpose: a recognition rate of 97.49% with AR-PolyU database and an equal error rate of 1.10% on the uB database using only two training samples per subject have been obtained. Hardware results demonstrate that preprocessing can easily be performed during the acquisition phase, and multimodal biometric recognition can be treated almost instantly (0.4 ms on FPGA). We show the feasibility of a robust and efficient multimodal hardware biometric system that offers several advantages, such as user-friendliness and flexibility.

A 4.2 ps Time-Interval RMS Resolution Time-to-Digital Converter Using a Bin Decimation Method in an UltraScale FPGA

NASA Astrophysics Data System (ADS)

Wang, Yonggang; Liu, Chong

2016-10-01

The common solution for a field programmable gate array (FPGA)-based time-to-digital converter (TDC) is constructing a tapped delay line (TDL) for time interpolation to yield a sub-clock time resolution. The granularity and uniformity of the delay elements of TDL determine the TDC time resolution. In this paper, we propose a dual-sampling TDL architecture and a bin decimation method that could make the delay elements as small and uniform as possible, so that the implemented TDCs can achieve a high time resolution beyond the intrinsic cell delay. Two identical full hardware-based TDCs were implemented in a Xilinx UltraScale FPGA for performance evaluation. For fixed time intervals in the range from 0 to 440 ns, the average time-interval RMS resolution is measured by the two TDCs with 4.2 ps, thus the timestamp resolution of single TDC is derived as 2.97 ps. The maximum hit rate of the TDC is as high as half the system clock rate of FPGA, namely 250 MHz in our demo prototype. Because the conventional online bin-by-bin calibration is not needed, the implementation of the proposed TDC is straightforward and relatively resource-saving.

A hardware architecture for real-time shadow removal in high-contrast video

NASA Astrophysics Data System (ADS)

Verdugo, Pablo; Pezoa, Jorge E.; Figueroa, Miguel

2017-09-01

Broadcasting an outdoor sports event at daytime is a challenging task due to the high contrast that exists between areas in the shadow and light conditions within the same scene. Commercial cameras typically do not handle the high dynamic range of such scenes in a proper manner, resulting in broadcast streams with very little shadow detail. We propose a hardware architecture for real-time shadow removal in high-resolution video, which reduces the shadow effect and simultaneously improves shadow details. The algorithm operates only on the shadow portions of each video frame, thus improving the results and producing more realistic images than algorithms that operate on the entire frame, such as simplified Retinex and histogram shifting. The architecture receives an input in the RGB color space, transforms it into the YIQ space, and uses color information from both spaces to produce a mask of the shadow areas present in the image. The mask is then filtered using a connected components algorithm to eliminate false positives and negatives. The hardware uses pixel information at the edges of the mask to estimate the illumination ratio between light and shadow in the image, which is then used to correct the shadow area. Our prototype implementation simultaneously processes up to 7 video streams of 1920×1080 pixels at 60 frames per second on a Xilinx Kintex-7 XC7K325T FPGA.

Video rate morphological processor based on a redundant number representation

NASA Astrophysics Data System (ADS)

Kuczborski, Wojciech; Attikiouzel, Yianni; Crebbin, Gregory A.

1992-03-01

This paper presents a video rate morphological processor for automated visual inspection of printed circuit boards, integrated circuit masks, and other complex objects. Inspection algorithms are based on gray-scale mathematical morphology. Hardware complexity of the known methods of real-time implementation of gray-scale morphology--the umbra transform and the threshold decomposition--has prompted us to propose a novel technique which applied an arithmetic system without carrying propagation. After considering several arithmetic systems, a redundant number representation has been selected for implementation. Two options are analyzed here. The first is a pure signed digit number representation (SDNR) with the base of 4. The second option is a combination of the base-2 SDNR (to represent gray levels of images) and the conventional twos complement code (to represent gray levels of structuring elements). Operation principle of the morphological processor is based on the concept of the digit level systolic array. Individual processing units and small memory elements create a pipeline. The memory elements store current image windows (kernels). All operation primitives of processing units apply a unified direction of digit processing: most significant digit first (MSDF). The implementation technology is based on the field programmable gate arrays by Xilinx. This paper justified the rationality of a new approach to logic design, which is the decomposition of Boolean functions instead of Boolean minimization.

Extending the IEEE 802.15.4 Security Suite with a Compact Implementation of the NIST P-192/B-163 Elliptic Curves

PubMed Central

de la Piedra, Antonio; Braeken, An; Touhafi, Abdellah

2013-01-01

Typically, commercial sensor nodes are equipped with MCUsclocked at a low-frequency (i.e., within the 4–12 MHz range). Consequently, executing cryptographic algorithms in those MCUs generally requires a huge amount of time. In this respect, the required energy consumption can be higher than using a separate accelerator based on a Field-programmable Gate Array (FPGA) that is switched on when needed. In this manuscript, we present the design of a cryptographic accelerator suitable for an FPGA-based sensor node and compliant with the IEEE802.15.4 standard. All the embedded resources of the target platform (Xilinx Artix-7) have been maximized in order to provide a cost-effective solution. Moreover, we have added key negotiation capabilities to the IEEE 802.15.4 security suite based on Elliptic Curve Cryptography (ECC;. Our results suggest that tailored accelerators based on FPGA can behave better in terms of energy than contemporary software solutions for motes, such as the TinyECC and NanoECC libraries. In this regard, a point multiplication (PM) can be performed between 8.58- and 15.4-times faster, 3.40- to 23.59-times faster (Elliptic Curve Diffie-Hellman, ECDH) and between 5.45- and 34.26-times faster (Elliptic Curve Integrated Encryption Scheme, ECIES). Moreover, the energy consumption was also improved with a factor of 8.96 (PM). PMID:23899936

A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar.

PubMed

Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun; Huang, Yuan-Hao

2018-04-05

Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

DOE PAGES

Claus, R.

2015-10-23

The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQmore » building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. Furthermore, the full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.« less

An FPGA Architecture for Extracting Real-Time Zernike Coefficients from Measured Phase Gradients

NASA Astrophysics Data System (ADS)

Moser, Steven; Lee, Peter; Podoleanu, Adrian

2015-04-01

Zernike modes are commonly used in adaptive optics systems to represent optical wavefronts. However, real-time calculation of Zernike modes is time consuming due to two factors: the large factorial components in the radial polynomials used to define them and the large inverse matrix calculation needed for the linear fit. This paper presents an efficient parallel method for calculating Zernike coefficients from phase gradients produced by a Shack-Hartman sensor and its real-time implementation using an FPGA by pre-calculation and storage of subsections of the large inverse matrix. The architecture exploits symmetries within the Zernike modes to achieve a significant reduction in memory requirements and a speed-up of 2.9 when compared to published results utilising a 2D-FFT method for a grid size of 8×8. Analysis of processor element internal word length requirements show that 24-bit precision in precalculated values of the Zernike mode partial derivatives ensures less than 0.5% error per Zernike coefficient and an overall error of <1%. The design has been synthesized on a Xilinx Spartan-6 XC6SLX45 FPGA. The resource utilisation on this device is <3% of slice registers, <15% of slice LUTs, and approximately 48% of available DSP blocks independent of the Shack-Hartmann grid size. Block RAM usage is <16% for Shack-Hartmann grid sizes up to 32×32.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

NASA Astrophysics Data System (ADS)

Claus, R.; ATLAS Collaboration

2016-07-01

The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

NASA Astrophysics Data System (ADS)

Bartoldus, R.; Claus, R.; Garelli, N.; Herbst, R. T.; Huffer, M.; Iakovidis, G.; Iordanidou, K.; Kwan, K.; Kocian, M.; Lankford, A. J.; Moschovakos, P.; Nelson, A.; Ntekas, K.; Ruckman, L.; Russell, J.; Schernau, M.; Schlenker, S.; Su, D.; Valderanis, C.; Wittgen, M.; Yildiz, S. C.

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2.

Conceptual design of the SMART dosimeter

NASA Astrophysics Data System (ADS)

Johnson, Erik B.; Vogel, Sam; Frank, Rebecca; Stoddard, Graham; Vera, Alonzo; Alexander, David; Christian, James

2017-08-01

Active dosimeters for astronauts and space weather monitors are critical tools for mitigating radiation induced health issues or system failure on capital equipment. Commercial spaceflight, deep space flight, and satellites require smarter, smaller, and lower power dosimeters. There are a number of instruments with flight heritage, yet as identified in NASA's roadmaps, these technologies do not lend themselves to a viable solution for active dosimetry for an astronaut, particularly for deep space missions. For future missions, nano- and micro-satellites will require compact instruments that will accurately assess the radiation hazard without consuming major resources on the spacecraft. RMD has developed the methods for growing an advanced scintillation material called phenylcarbazole, which provides pulse shape discrimination between protons and electrons. When used in combination with an anti-coincidence detector system, an assessment of the dose from charged ions and neutral particles can be determined. This is valuable as damage on a system (such as silicon or tissue) is dependent on the particle species. Using this crystal with readout electronics developed in partnership with COSMIAC at the University of New Mexico, the design of the Small Mixed field Autonomous Radiation Tracker (SMART) Dosimeter consists of a low-power analog to digital conversion scheme with low-power digital signal processing algorithms, which are to be implemented within a compact system on a chip, such as the Xilinx Zynq series. A review of the conceptual design is presented.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

DOE PAGES

Bartoldus, R.; Claus, R.; Garelli, N.; ...

2016-01-25

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all ofmore » these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. In conclusion, we will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2.« less

A Front-End Electronics Prototype Based on Gigabit Ethernet for the ATLAS Small-Strip Thin Gap Chamber

NASA Astrophysics Data System (ADS)

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Wang, Xinxin; Geng, Tianru; Yang, Hang; Liu, Shengquan; Han, Liang; Jin, Ge

2017-06-01

A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail.

Extending the IEEE 802.15.4 security suite with a compact implementation of the NIST P-192/B-163 elliptic curves.

PubMed

de la Piedra, Antonio; Braeken, An; Touhafi, Abdellah

2013-07-29

Typically, commercial sensor nodes are equipped with MCUsclocked at a low-frequency (i.e., within the 4-12 MHz range). Consequently, executing cryptographic algorithms in those MCUs generally requires a huge amount of time. In this respect, the required energy consumption can be higher than using a separate accelerator based on a Field-programmable Gate Array (FPGA) that is switched on when needed. In this manuscript, we present the design of a cryptographic accelerator suitable for an FPGA-based sensor node and compliant with the IEEE802.15.4 standard. All the embedded resources of the target platform (Xilinx Artix-7) have been maximized in order to provide a cost-effective solution. Moreover, we have added key negotiation capabilities to the IEEE 802.15.4 security suite based on Elliptic Curve Cryptography (ECC). Our results suggest that tailored accelerators based on FPGA can behave better in terms of energy than contemporary software solutions for motes, such as the TinyECC and NanoECC libraries. In this regard, a point multiplication (PM) can be performed between 8.58- and 15.4-times faster, 3.40- to 23.59-times faster (Elliptic Curve Diffie-Hellman, ECDH) and between 5.45- and 34.26-times faster (Elliptic Curve Integrated Encryption Scheme, ECIES). Moreover, the energy consumption was also improved with a factor of 8.96 (PM).

Reliable and redundant FPGA based read-out design in the ATLAS TileCal Demonstrator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akerstedt, Henrik; Muschter, Steffen; Drake, Gary

The Tile Calorimeter at ATLAS [1] is a hadron calorimeter based on steel plates and scintillating tiles read out by PMTs. The current read-out system uses standard ADCs and custom ASICs to digitize and temporarily store the data on the detector. However, only a subset of the data is actually read out to the counting room. The on-detector electronics will be replaced around 2023. To achieve the required reliability the upgraded system will be highly redundant. Here the ASICs will be replaced with Kintex-7 FPGAs from Xilinx. This, in addition to the use of multiple 10 Gbps optical read-out links,more » will allow a full read-out of all detector data. Due to the higher radiation levels expected when the beam luminosity is increased, opportunities for repairs will be less frequent. The circuitry and firmware must therefore be designed for sufficiently high reliability using redundancy and radiation tolerant components. Within a year, a hybrid demonstrator including the new readout system will be installed in one slice of the ATLAS Tile Calorimeter. This will allow the proposed upgrade to be thoroughly evaluated well before the planned 2023 deployment in all slices, especially with regard to long term reliability. Different firmware strategies alongside with their integration in the demonstrator are presented in the context of high reliability protection against hardware malfunction and radiation induced errors.« less

Efficient lossy compression implementations of hyperspectral images: tools, hardware platforms, and comparisons

NASA Astrophysics Data System (ADS)

García, Aday; Santos, Lucana; López, Sebastián.; Callicó, Gustavo M.; Lopez, Jose F.; Sarmiento, Roberto

2014-05-01

Efficient onboard satellite hyperspectral image compression represents a necessity and a challenge for current and future space missions. Therefore, it is mandatory to provide hardware implementations for this type of algorithms in order to achieve the constraints required for onboard compression. In this work, we implement the Lossy Compression for Exomars (LCE) algorithm on an FPGA by means of high-level synthesis (HSL) in order to shorten the design cycle. Specifically, we use CatapultC HLS tool to obtain a VHDL description of the LCE algorithm from C-language specifications. Two different approaches are followed for HLS: on one hand, introducing the whole C-language description in CatapultC and on the other hand, splitting the C-language description in functional modules to be implemented independently with CatapultC, connecting and controlling them by an RTL description code without HLS. In both cases the goal is to obtain an FPGA implementation. We explain the several changes applied to the original Clanguage source code in order to optimize the results obtained by CatapultC for both approaches. Experimental results show low area occupancy of less than 15% for a SRAM-based Virtex-5 FPGA and a maximum frequency above 80 MHz. Additionally, the LCE compressor was implemented into an RTAX2000S antifuse-based FPGA, showing an area occupancy of 75% and a frequency around 53 MHz. All these serve to demonstrate that the LCE algorithm can be efficiently executed on an FPGA onboard a satellite. A comparison between both implementation approaches is also provided. The performance of the algorithm is finally compared with implementations on other technologies, specifically a graphics processing unit (GPU) and a single-threaded CPU.

Estimating the circuit delay of FPGA with a transfer learning method

NASA Astrophysics Data System (ADS)

Cui, Xiuhai; Liu, Datong; Peng, Yu; Peng, Xiyuan

2017-10-01

With the increase of FPGA (Field Programmable Gate Array, FPGA) functionality, FPGA has become an on-chip system platform. Due to increase the complexity of FPGA, estimating the delay of FPGA is a very challenge work. To solve the problems, we propose a transfer learning estimation delay (TLED) method to simplify the delay estimation of different speed grade FPGA. In fact, the same style different speed grade FPGA comes from the same process and layout. The delay has some correlation among different speed grade FPGA. Therefore, one kind of speed grade FPGA is chosen as a basic training sample in this paper. Other training samples of different speed grade can get from the basic training samples through of transfer learning. At the same time, we also select a few target FPGA samples as training samples. A general predictive model is trained by these samples. Thus one kind of estimation model is used to estimate different speed grade FPGA circuit delay. The framework of TRED includes three phases: 1) Building a basic circuit delay library which includes multipliers, adders, shifters, and so on. These circuits are used to train and build the predictive model. 2) By contrasting experiments among different algorithms, the forest random algorithm is selected to train predictive model. 3) The target circuit delay is predicted by the predictive model. The Artix-7, Kintex-7, and Virtex-7 are selected to do experiments. Each of them includes -1, -2, -2l, and -3 different speed grade. The experiments show the delay estimation accuracy score is more than 92% with the TLED method. This result shows that the TLED method is a feasible delay assessment method, especially in the high-level synthesis stage of FPGA tool, which is an efficient and effective delay assessment method.

Adaptive Controller for Compact Fourier Transform Spectrometer with Space Applications

NASA Astrophysics Data System (ADS)

Keymeulen, D.; Yiu, P.; Berisford, D. F.; Hand, K. P.; Carlson, R. W.; Conroy, M.

2014-12-01

Here we present noise mitigation techniques developed as part of an adaptive controller for a very compact Compositional InfraRed Interferometric Spectrometer (CIRIS) implemented on a stand-alone field programmable gate array (FPGA) architecture with emphasis on space applications in high radiation environments such as Europa. CIRIS is a novel take on traditional Fourier Transform Spectrometers (FTS) and replaces linearly moving mirrors (characteristic of Michelson interferometers) with a constant-velocity rotating refractor to variably phase shift and alter the path length of incoming light. The design eschews a monochromatic reference laser typically used for sampling clock generation and instead utilizes constant time-sampling via internally generated clocks. This allows for a compact and robust device, making it ideal for spaceborne measurements in the near-IR to thermal-IR band (2-12 µm) on planetary exploration missions. The instrument's embedded microcontroller is implemented on a VIRTEX-5 FPGA and a PowerPC with the aim of sampling the instrument's detector and optical rotary encoder in order to construct interferograms. Subsequent onboard signal processing provides spectral immunity from the noise effects introduced by the compact design's removal of a reference laser and by the radiation encountered during space flight to destinations such as Europa. A variety of signal processing techniques including resampling, radiation peak removal, Fast Fourier Transform (FFT), spectral feature alignment, dispersion correction and calibration processes are applied to compose the sample spectrum in real-time with signal-to-noise-ratio (SNR) performance comparable to laser-based FTS designs in radiation-free environments. The instrument's FPGA controller is demonstrated with the FTS to characterize its noise mitigation techniques and highlight its suitability for implementation in space systems.

A high throughput architecture for a low complexity soft-output demapping algorithm

NASA Astrophysics Data System (ADS)

Ali, I.; Wasenmüller, U.; Wehn, N.

2015-11-01

Iterative channel decoders such as Turbo-Code and LDPC decoders show exceptional performance and therefore they are a part of many wireless communication receivers nowadays. These decoders require a soft input, i.e., the logarithmic likelihood ratio (LLR) of the received bits with a typical quantization of 4 to 6 bits. For computing the LLR values from a received complex symbol, a soft demapper is employed in the receiver. The implementation cost of traditional soft-output demapping methods is relatively large in high order modulation systems, and therefore low complexity demapping algorithms are indispensable in low power receivers. In the presence of multiple wireless communication standards where each standard defines multiple modulation schemes, there is a need to have an efficient demapper architecture covering all the flexibility requirements of these standards. Another challenge associated with hardware implementation of the demapper is to achieve a very high throughput in double iterative systems, for instance, MIMO and Code-Aided Synchronization. In this paper, we present a comprehensive communication and hardware performance evaluation of low complexity soft-output demapping algorithms to select the best algorithm for implementation. The main goal of this work is to design a high throughput, flexible, and area efficient architecture. We describe architectures to execute the investigated algorithms. We implement these architectures on a FPGA device to evaluate their hardware performance. The work has resulted in a hardware architecture based on the figured out best low complexity algorithm delivering a high throughput of 166 Msymbols/second for Gray mapped 16-QAM modulation on Virtex-5. This efficient architecture occupies only 127 slice registers, 248 slice LUTs and 2 DSP48Es.

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging.

PubMed

Ibrahim, Aya; Hager, Pascal A; Bartolini, Andrea; Angiolini, Federico; Arditi, Marcel; Thiran, Jean-Philippe; Benini, Luca; De Micheli, Giovanni

2017-08-01

Ultrasound imaging is a reference medical diagnostic technique, thanks to its blend of versatility, effectiveness, and moderate cost. The core computation of all ultrasound imaging methods is based on simple formulae, except for those required to calculate acoustic propagation delays with high precision and throughput. Unfortunately, advanced three-dimensional (3-D) systems require the calculation or storage of billions of such delay values per frame, which is a challenge. In 2-D systems, this requirement can be four orders of magnitude lower, but efficient computation is still crucial in view of low-power implementations that can be battery-operated, enabling usage in numerous additional scenarios. In this paper, we explore two smart designs of the delay generation function. To quantify their hardware cost, we implement them on FPGA and study their footprint and performance. We evaluate how these architectures scale to different ultrasound applications, from a low-power 2-D system to a next-generation 3-D machine. When using numerical approximations, we demonstrate the ability to generate delay values with sufficient throughput to support 10 000-channel 3-D imaging at up to 30 fps while using 63% of a Virtex 7 FPGA, requiring 24 MB of external memory accessed at about 32 GB/s bandwidth. Alternatively, with similar FPGA occupation, we show an exact calculation method that reaches 24 fps on 1225-channel 3-D imaging and does not require external memory at all. Both designs can be scaled to use a negligible amount of resources for 2-D imaging in low-power applications and for ultrafast 2-D imaging at hundreds of frames per second.

HDL Based FPGA Interface Library for Data Acquisition and Multipurpose Real Time Algorithms

NASA Astrophysics Data System (ADS)

Fernandes, Ana M.; Pereira, R. C.; Sousa, J.; Batista, A. J. N.; Combo, A.; Carvalho, B. B.; Correia, C. M. B. A.; Varandas, C. A. F.

2011-08-01

The inherent parallelism of the logic resources, the flexibility in its configuration and the performance at high processing frequencies makes the field programmable gate array (FPGA) the most suitable device to be used both for real time algorithm processing and data transfer in instrumentation modules. Moreover, the reconfigurability of these FPGA based modules enables exploiting different applications on the same module. When using a reconfigurable module for various applications, the availability of a common interface library for easier implementation of the algorithms on the FPGA leads to more efficient development. The FPGA configuration is usually specified in a hardware description language (HDL) or other higher level descriptive language. The critical paths, such as the management of internal hardware clocks that require deep knowledge of the module behavior shall be implemented in HDL to optimize the timing constraints. The common interface library should include these critical paths, freeing the application designer from hardware complexity and able to choose any of the available high-level abstraction languages for the algorithm implementation. With this purpose a modular Verilog code was developed for the Virtex 4 FPGA of the in-house Transient Recorder and Processor (TRP) hardware module, based on the Advanced Telecommunications Computing Architecture (ATCA), with eight channels sampling at up to 400 MSamples/s (MSPS). The TRP was designed to perform real time Pulse Height Analysis (PHA), Pulse Shape Discrimination (PSD) and Pile-Up Rejection (PUR) algorithms at a high count rate (few Mevent/s). A brief description of this modular code is presented and examples of its use as an interface with end user algorithms, including a PHA with PUR, are described.

A memory efficient implementation scheme of Gauss error function in a Laguerre-Volterra network for neuroprosthetic devices

NASA Astrophysics Data System (ADS)

Li, Will X. Y.; Cui, Ke; Zhang, Wei

2017-04-01

Cognitive neural prosthesis is a manmade device which can be used to restore or compensate for lost human cognitive modalities. The generalized Laguerre-Volterra (GLV) network serves as a robust mathematical underpinning for the development of such prosthetic instrument. In this paper, a hardware implementation scheme of Gauss error function for the GLV network targeting reconfigurable platforms is reported. Numerical approximations are formulated which transform the computation of nonelementary function into combinational operations of elementary functions, and memory-intensive look-up table (LUT) based approaches can therefore be circumvented. The computational precision can be made adjustable with the utilization of an error compensation scheme, which is proposed based on the experimental observation of the mathematical characteristics of the error trajectory. The precision can be further customizable by exploiting the run-time characteristics of the reconfigurable system. Compared to the polynomial expansion based implementation scheme, the utilization of slice LUTs, occupied slices, and DSP48E1s on a Xilinx XC6VLX240T field-programmable gate array has decreased by 94.2%, 94.1%, and 90.0%, respectively. While compared to the look-up table based scheme, 1.0 ×1017 bits of storage can be spared under the maximum allowable error of 1.0 ×10-3 . The proposed implementation scheme can be employed in the study of large-scale neural ensemble activity and in the design and development of neural prosthetic device.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

PubMed

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-30

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

PubMed Central

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-01

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

JPEG XS, a new standard for visually lossless low-latency lightweight image compression

NASA Astrophysics Data System (ADS)

Descampe, Antonin; Keinert, Joachim; Richter, Thomas; Fößel, Siegfried; Rouvroy, Gaël.

2017-09-01

JPEG XS is an upcoming standard from the JPEG Committee (formally known as ISO/IEC SC29 WG1). It aims to provide an interoperable visually lossless low-latency lightweight codec for a wide range of applications including mezzanine compression in broadcast and Pro-AV markets. This requires optimal support of a wide range of implementation technologies such as FPGAs, CPUs and GPUs. Targeted use cases are professional video links, IP transport, Ethernet transport, real-time video storage, video memory buffers, and omnidirectional video capture and rendering. In addition to the evaluation of the visual transparency of the selected technologies, a detailed analysis of the hardware and software complexity as well as the latency has been done to make sure that the new codec meets the requirements of the above-mentioned use cases. In particular, the end-to-end latency has been constrained to a maximum of 32 lines. Concerning the hardware complexity, neither encoder nor decoder should require more than 50% of an FPGA similar to Xilinx Artix 7 or 25% of an FPGA similar to Altera Cyclon 5. This process resulted in a coding scheme made of an optional color transform, a wavelet transform, the entropy coding of the highest magnitude level of groups of coefficients, and the raw inclusion of the truncated wavelet coefficients. This paper presents the details and status of the standardization process, a technical description of the future standard, and the latest performance evaluation results.

Field Programmable Gate Array Based Parallel Strapdown Algorithm Design for Strapdown Inertial Navigation Systems

PubMed Central

Li, Zong-Tao; Wu, Tie-Jun; Lin, Can-Long; Ma, Long-Hua

2011-01-01

A new generalized optimum strapdown algorithm with coning and sculling compensation is presented, in which the position, velocity and attitude updating operations are carried out based on the single-speed structure in which all computations are executed at a single updating rate that is sufficiently high to accurately account for high frequency angular rate and acceleration rectification effects. Different from existing algorithms, the updating rates of the coning and sculling compensations are unrelated with the number of the gyro incremental angle samples and the number of the accelerometer incremental velocity samples. When the output sampling rate of inertial sensors remains constant, this algorithm allows increasing the updating rate of the coning and sculling compensation, yet with more numbers of gyro incremental angle and accelerometer incremental velocity in order to improve the accuracy of system. Then, in order to implement the new strapdown algorithm in a single FPGA chip, the parallelization of the algorithm is designed and its computational complexity is analyzed. The performance of the proposed parallel strapdown algorithm is tested on the Xilinx ISE 12.3 software platform and the FPGA device XC6VLX550T hardware platform on the basis of some fighter data. It is shown that this parallel strapdown algorithm on the FPGA platform can greatly decrease the execution time of algorithm to meet the real-time and high precision requirements of system on the high dynamic environment, relative to the existing implemented on the DSP platform. PMID:22164058

A 3.9 ps Time-Interval RMS Precision Time-to-Digital Converter Using a Dual-Sampling Method in an UltraScale FPGA

NASA Astrophysics Data System (ADS)

Wang, Yonggang; Liu, Chong

2016-10-01

Field programmable gate arrays (FPGAs) manufactured with more advanced processing technology have faster carry chains and smaller delay elements, which are favorable for the design of tapped delay line (TDL)-style time-to-digital converters (TDCs) in FPGA. However, new challenges are posed in using them to implement TDCs with a high time precision. In this paper, we propose a bin realignment method and a dual-sampling method for TDC implementation in a Xilinx UltraScale FPGA. The former realigns the disordered time delay taps so that the TDC precision can approach the limit of its delay granularity, while the latter doubles the number of taps in the delay line so that the TDC precision beyond the cell delay limitation can be expected. Two TDC channels were implemented in a Kintex UltraScale FPGA, and the effectiveness of the new methods was evaluated. For fixed time intervals in the range from 0 to 440 ns, the average RMS precision measured by the two TDC channels reaches 5.8 ps using the bin realignment, and it further improves to 3.9 ps by using the dual-sampling method. The time precision has a 5.6% variation in the measured temperature range. Every part of the TDC, including dual-sampling, encoding, and on-line calibration, could run at a 500 MHz clock frequency. The system measurement dead time is only 4 ns.

A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar

PubMed Central

Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun

2018-01-01

Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256×13 real-time radar image display with a throughput of 28.2 frames per second. PMID:29621170

Test Waveform Applications for JPL STRS Operating Environment

NASA Technical Reports Server (NTRS)

Lux, James P.; Peters, Kenneth J.; Taylor, Gregory H.; Lang, Minh; Stern, Ryan A.; Duncan, Courtney B.

2013-01-01

This software demonstrates use of the JPL Space Telecommunications Radio System (STRS) Operating Environment (OE), tests APIs (application programming interfaces) presented by JPL STRS OE, and allows for basic testing of the underlying hardware platform. This software uses the JPL STRS Operating Environment ["JPL Space Tele com - munications Rad io System Operating Environment,"(NPO-4776) NASA Tech Briefs, commercial edition, Vol. 37, No. 1 (January 2013), p. 47] to interact with the JPL-SDR Software Defined Radio developed for the CoNNeCT (COmmunications, Navigation, and Networking rEconfigurable Testbed) Project as part of the SCaN Testbed installed on the International Space Station (ISS). These are the first applications that are compliant with the new NASA STRS Architecture Standard. Several example waveform applications are provided to demonstrate use of the JPL STRS OE for the JPL-SDR platform used for the CoNNeCT Project. The waveforms provide a simple digitizer and playback capability for the SBand RF slice, and a simple digitizer for the GPS slice [CoNNeCT Global Positioning System RF Module, (NPO-47764) NASA Tech Briefs, commercial edition, Vol. 36, No. 3 (March 2012), p. 36]. These waveforms may be used for hardware test, as well as for on-orbit or laboratory checkout. Additional example waveforms implement SpaceWire and timer modules, which can be used for time transfer and demonstration of communication between the two Xilinx FPGAs in the JPLSDR. The waveforms are also compatible with ground-based use of the JPL STRS OE on radio breadboards and Linux.

Efficient Hardware Implementation of the Horn-Schunck Algorithm for High-Resolution Real-Time Dense Optical Flow Sensor

PubMed Central

Komorkiewicz, Mateusz; Kryjak, Tomasz; Gorgon, Marek

2014-01-01

This article presents an efficient hardware implementation of the Horn-Schunck algorithm that can be used in an embedded optical flow sensor. An architecture is proposed, that realises the iterative Horn-Schunck algorithm in a pipelined manner. This modification allows to achieve data throughput of 175 MPixels/s and makes processing of Full HD video stream (1, 920 × 1, 080 @ 60 fps) possible. The structure of the optical flow module as well as pre- and post-filtering blocks and a flow reliability computation unit is described in details. Three versions of optical flow modules, with different numerical precision, working frequency and obtained results accuracy are proposed. The errors caused by switching from floating- to fixed-point computations are also evaluated. The described architecture was tested on popular sequences from an optical flow dataset of the Middlebury University. It achieves state-of-the-art results among hardware implementations of single scale methods. The designed fixed-point architecture achieves performance of 418 GOPS with power efficiency of 34 GOPS/W. The proposed floating-point module achieves 103 GFLOPS, with power efficiency of 24 GFLOPS/W. Moreover, a 100 times speedup compared to a modern CPU with SIMD support is reported. A complete, working vision system realized on Xilinx VC707 evaluation board is also presented. It is able to compute optical flow for Full HD video stream received from an HDMI camera in real-time. The obtained results prove that FPGA devices are an ideal platform for embedded vision systems. PMID:24526303

Development of a Low-cost, FPGA-based, Delay Line Particle Detector for Satellite and Sounding Rocket Applications

NASA Astrophysics Data System (ADS)

Harrington, M.; Kujawski, J. T.; Adrian, M. L.; Weatherwax, A. T.

2013-12-01

Electrons are, by definition, a fundamental, chemical and electromagnetic constituent of any plasma. This is especially true within the partially ionized plasmas of Earth's ionosphere where electrons are a critical component of a vast array of plasma processes. Siena College is working on a novel method of processing information from electron spectrometer anodes using delay line techniques and inexpensive COTS electronics to track the movement of high-energy particles. Electron spectrometers use a variety of techniques to determine where an amplified electron cloud falls onto a collecting surface. One traditional method divides the collecting surface into sectors and uses a single detector for each sector. However, as the angular and spatial resolution increases, so does the number of detectors, increasing power consumption, cost, size, and weight of the system. An alternative approach is to connect each sector with a delay line built within the PCB material which is shielded from cross talk by a flooded ground plane. Only one pair of detectors (e.g., one at each end of the chain) are needed with the delay line technique which is different from traditional delay line detectors which use either Application Specific Integrated Circuits (ASICs) or very fast clocks. In this paper, we report on the implementation and testing of a delay line detector using a low-cost Xilinx FPGA and a thirty-two sector delay system. This Delay Line Detector has potential satellite and rocket flight applications due to its low cost, small size and power efficiency

Software interface for high-speed readout of particle detectors based on the CoaXPress communication standard

NASA Astrophysics Data System (ADS)

Hejtmánek, M.; Neue, G.; Voleš, P.

2015-06-01

This article is devoted to the software design and development of a high-speed readout application used for interfacing particle detectors via the CoaXPress communication standard. The CoaXPress provides an asymmetric high-speed serial connection over a single coaxial cable. It uses a widely available 75 Ω BNC standard and can operate in various modes with a data throughput ranging from 1.25 Gbps up to 25 Gbps. Moreover, it supports a low speed uplink with a fixed bit rate of 20.833 Mbps, which can be used to control and upload configuration data to the particle detector. The CoaXPress interface is an upcoming standard in medical imaging, therefore its usage promises long-term compatibility and versatility. This work presents an example of how to develop DAQ system for a pixel detector. For this purpose, a flexible DAQ card was developed using the XILINX Spartan 6 FPGA. The DAQ card is connected to the framegrabber FireBird CXP6 Quad, which is plugged in the PCI Express bus of the standard PC. The data transmission was performed between the FPGA and framegrabber card via the standard coaxial cable in communication mode with a bit rate of 3.125 Gbps. Using the Medipix2 Quad pixel detector, the framerate of 100 fps was achieved. The front-end application makes use of the FireBird framegrabber software development kit and is suitable for data acquisition as well as control of the detector through the registers implemented in the FPGA.

FPGA-accelerated adaptive optics wavefront control

NASA Astrophysics Data System (ADS)

Mauch, S.; Reger, J.; Reinlein, C.; Appelfelder, M.; Goy, M.; Beckert, E.; Tünnermann, A.

2014-03-01

The speed of real-time adaptive optical systems is primarily restricted by the data processing hardware and computational aspects. Furthermore, the application of mirror layouts with increasing numbers of actuators reduces the bandwidth (speed) of the system and, thus, the number of applicable control algorithms. This burden turns out a key-impediment for deformable mirrors with continuous mirror surface and highly coupled actuator influence functions. In this regard, specialized hardware is necessary for high performance real-time control applications. Our approach to overcome this challenge is an adaptive optics system based on a Shack-Hartmann wavefront sensor (SHWFS) with a CameraLink interface. The data processing is based on a high performance Intel Core i7 Quadcore hard real-time Linux system. Employing a Xilinx Kintex-7 FPGA, an own developed PCie card is outlined in order to accelerate the analysis of a Shack-Hartmann Wavefront Sensor. A recently developed real-time capable spot detection algorithm evaluates the wavefront. The main features of the presented system are the reduction of latency and the acceleration of computation For example, matrix multiplications which in general are of complexity O(n3 are accelerated by using the DSP48 slices of the field-programmable gate array (FPGA) as well as a novel hardware implementation of the SHWFS algorithm. Further benefits are the Streaming SIMD Extensions (SSE) which intensively use the parallelization capability of the processor for further reducing the latency and increasing the bandwidth of the closed-loop. Due to this approach, up to 64 actuators of a deformable mirror can be handled and controlled without noticeable restriction from computational burdens.

Efficient hardware implementation of the Horn-Schunck algorithm for high-resolution real-time dense optical flow sensor.

PubMed

Komorkiewicz, Mateusz; Kryjak, Tomasz; Gorgon, Marek

2014-02-12

This article presents an efficient hardware implementation of the Horn-Schunck algorithm that can be used in an embedded optical flow sensor. An architecture is proposed, that realises the iterative Horn-Schunck algorithm in a pipelined manner. This modification allows to achieve data throughput of 175 MPixels/s and makes processing of Full HD video stream (1; 920 × 1; 080 @ 60 fps) possible. The structure of the optical flow module as well as pre- and post-filtering blocks and a flow reliability computation unit is described in details. Three versions of optical flow modules, with different numerical precision, working frequency and obtained results accuracy are proposed. The errors caused by switching from floating- to fixed-point computations are also evaluated. The described architecture was tested on popular sequences from an optical flow dataset of the Middlebury University. It achieves state-of-the-art results among hardware implementations of single scale methods. The designed fixed-point architecture achieves performance of 418 GOPS with power efficiency of 34 GOPS/W. The proposed floating-point module achieves 103 GFLOPS, with power efficiency of 24 GFLOPS/W. Moreover, a 100 times speedup compared to a modern CPU with SIMD support is reported. A complete, working vision system realized on Xilinx VC707 evaluation board is also presented. It is able to compute optical flow for Full HD video stream received from an HDMI camera in real-time. The obtained results prove that FPGA devices are an ideal platform for embedded vision systems.

DSPACE hardware architecture for on-board real-time image/video processing in European space missions

NASA Astrophysics Data System (ADS)

Saponara, Sergio; Donati, Massimiliano; Fanucci, Luca; Odendahl, Maximilian; Leupers, Reiner; Errico, Walter

2013-02-01

The on-board data processing is a vital task for any satellite and spacecraft due to the importance of elaborate the sensing data before sending them to the Earth, in order to exploit effectively the bandwidth to the ground station. In the last years the amount of sensing data collected by scientific and commercial space missions has increased significantly, while the available downlink bandwidth is comparatively stable. The increasing demand of on-board real-time processing capabilities represents one of the critical issues in forthcoming European missions. Faster and faster signal and image processing algorithms are required to accomplish planetary observation, surveillance, Synthetic Aperture Radar imaging and telecommunications. The only available space-qualified Digital Signal Processor (DSP) free of International Traffic in Arms Regulations (ITAR) restrictions faces inadequate performance, thus the development of a next generation European DSP is well known to the space community. The DSPACE space-qualified DSP architecture fills the gap between the computational requirements and the available devices. It leverages a pipelined and massively parallel core based on the Very Long Instruction Word (VLIW) paradigm, with 64 registers and 8 operational units, along with cache memories, memory controllers and SpaceWire interfaces. Both the synthesizable VHDL and the software development tools are generated from the LISA high-level model. A Xilinx-XC7K325T FPGA is chosen to realize a compact PCI demonstrator board. Finally first synthesis results on CMOS standard cell technology (ASIC 180 nm) show an area of around 380 kgates and a peak performance of 1000 MIPS and 750 MFLOPS at 125MHz.

High dynamic range adaptive real-time smart camera: an overview of the HDR-ARTiST project

NASA Astrophysics Data System (ADS)

Lapray, Pierre-Jean; Heyrman, Barthélémy; Ginhac, Dominique

2015-04-01

Standard cameras capture only a fraction of the information that is visible to the human visual system. This is specifically true for natural scenes including areas of low and high illumination due to transitions between sunlit and shaded areas. When capturing such a scene, many cameras are unable to store the full Dynamic Range (DR) resulting in low quality video where details are concealed in shadows or washed out by sunlight. The imaging technique that can overcome this problem is called HDR (High Dynamic Range) imaging. This paper describes a complete smart camera built around a standard off-the-shelf LDR (Low Dynamic Range) sensor and a Virtex-6 FPGA board. This smart camera called HDR-ARtiSt (High Dynamic Range Adaptive Real-time Smart camera) is able to produce a real-time HDR live video color stream by recording and combining multiple acquisitions of the same scene while varying the exposure time. This technique appears as one of the most appropriate and cheapest solution to enhance the dynamic range of real-life environments. HDR-ARtiSt embeds real-time multiple captures, HDR processing, data display and transfer of a HDR color video for a full sensor resolution (1280 1024 pixels) at 60 frames per second. The main contributions of this work are: (1) Multiple Exposure Control (MEC) dedicated to the smart image capture with alternating three exposure times that are dynamically evaluated from frame to frame, (2) Multi-streaming Memory Management Unit (MMMU) dedicated to the memory read/write operations of the three parallel video streams, corresponding to the different exposure times, (3) HRD creating by combining the video streams using a specific hardware version of the Devebecs technique, and (4) Global Tone Mapping (GTM) of the HDR scene for display on a standard LCD monitor.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array—Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

PubMed Central

Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-01-01

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array—application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. PMID:28672813

Real-Time Spaceborne Synthetic Aperture Radar Float-Point Imaging System Using Optimized Mapping Methodology and a Multi-Node Parallel Accelerating Technique

PubMed Central

Li, Bingyi; Chen, Liang; Yu, Wenyue; Xie, Yizhuang; Bian, Mingming; Zhang, Qingjun; Pang, Long

2018-01-01

With the development of satellite load technology and very large-scale integrated (VLSI) circuit technology, on-board real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. A key goal of the on-board SAR imaging system design is to achieve high real-time processing performance under severe size, weight, and power consumption constraints. This paper presents a multi-node prototype system for real-time SAR imaging processing. We decompose the commonly used chirp scaling (CS) SAR imaging algorithm into two parts according to the computing features. The linearization and logic-memory optimum allocation methods are adopted to realize the nonlinear part in a reconfigurable structure, and the two-part bandwidth balance method is used to realize the linear part. Thus, float-point SAR imaging processing can be integrated into a single Field Programmable Gate Array (FPGA) chip instead of relying on distributed technologies. A single-processing node requires 10.6 s and consumes 17 W to focus on 25-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. The design methodology of the multi-FPGA parallel accelerating system under the real-time principle is introduced. As a proof of concept, a prototype with four processing nodes and one master node is implemented using a Xilinx xc6vlx315t FPGA. The weight and volume of one single machine are 10 kg and 32 cm × 24 cm × 20 cm, respectively, and the power consumption is under 100 W. The real-time performance of the proposed design is demonstrated on Chinese Gaofen-3 stripmap continuous imaging. PMID:29495637

An embedded face-classification system for infrared images on an FPGA

NASA Astrophysics Data System (ADS)

Soto, Javier E.; Figueroa, Miguel

2014-10-01

We present a face-classification architecture for long-wave infrared (IR) images implemented on a Field Programmable Gate Array (FPGA). The circuit is fast, compact and low power, can recognize faces in real time and be embedded in a larger image-processing and computer vision system operating locally on an IR camera. The algorithm uses Local Binary Patterns (LBP) to perform feature extraction on each IR image. First, each pixel in the image is represented as an LBP pattern that encodes the similarity between the pixel and its neighbors. Uniform LBP codes are then used to reduce the number of patterns to 59 while preserving more than 90% of the information contained in the original LBP representation. Then, the image is divided into 64 non-overlapping regions, and each region is represented as a 59-bin histogram of patterns. Finally, the algorithm concatenates all 64 regions to create a 3,776-bin spatially enhanced histogram. We reduce the dimensionality of this histogram using Linear Discriminant Analysis (LDA), which improves clustering and enables us to store an entire database of 53 subjects on-chip. During classification, the circuit applies LBP and LDA to each incoming IR image in real time, and compares the resulting feature vector to each pattern stored in the local database using the Manhattan distance. We implemented the circuit on a Xilinx Artix-7 XC7A100T FPGA and tested it with the UCHThermalFace database, which consists of 28 81 x 150-pixel images of 53 subjects in indoor and outdoor conditions. The circuit achieves a 98.6% hit ratio, trained with 16 images and tested with 12 images of each subject in the database. Using a 100 MHz clock, the circuit classifies 8,230 images per second, and consumes only 309mW.

Rapid-X - An FPGA Development Toolset Using a Custom Simulink Library for MTCA.4 Modules

NASA Astrophysics Data System (ADS)

Prędki, Paweł; Heuer, Michael; Butkowski, Łukasz; Przygoda, Konrad; Schlarb, Holger; Napieralski, Andrzej

2015-06-01

The recent introduction of advanced hardware architectures such as the Micro Telecommunications Computing Architecture (MTCA) caused a change in the approach to implementation of control schemes in many fields. The development has been moving away from traditional programming languages ( C/C++), to hardware description languages (VHDL, Verilog), which are used in FPGA development. With MATLAB/Simulink it is possible to describe complex systems with block diagrams and simulate their behavior. Those diagrams are then used by the HDL experts to implement exactly the required functionality in hardware. Both the porting of existing applications and adaptation of new ones require a lot of development time from them. To solve this, Xilinx System Generator, a toolbox for MATLAB/Simulink, allows rapid prototyping of those block diagrams using hardware modelling. It is still up to the firmware developer to merge this structure with the hardware-dependent HDL project. This prevents the application engineer from quickly verifying the proposed schemes in real hardware. The framework described in this article overcomes these challenges, offering a hardware-independent library of components that can be used in Simulink/System Generator models. The components are subsequently translated into VHDL entities and integrated with a pre-prepared VHDL project template. Furthermore, the entire implementation process is run in the background, giving the user an almost one-click path from control scheme modelling and simulation to bit-file generation. This approach allows the application engineers to quickly develop new schemes and test them in real hardware environment. The applications may range from simple data logging or signal generation ones to very advanced controllers. Taking advantage of the Simulink simulation capabilities and user-friendly hardware implementation routines, the framework significantly decreases the development time of FPGA-based applications.

An orthogonal wavelet division multiple-access processor architecture for LTE-advanced wireless/radio-over-fiber systems over heterogeneous networks

NASA Astrophysics Data System (ADS)

Mahapatra, Chinmaya; Leung, Victor CM; Stouraitis, Thanos

2014-12-01

The increase in internet traffic, number of users, and availability of mobile devices poses a challenge to wireless technologies. In long-term evolution (LTE) advanced system, heterogeneous networks (HetNet) using centralized coordinated multipoint (CoMP) transmitting radio over optical fibers (LTE A-ROF) have provided a feasible way of satisfying user demands. In this paper, an orthogonal wavelet division multiple-access (OWDMA) processor architecture is proposed, which is shown to be better suited to LTE advanced systems as compared to orthogonal frequency division multiple access (OFDMA) as in LTE systems 3GPP rel.8 (3GPP, http://www.3gpp.org/DynaReport/36300.htm). ROF systems are a viable alternative to satisfy large data demands; hence, the performance in ROF systems is also evaluated. To validate the architecture, the circuit is designed and synthesized on a Xilinx vertex-6 field-programmable gate array (FPGA). The synthesis results show that the circuit performs with a clock period as short as 7.036 ns (i.e., a maximum clock frequency of 142.13 MHz) for transform size of 512. A pipelined version of the architecture reduces the power consumption by approximately 89%. We compare our architecture with similar available architectures for resource utilization and timing and provide performance comparison with OFDMA systems for various quality metrics of communication systems. The OWDMA architecture is found to perform better than OFDMA for bit error rate (BER) performance versus signal-to-noise ratio (SNR) in wireless channel as well as ROF media. It also gives higher throughput and mitigates the bad effect of peak-to-average-power ratio (PAPR).

ICE: A Scalable, Low-Cost FPGA-Based Telescope Signal Processing and Networking System

NASA Astrophysics Data System (ADS)

Bandura, K.; Bender, A. N.; Cliche, J. F.; de Haan, T.; Dobbs, M. A.; Gilbert, A. J.; Griffin, S.; Hsyu, G.; Ittah, D.; Parra, J. Mena; Montgomery, J.; Pinsonneault-Marotte, T.; Siegel, S.; Smecher, G.; Tang, Q. Y.; Vanderlinde, K.; Whitehorn, N.

2016-03-01

We present an overview of the ‘ICE’ hardware and software framework that implements large arrays of interconnected field-programmable gate array (FPGA)-based data acquisition, signal processing and networking nodes economically. The system was conceived for application to radio, millimeter and sub-millimeter telescope readout systems that have requirements beyond typical off-the-shelf processing systems, such as careful control of interference signals produced by the digital electronics, and clocking of all elements in the system from a single precise observatory-derived oscillator. A new generation of telescopes operating at these frequency bands and designed with a vastly increased emphasis on digital signal processing to support their detector multiplexing technology or high-bandwidth correlators — data rates exceeding a terabyte per second — are becoming common. The ICE system is built around a custom FPGA motherboard that makes use of an Xilinx Kintex-7 FPGA and ARM-based co-processor. The system is specialized for specific applications through software, firmware and custom mezzanine daughter boards that interface to the FPGA through the industry-standard FPGA mezzanine card (FMC) specifications. For high density applications, the motherboards are packaged in 16-slot crates with ICE backplanes that implement a low-cost passive full-mesh network between the motherboards in a crate, allow high bandwidth interconnection between crates and enable data offload to a computer cluster. A Python-based control software library automatically detects and operates the hardware in the array. Examples of specific telescope applications of the ICE framework are presented, namely the frequency-multiplexed bolometer readout systems used for the South Pole Telescope (SPT) and Simons Array and the digitizer, F-engine, and networking engine for the Canadian Hydrogen Intensity Mapping Experiment (CHIME) and Hydrogen Intensity and Real-time Analysis eXperiment (HIRAX) radio interferometers.

Real-time implementation of a multispectral mine target detection algorithm

NASA Astrophysics Data System (ADS)

Samson, Joseph W.; Witter, Lester J.; Kenton, Arthur C.; Holloway, John H., Jr.

2003-09-01

Spatial-spectral anomaly detection (the "RX Algorithm") has been exploited on the USMC's Coastal Battlefield Reconnaissance and Analysis (COBRA) Advanced Technology Demonstration (ATD) and several associated technology base studies, and has been found to be a useful method for the automated detection of surface-emplaced antitank land mines in airborne multispectral imagery. RX is a complex image processing algorithm that involves the direct spatial convolution of a target/background mask template over each multispectral image, coupled with a spatially variant background spectral covariance matrix estimation and inversion. The RX throughput on the ATD was about 38X real time using a single Sun UltraSparc system. A goal to demonstrate RX in real-time was begun in FY01. We now report the development and demonstration of a Field Programmable Gate Array (FPGA) solution that achieves a real-time implementation of the RX algorithm at video rates using COBRA ATD data. The approach uses an Annapolis Microsystems Firebird PMC card containing a Xilinx XCV2000E FPGA with over 2,500,000 logic gates and 18MBytes of memory. A prototype system was configured using a Tek Microsystems VME board with dual-PowerPC G4 processors and two PMC slots. The RX algorithm was translated from its C programming implementation into the VHDL language and synthesized into gates that were loaded into the FPGA. The VHDL/synthesizer approach allows key RX parameters to be quickly changed and a new implementation automatically generated. Reprogramming the FPGA is done rapidly and in-circuit. Implementation of the RX algorithm in a single FPGA is a major first step toward achieving real-time land mine detection.

An FPGA-based High Speed Parallel Signal Processing System for Adaptive Optics Testbed

NASA Astrophysics Data System (ADS)

Kim, H.; Choi, Y.; Yang, Y.

In this paper a state-of-the-art FPGA (Field Programmable Gate Array) based high speed parallel signal processing system (SPS) for adaptive optics (AO) testbed with 1 kHz wavefront error (WFE) correction frequency is reported. The AO system consists of Shack-Hartmann sensor (SHS) and deformable mirror (DM), tip-tilt sensor (TTS), tip-tilt mirror (TTM) and an FPGA-based high performance SPS to correct wavefront aberrations. The SHS is composed of 400 subapertures and the DM 277 actuators with Fried geometry, requiring high speed parallel computing capability SPS. In this study, the target WFE correction speed is 1 kHz; therefore, it requires massive parallel computing capabilities as well as strict hard real time constraints on measurements from sensors, matrix computation latency for correction algorithms, and output of control signals for actuators. In order to meet them, an FPGA based real-time SPS with parallel computing capabilities is proposed. In particular, the SPS is made up of a National Instrument's (NI's) real time computer and five FPGA boards based on state-of-the-art Xilinx Kintex 7 FPGA. Programming is done with NI's LabView environment, providing flexibility when applying different algorithms for WFE correction. It also facilitates faster programming and debugging environment as compared to conventional ones. One of the five FPGA's is assigned to measure TTS and calculate control signals for TTM, while the rest four are used to receive SHS signal, calculate slops for each subaperture and correction signal for DM. With this parallel processing capabilities of the SPS the overall closed-loop WFE correction speed of 1 kHz has been achieved. System requirements, architecture and implementation issues are described; furthermore, experimental results are also given.

FPGA wavelet processor design using language for instruction-set architectures (LISA)

NASA Astrophysics Data System (ADS)

Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

2007-04-01

The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.

A bunch to bucket phase detector for the RHIC LLRF upgrade platform

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, K.S.; Harvey, M.; Hayes, T.

2011-03-28

As part of the overall development effort for the RHIC LLRF Upgrade Platform [1,2,3], a generic four channel 16 bit Analog-to-Digital Converter (ADC) daughter module was developed to provide high speed, wide dynamic range digitizing and processing of signals from DC to several hundred megahertz. The first operational use of this card was to implement the bunch to bucket phase detector for the RHIC LLRF beam control feedback loops. This paper will describe the design and performance features of this daughter module as a bunch to bucket phase detector, and also provide an overview of its place within the overallmore » LLRF platform architecture as a high performance digitizer and signal processing module suitable to a variety of applications. In modern digital control and signal processing systems, ADCs provide the interface between the analog and digital signal domains. Once digitized, signals are then typically processed using algorithms implemented in field programmable gate array (FPGA) logic, general purpose processors (GPPs), digital signal processors (DSPs) or a combination of these. For the recently developed and commissioned RHIC LLRF Upgrade Platform, we've developed a four channel ADC daughter module based on the Linear Technology LTC2209 16 bit, 160 MSPS ADC and the Xilinx V5FX70T FPGA. The module is designed to be relatively generic in application, and with minimal analog filtering on board, is capable of processing signals from DC to 500 MHz or more. The module's first application was to implement the bunch to bucket phase detector (BTB-PD) for the RHIC LLRF system. The same module also provides DC digitizing of analog processed BPM signals used by the LLRF system for radial feedback.« less

Design of the SLAC RCE Platform: A General Purpose ATCA Based Data Acquisition System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Herbst, R.; Claus, R.; Freytag, M.

2015-01-23

The SLAC RCE platform is a general purpose clustered data acquisition system implemented on a custom ATCA compliant blade, called the Cluster On Board (COB). The core of the system is the Reconfigurable Cluster Element (RCE), which is a system-on-chip design based upon the Xilinx Zynq family of FPGAs, mounted on custom COB daughter-boards. The Zynq architecture couples a dual core ARM Cortex A9 based processor with a high performance 28nm FPGA. The RCE has 12 external general purpose bi-directional high speed links, each supporting serial rates of up to 12Gbps. 8 RCE nodes are included on a COB, eachmore » with a 10Gbps connection to an on-board 24-port Ethernet switch integrated circuit. The COB is designed to be used with a standard full-mesh ATCA backplane allowing multiple RCE nodes to be tightly interconnected with minimal interconnect latency. Multiple shelves can be clustered using the front panel 10-gbps connections. The COB also supports local and inter-blade timing and trigger distribution. An experiment specific Rear Transition Module adapts the 96 high speed serial links to specific experiments and allows an experiment-specific timing and busy feedback connection. This coupling of processors with a high performance FPGA fabric in a low latency, multiple node cluster allows high speed data processing that can be easily adapted to any physics experiment. RTEMS and Linux are both ported to the module. The RCE has been used or is the baseline for several current and proposed experiments (LCLS, HPS, LSST, ATLAS-CSC, LBNE, DarkSide, ILC-SiD, etc).« less

IEEE 1588 Time Synchronization Board in MTCA.4 Form Factor

NASA Astrophysics Data System (ADS)

Jabłoński, G.; Makowski, D.; Mielczarek, A.; Orlikowski, M.; Perek, P.; Napieralski, A.; Makijarvi, P.; Simrock, S.

2015-06-01

Distributed data acquisition and control systems in large-scale scientific experiments, like e.g. ITER, require time synchronization with nanosecond precision. A protocol commonly used for that purpose is the Precise Timing Protocol (PTP), also known as IEEE 1588 standard. It uses the standard Ethernet signalling and protocols and allows obtaining timing accuracy of the order of tens of nanoseconds. The MTCA.4 is gradually becoming the platform of choice for building such systems. Currently there is no commercially available implementation of the PTP receiver on that platform. In this paper, we present a module in the MTCA.4 form factor supporting this standard. The module may be used as a timing receiver providing reference clocks in an MTCA.4 chassis, generating a Pulse Per Second (PPS) signal and allowing generation of triggers and timestamping of events on 8 configurable backplane lines and two front panel connectors. The module is based on the Xilinx Spartan 6 FPGA and thermally stabilized Voltage Controlled Oscillator controlled by the digital-to-analog converter. The board supports standalone operation, without the support from the host operating system, as the entire control algorithm is run on a Microblaze CPU implemented in the FPGA. The software support for the card includes the low-level API in the form of Linux driver, user-mode library, high-level API: ITER Nominal Device Support and EPICS IOC. The device has been tested in the ITER timing distribution network (TCN) with three cascaded PTP-enabled Hirschmann switches and a GPS reference clock source. An RMS synchronization accuracy, measured by direct comparison of the PPS signals, better than 20 ns has been obtained.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

PubMed

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-06-24

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

First results of the silicon telescope using an 'artificial retina' for fast track finding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Neri, N.; Abba, A.; Caponio, F.

We present the first results of the prototype of a silicon tracker with trigger capabilities based on a novel approach for fast track finding. The working principle of the 'artificial retina' is inspired by the processing of visual images by the brain and it is based on extensive parallelization of data distribution and pattern recognition. The algorithm has been implemented in commercial FPGAs in three main logic modules: a switch for the routing of the detector hits, a pool of engines for the digital processing of the hits, and a block for the calculation of the track parameters. The architecturemore » is fully pipelined and allows the reconstruction of real-time tracks with a latency less then 100 clock cycles, corresponding to 0.25 microsecond at 400 MHz clock. The silicon telescope consists of 8 layers of single-sided silicon strip detectors with 512 strips each. The detector size is about 10 cm x 10 cm and the strip pitch is 183 μm. The detectors are read out by the Beetle chip, a custom ASICs developed for LHCb, which provides the measurement of the hit position and pulse height of 128 channels. The 'artificial retina' algorithm has been implemented on custom data acquisition boards based on FPGAs Xilinx Kintex 7 lx160. The parameters of the tracks detected are finally transferred to host PC via USB 3.0. The boards manage the read-out ASICs and the sampling of the analog channels. The read-out is performed at 40 MHz on 4 channels for each ASIC that corresponds to a decoding of the telescope information at 1.1 MHz. We report on the first results of the fast tracking device and compare with simulations. (authors)« less

PiHi Observations at the ATA, Conventional and Unconventional SETI

NASA Astrophysics Data System (ADS)

Harp, Gerald; Wilcox, B.; Arbunich, J.; Blair, S.; Backus, P. R.; Tarter, J. C.; Shostak, S.; Jordan, J.; Kilsdonk, T.; Ackermann, R. F.; Ross, J.; ATA Team

2010-01-01

Many radio SETI searches focus on the frequency range where the HI (1.42 GHz) and OH lines (1.6-1.7 GHz) lines are landmarks delineating the water hole This is only a small fraction of the terrestrial microwave window (TMW) from 1-10 GHz. This survey occurs near the center of the TMW at 4.462336275 GHz or π times the HI frequency. We call this the PiHI ("pie high") survey. The inspiration for PiHI observations comes from Carl Sagan in his book, Contact. This survey builds upon and extends a previous survey at PiHI (Blair, D. G. et al. (1992), MNRAS, 257, 105) with greater sensitivity, resolution, and coverage. We survey the nearest 94 main sequence stars in the HabCat catalog (Turnbull, M. C. and Tarter, J. C. (2003), ApJS, 145, 181) with spectral classes between F9 and G7 (max. radius 62 pc). The ATA's flexibility allows simultaneous measurements of targeted observations on stars (with beamformers) and 1° FOV "blind” observations of the areas around target stars (with imaging correlator). The targeted observations are carried out with a high resolution (0.7 Hz) spectrometer and integration times on the order of 200 s. The spectral imaging correlator measures a 50 x 50 grid of points with 3 kHz spectral resolution. This survey shows several signals of minor interest were discovered, though none of the signals reported are continuously "on,” which is an important characteristic for the positive identification of an ETI signal. The ATA has been funded through generous grants from the Paul G. Allen Family Foundation, the SETI Institute, UC Berkeley, the National Science Foundation (Grant No. 0540599), Sun Microsystems, Xilinx, Nathan Myhrvold, Greg Papadopoulos, and other corporations and individual donors.

Harmonic analysis and FPGA implementation of SHE controlled three phase CHB 11-level inverter in MV drives using deterministic and stochastic optimization techniques.

PubMed

Vesapogu, Joshi Manohar; Peddakotla, Sujatha; Kuppa, Seetha Rama Anjaneyulu

2013-01-01

With the advancements in semiconductor technology, high power medium voltage (MV) Drives are extensively used in numerous industrial applications. Challenging technical requirements of MV Drives is to control multilevel inverter (MLI) with less Total harmonic distortion (%THD) which satisfies IEEE standard 519-1992 harmonic guidelines and less switching losses. Among all modulation control strategies for MLI, Selective harmonic elimination (SHE) technique is one of the traditionally preferred modulation control technique at fundamental switching frequency with better harmonic profile. On the other hand, the equations which are formed by SHE technique are highly non-linear in nature, may exist multiple, single or even no solution at particular modulation index (MI). However, in some MV Drive applications, it is required to operate over a range of MI. Providing analytical solutions for SHE equations during the whole range of MI from 0 to 1, has been a challenging task for researchers. In this paper, an attempt is made to solve SHE equations by using deterministic and stochastic optimization methods and comparative harmonic analysis has been carried out. An effective algorithm which minimizes %THD with less computational effort among all optimization algorithms has been presented. To validate the effectiveness of proposed MPSO technique, an experiment is carried out on a low power proto type of three phase CHB 11- level Inverter using FPGA based Xilinx's Spartan -3A DSP Controller. The experimental results proved that MPSO technique has successfully solved SHE equations over all range of MI from 0 to 1, the %THD obtained over major range of MI also satisfies IEEE 519-1992 harmonic guidelines too.

A custom hardware classifier for bruised apple detection in hyperspectral images

NASA Astrophysics Data System (ADS)

Cárdenas, Javier; Figueroa, Miguel; Pezoa, Jorge E.

2015-09-01

We present a custom digital architecture for bruised apple classification using hyperspectral images in the near infrared (NIR) spectrum. The algorithm classifies each pixel in an image into one of three classes: bruised, non-bruised, and background. We extract two 5-element feature vectors for each pixel using only 10 out of the 236 spectral bands provided by the hyperspectral camera, thereby greatly reducing both the requirements of the imager and the computational complexity of the algorithm. We then use two linear-kernel support vector machine (SVM) to classify each pixel. Each SVM was trained with 504 windows of size 17×17-pixel taken from 14 hyperspectral images of 320×320 pixels each, for each class. The architecture then computes the percentage of bruised pixels in each apple in order to adequately classify the fruit. We implemented the architecture on a Xilinx Zynq Z-7010 field-programmable gate array (FPGA) and tested it on images from a NIR N17E push-broom camera with a frame rate of 25 fps, a band-pixel rate of 1.888 MHz, and 236 spectral bands between 900 and 1700 nanometers in laboratory conditions. Using 28-bit fixed-point arithmetic, the circuit accurately discriminates 95.2% of the pixels corresponding to an apple, 81% of the pixels corresponding to a bruised apple, and 96.4% of the background. With the default threshold settings, the highest false positive (FP) for a bruised apple is 18.7%. The circuit operates at the native frame rate of the camera, consumes 67 mW of dynamic power, and uses less than 10% of the logic resources on the FPGA.

A wireless transmission neural interface system for unconstrained non-human primates.

PubMed

Fernandez-Leon, Jose A; Parajuli, Arun; Franklin, Robert; Sorenson, Michael; Felleman, Daniel J; Hansen, Bryan J; Hu, Ming; Dragoi, Valentin

2015-10-01

Studying the brain in large animal models in a restrained laboratory rig severely limits our capacity to examine brain circuits in experimental and clinical applications. To overcome these limitations, we developed a high-fidelity 96-channel wireless system to record extracellular spikes and local field potentials from the neocortex. A removable, external case of the wireless device is attached to a titanium pedestal placed in the animal skull. Broadband neural signals are amplified, multiplexed, and continuously transmitted as TCP/IP data at a sustained rate of 24 Mbps. A Xilinx Spartan 6 FPGA assembles the digital signals into serial data frames for transmission at 20 kHz though an 802.11n wireless data link on a frequency-shift key-modulated signal at 5.7-5.8 GHz to a receiver up to 10 m away. The system is powered by two CR123A, 3 V batteries for 2 h of operation. We implanted a multi-electrode array in visual area V4 of one anesthetized monkey (Macaca fascicularis) and in the dorsolateral prefrontal cortex (dlPFC) of a freely moving monkey (Macaca mulatta). The implanted recording arrays were electrically stable and delivered broadband neural data over a year of testing. For the first time, we compared dlPFC neuronal responses to the same set of stimuli (food reward) in restrained and freely moving conditions. Although we did not find differences in neuronal responses as a function of reward type in the restrained and unrestrained conditions, there were significant differences in correlated activity. This demonstrates that measuring neural responses in freely moving animals can capture phenomena that are absent in the traditional head-fixed paradigm. We implemented a wireless neural interface for multi-electrode recordings in freely moving non-human primates, which can potentially move systems neuroscience to a new direction by allowing one to record neural signals while animals interact with their environment.

A wireless transmission neural interface system for unconstrained non-human primates

PubMed Central

Fernandez-Leon, Jose A.; Parajuli, Arun; Franklin, Robert; Sorenson, Michael; Felleman, Daniel J.; Hansen, Bryan J.; Hu, Ming; Dragoi, Valentin

2018-01-01

Objective Studying the brain in large animal models in a restrained laboratory rig severely limits our capacity to examine brain circuits in experimental and clinical applications. Approach To overcome these limitations, we developed a high-fidelity 96-channel wireless system to record extracellular spikes and local field potentials from neocortex. A removable, external case of the wireless device is attached to a titanium pedestal placed in the animal skull. Broadband neural signals are amplified, multiplexed, and continuously transmitted as TCP/IP data at a sustained rate of 24 Mbps. A Xilinx Spartan 6 FPGA assembles the digital signals into serial data frames for transmission at 20 kHz though an 802.11n wireless data link on a frequency shift key modulated signal at 5.7-5.8 GHz to a receiver up to 10 m away. The system is powered by two CR123A, 3-V batteries for 2 hours of operation. Main results We implanted a multi-electrode array in visual area V4 of one anesthetized monkey (Macaca fascicularis) and in the dorsolateral prefrontal cortex (dlPFC) of a freely moving monkey (Macaca mulatta). The implanted recording arrays were electrically stable and delivered broadband neural data over a year of testing. For the first time, we compared dlPFC neuronal responses to the same set of stimuli (food reward) in restrained and freely moving conditions. Although we did not find differences in neuronal responses as a function of reward type in the restrained and unrestrained conditions, there were significant differences in correlated activity. This demonstrates that measuring neural responses in freely-moving animals can capture phenomena that are absent in the traditional head-fixed paradigm. Significance We implemented a wireless neural interface for multi-electrode recordings in freely moving non-human primates which can potentially move systems neuroscience to a new direction by allowing to record neural signals while animals interact with their environment. PMID:26269496

A traffic analyzer for multiple SpaceWire links

NASA Astrophysics Data System (ADS)

Liu, Scige J.; Giusi, Giovanni; Di Giorgio, Anna M.; Vertolli, Nello; Galli, Emanuele; Biondi, David; Farina, Maria; Pezzuto, Stefano; Spinoglio, Luigi

2014-07-01

Modern space missions are becoming increasingly complex: the interconnection of the units in a satellite is now a network of terminals linked together through routers, where devices with different level of automation and intelligence share the same data-network. The traceability of the network transactions is performed mostly at terminal level through log analysis and hence it is difficult to verify in real time the reliability of the interconnections and the interchange protocols. To improve and ease the traffic analysis in a SpaceWire network we implemented a low-level link analyzer, with the specific goal to simplify the integration and test phases in the development of space instrumentation. The traffic analyzer collects signals coming from pod probes connected in-series on the interested links between two SpaceWire terminals. With respect to the standard traffic analyzers, the design of this new tool includes the possibility to internally reshape the LVDS signal. This improvement increases the robustness of the analyzer towards environmental noise effects and guarantees a deterministic delay on all analyzed signals. The analyzer core is implemented on a Xilinx FPGA, programmed to decode the bidirectional LVDS signals at Link and Network level. Successively, the core packetizes protocol characters in homogeneous sets of time ordered events. The analyzer provides time-tagging functionality for each characters set, with a precision down to the FPGA Clock, i.e. about 20nsec in the adopted HW environment. The use of a common time reference for each character stream allows synchronous performance measurements. The collected information is then routed to an external computer for quick analysis: this is done via high-speed USB2 connection. With this analyzer it is possible to verify the link performances in terms of induced delays in the transmitted signals. A case study focused on the analysis of the Time-Code synchronization in presence of a SpaceWire Router is shown in this paper as well.

Fast particles identification in programmable form at level-0 trigger by means of the 3D-Flow system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Crosetto, Dario B.

1998-10-30

The 3D-Flow Processor system is a new, technology-independent concept in very fast, real-time system architectures. Based on either an FPGA or an ASIC implementation, it can address, in a fully programmable manner, applications where commercially available processors would fail because of throughput requirements. Possible applications include filtering-algorithms (pattern recognition) from the input of multiple sensors, as well as moving any input validated by these filtering-algorithms to a single output channel. Both operations can easily be implemented on a 3D-Flow system to achieve a real-time processing system with a very short lag time. This system can be built either with off-the-shelfmore » FPGAs or, for higher data rates, with CMOS chips containing 4 to 16 processors each. The basic building block of the system, a 3D-Flow processor, has been successfully designed in VHDL code written in ''Generic HDL'' (mostly made of reusable blocks that are synthesizable in different technologies, or FPGAs), to produce a netlist for a four-processor ASIC featuring 0.35 micron CBA (Ceil Base Array) technology at 3.3 Volts, 884 mW power dissipation at 60 MHz and 63.75 mm sq. die size. The same VHDL code has been targeted to three FPGA manufacturers (Altera EPF10K250A, ORCA-Lucent Technologies 0R3T165 and Xilinx XCV1000). A complete set of software tools, the 3D-Flow System Manager, equally applicable to ASIC or FPGA implementations, has been produced to provide full system simulation, application development, real-time monitoring, and run-time fault recovery. Today's technology can accommodate 16 processors per chip in a medium size die, at a cost per processor of less than $5 based on the current silicon die/size technology cost.« less

Development of an ADC radiation tolerance characterization system for the upgrade of the ATLAS LAr calorimeter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Hong-Bin; Chen, Hu-Cheng; Chen, Kai

ATLAS LAr calorimeter will undergo its Phase-I upgrade during the long shutdown (LS2) in 2018, and a new LAr Trigger Digitizer Board (LTDB) will be designed and installed. Several commercial-off-the-shelf (COTS) multi-channel high-speed ADCs have been selected as possible backups of the radiation tolerant ADC ASICs for the LTDB. Here, to evaluate the radiation tolerance of these backup commercial ADCs, we developed an ADC radiation tolerance characterization system, which includes the ADC boards, data acquisition (DAQ) board, signal generator, external power supplies and a host computer. The ADC board is custom designed for different ADCs, with ADC drivers and clockmore » distribution circuits integrated on board. The Xilinx ZC706 FPGA development board is used as a DAQ board. The data from the ADC are routed to the FPGA through the FMC (FPGA Mezzanine Card) connector, de-serialized and monitored by the FPGA, and then transmitted to the host computer through the Gigabit Ethernet. A software program has been developed with Python, and all the commands are sent to the DAQ board through Gigabit Ethernet by this program. Two ADC boards have been designed for the ADC, ADS52J90 from Texas Instruments and AD9249 from Analog Devices respectively. TID tests for both ADCs have been performed at BNL, and an SEE test for the ADS52J90 has been performed at Massachusetts General Hospital (MGH). Test results have been analyzed and presented. The test results demonstrate that this test system is very versatile, and works well for the radiation tolerance characterization of commercial multi-channel high-speed ADCs for the upgrade of the ATLAS LAr calorimeter. It is applicable to other collider physics experiments where radiation tolerance is required as well.« less

Rapid algorithm prototyping and implementation for power quality measurement

NASA Astrophysics Data System (ADS)

Kołek, Krzysztof; Piątek, Krzysztof

2015-12-01

This article presents a Model-Based Design (MBD) approach to rapidly implement power quality (PQ) metering algorithms. Power supply quality is a very important aspect of modern power systems and will become even more important in future smart grids. In this case, maintaining the PQ parameters at the desired level will require efficient implementation methods of the metering algorithms. Currently, the development of new, advanced PQ metering algorithms requires new hardware with adequate computational capability and time intensive, cost-ineffective manual implementations. An alternative, considered here, is an MBD approach. The MBD approach focuses on the modelling and validation of the model by simulation, which is well-supported by a Computer-Aided Engineering (CAE) packages. This paper presents two algorithms utilized in modern PQ meters: a phase-locked loop based on an Enhanced Phase Locked Loop (EPLL), and the flicker measurement according to the IEC 61000-4-15 standard. The algorithms were chosen because of their complexity and non-trivial development. They were first modelled in the MATLAB/Simulink package, then tested and validated in a simulation environment. The models, in the form of Simulink diagrams, were next used to automatically generate C code. The code was compiled and executed in real-time on the Zynq Xilinx platform that combines a reconfigurable Field Programmable Gate Array (FPGA) with a dual-core processor. The MBD development of PQ algorithms, automatic code generation, and compilation form a rapid algorithm prototyping and implementation path for PQ measurements. The main advantage of this approach is the ability to focus on the design, validation, and testing stages while skipping over implementation issues. The code generation process renders production-ready code that can be easily used on the target hardware. This is especially important when standards for PQ measurement are in constant development, and the PQ issues in emerging smart grids will require tools for rapid development and implementation of such algorithms.

Development of an ADC radiation tolerance characterization system for the upgrade of the ATLAS LAr calorimeter

DOE PAGES

Liu, Hong-Bin; Chen, Hu-Cheng; Chen, Kai; ...

2017-02-01

ATLAS LAr calorimeter will undergo its Phase-I upgrade during the long shutdown (LS2) in 2018, and a new LAr Trigger Digitizer Board (LTDB) will be designed and installed. Several commercial-off-the-shelf (COTS) multi-channel high-speed ADCs have been selected as possible backups of the radiation tolerant ADC ASICs for the LTDB. Here, to evaluate the radiation tolerance of these backup commercial ADCs, we developed an ADC radiation tolerance characterization system, which includes the ADC boards, data acquisition (DAQ) board, signal generator, external power supplies and a host computer. The ADC board is custom designed for different ADCs, with ADC drivers and clockmore » distribution circuits integrated on board. The Xilinx ZC706 FPGA development board is used as a DAQ board. The data from the ADC are routed to the FPGA through the FMC (FPGA Mezzanine Card) connector, de-serialized and monitored by the FPGA, and then transmitted to the host computer through the Gigabit Ethernet. A software program has been developed with Python, and all the commands are sent to the DAQ board through Gigabit Ethernet by this program. Two ADC boards have been designed for the ADC, ADS52J90 from Texas Instruments and AD9249 from Analog Devices respectively. TID tests for both ADCs have been performed at BNL, and an SEE test for the ADS52J90 has been performed at Massachusetts General Hospital (MGH). Test results have been analyzed and presented. The test results demonstrate that this test system is very versatile, and works well for the radiation tolerance characterization of commercial multi-channel high-speed ADCs for the upgrade of the ATLAS LAr calorimeter. It is applicable to other collider physics experiments where radiation tolerance is required as well.« less

Development of an ADC radiation tolerance characterization system for the upgrade of the ATLAS LAr calorimeter

NASA Astrophysics Data System (ADS)

Liu, Hong-Bin; Chen, Hu-Cheng; Chen, Kai; Kierstead, James; Lanni, Francesco; Takai, Helio; Jin, Ge

2017-02-01

ATLAS LAr calorimeter will undergo its Phase-I upgrade during the long shutdown (LS2) in 2018, and a new LAr Trigger Digitizer Board (LTDB) will be designed and installed. Several commercial-off-the-shelf (COTS) multi-channel high-speed ADCs have been selected as possible backups of the radiation tolerant ADC ASICs for the LTDB. To evaluate the radiation tolerance of these backup commercial ADCs, we developed an ADC radiation tolerance characterization system, which includes the ADC boards, data acquisition (DAQ) board, signal generator, external power supplies and a host computer. The ADC board is custom designed for different ADCs, with ADC drivers and clock distribution circuits integrated on board. The Xilinx ZC706 FPGA development board is used as a DAQ board. The data from the ADC are routed to the FPGA through the FMC (FPGA Mezzanine Card) connector, de-serialized and monitored by the FPGA, and then transmitted to the host computer through the Gigabit Ethernet. A software program has been developed with Python, and all the commands are sent to the DAQ board through Gigabit Ethernet by this program. Two ADC boards have been designed for the ADC, ADS52J90 from Texas Instruments and AD9249 from Analog Devices respectively. TID tests for both ADCs have been performed at BNL, and an SEE test for the ADS52J90 has been performed at Massachusetts General Hospital (MGH). Test results have been analyzed and presented. The test results demonstrate that this test system is very versatile, and works well for the radiation tolerance characterization of commercial multi-channel high-speed ADCs for the upgrade of the ATLAS LAr calorimeter. It is applicable to other collider physics experiments where radiation tolerance is required as well. Supported by the U. S. Department of Energy (DE-SC001270)

LinoSPAD: a time-resolved 256×1 CMOS SPAD line sensor system featuring 64 FPGA-based TDC channels running at up to 8.5 giga-events per second

NASA Astrophysics Data System (ADS)

Burri, Samuel; Homulle, Harald; Bruschini, Claudio; Charbon, Edoardo

2016-04-01

LinoSPAD is a reconfigurable camera sensor with a 256×1 CMOS SPAD (single-photon avalanche diode) pixel array connected to a low cost Xilinx Spartan 6 FPGA. The LinoSPAD sensor's line of pixels has a pitch of 24 μm and 40% fill factor. The FPGA implements an array of 64 TDCs and histogram engines capable of processing up to 8.5 giga-photons per second. The LinoSPAD sensor measures 1.68 mm×6.8 mm and each pixel has a direct digital output to connect to the FPGA. The chip is bonded on a carrier PCB to connect to the FPGA motherboard. 64 carry chain based TDCs sampled at 400 MHz can generate a timestamp every 7.5 ns with a mean time resolution below 25 ps per code. The 64 histogram engines provide time-of-arrival histograms covering up to 50 ns. An alternative mode allows the readout of 28 bit timestamps which have a range of up to 4.5 ms. Since the FPGA TDCs have considerable non-linearity we implemented a correction module capable of increasing histogram linearity at real-time. The TDC array is interfaced to a computer using a super-speed USB3 link to transfer over 150k histograms per second for the 12.5 ns reference period used in our characterization. After characterization and subsequent programming of the post-processing we measure an instrument response histogram shorter than 100 ps FWHM using a strong laser pulse with 50 ps FWHM. A timing resolution that when combined with the high fill factor makes the sensor well suited for a wide variety of applications from fluorescence lifetime microscopy over Raman spectroscopy to 3D time-of-flight.

A wireless transmission neural interface system for unconstrained non-human primates

NASA Astrophysics Data System (ADS)

Fernandez-Leon, Jose A.; Parajuli, Arun; Franklin, Robert; Sorenson, Michael; Felleman, Daniel J.; Hansen, Bryan J.; Hu, Ming; Dragoi, Valentin

2015-10-01

Objective. Studying the brain in large animal models in a restrained laboratory rig severely limits our capacity to examine brain circuits in experimental and clinical applications. Approach. To overcome these limitations, we developed a high-fidelity 96-channel wireless system to record extracellular spikes and local field potentials from the neocortex. A removable, external case of the wireless device is attached to a titanium pedestal placed in the animal skull. Broadband neural signals are amplified, multiplexed, and continuously transmitted as TCP/IP data at a sustained rate of 24 Mbps. A Xilinx Spartan 6 FPGA assembles the digital signals into serial data frames for transmission at 20 kHz though an 802.11n wireless data link on a frequency-shift key-modulated signal at 5.7-5.8 GHz to a receiver up to 10 m away. The system is powered by two CR123A, 3 V batteries for 2 h of operation. Main results. We implanted a multi-electrode array in visual area V4 of one anesthetized monkey (Macaca fascicularis) and in the dorsolateral prefrontal cortex (dlPFC) of a freely moving monkey (Macaca mulatta). The implanted recording arrays were electrically stable and delivered broadband neural data over a year of testing. For the first time, we compared dlPFC neuronal responses to the same set of stimuli (food reward) in restrained and freely moving conditions. Although we did not find differences in neuronal responses as a function of reward type in the restrained and unrestrained conditions, there were significant differences in correlated activity. This demonstrates that measuring neural responses in freely moving animals can capture phenomena that are absent in the traditional head-fixed paradigm. Significance. We implemented a wireless neural interface for multi-electrode recordings in freely moving non-human primates, which can potentially move systems neuroscience to a new direction by allowing one to record neural signals while animals interact with their environment.

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EPA Pesticide Factsheets

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Federal Register 2010, 2011, 2012, 2013, 2014

2011-10-03

....aa; II.D.1.bb; II.D.1.kk; II.D.1.nn; II.D.1.oo; II.D.1.aaa; II.D.1.bbb; II.D.1.ccc; II.D.1.fff; II.D...; II.D.1.y; II.D.1.aa; II.D.1.bb; II.D.1.kk; II.D.1.nn; II.D.1.oo; II.D.1.aaa; II.D.1.bbb; II.D.1.ccc...

Free metal ion depletion by "Good's" buffers. III. N-(2-acetamido)iminodiacetic acid, 2:1 complexes with zinc(II), cobalt(II), nickel(II), and copper(II); amide deprotonation by Zn(II), Co(II), and Cu(II).

PubMed

Lance, E A; Rhodes, C W; Nakon, R

1983-09-01

Potentiometric, visible, infrared, electron spin, and nuclear magnetic resonance studies of the complexation of N-(2-acetamido)iminodiacetic acid (H2ADA) by Ca(II), Mg(II), Mn(II), Zn(II), Co(II), Ni(II), and Cu(II) are reported. Ca(II) and Mg(II) were found not to form 2:1 ADA2- to M(II) complexes, while Mn(II), Cu(II), Ni(II), Zn(II), and Co(II) did form 2:1 metal chelates at or below physiological pH values. Co(II) and Zn(II), but not Cu(II), were found to induce stepwise deprotonation of the amide groups to form [M(H-1ADA)4-(2)]. Formation (affinity) constants for the various metal complexes are reported, and the probable structures of the various metal chelates in solution are discussed on the basis of various spectral data.

First light on a new fully digital camera based on SiPM for CTA SST-1M telescope

NASA Astrophysics Data System (ADS)

della Volpe, Domenico; Al Samarai, Imen; Alispach, Cyril; Bulik, Tomasz; Borkowski, Jerzy; Cadoux, Franck; Coco, Victor; Favre, Yannick; Grudzińska, Mira; Heller, Matthieu; Jamrozy, Marek; Kasperek, Jerzy; Lyard, Etienne; Mach, Emil; Mandat, Dusan; Michałowski, Jerzy; Moderski, Rafal; Montaruli, Teresa; Neronov, Andrii; Niemiec, Jacek; Njoh Ekoume, T. R. S.; Ostrowski, Michal; Paśko, Paweł; Pech, Miroslav; Rajda, Pawel; Rafalski, Jakub; Schovanek, Petr; Seweryn, Karol; Skowron, Krzysztof; Sliusar, Vitalii; Stawarz, Łukasz; Stodulska, Magdalena; Stodulski, Marek; Travnicek, Petr; Troyano Pujadas, Isaac; Walter, Roland; Zagdański, Adam; Zietara, Krzysztof

2017-08-01

The Cherenkov Telescope Array (CTA) will explore with unprecedented precision the Universe in the gammaray domain covering an energy range from 50 GeV to more the 300 TeV. To cover such a broad range with a sensitivity which will be ten time better than actual instruments, different types of telescopes are needed: the Large Size Telescopes (LSTs), with a ˜24 m diameter mirror, a Medium Size Telescopes (MSTs), with a ˜12 m mirror and the small size telescopes (SSTs), with a ˜4 m diameter mirror. The single mirror small size telescope (SST-1M), one of the proposed solutions to become part of the small-size telescopes of CTA, will be equipped with an innovative camera. The SST-1M has a Davies-Cotton optical design with a mirror dish of 4 m diameter and focal ratio 1.4 focussing the Cherenkov light produced in atmospheric showers onto a 90 cm wide hexagonal camera providing a FoV of 9 degrees. The camera is an innovative design based on silicon photomultipliers (SiPM ) and adopting a fully digital trigger and readout architecture. The camera features 1296 custom designed large area hexagonal SiPM coupled to hollow optical concentrators to achieve a pixel size of almost 2.4 cm. The SiPM is a custom design developed with Hamamatsu and with its active area of almost 1 cm2 is one of the largest monolithic SiPM existing. Also the optical concentrators are innovative being light funnels made of a polycarbonate substrate coated with a custom designed UV-enhancing coating. The analog signals coming from the SiPM are fed into the fully digital readout electronics, where digital data are processed by high-speed FPGAs both for trigger and readout. The trigger logic, implemented into an Virtex 7 FPGA, uses the digital data to elaborate a trigger decision by matching data against predefined patterns. This approach is extremely flexible and allows improvements and continued evolutions of the system. The prototype camera is being tested in laboratory prior to its installation expected in fall 2017 on the telescope prototype in Krakow (Poland). In this contribution, we will describe the design of the camera and show the performance measured in laboratory.

Effect of Cu(II), Cd(II) and Zn(II) on Pb(II) biosorption by algae Gelidium-derived materials.

PubMed

Vilar, Vítor J P; Botelho, Cidália M S; Boaventura, Rui A R

2008-06-15

Biosorption of Pb(II), Cu(II), Cd(II) and Zn(II) from binary metal solutions onto the algae Gelidium sesquipedale, an algal industrial waste and a waste-based composite material was investigated at pH 5.3, in a batch system. Binary Pb(II)/Cu(II), Pb(II)/Cd(II) and Pb(II)/Zn(II) solutions have been tested. For the same equilibrium concentrations of both metal ions (1 mmol l(-1)), approximately 66, 85 and 86% of the total uptake capacity of the biosorbents is taken by lead ions in the systems Pb(II)/Cu(II), Pb(II)/Cd(II) and Pb(II)/Zn(II), respectively. Two-metal results were fitted to a discrete and a continuous model, showing the inhibition of the primary metal biosorption by the co-cation. The model parameters suggest that Cd(II) and Zn(II) have the same decreasing effect on the Pb(II) uptake capacity. The uptake of Pb(II) was highly sensitive to the presence of Cu(II). From the discrete model it was possible to obtain the Langmuir affinity constant for Pb(II) biosorption. The presence of the co-cations decreases the apparent affinity of Pb(II). The experimental results were successfully fitted by the continuous model, at different pH values, for each biosorbent. The following sequence for the equilibrium affinity constants was found: Pb>Cu>Cd approximately Zn.

Approximating Smooth Step Functions Using Partial Fourier Series Sums

DTIC Science & Technology

2012-09-01

interp1(xt(ii), smoothstepbez( t(ii), min(t(ii)), max(t(ii)), ’y’), t(ii), ’linear’, ’ extrap ’); ii = find( abs(t - tau/2) <= epi ); iii = t(ii...interp1( xt(ii), smoothstepbez( rt, min(rt), max(rt), ’y’), t(ii), ’linear’, ’ extrap ’ ); % stepm(ii) = 1 - interp1(xt(ii), smoothstepbez( t(ii...min(t(ii)), max(t(ii)), ’y’), t(ii), ’linear’, ’ extrap ’); In this case, because x is also defined as a function of the independent parameter

78 FR 69302 - National Oil and Hazardous Substances Pollution Contingency Plan; National Priorities List...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-11-19

..., II-T, III-C, I-C, II-U, I-B, I-E, I-G, I-H, I-I, I-J, I-L, I-M, I-P, II-G, II-I, II-P, III-D, I-K, I..., I-H, I-I, I-J, I-L, I-M, I-P, II-G, II-I, II-P, III-D, I-K, I-N, I-O, I-S, II-E, II-L, II-M, II-R, I... 102(h) of CERCLA, to document that all environmental impacts associated with the DON's activities on...

Development of a beam test telescope based on the Alibava readout system

NASA Astrophysics Data System (ADS)

Marco-Hernández, R.

2011-01-01

A telescope for a beam test have been developed as a result of a collaboration among the University of Liverpool, Centro Nacional de Microelectrónica (CNM) of Barcelona and Instituto de Física Corpuscular (IFIC) of Valencia. This system is intended to carry out both analogue charge collection and spatial resolution measurements with different types of microstrip or pixel silicon detectors in a beam test environment. The telescope has four XY measurement as well as trigger planes (XYT board) and it can accommodate up to twelve devices under test (DUT board). The DUT board uses two Beetle ASICs for the readout of chilled silicon detectors. The board could operate in a self-triggering mode. The board features a temperature sensor and it can be mounted on a rotary stage. A peltier element is used for cooling the DUT. Each XYT board measures the track space points using two silicon strip detectors connected to two Beetle ASICs. It can also trigger on the particle tracks in the beam test. The board includes a CPLD which allows for the synchronization of the trigger signal to a common clock frequency, delaying and implementing coincidence with other XYT boards. An Alibava mother board is used to read out and to control each XYT/DUT board from a common trigger signal and a common clock signal. The Alibava board has a TDC on board to have a time stamp of each trigger. The data collected by each Alibava board is sent to a master card by means of a local data/address bus following a custom digital protocol. The master board distributes the trigger, clock and reset signals. It also merges the data streams from up to sixteen Alibava boards. The board has also a test channel for testing in a standard mode a XYT or DUT board. This board is implemented with a Xilinx development board and a custom patch board. The master board is connected with the DAQ software via 100M Ethernet. Track based alignment software has also been developed for the data obtained with the DAQ software.

Relative abundance of chemical forms of Cu(II) and Cd(II) on soybean roots as influenced by pH, cations and organic acids

PubMed Central

Zhou, Qin; Liu, Zhao-dong; Liu, Yuan; Jiang, Jun; Xu, Ren-kou

2016-01-01

Little information is available on chemical forms of heavy metals on integrate plant roots. KNO3 (1 M), 0.05M EDTA at pH6 and 0.01 M HCl were used sequentially to extract the exchangeable, complexed and precipitated forms of Cu(II) and Cd(II) from soybean roots and then to investigate chemical form distribution of Cu(II) and Cd(II) on soybean roots. Cu(II) and Cd(II) adsorbed on soybean roots were mainly exchangeable form, followed by complexed form, while their precipitated forms were very low under acidic conditions. Soybean roots had a higher adsorption affinity to Cu(II) than Cd(II), leading to higher toxic of Cu(II) than Cd(II). An increase in solution pH increased negative charge on soybean and thus increased exchangeable Cu(II) and Cd(II) on the roots. Ca2+, Mg2+ and NH4+ reduced exchangeable Cu(II) and Cd(II) levels on soybean roots and these cations showed greater effects on Cd(II) than Cu(II) due to greater adsorption affinity of the roots to Cu(II) than Cd(II). L-malic and citric acids decreased exchangeable and complexed Cu(II) on soybean roots. In conclusion, Cu(II) and Cd(II) mainly existed as exchangeable and complexed forms on soybean roots. Ca2+ and Mg2+ cations and citric and L-malic acids can potentially alleviate Cu(II) and Cd(II) toxicity to plants. PMID:27805020

Solid Phase Extraction of Trace Al(III), Fe(II), Co(II), Cu(II), Cd(II) and Pb(II) Ions in Beverages on Functionalized Polymer Microspheres Prior to Flame Atomic Absorption Spectrometric Determinations.

PubMed

Berber, Hale; Alpdogan, Güzin

2017-01-01

In this study, poly(glycidyl methacrylate-methyl methacrylate-divinylbenzene) was synthesized in the form of microspheres, and then functionalized by 2-aminobenzothiazole ligand. The sorption properties of these functionalized microspheres were investigated for separation, preconcentration and determination of Al(III), Fe(II), Co(II), Cu(II), Cd(II) and Pb(II) ions using flame atomic absorption spectrometry. The optimum pH values for quantitative sorption were 2 - 4, 5 - 8, 6 - 8, 4 - 6, 2 - 6 and 2 - 3 for Al(III), Fe(II), Co(II), Cu(II), Cd(II) and Pb(II), respectively, and also the highest sorption capacity of the functionalized microspheres was found to be for Cu(II) with the value of 1.87 mmol g -1 . The detection limits (3σ; N = 6) obtained for the studied metals in the optimal conditions were observed in the range of 0.26 - 2.20 μg L -1 . The proposed method was successfully applied to different beverage samples for the determination of Al(III), Fe(II), Co(II), Cu(II), Cd(II) and Pb(II) ions, with the relative standard deviation of <3.7%.

Invariant Chain Complexes and Clusters as Platforms for MIF Signaling

PubMed Central

Lindner, Robert

2017-01-01

Invariant chain (Ii/CD74) has been identified as a surface receptor for migration inhibitory factor (MIF). Most cells that express Ii also synthesize major histocompatibility complex class II (MHC II) molecules, which depend on Ii as a chaperone and a targeting factor. The assembly of nonameric complexes consisting of one Ii trimer and three MHC II molecules (each of which is a heterodimer) has been regarded as a prerequisite for efficient delivery to the cell surface. Due to rapid endocytosis, however, only low levels of Ii-MHC II complexes are displayed on the cell surface of professional antigen presenting cells and very little free Ii trimers. The association of Ii and MHC II has been reported to block the interaction with MIF, thus questioning the role of surface Ii as a receptor for MIF on MHC II-expressing cells. Recent work offers a potential solution to this conundrum: Many Ii-complexes at the cell surface appear to be under-saturated with MHC II, leaving unoccupied Ii subunits as potential binding sites for MIF. Some of this work also sheds light on novel aspects of signal transduction by Ii-bound MIF in B-lymphocytes: membrane raft association of Ii-MHC II complexes enables MIF to target Ii-MHC II to antigen-clustered B-cell-receptors (BCR) and to foster BCR-driven signaling and intracellular trafficking. PMID:28208600

Binding Selectivity of Methanobactin from Methylosinus trichosporium OB3b for Copper(I), Silver(I), Zinc(II), Nickel(II), Cobalt(II), Manganese(II), Lead(II), and Iron(II)

NASA Astrophysics Data System (ADS)

McCabe, Jacob W.; Vangala, Rajpal; Angel, Laurence A.

2017-12-01

Methanobactin (Mb) from Methylosinus trichosporium OB3b is a member of a class of metal binding peptides identified in methanotrophic bacteria. Mb will selectively bind and reduce Cu(II) to Cu(I), and is thought to mediate the acquisition of the copper cofactor for the enzyme methane monooxygenase. These copper chelating properties of Mb make it potentially useful as a chelating agent for treatment of diseases where copper plays a role including Wilson's disease, cancers, and neurodegenerative diseases. Utilizing traveling wave ion mobility-mass spectrometry (TWIMS), the competition for the Mb copper binding site from Ag(I), Pb(II), Co(II), Fe(II), Mn(II), Ni(II), and Zn(II) has been determined by a series of metal ion titrations, pH titrations, and metal ion displacement titrations. The TWIMS analyses allowed for the explicit identification and quantification of all the individual Mb species present during the titrations and measured their collision cross-sections and collision-induced dissociation patterns. The results showed Ag(I) and Ni(II) could irreversibly bind to Mb and not be effectively displaced by Cu(I), whereas Ag(I) could also partially displace Cu(I) from the Mb complex. At pH ≈ 6.5, the Mb binding selectivity follows the order Ag(I)≈Cu(I)>Ni(II)≈Zn(II)>Co(II)>>Mn(II)≈Pb(II)>Fe(II), and at pH 7.5 to 10.4 the order is Ag(I)>Cu(I)>Ni(II)>Co(II)>Zn(II)>Mn(II)≈Pb(II)>Fe(II). Breakdown curves of the disulfide reduced Cu(I) and Ag(I) complexes showed a correlation existed between their relative stability and their compact folded structure indicated by their CCS. Fluorescence spectroscopy, which allowed the determination of the binding constant, compared well with the TWIMS analyses, with the exception of the Ni(II) complex. [Figure not available: see fulltext.

Binding Selectivity of Methanobactin from Methylosinus trichosporium OB3b for Copper(I), Silver(I), Zinc(II), Nickel(II), Cobalt(II), Manganese(II), Lead(II), and Iron(II).

PubMed

McCabe, Jacob W; Vangala, Rajpal; Angel, Laurence A

2017-12-01

Methanobactin (Mb) from Methylosinus trichosporium OB3b is a member of a class of metal binding peptides identified in methanotrophic bacteria. Mb will selectively bind and reduce Cu(II) to Cu(I), and is thought to mediate the acquisition of the copper cofactor for the enzyme methane monooxygenase. These copper chelating properties of Mb make it potentially useful as a chelating agent for treatment of diseases where copper plays a role including Wilson's disease, cancers, and neurodegenerative diseases. Utilizing traveling wave ion mobility-mass spectrometry (TWIMS), the competition for the Mb copper binding site from Ag(I), Pb(II), Co(II), Fe(II), Mn(II), Ni(II), and Zn(II) has been determined by a series of metal ion titrations, pH titrations, and metal ion displacement titrations. The TWIMS analyses allowed for the explicit identification and quantification of all the individual Mb species present during the titrations and measured their collision cross-sections and collision-induced dissociation patterns. The results showed Ag(I) and Ni(II) could irreversibly bind to Mb and not be effectively displaced by Cu(I), whereas Ag(I) could also partially displace Cu(I) from the Mb complex. At pH ≈ 6.5, the Mb binding selectivity follows the order Ag(I)≈Cu(I)>Ni(II)≈Zn(II)>Co(II)>Mn(II)≈Pb(II)>Fe(II), and at pH 7.5 to 10.4 the order is Ag(I)>Cu(I)>Ni(II)>Co(II)>Zn(II)>Mn(II)≈Pb(II)>Fe(II). Breakdown curves of the disulfide reduced Cu(I) and Ag(I) complexes showed a correlation existed between their relative stability and their compact folded structure indicated by their CCS. Fluorescence spectroscopy, which allowed the determination of the binding constant, compared well with the TWIMS analyses, with the exception of the Ni(II) complex. Graphical abstract ᅟ.

Structural alteration of hexagonal birnessite by aqueous Mn(II): Impacts on Ni(II) sorption

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lefkowitz, Joshua P.; Elzinga, Evert J.

We studied the impacts of aqueous Mn(II) (1 mM) on the sorption of Ni(II) (200 μM) by hexagonal birnessite (0.1 g L- 1) at pH 6.5 and 7.5 with batch experiments and XRD, ATR-FTIR and Ni K-edge EXAFS analyses. In the absence of Mn(II)aq, sorbed Ni(II) was coordinated predominantly as triple corner-sharing complexes at layer vacancies at both pH values. Introduction of Mn(II)aq into Ni(II)-birnessite suspensions at pH 6.5 caused Ni(II) desorption and led to the formation of edge-sharing Ni(II) complexes. This was attributed to competitive displacement of Ni(II) from layer vacancies by either Mn(II) or by Mn(III) formed throughmore » interfacial Mn(II)-Mn(IV) comproportionation, and/or incorporation of Ni(II) into the birnessite lattice promoted by Mn(II)-catalyzed recrystallization of the sorbent. Similar to Mn(II)aq, the presence of HEPES or MES caused the formation of edge-sharing Ni(II) sorption complexes in Ni(II)-birnessite suspensions, which was attributed to partial reduction of the sorbent by the buffers. At pH 7.5, interaction with aqueous Mn(II) caused reductive transformation of birnessite into secondary feitknechtite that incorporated Ni(II), enhancing removal of Ni(II) from solution. These results demonstrate that reductive alteration of phyllomanganates may significantly affect the speciation and solubility of Ni(II) in anoxic and suboxic environments.« less

Manganese acquisition by Lactobacillus plantarum

DOE Office of Scientific and Technical Information (OSTI.GOV)

Archibald, F.S.; Duong, M.N.

1984-04-01

Lactobacillus plantarum has an unusually high Mn(II) requirement for growth and accumulated over 30 mM intracellular Mn(II). The acquisition of Mn(II) by L. plantarum occurred via a specific active transport system powered by the transmembrane proton gradient. The Mn(II) uptake system has a K/sub m/ of 0.2 ..mu..M and a V/sub max/ of 24 nmol mg/sup -1/ of protein min/sup -1/. Above a medium Mn(II) concentration of 200 ..mu..M, the intracellular Mn(II) level was independent of the medium Mn(II) and unresponsive to oxygen stresses but was reduced by phosphate limitation. At a pH of 5.5, citrate, isocitrate, and cis-aconitate effectivelymore » promoted MN(II) uptake, although measurable levels of 1,5-(/sup 14/C)citrate were not accumulated. When cells were presented with equimolar Mn(II) and Cd(II), Cd(II) was preferentially taken up by the Mn(II) transport system. Both Mn(II) and Cd(II) uptake were greatly increased by Mn(II) starvation. Mn(II) uptake by Mn(II)-starved cells was subject to a negative feedback regulatory mechanism functioning less than 1 min after exposure of the cells to Mn(II) and independent of protein synthesis. When presented with a relatively large amount of exogenous Mn(II), Mn(II)-starved cells exhibited a measurable efflux of their internal Mn(II), but the rate was only a small fraction of the maximal Mn(II) uptake rate.« less

The TFIID components human TAF(II)140 and Drosophila BIP2 (TAF(II)155) are novel metazoan homologues of yeast TAF(II)47 containing a histone fold and a PHD finger.

PubMed

Gangloff, Y G; Pointud, J C; Thuault, S; Carré, L; Romier, C; Muratoglu, S; Brand, M; Tora, L; Couderc, J L; Davidson, I

2001-08-01

The RNA polymerase II transcription factor TFIID comprises the TATA binding protein (TBP) and a set of TBP-associated factors (TAF(II)s). TFIID has been extensively characterized for yeast, Drosophila, and humans, demonstrating a high degree of conservation of both the amino acid sequences of the constituent TAF(II)s and overall molecular organization. In recent years, it has been assumed that all the metazoan TAF(II)s have been identified, yet no metazoan homologues of yeast TAF(II)47 (yTAF(II)47) and yTAF(II)65 are known. Both of these yTAF(II)s contain a histone fold domain (HFD) which selectively heterodimerizes with that of yTAF(II)25. We have cloned a novel mouse protein, TAF(II)140, containing an HFD and a plant homeodomain (PHD) finger, which we demonstrated by immunoprecipitation to be a mammalian TFIID component. TAF(II)140 shows extensive sequence similarity to Drosophila BIP2 (dBIP2) (dTAF(II)155), which we also show to be a component of Drosophila TFIID. These proteins are metazoan homologues of yTAF(II)47 as their HFDs selectively heterodimerize with dTAF(II)24 and human TAF(II)30, metazoan homologues of yTAF(II)25. We further show that yTAF(II)65 shares two domains with the Drosophila Prodos protein, a recently described potential dTAF(II). These conserved domains are critical for yTAF(II)65 function in vivo. Our results therefore identify metazoan homologues of yTAF(II)47 and yTAF(II)65.

Metabolomic Analysis of the Secretome of Human Embryonic Stem Cells Following Methyl Parathion and Methyl Paraoxon Exposure Phase 2: Metabolite Downselection for Structural Confirmation

DTIC Science & Technology

2013-12-01

degradation 2 Pipecolic acid II 2-keto-6- aminocaproate II Pyruvate metabolism 1 Malic acid I Purine metabolism 1 Guanine I Propanoate metabolism 1...acetamidobutanoic acid II cis-4-hydroxy-D-proline II D-arginine and D-ornithine metabolism 4 Ornithine II 5-amino-2-oxopentanoic acid II 2-amino-4-oxo...pentanoic acid II (2R,4S)-2,4-diaminopentanoate II Gly, Ser, and Thr metabolism 3 L-cystathionine II Choline II 5-aminolevulinic acid II Val

Macrocyclic receptor showing extremely high Sr(II)/Ca(II) and Pb(II)/Ca(II) selectivities with potential application in chelation treatment of metal intoxication.

PubMed

Ferreirós-Martínez, Raquel; Esteban-Gómez, David; Tóth, Éva; de Blas, Andrés; Platas-Iglesias, Carlos; Rodríguez-Blas, Teresa

2011-04-18

Herein we report a detailed investigation of the complexation properties of the macrocyclic decadentate receptor N,N'-Bis[(6-carboxy-2-pyridil)methyl]-4,13-diaza-18-crown-6 (H(2)bp18c6) toward different divalent metal ions [Zn(II), Cd(II), Pb(II), Sr(II), and Ca(II)] in aqueous solution. We have found that this ligand is especially suited for the complexation of large metal ions such as Sr(II) and Pb(II), which results in very high Pb(II)/Ca(II) and Pb(II)/Zn(II) selectivities (in fact, higher than those found for ligands widely used for the treatment of lead poisoning such as ethylenediaminetetraacetic acid (edta)), as well as in the highest Sr(II)/Ca(II) selectivity reported so far. These results have been rationalized on the basis of the structure of the complexes. X-ray crystal diffraction, (1)H and (13)C NMR spectroscopy, as well as theoretical calculations at the density functional theory (B3LYP) level have been performed. Our results indicate that for large metal ions such as Pb(II) and Sr(II) the most stable conformation is Δ(δλδ)(δλδ), while for Ca(II) our calculations predict the Δ(λδλ)(λδλ) form being the most stable one. The selectivity that bp18c6(2-) shows for Sr(II) over Ca(II) can be attributed to a better fit between the large Sr(II) ions and the relatively large crown fragment of the ligand. The X-ray crystal structure of the Pb(II) complex shows that the Δ(δλδ)(δλδ) conformation observed in solution is also maintained in the solid state. The Pb(II) ion is endocyclically coordinated, being directly bound to the 10 donor atoms of the ligand. The bond distances to the donor atoms of the pendant arms (2.55-2.60 Å) are substantially shorter than those between the metal ion and the donor atoms of the crown moiety (2.92-3.04 Å). This is a typical situation observed for the so-called hemidirected compounds, in which the Pb(II) lone pair is stereochemically active. The X-ray structures of the Zn(II) and Cd(II) complexes show that these metal ions are exocyclically coordinated by the ligand, which explains the high Pb(II)/Cd(II) and Pb(II)/Zn(II) selectivities. Our receptor bp18c6(2-) shows promise for application in chelation treatment of metal intoxication by Pb(II) and (90)Sr(II).

Dinuclear complexes containing linear M-F-M [M = Mn(II), Fe(II), Co(II), Ni(II), Cu(II), Zn(II), Cd(II)] bridges: trends in structures, antiferromagnetic superexchange interactions, and spectroscopic properties.

PubMed

Reger, Daniel L; Pascui, Andrea E; Smith, Mark D; Jezierska, Julia; Ozarowski, Andrew

2012-11-05

The reaction of M(BF(4))(2)·xH(2)O, where M is Fe(II), Co(II), Ni(II), Cu(II), Zn(II), and Cd(II), with the new ditopic ligand m-bis[bis(3,5-dimethyl-1-pyrazolyl)methyl]benzene (L(m)*) leads to the formation of monofluoride-bridged dinuclear metallacycles of the formula [M(2)(μ-F)(μ-L(m)*)(2)](BF(4))(3). The analogous manganese(II) species, [Mn(2)(μ-F)(μ-L(m)*)(2)](ClO(4))(3), was isolated starting with Mn(ClO(4))(2)·6H(2)O using NaBF(4) as the source of the bridging fluoride. In all of these complexes, the geometry around the metal centers is trigonal bipyramidal, and the fluoride bridges are linear. The (1)H, (13)C, and (19)F NMR spectra of the zinc(II) and cadmium(II) compounds and the (113)Cd NMR of the cadmium(II) compound indicate that the metallacycles retain their structure in acetonitrile and acetone solution. The compounds with M = Mn(II), Fe(II), Co(II), Ni(II), and Cu(II) are antiferromagnetically coupled, although the magnitude of the coupling increases dramatically with the metal as one moves to the right across the periodic table: Mn(II) (-6.7 cm(-1)) < Fe(II) (-16.3 cm(-1)) < Co(II) (-24.1 cm(-1)) < Ni(II) (-39.0 cm(-1)) ≪ Cu(II) (-322 cm(-1)). High-field EPR spectra of the copper(II) complexes were interpreted using the coupled-spin Hamiltonian with g(x) = 2.150, g(y) = 2.329, g(z) = 2.010, D = 0.173 cm(-1), and E = 0.089 cm(-1). Interpretation of the EPR spectra of the iron(II) and manganese(II) complexes required the spin Hamiltonian using the noncoupled spin operators of two metal ions. The values g(x) = 2.26, g(y) = 2.29, g(z) = 1.99, J = -16.0 cm(-1), D(1) = -9.89 cm(-1), and D(12) = -0.065 cm(-1) were obtained for the iron(II) complex and g(x) = g(y) = g(z) = 2.00, D(1) = -0.3254 cm(-1), E(1) = -0.0153, J = -6.7 cm(-1), and D(12) = 0.0302 cm(-1) were found for the manganese(II) complex. Density functional theory (DFT) calculations of the exchange integrals and the zero-field splitting on manganese(II) and iron(II) ions were performed using the hybrid B3LYP functional in association with the TZVPP basis set, resulting in reasonable agreement with experiment.

Metal (II) Complexes Derived from Naphthofuran-2-carbohydrazide and Diacetylmonoxime Schiff Base: Synthesis, Spectroscopic, Electrochemical, and Biological Investigation

PubMed Central

Sumathi, R. B.; Halli, M. B.

2014-01-01

A new Schiff base and a new series of Co(II), Ni(II), Cu(II), Cd(II), and Hg(II) complexes were synthesized by the condensation of naphthofuran-2-carbohydrazide and diacetylmonoxime. Metal complexes of the Schiff base were prepared from their chloride salts of Co(II), Ni(II), Cu(II), Cd(II), and Hg(II) in ethanol. The ligand along with its metal complexes have been characterized on the basis of analytical data, IR, electronic, mass, 1HNMR, ESR spectral data, thermal studies, magnetic susceptibility, and molar conductance measurements. The nonelectrolytic behaviour of the complexes was assessed from the measured low conductance data. The elemental analysis of the complexes confirm the stoichiometry of the type CuL2Cl2 and MLCl2 where M = Ni(II), Co(II), Cd(II), and Hg(II) and L = Schiff base. The redox property of the Cu(II) complex was investigated by electrochemical method using cyclic voltammetry. In the light of these results, Co(II), Ni(II), and Cu(II) complexes are assigned octahedral geometry, Cd(II), and Hg(II) complexes tetrahedral geometry. In order to evaluate the effect of metal ions upon chelation, both the ligand and its metal complexes were screened for their antibacterial and antifungal activities by minimum inhibitory concentration (MIC) method. The DNA cleaving capacity of all the complexes was analysed by agarose gel electrophoresis method. PMID:24592203

A magnetostructural study of linear NiII MnIII NiII, NiII CrIII NiII and triangular Ni(II)3 species containing (pyridine-2-aldoximato)nickel(II) unit as a building block.

PubMed

Weyhermüller, Thomas; Wagner, Rita; Khanra, Sumit; Chaudhuri, Phalguni

2005-08-07

Three trinuclear complexes, NiII MnIII NiII, NiII CrIII NiII and Ni(II)3 based on (pyridine-2-aldoximato)nickel(II) units are described. Two of them, and , contain metal-centers in linear arrangement, as is revealed by X-ray diffraction. Complex is a homonuclear complex in which the three nickel(II) centers are disposed in a triangular fashion. The compounds were characterized by various physical methods including cyclic voltammetric and variable-temperature (2-290 K) susceptibility measurements. Complexes and display antiferromagnetic exchange coupling of the neighbouring metal centers, while weak ferromagnetic spin exchange between the adjacent Ni II and Cr III ions in is observed. The experimental magnetic data were simulated by using appropriate models.

Comparative study on kinetic adsorption of Cu(II), Cd(II) and Ni(II) ions from aqueous solutions using activated sludge and dried sludge

NASA Astrophysics Data System (ADS)

Ong, Soon-An; Toorisaka, Eiichi; Hirata, Makoto; Hano, Tadashi

2013-03-01

The adsorption of Cu(II), Cd(II) and Ni(II) ions from aqueous solutions by activated sludge and dried sludge was investigated under laboratory conditions to assess its potential in removing metal ions. The adsorption behavior of metal ions onto activated sludge and dried sludge was analyzed with Weber-Morris intra-particle diffusion model, Lagergren first-order model and pseudo second-order model. The rate constant of intra-particle diffusion on activated sludge and dried sludge increased in the sequence of Cu(II) > Ni(II) > Cd(II). According to the regression coefficients, it was observed that the kinetic adsorption data can fit better by the pseudo second-order model compared to the first-order Lagergren model with R 2 > 0.997. The adsorption capacities of metal ions onto activated sludge and dried sludge followed the sequence Ni(II) ≈ Cu(II) > Cd(II) and Cu(II) > Ni(II) > Cd(II).

Coordination behavior of tetraaza [N4] ligand towards Co(II), Ni(II), Cu(II), Cu(I) and Pd(II) complexes: Synthesis, spectroscopic characterization and anticancer activity

NASA Astrophysics Data System (ADS)

El-Boraey, Hanaa A.

2012-11-01

Novel eight Co(II), Ni(II), Cu(II), Cu(I) and Pd(II) complexes with [N4] ligand (L) i.e. 2-amino-N-{2-[(2-aminobenzoyl)amino]ethyl}benzamide have been synthesized and structurally characterized by elemental analysis, spectral, thermal (TG/DTG), magnetic, and molar conductivity measurements. On the basis of IR, mass, electronic and EPR spectral studies an octahedral geometry has been proposed for Co(II), Ni(II) complexes and Cu(II) chloride complex, square-pyramidal for Cu(I) bromide complex. For Cu(II) nitrate complex (6), Pd(II) complex (8) square planar geometry was proposed. The EPR data of Cu(II) complexes in powdered form indicate dx2-y2 ground state of Cu(II) ion. The antitumor activity of the synthesized ligand and some selected metal complexes has been studied. The palladium(II) complex (8) was found to display cytotoxicity (IC50 = 25.6 and 41 μM) against human breast cancer cell line MCF-7 and human hepatocarcinoma HEPG2 cell line.

Synthesis, spectroscopic characterization, first order nonlinear optical properties and DFT calculations of novel Mn(II), Co(II), Ni(II), Cu(II) and Zn(II) complexes with 1,3-diphenyl-4-phenylazo-5-pyrazolone ligand

NASA Astrophysics Data System (ADS)

Abdel-Latif, Samir A.; Mohamed, Adel A.

2018-02-01

Novel Mn(II), Co(II), Ni(II), Cu(II) and Zn(II) metal ions with 1,3-diphenyl-4-phenylazo-5-pyrazolone (L) have been prepared and characterized using different analytical and spectroscopic techniques. 1:1 Complexes of Mn(II), Co(II) and Zn(II) are distorted octahedral whereas Ni(II) complex is square planar and Cu(II) is distorted trigonal bipyramid. 1:2 Complexes of Mn(II), Co(II), Cu(II) and Zn(II) are distorted trigonal bipyramid whereas Ni(II) complex is distorted tetrahedral. All complexes behave as non-ionic in dimethyl formamide (DMF). The electronic structure and nonlinear optical parameters (NLO) of the complexes were investigated theoretically at the B3LYP/GEN level of theory. Molecular stability and bond strengths have been investigated by applying natural bond orbital (NBO) analysis. The geometries of the studied complexes are non-planner. DFT calculations have been also carried out to calculate the global properties; hardness (η), global softness (S) and electronegativity (χ). The calculated small energy gap between HOMO and LUMO energies shows that the charge transfer occurs within the complexes. The total static dipole moment (μtot), the mean polarizability (<α>), the anisotropy of the polarizability (Δα) and the mean first-order hyperpolarizability (<β>) were calculated and compared with urea as a reference material. The complexes show implying optical properties.

76 FR 4271 - Approval and Promulgation of State Implementation Plans; State of Colorado Regulation Number 3...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-01-25

... action on the revision to APEN exemption II.D.1.uuu., because we proposed approval of the revision in the....uuu; II.D.1.eeee. No Action--Un-Revised Provisions.. II.B; II.B.1.a; II.B.3.b; II.B.4; II.B.5; II.B.6...

Electronic Equipment Reliability Data,

DTIC Science & Technology

1986-04-02

MTBF RELATIONSHIPS 2- 60 (INDEPENDENT OF PREDICTED MTBF) vii LIST OF FIGURES Page FIGURE 1: CONTROLS/DISPLAYS FIELD MTBF VERSUS PREDICTED MTBF 2-9 FIGURE...LJ LO C-.. c’J - - IL D LLLJ c c 1,P, 4-) CD ui on LU V)4-> LD 2 2- 60 field maintenance data (MTBMAFIELD) and observed field failure data (MTBFFIELD...w N w DLM I_, II II uh II |II II II II L II II it 00I II I-. m . LI I I I I I I I I I I I I- - - - - I I I I I I I Of m- I C II ~ 1 1 10 0 0 0 01 1 1

Structural, spectroscopic and thermal characterization of 2-tert-butylaminomethylpyridine-6-carboxylic acid methylester and its Fe(III), Co(II), Ni(II), Cu(II), Zn(II) and UO(2)(II) complexes.

PubMed

Mohamed, Gehad G; El-Gamel, Nadia E A

2005-04-01

Fe(III), Co(II), Ni(II), Cu(II), Zn(II) and UO(2)(II) complexes with the ligand 2-tert-butylaminomethylpyridine-6-carboxylic acid methylester (HL(2)) have been prepared and characterized by elemental analyses, molar conductance, magnetic moment, thermal analysis and spectral data. 1:1 M:HL(2) complexes, with the general formula [M(HL(2))X(2)].nH(2)O (where M = Co(II) (X = Cl, n = 0), Ni(II) (X = Cl, n = 3), Cu(II) (grey colour, X = AcO, n = 1), Cu(II) (yellow colour, X = Cl, n = 0) and Zn(II) (X = Br, n = 0). In addition, the Fe(III) and UO(2)(II) complexes of the type 1:2 M:HL(2) and with the formulae [Fe(L(2))(2)]Cl and [UO(2)(HL(2))(2)](NO(3))(2) are prepared. From the IR data, it is seen that HL(2) ligand behaves as a terdentate ligand coordinated to the metal ions via the pyridyl N, carboxylate O and protonated NH group; except the Fe(III) complex, it coordinates via the deprotonated NH group. This is supported by the molar conductance data, which show that all the complexes are non-electrolytes, while the Fe(III) and UO(2)(II) complexes are 1:1 electrolytes. IR and H1-NMR spectral studies suggest a similar behaviour of the Zn(II) complex in solid and solution states. From the solid reflectance spectral data and magnetic moment measurements, the complexes have a trigonal bipyramidal (Co(II), Ni(II), Cu(II) and Zn(II) complexes) and octahedral (Fe(III), UO(2)(II) complexes) geometrical structures. The thermal behaviour of the complexes is studied and the different dynamic parameters are calculated applying Coats-Redfern equation.

Developmental and transcriptional consequences of mutations in Drosophila TAF(II)60.

PubMed

Aoyagi, N; Wassarman, D A

2001-10-01

In vitro, the TAF(II)60 component of the TFIID complex contributes to RNA polymerase II transcription initiation by serving as a coactivator that interacts with specific activator proteins and possibly as a promoter selectivity factor that interacts with the downstream promoter element. In vivo roles for TAF(II)60 in metazoan transcription are not as clear. Here we have investigated the developmental and transcriptional requirements for TAF(II)60 by analyzing four independent Drosophila melanogaster TAF(II)60 mutants. Loss-of-function mutations in Drosophila TAF(II)60 result in lethality, indicating that TAF(II)60 provides a nonredundant function in vivo. Molecular analysis of TAF(II)60 alleles revealed that essential TAF(II)60 functions are provided by two evolutionarily conserved regions located in the N-terminal half of the protein. TAF(II)60 is required at all stages of Drosophila development, in both germ cells and somatic cells. Expression of TAF(II)60 from a transgene rescued the lethality of TAF(II)60 mutants and exposed requirements for TAF(II)60 during imaginal development, spermatogenesis, and oogenesis. Phenotypes of rescued TAF(II)60 mutant flies implicate TAF(II)60 in transcriptional mechanisms that regulate cell growth and cell fate specification and suggest that TAF(II)60 is a limiting component of the machinery that regulates the transcription of dosage-sensitive genes. Finally, TAF(II)60 plays roles in developmental regulation of gene expression that are distinct from those of other TAF(II) proteins.

Adsorption of Pb(II), Cu(II), Cd(II), Zn(II), Ni(II), Fe(II), and As(V) on bacterially produced metal sulfides.

PubMed

Jong, Tony; Parry, David L

2004-07-01

The adsorption of Pb(II), Cu(II), Cd(II), Zn(II), Ni(II), Fe(II) and As(V) onto bacterially produced metal sulfide (BPMS) material was investigated using a batch equilibrium method. It was found that the sulfide material had adsorptive properties comparable with those of other adsorbents with respect to the specific uptake of a range of metals and, the levels to which dissolved metal concentrations in solution can be reduced. The percentage of adsorption increased with increasing pH and adsorbent dose, but decreased with increasing initial dissolved metal concentration. The pH of the solution was the most important parameter controlling adsorption of Cd(II), Cu(II), Fe(II), Ni(II), Pb(II), Zn(II), and As(V) by BPMS. The adsorption data were successfully modeled using the Langmuir adsorption isotherm. Desorption experiments showed that the reversibility of adsorption was low, suggesting high-affinity adsorption governed by chemisorption. The mechanism of adsorption for the divalent metals was thought to be the formation of strong, inner-sphere complexes involving surface hydroxyl groups. However, the mechanism for the adsorption of As(V) by BPMS appears to be distinct from that of surface hydroxyl exchange. These results have important implications to the management of metal sulfide sludge produced by bacterial sulfate reduction.

Draft Background Document: Summary of Data on Municipal ...

EPA Pesticide Factsheets

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Synthesis, characterization and antimicrobial studies of Schiff base complexes

NASA Astrophysics Data System (ADS)

Zafar, Hina; Ahmad, Anis; Khan, Asad U.; Khan, Tahir Ali

2015-10-01

The Schiff base complexes, MLCl2 [M = Fe(II), Co(II), Ni(II), Cu(II) and Zn(II)] have been synthesized by the template reaction of respective metal ions with 2-acetylpyrrole and 1,3-diaminopropane in 1:2:1 M ratio. The complexes have been characterized by elemental analyses, ESI - mass, NMR (1H and 13C), IR, XRD, electronic and EPR spectral studies, magnetic susceptibility and molar conductance measurements. These studies show that all the complexes have octahedral arrangement around the metal ions. The molar conductance measurements of all the complexes in DMSO indicate their non-electrolytic nature. The complexes were screened for their antibacterial activity in vitro against Gram-positive (Streptococcus pyogenes) and Gram-negative (Klebsiella pneumoniae) bacteria. Among the metal complexes studied the copper complex [CuLCl2], showed highest antibacterial activity nearly equal to standard drug ciprofloxacin. Other complexes also showed considerable antibacterial activity. The relative order of activity against S. Pyogenes is as Cu(II) > Zn(II) > Co(II) = Fe(II) > Ni(II) and with K. Pneumonia is as Cu(II) > Co(II) > Zn(II) > Fe(II) > Ni(II).

Kangaroo IGF-II is structurally and functionally similar to the human [Ser29]-IGF-II variant.

PubMed

Yandell, C A; Francis, G L; Wheldrake, J F; Upton, Z

1999-06-01

Kangaroo IGF-II has been purified from western grey kangaroo (Macropus fuliginosus) serum and characterised in a number of in vitro assays. In addition, the complete cDNA sequence of mature IGF-II has been obtained by reverse-transcription polymerase chain reaction. Comparison of the kangaroo IGF-II cDNA sequence with known IGF-II sequences from other species revealed that it is very similar to the human variant, [Ser29]-hIGF-II. Both the variant and kangaroo IGF-II contain an insert of nine nucleotides that encode the amino acids Leu-Pro-Gly at the junction of the B and C domains of the mature protein. The deduced kangaroo IGF-II protein sequence also contains three other amino acid changes that are not observed in human IGF-II. These amino acid differences share similarities with the changes described in many of the IGF-IIs reported for non-mammalian species. Characterisation of human IGF-II, kangaroo IGF-II, chicken IGF-II and [Ser29]-hIGF-II in a number of in vitro assays revealed that all four proteins are functionally very similar. No significant differences were observed in the ability of the IGF-IIs to bind to the bovine IGF-II/cation-independent mannose 6-phosphate receptor or to stimulate protein synthesis in rat L6 myoblasts. However, differences were observed in their abilities to bind to IGF-binding proteins (IGFBPs) present in human serum. Kangaroo, chicken and [Ser29]-hIGF-II had lower apparent affinities for human IGFBPs than did human IGF-II. Thus, it appears that the major circulating form of IGF-II in the kangaroo and a minor form of IGF-II found in human serum are structurally and functionally very similar. This suggests that the splice site that generates both the variant and major form of human IGF-II must have evolved after the divergence of marsupials from placental mammals.

40 CFR Table II-1 to Subpart II of... - Emission Factors

Code of Federal Regulations, 2014 CFR

2014-07-01

... 40 Protection of Environment 21 2014-07-01 2014-07-01 false Emission Factors II Table II-1 to Subpart II of Part 98 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR PROGRAMS (CONTINUED) MANDATORY GREENHOUSE GAS REPORTING Industrial Wastewater Treatment Pt. 98, Subpt. II, Table II-1...

40 CFR Table II-1 to Subpart II of... - Emission Factors

Code of Federal Regulations, 2013 CFR

2013-07-01

... 40 Protection of Environment 22 2013-07-01 2013-07-01 false Emission Factors II Table II-1 to Subpart II of Part 98 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR PROGRAMS (CONTINUED) MANDATORY GREENHOUSE GAS REPORTING Industrial Wastewater Treatment Pt. 98, Subpt. II, Table II-1...

Mechanisms of electron transfer from structrual Fe(II) in reduced nontronite to oxygen for production of hydroxyl radicals

NASA Astrophysics Data System (ADS)

Yuan, Songhu; Liu, Xixiang; Liao, Wenjuan; Zhang, Peng; Wang, Xiaoming; Tong, Man

2018-02-01

Production of hydroxyl radicals (radOH) has been recently revealed upon oxygenation of sediments in redox-dynamic subsurface environments. In particular, Fe(II)-bearing clay minerals are the major sediment components contributing to radOH production upon oxygenation, and the produced radOH can oxidize contaminants and inactivate bacteria. Whereas, the mechanisms of radOH production from oxygenation of Fe(II)-bearing clay minerals remain elusive. The objectives of this study were to identify the structural variation of Fe(II) entities during the oxidation of Fe(II)-bearing clay minerals by O2, and to unravel the mechanisms of electron transfer within the mineral structure and from mineral to O2 for radOH production. Nontronite (NAu-2, 23% Fe) which was chemically reduced to 54.5% Fe(II) in total Fe was used as a model Fe(II)-bearing clay mineral. Production of radOH and oxidation of Fe(II) were measured during the oxidation of reduced NAu-2 by O2. A wide spectrum of spectroscopic techniques, including Fourier transform infrared spectroscopy (FTIR), Fe K-edge X-ray absorption spectroscopy (XAS), Mössbauer spectra, and X-ray photoelectron spectroscopy (XPS), were employed to explore the structural variation of Fe(II) entities in NAu-2 and the electron transfer within NAu-2 and from NAu-2 to O2. For 180 min oxidation of 1 g/L reduced NAu-2, a biphasic radOH production was observed, being quick within the initial 15 min and slow afterwards. Production of radOH correlates well with oxidation of Fe(II) in the reduced NAu-2. Within the initial 15 min, trioctahedral Fe(II)-Fe(II)-Fe(II) entities and edge Fe(II) in the reduced NAu-2 were preferentially and quickly oxidized, and electrons from the interior Fe(II)-Fe(II)-Fe(II) entities were most likely ejected from the basal siloxane plane to O2. Meanwhile, trioctahedral Fe(II)-Fe(II)-Fe(II) entities were mainly transformed to dioctahedral Fe(II)-Fe(II) entities. When the time of oxygenation was longer than 15 min, dioctahedral Al-Fe(II), Fe(II)-Fe(II) and Fe(II)-Fe(III) entities were slowly oxidized, and the interior electrons were transported through Fe(II)-O-Fe(III) linkages to edges and then ejected to O2. In the slow stage of oxidation, electrons from interior Fe(II) accumulated towards the near surface layers and fueled the regeneration of edge Fe(II) for radOH production. In both stages, one-electron transfer mechanism with the involvement of O2rad - and H2O2 applies for radOH production from the oxidation of structural Fe(II) by O2. The mechanisms unraveled in this study advance the understanding of reactive oxygen species (ROS) production and structural Fe variation when Fe(II)-bearing clay minerals are oxygenated in redox-dynamic systems.

Synthesis and characterization of hydroxyapatite nanoparticles impregnated on apple pomace to enhanced adsorption of Pb(II), Cd(II), and Ni(II) ions from aqueous solution.

PubMed

Chand, Piar; Pakade, Yogesh B

2015-07-01

Hydroxyapatite nanoparticles were synthesized, characterized, and impregnated onto apple pomace surface (HANP@AP) for efficient removal of Pb(II), Cd(II), and Ni(II) ions from water. HANP@AP was characterized by Fourier transform infrared spectroscopy (FTIR), scanning electron microscopy (SEM), energy-dispersive spectroscopy (EDS), transmission electron microscope (TEM), X-ray diffraction (XRD), and surface area analysis. Batch sorption studies were carried out to investigate the influence of different parameters as amount of dose (g), pH, time (min), and initial concentration (mg L(-1)) on adsorption process. Experimental kinetic data followed pseudo-second-order model and equilibrium data well fitted to Langmuir adsorption model with maximum adsorption capacities of 303, 250, and 100 mg g(-1) for Pb(II), Cd(II), and Ni(II) ions, respectively. Competitive adsorption of Pb(II), Cd(II), and Ni(II) ions in presences of each other was studied to evaluate the removal efficiency of HANP@AP against multi metal-loaded water. HANP@AP was successfully applied to real industrial wastewater with 100 % removal of all three metal ions even at high concentration. HANP@AP could be recycled for four, four, and three cycles in case of Pb(II), Cd(II) and Ni(II), respectively. The study showed that HANP@AP is fast, cost effective, and environmental friendly adsorbent for removal of Pb(II), Cd(II), and Ni(II) ions from real industrial wastewater.

Dynamic adsorption of mixtures of Rhodamine B, Pb (II), Cu (II) and Zn(II) ions on composites chitosan-silica-polyethylene glycol membrane

NASA Astrophysics Data System (ADS)

Mahatmanti, F. W.; Rengga, W. D. P.; Kusumastuti, E.; Nuryono

2018-04-01

The adsorption of a solution mixture of Rhodamine B, Pb (II), Cu (II) and Zn(II) was studied using dynamic methods employing chitosan-silica-polyethylene glycol (Ch/Si/P) composite membrane as an adsorptive membrane. The composite Ch/Si/P membrane was prepared by mixing a chitosan-based membrane with silica isolated from rice husk ash (ASP) and polyethylene glycol (PEG) as a plasticizer. The resultant composite membrane was a stronger and more flexible membrane than the original chitosan-based membrane as indicated by the maximum percentage of elongation (20.5 %) and minimum Young’s Modulus (80.5 MPa). The composite membrane also showed increased mechanical and hydrophilic properties compared to the chitosan membranes. The membrane was used as adsorption membrane for Pb (II), Cu (II), Cd (II) ions and Rhodamine B dyes in a dynamic system where the permeation and selectivity were determined. The permeation of the components was observed to be in the following order: Rhodamine B > Cd (II) > Pb (II) > Cu (II) whereas the selectivity was shown to decrease the order of Cu (II) > Pb (II) > Cd (II) > Rhodamine B.

Murine lymphoma L5178Y cells resistant to purine antagonists: differences in cross-resistance to thioguanine-platinum(II) and selenoguanine-platinum(II).

PubMed

Kanzawa, F; Maeda, M; Sasaki, T; Hoshi, A; Kuretani, K

1982-02-01

To determine whether the antitumor activities of thioguanine-platinum(II) [TG-Pt(II)] and selenoguanine-platinum(II) [SeG-Pt(II)] are due to direct actions of these compounds or to the actions of their hydrolysis products, studies were made on a purine antagonist-resistant, murine lymphoma L5178Y/MP subline that lacked the anabolic enzyme hypoxanthine-guanine phosphoribosyltransferase necessary for tumor inhibition. The L5178Y/MP subline proved to be highly resistant to both TG-Pt(II) and thioguanine; the resistance ratios to the two compounds were almost identical. The subline showed high resistance to selenoguanine, but the cross-resistance to SeG-Pt(II) was negligible. Whether the compounds exhibit the delayed cytotoxicity characteristic of purine antagonists was also investigated. Delayed cytotoxicity was demonstrated for TG-Pt(II) as well as for thioguanine and other purine antagonists but not for SeG-Pt(II) or cis-dichlorodiammineplatinum(II). Experiments on cross-resistance and delayed cytotoxicity showed differences in the cytotoxicities of TG-Pt(II) and SeG-Pt(II): TG-Pt(II) exerted its activity through its hydrolysis product thioguanine, whereas SeG-Pt(II) compound was cytotoxic itself.

Nanomolar Copper Enhances Mercury Methylation by Desulfovibrio desulfuricans ND132

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Xia; Johs, Alexander; Zhao, Linduo

Methylmercury (MeHg) is produced by certain anaerobic microorganisms, such as the sulfate-reducing bacterium Desulfovibrio desulfuricans ND132, but environmental factors affecting inorganic mercury [Hg(II)] uptake and methylation remain unclear. We report that the presence of a small amount of copper ions [Cu(II), <100 nM] enhances Hg(II) uptake and methylation by washed cells of ND132, while Hg(II) methylation is inhibited at higher Cu(II) concentrations because of the toxicity of copper to the microorganism. The enhancement or inhibitory effect of Cu(II) is dependent on both time and concentration. The presence of nanomolar concentrations of Cu(II) facilitates rapid uptake of Hg(II) (within minutes) andmore » doubles MeHg production within a 24 h period, but micromolar concentrations of Cu(II) completely inhibit Hg(II) methylation. Metal ions such as zinc [Zn(II)] and nickel [Ni(II)] also inhibit but do not enhance Hg(II) methylation under the same experimental conditions. Furthermore, these observations suggest a synergistic effect of Cu(II) on Hg(II) uptake and methylation, possibly facilitated by copper transporters or metallochaperones in this organism, and highlight the fact that complex environmental factors affect MeHg production in the environment.« less

Biosorption characteristics of copper (II), chromium (III), nickel (II), and lead (II) from aqueous solutions by Chara sp. and Cladophora sp.

PubMed

Elmaci, Ayşe; Yonar, Taner; Ozengin, Nihan

2007-09-01

The aim of this research was to expose individual removals of copper, chromium, nickel, and lead from aqueous solutions via biosorption using nonliving algae species, Chara sp. and Cladophora sp. Optimum pH values for biosorption of copper (II), chromium (III), nickel (II), and lead (II) from aqueous solutions were determined to be 6, 7, 7, and 3 for Cladophora sp. and 5, 3, 5, and 4 for Chara sp. respectively. Maximum adsorption capacities of Chara sp. [10.54 for chromium (III) and 61.72 for lead (II)] and Cladophora sp. [6.59 for chromium (III) and 16.75 and 23.25 for lead (II)] for chromium (III) and lead (II) are similar. On the other hand, copper (II) and nickel (II) biosorption capacity of Cladophora sp. [14.28 for copper (II) and 16.75 for nickel (II)] is greater than Chara sp. [6.506 for copper (II) and 11.76 for nickel (II)]. Significantly high correlation coefficients indicated for the Langmuir adsorption isotherm models can be used to describe the equilibrium behavior of copper, chromium, nickel, and lead adsorption onto Cladophora sp. and Chara sp.

Comparison and characterization of biosorption by Weissella viridescens MYU 205 of periodic group 12 metal ions.

PubMed

Kinoshita, Hideki; Ohtake, Fumika; Ariga, Yuuki; Kimura, Kazuhiko

2016-02-01

Because heavy metals cause various health hazards, we studied biosorption by Weissella viridescens MYU 205. MYU 205 showed high biosorption for Cd (II) and Hg (II) and was low for Zn (II). The Hg (II) biosorption rate was high at about 80%. Different biosorptions were shown for each metal after successive incubation. About 20% of the Zn (II) biosorption was observed after 3 h. Cd (II) biosorption increased in a time-dependent manner until 3 h, then gradually decreased. Hg (II) was immediately sorbed at 79.6 ± 4.7% and decreased at 3 h to 52.9 ± 2.6%, and then gradually increased to 77.8 ± 3.6%. Using heat-killed cells, the rate of biosorption of Zn (II) and Cd (II) decreased whereas Hg (II) tended to increase. The metal resistance was high, that is Zn (II) > Cd (II) > Hg (II); while the affinity was opposite where MYU 205 showed high affinity to Hg (II) and low affinity to Zn (II). Our data shows lactic acid bacteria may be powerful heavy metal sorbents for detoxification. © 2015 Japanese Society of Animal Science.

Nanomolar Copper Enhances Mercury Methylation by Desulfovibrio desulfuricans ND132

DOE PAGES

Lu, Xia; Johs, Alexander; Zhao, Linduo; ...

2018-05-29

Methylmercury (MeHg) is produced by certain anaerobic microorganisms, such as the sulfate-reducing bacterium Desulfovibrio desulfuricans ND132, but environmental factors affecting inorganic mercury [Hg(II)] uptake and methylation remain unclear. We report that the presence of a small amount of copper ions [Cu(II), <100 nM] enhances Hg(II) uptake and methylation by washed cells of ND132, while Hg(II) methylation is inhibited at higher Cu(II) concentrations because of the toxicity of copper to the microorganism. The enhancement or inhibitory effect of Cu(II) is dependent on both time and concentration. The presence of nanomolar concentrations of Cu(II) facilitates rapid uptake of Hg(II) (within minutes) andmore » doubles MeHg production within a 24 h period, but micromolar concentrations of Cu(II) completely inhibit Hg(II) methylation. Metal ions such as zinc [Zn(II)] and nickel [Ni(II)] also inhibit but do not enhance Hg(II) methylation under the same experimental conditions. Furthermore, these observations suggest a synergistic effect of Cu(II) on Hg(II) uptake and methylation, possibly facilitated by copper transporters or metallochaperones in this organism, and highlight the fact that complex environmental factors affect MeHg production in the environment.« less

Fe (III), Co(II), Ni(II), Cu(II) and Zn(II) complexes of schiff bases based-on glycine and phenylalanine: Synthesis, magnetic/thermal properties and antimicrobial activity

NASA Astrophysics Data System (ADS)

Sevgi, Fatih; Bagkesici, Ugur; Kursunlu, Ahmed Nuri; Guler, Ersin

2018-02-01

Zinc (II), copper (II), nickel (II), cobalt (II) and iron (III) complexes of Schiff bases (LG, LP) derived from 2-hydroxynaphthaldehyde with glycine and phenylalanine were reported and characterized by 1H NMR, 13C NMR, elemental analyses, melting point, FT-IR, magnetic susceptibility and thermal analyses (TGA). TGA data show that iron and cobalt include to the coordinated water and metal:ligand ratio is 1:2 while the complex stoichiometry for Ni (II), Cu (II) and Zn (II) complexes is 1:1. As expected, Ni (II) and Zn (II) complexes are diamagnetic; Cu (II), Co (II) and Fe (III) complexes are paramagnetic character due to a strong ligand of LG and LP. The LG, LP and their metal complexes were screened for their antimicrobial activities against five Gram-positive (Staphylococcus aureus, Methicillin resistant Staphylococcus aureus (MRSA), Bacillus cereus, Streptococcus mutans and Enterococcus faecalis) and three Gram-negative (Escherichia coli, Klebsiella pneumoniae and Pseudomonas aeruginosa) and one fungi (Candida albicans) by using broth microdilution techniques. The activity data show that ligands and their metal complexes exhibited moderate to good activity against Gram-positive bacteria and fungi.

Cadmium(II) and lead(II) adsorption onto hetero-atom functional mesoporous silica and activated carbon

NASA Astrophysics Data System (ADS)

Machida, Motoi; Fotoohi, Babak; Amamo, Yoshimasa; Mercier, Louis

2012-07-01

Adsorption of cadmium(II) and lead(II) on amino-, mercapto-functionalized mesoporous silica (HMS) and carboxylic-functionalized activated carbon (AC) were examined. The resultant isotherms fitted the Langmuir model and amino-functionalized HMS exhibited the highest adsorption capacity for both cadmium(II) and lead(II). Adsorption affinities for cadmium(II) were always greater than those for lead(II) in all three adsorbent types, while the difference between the two values was the largest for mercapto-functionalized HMS indicating a selective adsorption of cadmium(II). Influence of equilibrium solution pH on adsorption of cadmium(II), lead(II) and their binary mixtures was also studied. Carboxylic-functionalized AC adsorbed cadmium(II) and lead(II) in a wide pH range than conditions for the mercapto-functionalized HMS. It was concluded that each functional group had its own characteristics and advantages for adsorption of heavy metal ions; amino-groups showed high adsorption capacity, while mercapto-groups had good selectivity toward cadmium(II) adsorption and a wide solution pH in adsorption by carboxylic-groups were established in this study.

Synthesis, spectroscopic characterization, thermal analysis and electrical conductivity studies of Mg(II), Ca(II), Sr(II) and Ba(II) vitamin B2 complexes

NASA Astrophysics Data System (ADS)

Refat, Moamen S.; Moussa, Mohamed A. A.; Mohamed, Soha F.

2011-05-01

Riboflavin (RF) complexes of Mg(II), Ca(II), Sr(II) and Ba(II) were successfully synthesized. Structures of metal complexes obtained were confirmed and characterized by elemental analysis, molar conductance, and infrared spectra. DC electrical conductivity measurements indicated that the alkaline earth metal (II) complexes of RF ligand are non-electrolytes. Elemental analysis of chelates suggest that the metal(II) ligand ratio is 1:2 with structure formula as [M(RF) 2( X) 2]· nH 2O. Infrared assignments clearly show that RF ligand coordinated as a bidentate feature through azomethine nitrogen of pyrazine ring and C dbnd O of pyrimidine-2,4-dione. Thermal analyses of Mg(II), Ca(II), Sr(II) and Ba(II) complexes were investigated using (TG/DSC) under atmospheric nitrogen between 30 and 800 °C. The surface morphology of the complexes was studied by SEM. The electrical conductivities of RF and its metal complexes were also measured with DC electrical conductivity in the temperature range from room to 483 K.

Nucleoside-2',3'/3',5'-bis(thio)phosphate antioxidants are also capable of disassembly of amyloid beta42-Zn(ii)/Cu(ii) aggregates via Zn(ii)/Cu(ii)-chelation.

PubMed

Hevroni, Bosmat Levi; Major, Dan Thomas; Dixit, Mudit; Mhashal, Anil Ranu; Das, Susanta; Fischer, Bilha

2016-05-18

Currently, there is an urgent need for biocompatible metal-ion chelators capable of antioxidant activity and disassembly of amyloid beta (Aβ)-aggregates as potential therapeutics for Alzheimer's disease (AD). We recently demonstrated the promising antioxidant activity of adenine/guanine 2',3' or 3',5'-bis(thio)phosphate analogues, 2'-dA/G3'5'PO/S and A2'3'PO/S, and their affinity to Zn(ii)-ions. These findings encouraged us to evaluate them as agents for the dissolution of Aβ42-Zn(ii)/Cu(ii) aggregates. Specifically, we explored their ability to bind Cu(ii)/Zn(ii)-ions, the geometry and stoichiometry of these complexes, Cu(ii)/Zn(ii)-binding-sites and binding mode, and the ability of these analogues to dissolve Aβ42-Zn(ii)/Cu(ii) aggregates, as well as their effect on the secondary structure of those aggregates. Finally, we identified the most promising agents for dissolution of Aβ42-Zn(ii)/Cu(ii) aggregates. Specifically, we observed the formation of a 1 : 1 complex between 2'-dG3'5'PO and Cu(ii), involving O4 ligands. Zn(ii) was coordinated by both thiophosphate groups of 2'-dA3'5'PS and A2'3'PS involving O2S2 ligands in a 1 : 1 stoichiometry. A2'3'PS dissolves Aβ42-Zn(ii) and Aβ42-Cu(ii) aggregates as effectively as, and 2.5-fold more effectively than EDTA, respectively. Furthermore, 2'-dG3'5'PS and A2'3'PS reverted the Aβ42-M(ii) structure, back to that of the free Aβ42. Finally, cryo-TEM and TEM images confirmed the disassembly of Aβ42 and Aβ42-M(ii) aggregates by A2'3'PS. Hence, 2'-dG3'5'PS and A2'3'PS may serve as promising scaffolds for new AD therapeutics, acting as both effective antioxidants and agents for solubilization of Aβ42-Cu(ii)/Zn(ii) aggregates.

Average [O II] nebular emission associated with Mg II absorbers: dependence on Fe II absorption

NASA Astrophysics Data System (ADS)

Joshi, Ravi; Srianand, Raghunathan; Petitjean, Patrick; Noterdaeme, Pasquier

2018-05-01

We investigate the effect of Fe II equivalent width (W2600) and fibre size on the average luminosity of [O II] λλ3727, 3729 nebular emission associated with Mg II absorbers (at 0.55 ≤ z ≤ 1.3) in the composite spectra of quasars obtained with 3 and 2 arcsec fibres in the Sloan Digital Sky Survey. We confirm the presence of strong correlations between [O II] luminosity (L_{[O II]}) and equivalent width (W2796) and redshift of Mg II absorbers. However, we show L_{[O II]} and average luminosity surface density suffer from fibre size effects. More importantly, for a given fibre size, the average L_{[O II]} strongly depends on the equivalent width of Fe II absorption lines and found to be higher for Mg II absorbers with R ≡W2600/W2796 ≥ 0.5. In fact, we show the observed strong correlations of L_{[O II]} with W2796 and z of Mg II absorbers are mainly driven by such systems. Direct [O II] detections also confirm the link between L_{[O II]} and R. Therefore, one has to pay attention to the fibre losses and dependence of redshift evolution of Mg II absorbers on W2600 before using them as a luminosity unbiased probe of global star formation rate density. We show that the [O II] nebular emission detected in the stacked spectrum is not dominated by few direct detections (i.e. detections ≥3σ significant level). On an average, the systems with R ≥ 0.5 and W2796 ≥ 2 Å are more reddened, showing colour excess E(B - V) ˜ 0.02, with respect to the systems with R < 0.5 and most likely trace the high H I column density systems.

Simultaneous Stripping Detection of Pb(II), Cd(II) and Zn(II) Using a Bimetallic Hg-Bi/Single-Walled Carbon Nanotubes Composite Electrode

PubMed Central

Ouyang, Ruizhuo; Zhu, Zhenqian; Tatum, Clarissa E.; Chambers, James Q.; Xue, Zi-Ling

2011-01-01

A new, sensitive platform for the simultaneous electrochemical assay of Zn(II), Cd(II) and Pb(II) in aqueous solution has been developed. The platform is based on a new bimetallic Hg-Bi/single-walled carbon nanotubes (SWNTs) composite modified glassy carbon electrode (GCE), demonstrating remarkably improved performance for the anodic stripping assay of Zn(II), Cd(II) and Pb(II). The synergistic effect of Hg and Bi as well as the enlarged, activated surface and good electrical conductivity of SWNTs on GCE contribute to the enhanced activity of the proposed electrode. The analytical curves for Zn(II), Cd(II) an Pb(II) cover two linear ranges varying from 0.5 to 11 μg L-1 and 10 to 130 μg L-1 with correlation coefficients higher than 0.992. The limits of detection for Zn(II), Cd(II) are lower than 2 μg L-1 (S/N = 3). For Pb(II), moreover, there is another lower, linear range from 5 to 1100 ng L-1 with a coefficient of 0.987 and a detection limit of 0.12 ng L-1. By using the standard addition method, Zn(II), Cd(II) and Pb(II) ions in river samples were successfully determined. These results suggest that the proposed method can be applied as a simple, efficient alternative for the simultaneous monitoring of heavy metals in water samples. In addition, this method demonstrates the powerful application of carbon nanotubes in electrochemical analysis of heavy metals. PMID:21660117

Heterobimetallic Complexes with MIII-(μ-OH)-MII Cores (MIII = Fe, Mn, Ga; MII = Ca, Sr, and Ba): Structural, Kinetic, and Redox Properties.

PubMed

Park, Young Jun; Cook, Sarah A; Sickerman, Nathaniel S; Sano, Yohei; Ziller, Joseph W; Borovik, A S

2013-02-01

The effects of redox-inactive metal ions on dioxygen activation were explored using a new Fe II complex containing a tripodal ligand with 3 sulfonamido groups. This iron complex exhibited a faster initial rate for the reduction of O 2 than its Mn II analog. Increases in initial rates were also observed in the presence of group 2 metal ions for both the Fe II and Mn II complexes, which followed the trend NMe 4 + < Ba II < Ca II = Sr II . These studies led to the isolation of heterobimetallic complexes containing Fe III -( μ -OH)-M II cores (M II = Ca, Sr, and Ba) and one with a [Sr II (OH)Mn III ] + motif. The analogous [Ca II (OH)Ga III ] + complex was also prepared and its solid state molecular structure is nearly identical to that of the [Ca II (OH)Fe III ] + system. Nuclear magnetic resonance studies indicated that the diamagnetic [Ca II (OH)Ga III ] + complex retained its structure in solution. Electrochemical measurements on the heterobimetallic systems revealed similar one-electron reduction potentials for the [Ca II (OH)Fe III ] + and [Sr II (OH)Fe III ] + complexes, which were more positive than the potential observed for [Ba II (OH)Fe III ] + . Similar results were obtained for the heterobimetallic Mn II complexes. These findings suggest that Lewis acidity is not the only factor to consider when evaluating the effects of group 2 ions on redox processes, including those within the oxygen-evolving complex of Photosystem II.

The B2 Alternatively Spliced Isoform of Nonmuscle Myosin II-B Lacks Actin-activated MgATPase Activity and In Vitro Motility

PubMed Central

Kim, Kye-Young; Kawamoto, Sachiyo; Bao, Jianjun; Sellers, James R.; Adelstein, Robert S.

2008-01-01

We report the initial biochemical characterization of an alternatively spliced isoform of nonmuscle heavy meromyosin (HMM) II-B2 and compare it with HMM II-B0, the non-spliced isoform. HMM II-B2 is the HMM derivative of an alternatively spliced isoform of endogenous nonmuscle myosin (NM) II-B, which has 21-amino acids inserted into loop 2, near the actin-binding region. NM II-B2 is expressed in the Purkinje cells of the cerebellum as well as in other neuronal cells (Ma et al., Mol. Biol. Cell 15 (2006) 2138-2149). In contrast to any of the previously described isoforms of NM II (II-A, II-B0, II-B1, II-C0 and II-C1) or to smooth muscle myosin, the actin-activated MgATPase activity of HMM II-B2 is not significantly increased from a low, basal level by phosphorylation of the 20 kDa myosin light chain (MLC-20). Moreover, although HMM II-B2 can bind to actin in the absence of ATP and is released in its presence, it cannot propel actin in the sliding actin filament assay following MLC-20 phosphorylation. Unlike HMM II-B2, the actin-activated MgATPase activity of a chimeric HMM with the 21-amino acids II-B2 sequence inserted into the homologous location in the heavy chain of HMM II-C is increased following MLC-20 phosphorylation. This indicates that the effect of the II-B2 insert is myosin heavy chain specific. PMID:18060863

Electrochemical studies of DNA interaction and antimicrobial activities of MnII, FeIII, CoII and NiII Schiff base tetraazamacrocyclic complexes

NASA Astrophysics Data System (ADS)

Kumar, Anuj; Vashistha, Vinod Kumar; Tevatia, Prashant; Singh, Randhir

2017-04-01

Tetraazamacrocyclic complexes of MnII, FeIII, CoII and NiII have been synthesized by template method. These tetraazamacrocycles have been analyzed with various techniques like molar conductance, IR, UV-vis, mass spectral and cyclic voltammetric studies. On the basis of all these studies, octahedral geometry has been assigned to these tetraazamacrocyclic complexes. The DNA binding properties of these macrocyclic complexes have been investigated by electronic absorption spectra, fluorescence spectra, cyclic voltammetric and differential pulse voltammetric studies. The cyclic voltammetric data showed that ipc and ipa were effectively decreased in the presence of calf thymus DNA, which is a strong evidence for the interaction of these macrocyclic complexes with the calf thymus DNA (ct-DNA). The heterogeneous electron transfer rate constant found in the order: KCoII > KNiII > KMnII which indicates that CoII macrocyclic complex has formed a strong intercalated intermediate. The Stern-Volmer quenching constant (KSV) and voltammetric binding constant were found in the order KSV(CoII) > KSV(NiII) > KSV(MnII) and K+(CoII) > K+(NiII) > K+(MnII) which shows that CoII macrocyclic complex exhibits the high interaction affinity towards ct-DNA by the intercalation binding. Biological studies of the macrocyclic complexes compared with the standard drug like Gentamycin, have shown antibacterial activities against E. coli, P. aeruginosa, B. cereus, S. aureus and antifungal activity against C. albicans.

Synthesis, characterization, and ligand exchange reactivity of a series of first row divalent metal 3-hydroxyflavonolate complexes.

PubMed

Grubel, Katarzyna; Rudzka, Katarzyna; Arif, Atta M; Klotz, Katie L; Halfen, Jason A; Berreau, Lisa M

2010-01-04

A series of divalent metal flavonolate complexes of the general formula [(6-Ph(2)TPA)M(3-Hfl)]X (1-5-X; X = OTf(-) or ClO(4)(-); 6-Ph(2)TPA = N,N-bis((6-phenyl-2-pyridyl)methyl)-N-((2-pyridyl)methyl)amine; M = Mn(II), Co(II), Ni(II), Cu(II), Zn(II); 3-Hfl = 3-hydroxyflavonolate) were prepared and characterized by X-ray crystallography, elemental analysis, FTIR, UV-vis, (1)H NMR or EPR, and cyclic voltammetry. All of the complexes have a bidentate coordinated flavonolate ligand. The difference in M-O distances (Delta(M-O)) involving this ligand varies through the series, with the asymmetry of flavonolate coordination increasing in the order Mn(II) approximately Ni(II) < Cu(II) < Zn(II) < Co(II). The hypsochromic shift of the absorption band I (pi-->pi*) of the coordinated flavonolate ligand in 1-5-OTf (relative to that in free anion) increases in the order Ni(II) < Mn(II) < Cu(II) < Zn(II), Co(II). Previously reported 3-Hfl complexes of divalent metals fit well with this ordering. (1)H NMR studies indicate that the 3-Hfl complexes of Co(II), Ni(II), and Zn(II) exhibit a pseudo-octahedral geometry in solution. EPR studies suggest that the Mn(II) complex 1-OTf may form binuclear structures in solution. The mononuclear Cu(II) complex 4-OTf has a distorted square pyramidal geometry. The oxidation potential of the flavonolate ligand depends on the metal ion present and/or the solution structure of the complex, with the Mn(II) complex 1-OTf exhibiting the lowest potential, followed by the pseudo-octahedral Ni(II) and Zn(II) 3-Hfl complexes, and the distorted square pyramidal Cu(II) complex 4-OTf. The Mn(II) complex [(6-Ph(2)TPA)Mn(3-Hfl)]OTf (1-OTf) is unique in the series in undergoing ligand exchange reactions in the presence of M(ClO(4))(2).6H(2)O (M = Co, Ni, Zn) in CD(3)CN to produce [(6-Ph(2)TPA)M(CD(3)CN)(n)](X)(2), [Mn(3-Hfl)(2).0.5H(2)O], and MnX(2) (X = OTf(-) or ClO(4)(-)). Under similar conditions, the 3-Hfl complexes of Co(II), Ni(II), and Cu(II) undergo flavonolate ligand exchange to produce [(6-Ph(2)TPA)M(CD(3)CN)(n)](X)(2) (M = Co, Ni, Cu; n = 1 or 2) and [Zn(3-Hfl)(2).2H(2)O]. An Fe(II) complex of 3-Hfl, [(6-Ph(2)TPA)Fe(3-Hfl)]ClO(4) (8), was isolated and characterized by elemental analysis, FTIR, UV-vis, (1)H NMR, cyclic voltammetry, and a magnetic moment measurement. This complex reacts with O(2) to produce the diiron(III) mu-oxo compound [(6-Ph(2)TPAFe(3Hfl))(2)(mu-O)](ClO(4))(2) (6).

Ferrate(VI)-Prompted Removal of Metals in Aqueous Media: Mechanistic Delineation of Enhanced Efficiency via Metal Entrenchment in Magnetic Oxides

EPA Science Inventory

The removal efficiency of heavy metal ions (cadmium(II) – Cd(II), cobalt(II) – Co(II), nickel(II) – Ni(II), and copper(II) – Cu(II)) by potassium ferrate(VI) (K2FeO4, Fe(VI)), was studied as a function of added amount of Fe(VI) (or Fe) and varying pH. At pH = 6.6, the effective r...

78 FR 46369 - Importer of Controlled Substances; Notice of Application; Research Triangle Institute

Federal Register 2010, 2011, 2012, 2013, 2014

2013-07-31

... Anileridine (9020) II Bezitramide (9800) II Carfentanil (9743) II Coca Leaves (9040) II Cocaine (9041) II... controlled substances listed in schedule I or II, which fall under the authority of section 1002(a)(2)(B) of...

Maternal insulin-like growth factor-II promotes placental functional development via the type 2 IGF receptor in the guinea pig.

PubMed

Sferruzzi-Perri, A N; Owens, J A; Standen, P; Roberts, C T

2008-04-01

In guinea pigs, maternal insulin-like growth factor (IGF) infusion in early-pregnancy enhances placental transport near-term, increasing fetal growth and survival. The effects of IGF-II, but not IGF-I, appear due to enhanced placental labyrinthine (exchange) development. To determine if the type-2 IGF receptor (IGF2R) mediates these distinct actions of exogenous IGF-II in the mother, we compared the impact of IGF-II with an IGF-II analogue, Leu(27)-IGF-II, which only binds the IGF2R. IGF-II, Leu(27)-IGF-II (1mg/kg per day.sc) or vehicle were infused from days 20-38 of pregnancy (term = 67 days) and placental structure and uptake and transfer of [(3)H]-methyl-D-glucose (MG) and [(14)C]-amino-isobutyric acid (AIB) and fetal growth and plasma metabolites, were measured on day 62. Both IGF-II and Leu(27)-IGF-II increased the volume of placental labyrinth, trophoblast and maternal blood space within the labyrinth and total surface area of trophoblast for exchange, compared to vehicle. Leu(27)-IGF-II also reduced the barrier to diffusion (trophoblast thickness) compared to vehicle and IGF-II. Both IGF-II and Leu(27)-IGF-II increased fetal plasma amino acid concentrations and placental transfer of MG to the fetus compared to vehicle, with Leu(27)-IGF-II also increasing AIB transport compared with vehicle and IGF-II. In addition, Leu(27)-IGF-II increased fetal weight compared to vehicle. In conclusion, maternal treatment with IGF-II or Leu(27)-IGF-II in early gestation, induce similar placental and fetal outcomes near term. This suggests that maternal IGF-II in early gestation acts in part via the IGF2R to persistently enhance placental functional development and nutrient delivery and promote fetal growth.

Whole-genome sequence of Cupriavidus sp. strain BIS7, a heavy-metal-resistant bacterium.

PubMed

Hong, Kar Wai; Thinagaran, Dinaiz al; Gan, Han Ming; Yin, Wai-Fong; Chan, Kok-Gan

2012-11-01

Cupriavidus sp. strain BIS7 is a Malaysian tropical soil bacterium that exhibits broad heavy-metal resistance [Co(II), Zn(II), Ni(II), Se(IV), Cu(II), chromate, Co(III), Fe(II), and Fe(III)]. It is particularly resistant to Fe(II), Fe(III), and Zn(II). Here we present the assembly and annotation of its genome.

U.S. EPA, Pesticide Product Label, DIAZINON 4 SPRAY, 10/04/1993

EPA Pesticide Factsheets

2011-04-21

... iIiHf III lill ~lflilf IIH ; Ii f ti' '11-III'n! 1]1 Ihfl JIlL III illi'l f 111"1 ,1111 III ILl Iltll! II', ~tlf II JII! ,11111 ' I'i, t $'1 it I Itit ,.11 jilt! if II! W!JIIU, JI I i II t J IL If '"' : If 5.:0 ...

Iodometric determination of peroxydiphosphate in the presence of copper(II) or iron(II) as catalyst.

PubMed

Kapoor, S; Sharma, P D; Gupta, Y K

1975-09-01

Peroxydiphosphate can be determined iodometrically in the presence of a large excess of potassium iodide with copper(II) or iron(II) as catalyst through the operation of the Cu(II)/Cu(I) or Fe(II)/Fe(III) cycle. The method is applicable in HClO(4), H(2)SO(4), HCl and CH(3)COOH acid media in the range 0.1-1.0M studied. Nickel, manganese(II), cobalt(II), silver, chloride and phosphate are without effect.

THE CONNECTIONS BETWEEN THE UV AND OPTICAL Fe ii EMISSION LINES IN TYPE 1 AGNs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kovacević-Dojcinović, Jelena; Popović, Luka Č., E-mail: jkovacevic@aob.bg.ac.rs, E-mail: lpopovic@aob.bg.ac.rs

We investigate the spectral properties of the UV (λλ2650–3050 Å) and optical (λλ4000–5500 Å) Fe ii emission features in a sample of 293 Type 1 active galactic nuclei (AGNs) from the Sloan Digital Sky Survey database. We explore different correlations between their emission line properties, as well as the correlations with other emission lines from the spectral range. We find several interesting correlations and outline the most interesting results as follows. (i) There is a kinematical connection between the UV and optical Fe ii lines, indicating that the UV and optical Fe ii lines originate from the outer part ofmore » the broad line region, the so-called intermediate line region. (ii) The unexplained anticorrelations of the optical Fe ii equivalent width (EW Fe ii{sub opt}) versus EW [O iii] 5007 Å and EW Fe ii{sub opt} versus FWHM Hβ have not been detected for the UV Fe ii lines. (iii) The significant averaged redshift in the UV Fe ii lines, which is not present in optical Fe ii, indicates an inflow in the UV Fe ii emitting clouds, and probably their asymmetric distribution. (iv) Also, we confirm the anticorrelation between the intensity ratio of the optical and UV Fe ii lines and the FWHM of Hβ, and we find the anticorrelations of this ratio with the widths of Mg ii 2800 Å, optical Fe ii, and UV Fe ii. This indicates a very important role for the column density and microturbulence in the emitting gas. We discuss the starburst activity in high-density regions of young AGNs as a possible explanation of the detected optical Fe ii correlations and intensity line ratios of the UV and optical Fe ii lines.« less

Intracellular Zn(II) Intoxication Leads to Dysregulation of the PerR Regulon Resulting in Heme Toxicity in Bacillus subtilis

PubMed Central

2016-01-01

Transition metal ions (Zn(II), Cu(II)/(I), Fe(III)/(II), Mn(II)) are essential for life and participate in a wide range of biological functions. Cellular Zn(II) levels must be high enough to ensure that it can perform its essential roles. Yet, since Zn(II) binds to ligands with high avidity, excess Zn(II) can lead to protein mismetallation. The major targets of mismetallation, and the underlying causes of Zn(II) intoxication, are not well understood. Here, we use a forward genetic selection to identify targets of Zn(II) toxicity. In wild-type cells, in which Zn(II) efflux prevents intoxication of the cytoplasm, extracellular Zn(II) inhibits the electron transport chain due to the inactivation of the major aerobic cytochrome oxidase. This toxicity can be ameliorated by depression of an alternate oxidase or by mutations that restrict access of Zn(II) to the cell surface. Conversely, efflux deficient cells are sensitive to low levels of Zn(II) that do not inhibit the respiratory chain. Under these conditions, intracellular Zn(II) accumulates and leads to heme toxicity. Heme accumulation results from dysregulation of the regulon controlled by PerR, a metal-dependent repressor of peroxide stress genes. When metallated with Fe(II) or Mn(II), PerR represses both heme biosynthesis (hemAXCDBL operon) and the abundant heme protein catalase (katA). Metallation of PerR with Zn(II) disrupts this coordination, resulting in depression of heme biosynthesis but continued repression of catalase. Our results support a model in which excess heme partitions to the membrane and undergoes redox cycling catalyzed by reduced menaquinone thereby resulting in oxidative stress. PMID:27935957

Mitogen-activated protein kinase is required for the behavioral desensitization that occurs after repeated injections of angiotensin II

PubMed Central

Vento, Peter J.; Daniels, Derek

2013-01-01

Angiotensin II (AngII) acts on central angiotensin type 1 (AT1) receptors to increase water and saline intake. Prolonged exposure to AngII in cell culture models results in a desensitization of the AT1 receptor that is thought to involve receptor internalization, and a behavioral correlate of this desensitization has been shown in rats after repeated central injections of AngII. Specifically, rats given repeated injections of AngII drink less water than controls after a subsequent test injection of AngII. Under the same conditions, however, repeated injections of AngII have no effect on AngII-induced saline intake. Given earlier studies indicating that separate intracellular signaling pathways mediate AngII-induced water and saline intake, we hypothesized that the desensitization observed in rats may be incomplete, leaving the receptor able to activate mitogen-activated protein (MAP) kinases (ERK1/2), which play a role in AngII-induced saline intake without affecting water intake. In support of this hypothesis, we found no difference in MAP kinase phosphorylation after an AngII test injection in rats given prior treatment with repeated injections of vehicle, AngII, or Sar1,Ile4,Ile8-AngII (SII), an AngII analog that activates MAP kinase without G protein coupling. In addition, we found that pretreatment with the MAP kinase inhibitor U0126 completely blocked the desensitizing effect of repeated AngII injections on water intake. Furthermore, AngII-induced water intake was reduced similarly by repeated injections of AngII or SII. The results suggest that G protein-independent signaling is sufficient to produce behavioral desensitization of the angiotensin system and that the desensitization requires MAP kinase activation. PMID:22581747

Mitogen-activated protein kinase is required for the behavioural desensitization that occurs after repeated injections of angiotensin II.

PubMed

Vento, Peter J; Daniels, Derek

2012-12-01

Angiotensin II (Ang II) acts on central angiotensin type 1 (AT(1)) receptors to increase water and saline intake. Prolonged exposure to Ang II in cell culture models results in a desensitization of the AT(1) receptor that is thought to involve receptor internalization, and a behavioural correlate of this desensitization has been shown in rats after repeated central injections of Ang II. Specifically, rats given repeated injections of Ang II drink less water than control animals after a subsequent test injection of Ang II. In the same conditions, however, repeated injections of Ang II have no effect on Ang II-induced saline intake. Given earlier studies indicating that separate intracellular signalling pathways mediate Ang II-induced water and saline intake, we hypothesized that the desensitization observed in rats may be incomplete, leaving the receptor able to activate mitogen-activated protein (MAP) kinases (ERK1/2), which play a role in Ang II-induced saline intake without affecting water intake. In support of this hypothesis, we found no difference in MAP kinase phosphorylation after an Ang II test injection in rats given prior treatment with repeated injections of vehicle, Ang II or Sar(1),Ile(4),Ile(8)-Ang II (SII), an Ang II analogue that activates MAP kinase without G protein coupling. In addition, we found that pretreatment with the MAP kinase inhibitor U0126 completely blocked the desensitizing effect of repeated Ang II injections on water intake. Furthermore, Ang II-induced water intake was reduced to a similar extent by repeated injections of Ang II or SII. The results suggest that G protein-independent signalling is sufficient to produce behavioural desensitization of the angiotensin system and that the desensitization requires MAP kinase activation.

Metal selectivity of the E. coli nickel metallochaperone, SlyD

PubMed Central

Kaluarachchi, Harini; Siebel, Judith F.; Kaluarachchi-Duffy, Supipi; Krecisz, Sandra; Sutherland, Duncan E. K.; Stillman, Martin J.; Zamble, Deborah B.

2012-01-01

SlyD is a Ni(II)-binding protein that contributes to nickel homeostasis in Escherichia coli. The C-terminal domain of SlyD contains a rich variety of metal-binding amino acids, suggesting broader metal-binding capabilities, and previous work demonstrated that the protein can coordinate several types of first row transition metals. However, the binding of SlyD to metals other than Ni(II) has not been previously characterized. To further our understanding of the in vitro metal-binding activity of SlyD and how it correlates with the in vivo function of this protein, the interactions between SlyD and the series of biologically relevant transition metals Mn(II), Fe(II), Co(II), Cu(I) and Zn(II) were examined by using a combination of optical spectroscopy and mass spectrometry. SlyD binding to Mn(II) or to Fe(II) ions was not detected but the protein coordinates multiple ions of Co(II), Zn(II) and Cu(I) with appreciable affinities (KD ≤ nM), highlighting the promiscuous nature of this protein. The order of affinities of SlyD for the metals examined is Mn(II), Fe(II) < Co(II) < Ni(II) ~ Zn(II) ≪ Cu(I). Although the purified protein is unable to overcome the large thermodynamic preference for Cu(I) and exclude Zn(II) chelation in the presence of Ni(II), in vivo studies reveal a Ni(II)-specific function for the protein. Furthermore, these latter experiments support a specific role for SlyD as a [NiFe]-hydrogenase enzyme maturation factor. The implications of the divergence between the metal selectivity of SlyD in vitro and the specific activity in vivo are discussed. PMID:22047179

The response to oestrogen deprivation of the cartilage collagen degradation marker, CTX-II, is unique compared with other markers of collagen turnover

PubMed Central

Bay-Jensen, Anne-Christine; Tabassi, Nadine CB; Sondergaard, Lene V; Andersen, Thomas L; Dagnaes-Hansen, Frederik; Garnero, Patrick; Kassem, Moustapha; Delaissé, Jean-Marie

2009-01-01

Introduction The urinary level of the type II collagen degradation marker CTX-II is increased in postmenopausal women and in ovariectomised rats, suggesting that oestrogen deprivation induces cartilage breakdown. Here we investigate whether this response to oestrogen is also true for other type II collagen turnover markers known to be affected in osteoarthritis, and whether it relates to its presence in specific areas of cartilage tissue. Methods The type II collagen degradation markers CTX-II and Helix-II were measured in the body fluids of premenopausal and postmenopausal women and in those of ovariectomised rats receiving oestrogen or not. Levels of PIIANP, a marker of type II collagen synthesis, were also measured in rats. Rat knee cartilage was analysed for immunoreactivity of CTX-II and PIIANP and for type II collagen expression. Results As expected, urinary levels of CTX-II are significantly increased in postmenopausal women and also in oestrogen-deprived rats, although only transiently. However, in neither case were these elevations paralleled by a significant increase of Helix-II levels and PIIANP levels did not change at any time. CTX-II immunoreactivity and collagen expression were detected in different cartilage areas. The upper zone is the area where CTX-II immunoreactivity and collagen expression best reflected the differences in urinary levels of CTX-II measured in response to oestrogen. However, correlations between urinary levels of CTX-II and tissue immunostainings in individual rats were not statistically significant. Conclusions We found only a small effect of oestrogen deprivation on cartilage. It was detected by CTX-II, but not by other type II collagen turnover markers typically affected in osteoarthritis. PMID:20527083

Manganese(II), iron(II), cobalt(II), and copper(II) complexes of an extended inherently chiral tris-bipyridyl cage.

PubMed

Perkins, David F; Lindoy, Leonard F; McAuley, Alexander; Meehan, George V; Turner, Peter

2006-01-17

Manganese(II), iron(II), cobalt(II), and copper(II) derivatives of two inherently chiral, Tris(bipyridyl) cages (L and L') of type [ML]-(PF(6))(2)(solvent)(n) and [FeL'](ClO(4))(2) are reported, where L is the hexa-tertiary butyl-substituted derivative of L'. These products were obtained by using the free cage and metal template procedures; the latter involved the reductive amination of the respective Tris-dialdehyde precursor complexes of iron(II), cobalt(II), or nickel(II). Electrochemical, EPR, and NMR studies have been used to probe the nature of the individual complexes. X-ray structures of the manganese(II), iron(II), and copper(II) complexes of L and the iron(II) complex of L' are presented; these are compared with the previously reported structures of the corresponding nickel(II) complex and metal-free cage (L). In each complex the metal cation occupies the cage's central cavity and is coordinated to six nitrogens from the three bipyridyl groups. The cations [MnL](2+) and [FeL](2+) are isostructural but both exhibit a different arrangement of the bound cage to that observed in the corresponding nickel(II) and copper(II) complexes. The latter have an exo-exo arrangement of the bridgehead nitrogen lone pairs, with the metal inducing a triple helical twist that extends approximately 22 A along the axial length of each complex. In contrast, [MnL](2+) and [FeL](2+) have their terminal nitrogen lone pairs directed endo, causing a significant change in the configuration of the bound ligand. In [FeL'](2+), the cage has both bridgehead nitrogen lone pairs orientated exo. Semiempirical calculations indicate that the observed endo-endo and exo-exo arrangements are of comparable energy.

Mono-component versus binary isotherm models for Cu(II) and Pb(II) sorption from binary metal solution by the green alga Pithophora oedogonia.

PubMed

Kumar, Dhananjay; Singh, Alpana; Gaur, J P

2008-11-01

The sorption of Cu(II) and Pb(II) by Pithophora markedly decreased as the concentration of the secondary metal ion, Cu(II) or Pb(II), increased in the binary metal solution. However, the test alga showed a greater affinity to sorb Cu(II) than Pb(II) from the binary metal solution. Mono-component Freundlich, Langmuir, Redlich-Peterson and Sips isotherms successfully predicted the sorption of Cu(II) and Pb(II) from both single and binary metal solutions. None of the tested binary sorption isotherms could realistically predict Cu(II) and Pb(II) sorption capacity and affinity of the test alga for the binary metal solutions of varying composition, which mono-component isotherms could very well accomplish. Hence, mono-component isotherm modeling at different concentrations of the secondary metal ion seems to be a better option than binary isotherms for metal sorption from binary metal solution.

Protein kinase C βII and TGFβRII in ω-3 fatty acid–mediated inhibition of colon carcinogenesis

PubMed Central

Murray, Nicole R.; Weems, Capella; Chen, Lu; Leon, Jessica; Yu, Wangsheng; Davidson, Laurie A.; Jamieson, Lee; Chapkin, Robert S.; Thompson, E. Aubrey; Fields, Alan P.

2002-01-01

Încreasing evidence demonstrates that protein kinase C βII (PKCβII) promotes colon carcinogenesis. We previously reported that colonic PKCβII is induced during colon carcinogenesis in rodents and humans, and that elevated expression of PKCβII in the colon of transgenic mice enhances colon carcinogenesis. Here, we demonstrate that PKCβII represses transforming growth factor β receptor type II (TGFβRII) expression and reduces sensitivity to TGF-β–mediated growth inhibition in intestinal epithelial cells. Transgenic PKCβII mice exhibit hyperproliferation, enhanced colon carcinogenesis, and marked repression of TGFβRII expression. Chemopreventive dietary ω-3 fatty acids inhibit colonic PKCβII activity in vivo and block PKCβII-mediated hyperproliferation, enhanced carcinogenesis, and repression of TGFβRII expression in the colonic epithelium of transgenic PKCβII mice. These data indicate that dietary ω-3 fatty acids prevent colon cancer, at least in part, through inhibition of colonic PKCβII signaling and restoration of TGF-β responsiveness. PMID:12058013

Synthesis, characterization and anti-microbial evaluation of Cu(II), Ni(II), Pt(II) and Pd(II) sulfonylhydrazone complexes; 2D-QSAR analysis of Ni(II) complexes of sulfonylhydrazone derivatives

NASA Astrophysics Data System (ADS)

Özbek, Neslihan; Alyar, Saliha; Alyar, Hamit; Şahin, Ertan; Karacan, Nurcan

2013-05-01

Copper(II), nickel(II), platinum(II) and palladium(II) complexes with 2-hydroxy-1-naphthaldehyde-N-methylpropanesulfonylhydrazone (nafpsmh) derived from propanesulfonic acid-1-methylhydrazide (psmh) were synthesized, their structure were identified, and antimicrobial activity of the compounds was screened against three Gram-positive and three Gram-negative bacteria. The results of antimicrobial studies indicate that Pt(II) and Pd(II) complexes showed the most activity against all bacteria. The crystal structure of 2-hydroxy-1-naphthaldehyde-N-methylpropanesulfonylhydrazone (nafpsmh) was also investigated by X-ray analysis. A series of Ni(II) sulfonyl hydrazone complexes (1-33) was synthesized and tested in vitro against Escherichia coli and Staphylococcus aureus. Their antimicrobial activities were used in the QSAR analysis. Four-parameter QSAR models revealed that nucleophilic reaction index for Ni and O atoms, and HOMO-LUMO energy gap play key roles in the antimicrobial activity.

Synthesis, spectroscopic characterization and biological activities of N4O2 Schiff base ligand and its metal complexes of Co(II), Ni(II), Cu(II) and Zn(II)

NASA Astrophysics Data System (ADS)

Al-Resayes, Saud I.; Shakir, Mohammad; Abbasi, Ambreen; Amin, Kr. Mohammad Yusuf; Lateef, Abdul

The Schiff base ligand, bis(indoline-2-one)triethylenetetramine (L) obtained from condensation of triethylenetetramine and isatin was used to synthesize the complexes of type, [ML]Cl2 [M = Co(II), Ni(II), Cu(II) and Zn(II)]. L was characterized on the basis of the results of elemental analysis, FT-IR, 1H and 13C NMR, mass spectroscopic studies. The stoichiometry, bonding and stereochemistries of complexes were ascertained on the basis of results of elemental analysis, magnetic susceptibility values, molar conductance and various spectroscopic studies. EPR, UV-vis and magnetic moments revealed an octahedral geometry for complexes. L and its Cu(II) and Zn(II) complexes were screened for their antibacterial activity. Analgesic activity of Cu(II) and Zn(II) complexes was also tested in rats by tail flick method. Both complexes were found to possess good antibacterial and moderate analgesic activity.

Formation of Rhamnogalacturonan II-Borate Dimer in Pectin Determines Cell Wall Thickness of Pumpkin Tissue1

PubMed Central

Ishii, Tadashi; Matsunaga, Toshiro; Hayashi, Noriko

2001-01-01

Boron (B) deficiency results in inhibition of pumpkin (Cucurbia moschata Duchesne) growth that is accompanied by swelling of the cell walls. Monomeric rhamnogalacturonan II (mRG-II) accounted for 80% to 90% of the total RG-II in B-deficient walls, whereas the borate ester cross-linked RG-II dimer (dRG-II-B) accounted for more than 80% of the RG-II in control plants. The results of glycosyl residue and glycosyl linkage composition analyses of the RG-II from control and B-deficient plants were similar. Thus, B deficiency does not alter the primary structure of RG-II. The addition of 10B-enriched boric acid to B-deficient plants resulted within 5 h in the conversion of mRG-II to dRG-II-10B. The wall thickness of the 10B-treated plants and control plants was similar. The formation and possible functions of a borate ester cross-linked RG-II in the cell walls are discussed. PMID:11500567

Whole-Genome Sequence of Cupriavidus sp. Strain BIS7, a Heavy-Metal-Resistant Bacterium

PubMed Central

Hong, Kar Wai; Thinagaran, Dinaiz a/l; Gan, Han Ming; Yin, Wai-Fong

2012-01-01

Cupriavidus sp. strain BIS7 is a Malaysian tropical soil bacterium that exhibits broad heavy-metal resistance [Co(II), Zn(II), Ni(II), Se(IV), Cu(II), chromate, Co(III), Fe(II), and Fe(III)]. It is particularly resistant to Fe(II), Fe(III), and Zn(II). Here we present the assembly and annotation of its genome. PMID:23115161

Shark class II invariant chain reveals ancient conserved relationships with cathepsins and MHC class II.

PubMed

Criscitiello, Michael F; Ohta, Yuko; Graham, Matthew D; Eubanks, Jeannine O; Chen, Patricia L; Flajnik, Martin F

2012-03-01

The invariant chain (Ii) is the critical third chain required for the MHC class II heterodimer to be properly guided through the cell, loaded with peptide, and expressed on the surface of antigen presenting cells. Here, we report the isolation of the nurse shark Ii gene, and the comparative analysis of Ii splice variants, expression, genomic organization, predicted structure, and function throughout vertebrate evolution. Alternative splicing to yield Ii with and without the putative protease-protective, thyroglobulin-like domain is as ancient as the MHC-based adaptive immune system, as our analyses in shark and lizard further show conservation of this mechanism in all vertebrate classes except bony fish. Remarkable coordinate expression of Ii and class II was found in shark tissues. Conserved Ii residues and cathepsin L orthologs suggest their long co-evolution in the antigen presentation pathway, and genomic analyses suggest 450 million years of conserved Ii exon/intron structure. Other than an extended linker preceding the thyroglobulin-like domain in cartilaginous fish, the Ii gene and protein are predicted to have largely similar physiology from shark to man. Duplicated Ii genes found only in teleosts appear to have become sub-functionalized, as one form is predicted to play the same role as that mediated by Ii mRNA alternative splicing in all other vertebrate classes. No Ii homologs or potential ancestors of any of the functional Ii domains were found in the jawless fish or lower chordates. Copyright © 2011 Elsevier Ltd. All rights reserved.

Synthesis and application of surface-imprinted activated carbon sorbent for solid-phase extraction and determination of copper (II)

NASA Astrophysics Data System (ADS)

Li, Zhenhua; Li, Jingwen; Wang, Yanbin; Wei, Yajun

2014-01-01

A new Cu(II)-imprinted amino-functionalized activated carbon sorbent was prepared by a surface imprinting technique for selective solid-phase extraction (SPE) of Cu(II) prior to its determination by inductively coupled plasma atomic emission spectrometry (ICP-AES). Experimental conditions for effective adsorption of Cu(II) were optimized with respect to different experimental parameters using static and dynamic procedures in detail. Compared with non-imprinted sorbent, the ion-imprinted sorbent had higher selectivity and adsorption capacity for Cu(II). The maximum static adsorption capacity of the ion-imprinted and non-imprinted sorbent for Cu(II) was 26.71 and 6.86 mg g-1, respectively. The relatively selectivity factor values (αr) of Cu(II)/Zn(II), Cu(II)/Ni(II), Cu(II)/Co(II) and Cu(II)/Pb(II) were 166.16, 50.77, 72.26 and 175.77, respectively, which were greater than 1. Complete elution of the adsorbed Cu(II) from Cu(II)-imprinted sorbent was carried out using 2 mL of 0.1 mol L-1 EDTA solution. The relative standard deviation of the method was 2.4% for eleven replicate determinations. The method was validated for the analysis by two certified reference materials (GBW 08301, GBW 08303), the results obtained is in good agreement with standard values. The developed method was also successfully applied to the determination of trace copper in natural water samples with satisfactory results.

Synthesis and application of surface-imprinted activated carbon sorbent for solid-phase extraction and determination of copper (II).

PubMed

Li, Zhenhua; Li, Jingwen; Wang, Yanbin; Wei, Yajun

2014-01-03

A new Cu(II)-imprinted amino-functionalized activated carbon sorbent was prepared by a surface imprinting technique for selective solid-phase extraction (SPE) of Cu(II) prior to its determination by inductively coupled plasma atomic emission spectrometry (ICP-AES). Experimental conditions for effective adsorption of Cu(II) were optimized with respect to different experimental parameters using static and dynamic procedures in detail. Compared with non-imprinted sorbent, the ion-imprinted sorbent had higher selectivity and adsorption capacity for Cu(II). The maximum static adsorption capacity of the ion-imprinted and non-imprinted sorbent for Cu(II) was 26.71 and 6.86 mg g(-1), respectively. The relatively selectivity factor values (αr) of Cu(II)/Zn(II), Cu(II)/Ni(II), Cu(II)/Co(II) and Cu(II)/Pb(II) were 166.16, 50.77, 72.26 and 175.77, respectively, which were greater than 1. Complete elution of the adsorbed Cu(II) from Cu(II)-imprinted sorbent was carried out using 2 mL of 0.1 mol L(-1) EDTA solution. The relative standard deviation of the method was 2.4% for eleven replicate determinations. The method was validated for the analysis by two certified reference materials (GBW 08301, GBW 08303), the results obtained is in good agreement with standard values. The developed method was also successfully applied to the determination of trace copper in natural water samples with satisfactory results. Copyright © 2013 Elsevier B.V. All rights reserved.

Mercerized mesoporous date pit activated carbon—A novel adsorbent to sequester potentially toxic divalent heavy metals from water

PubMed Central

Aldawsari, Abdullah; Hameed, B. H.; Alqadami, Ayoub Abdullah; Siddiqui, Masoom Raza; Alothman, Zeid Abdullah; Ahmed, A. Yacine Badjah Hadj

2017-01-01

A substantive approach converting waste date pits to mercerized mesoporous date pit activated carbon (DPAC) and utilizing it in the removal of Cd(II), Cu(II), Pb(II), and Zn(II) was reported. In general, rapid heavy metals adsorption kinetics for Co range: 25–100 mg/L was observed, accomplishing 77–97% adsorption within 15 min, finally, attaining equilibrium in 360 min. Linear and non-linear isotherm studies revealed Langmuir model applicability for Cd(II) and Pb(II) adsorption, while Freundlich model was fitted to Zn(II) and Cu(II) adsorption. Maximum monolayer adsorption capacities (qm) for Cd(II), Pb(II), Cu(II), and Zn(II) obtained by non-linear isotherm model at 298 K were 212.1, 133.5, 194.4, and 111 mg/g, respectively. Kinetics modeling parameters showed the applicability of pseudo-second-order model. The activation energy (Ea) magnitude revealed physical nature of adsorption. Maximum elution of Cu(II) (81.6%), Zn(II) (70.1%), Pb(II) (96%), and Cd(II) (78.2%) were observed with 0.1 M HCl. Thermogravimetric analysis of DPAC showed a total weight loss (in two-stages) of 28.3%. Infra-red spectral analysis showed the presence of carboxyl and hydroxyl groups over DPAC surface. The peaks at 820, 825, 845 and 885 cm-1 attributed to Zn–O, Pb–O, Cd–O, and Cu–O appeared on heavy metals saturated DPAC, confirmed their binding on DPAC during the adsorption. PMID:28910368

Comparison on the Surface Structure Properties along with Fe(II) and Mn(II) Removal Characteristics of Rice Husk Ash, Inactive Saccharomyces cerevisiae Powder, and Rice Husk

PubMed Central

Jiang, Zhao; Cao, Bo; Su, Guangxia; Lu, Yan; Zhao, Jiaying; Shan, Dexin; Zhang, Xiuyuan; Wang, Ziyi

2016-01-01

This study selected solid wastes, such as rice husk ash (RHA), inactive Saccharomyces cerevisiae powder (ISP), and rice husk (RH), as the potential adsorbents for the removal of Fe(II) and Mn(II) in aqueous solution. The structural characteristics, functional groups, and elemental compositions were determined by scanning electron microscope (SEM) and Fourier translation infrared spectrum (FT-IR) analyses, respectively. Then the influence on the Fe(II) and Mn(II) removing efficiency by the factors, such as pH, adsorbent dosage, initial Fe(II) and Mn(II) concentration, and contact time, was investigated by the static batch test. The adsorption isotherm study results show that Langmuir equation can better fit the Fe(II) and Mn(II) adsorption process by the three adsorbents. The maximum adsorption amounts for Fe(II) were 6.211 mg/g, 4.464 mg/g, and 4.049 mg/g by RHA, ISP, and RH and for Mn(II) were 3.016 mg/g, 2.229 mg/g, and 1.889 mg/g, respectively. The adsorption kinetics results show that the pseudo-second-order kinetic model can better fit the Fe(II) and Mn(II) adsorption process. D-R model and thermodynamic parameters hint that the adsorption processes of Fe(II) and Mn(II) on the three adsorbents took place physically and the processes were feasible, spontaneous, and exothermic. PMID:28042571

Mercerized mesoporous date pit activated carbon-A novel adsorbent to sequester potentially toxic divalent heavy metals from water.

PubMed

Aldawsari, Abdullah; Khan, Moonis Ali; Hameed, B H; Alqadami, Ayoub Abdullah; Siddiqui, Masoom Raza; Alothman, Zeid Abdullah; Ahmed, A Yacine Badjah Hadj

2017-01-01

A substantive approach converting waste date pits to mercerized mesoporous date pit activated carbon (DPAC) and utilizing it in the removal of Cd(II), Cu(II), Pb(II), and Zn(II) was reported. In general, rapid heavy metals adsorption kinetics for Co range: 25-100 mg/L was observed, accomplishing 77-97% adsorption within 15 min, finally, attaining equilibrium in 360 min. Linear and non-linear isotherm studies revealed Langmuir model applicability for Cd(II) and Pb(II) adsorption, while Freundlich model was fitted to Zn(II) and Cu(II) adsorption. Maximum monolayer adsorption capacities (qm) for Cd(II), Pb(II), Cu(II), and Zn(II) obtained by non-linear isotherm model at 298 K were 212.1, 133.5, 194.4, and 111 mg/g, respectively. Kinetics modeling parameters showed the applicability of pseudo-second-order model. The activation energy (Ea) magnitude revealed physical nature of adsorption. Maximum elution of Cu(II) (81.6%), Zn(II) (70.1%), Pb(II) (96%), and Cd(II) (78.2%) were observed with 0.1 M HCl. Thermogravimetric analysis of DPAC showed a total weight loss (in two-stages) of 28.3%. Infra-red spectral analysis showed the presence of carboxyl and hydroxyl groups over DPAC surface. The peaks at 820, 825, 845 and 885 cm-1 attributed to Zn-O, Pb-O, Cd-O, and Cu-O appeared on heavy metals saturated DPAC, confirmed their binding on DPAC during the adsorption.

Synthesis, spectroscopic and thermal studies of transition metal complexes derived from benzil and diethylenetriamine

NASA Astrophysics Data System (ADS)

Khan, Sadaf; Nami, Shahab A. A.; Siddiqi, K. S.

2007-10-01

A macrocyclic ligand, bdta (where bdta = 3,6,9,12,15,18-hexaaza-1,2,10,11-tetraphenyl-2,9,11,18-tetraenecyclododecane) has been prepared by cyclocondensation of benzil with diethylenetriamine which efficiently encapsulates transition as well as pseudo-transition metal ions leading to the formation of M(bdta)Cl 2 type complexes [where M = Mn(II), Fe(II), Co(II), Ni(II), Cu(II), Zn(II), Cd(II) and Hg(II)]. The analytical, spectroscopic and magnetic moment data suggests an octahedral geometry for all the complexes. EPR spectra of Mn(II) and Cu(II) show considerable exchange interaction in the complex. They are non-conducting in DMSO. The TGA profile of the ligand and its complexes are identical and consists of two discreet stages. The voltammogram of Cu-complex exhibits a quasi-reversible one-electron transfer wave for Cu(II)/Cu(I) couple.

Synthesis, spectroscopic and thermal studies of transition metal complexes derived from benzil and diethylenetriamine.

PubMed

Khan, Sadaf; Nami, Shahab A A; Siddiqi, K S

2007-10-01

A macrocyclic ligand, bdta (where bdta=3,6,9,12,15,18-hexaaza-1,2,10,11-tetraphenyl-2,9,11,18-tetraenecyclododecane) has been prepared by cyclocondensation of benzil with diethylenetriamine which efficiently encapsulates transition as well as pseudo-transition metal ions leading to the formation of M(bdta)Cl2 type complexes [where M=Mn(II), Fe(II), Co(II), Ni(II), Cu(II), Zn(II), Cd(II) and Hg(II)]. The analytical, spectroscopic and magnetic moment data suggests an octahedral geometry for all the complexes. EPR spectra of Mn(II) and Cu(II) show considerable exchange interaction in the complex. They are non-conducting in DMSO. The TGA profile of the ligand and its complexes are identical and consists of two discreet stages. The voltammogram of Cu-complex exhibits a quasi-reversible one-electron transfer wave for Cu(II)/Cu(I) couple.

Patch testing with a new fragrance mix detects additional patients sensitive to perfumes and missed by the current fragrance mix.

PubMed

Frosch, Peter J; Pirker, Claudia; Rastogi, Suresh C; Andersen, Klaus E; Bruze, Magnus; Svedman, Cecilia; Goossens, An; White, Ian R; Uter, Wolfgang; Arnau, Elena Giménez; Lepoittevin, Jean-Pierre; Menné, Torkil; Johansen, Jeanne Duus

2005-04-01

The currently used 8% fragrance mix (FM I) does not identify all patients with a positive history of adverse reactions to fragrances. A new FM II with 6 frequently used chemicals was evaluated in 1701 consecutive patients patch tested in 6 dermatological centres in Europe. FM II was tested in 3 concentrations - 28% FM II contained 5% hydroxyisohexyl 3-cyclohexene carboxaldehyde (Lyral), 2% citral, 5% farnesol, 5% coumarin, 1% citronellol and 10%alpha-hexyl-cinnamic aldehyde; in 14% FM II, the single constituents' concentration was lowered to 50% and in 2.8% FM II to 10%. Each patient was classified regarding a history of adverse reactions to fragrances: certain, probable, questionable, none. Positive reactions to FM I occurred in 6.5% of the patients. Positive reactions to FM II were dose-dependent and increased from 1.3% (2.8% FM II), through 2.9% (14% FM II) to 4.1% (28% FM II). Reactions classified as doubtful or irritant varied considerably between the 6 centres, with a mean value of 7.2% for FM I and means ranging from 1.8% to 10.6% for FM II. 8.7% of the tested patients had a certain fragrance history. Of these, 25.2% were positive to FM I; reactivity to FM II was again dose-dependent and ranged from 8.1% to 17.6% in this subgroup. Comparing 2 groups of history - certain and none - values for sensitivity and specificity were calculated: sensitivity: FM I, 25.2%; 2.8% FM II, 8.1%; 14% FM II, 13.5%; 28% FM II, 17.6%; specificity: FM I, 96.5%; 2.8% FM II, 99.5%; 14% FM II, 98.8%; 28% FM II, 98.1%. 31/70 patients (44.3%) positive to 28% FM II were negative to FM I, with 14% FM II this proportion being 16/50 (32%). In the group of patients with a certain history, a total of 7 patients were found reacting to FM II only. Conversely, in the group of patients without any fragrance history, there were significantly more positive reactions to FM I than to any concentration of FM II. In conclusion, the new FM II detects additional patients sensitive to fragrances missed by FM I; the number of false-positive reactions is lower with FM II than with FM I. Considering sensitivity, specificity and the frequency of doubtful reactions, the medium concentration, 14% FM II, seems to be the most appropriate diagnostic screening tool.

Spectroscopic and biological studies of new mononuclear metal complexes of a bidentate NN and NO hydrazone-oxime ligand derived from egonol

NASA Astrophysics Data System (ADS)

Babahan, Ilknur; Emirdağ-Öztürk, Safiye; Poyrazoğlu-Çoban, Esin

2015-04-01

A novel ligand, vicinal dioxime ligand (egonol-hydrazone glyoxime) (LH2) was synthesized and characterized using 1H NMR, 13C NMR, MS, AAS, infrared spectroscopy, and magnetic susceptibility measurements. Mononuclear nickel (II), copper (II) and cobalt (II) complexes with a metal:ligand ratio of 1:2 for LH2 were also synthesized. Zn(II) forms complex [Zn(LH)Cl2] with a metal to ligand ratio of 1:1. IR spectrum shows that the ligand act in a bidentate manner and coordinates N4 donor groups of the ligands to NiII, CuII, CoII and ZnII ions. The detection of H-bonding (Osbnd H⋯O) in the [M(LH)2] metal complexes by IR spectra supported the square-planar MN4 coordination of Ni(II), Cu(II) and Co(II) complexes. The antimicrobial activities of compounds LH2 and their Ni(II), Cu(II), Co(II) and Zn(II) complexes were evaluated using the disc diffusion method against 16 bacteria and 5 yeasts. The minimal inhibitory concentrations (MICs) against all the bacteria and yeasts were also determined. Among the attempted test compounds, it is showed that all the compounds (L, LH2, [Ni(LH)2], [Cu(LH)2], [Co(LH)2(H2O)2], [Zn(LH)Cl2]) were effective against used test microorganisms.

Sorption selectivity of birnessite particle edges: a d-PDF analysis of Cd(ii) and Pb(ii) sorption by δ-MnO2 and ferrihydrite.

PubMed

van Genuchten, Case M; Peña, Jasquelin

2016-08-10

Birnessite minerals (layer-type MnO2), which bear both internal (cation vacancies) and external (particle edges) metal sorption sites, are important sinks of contaminants in soils and sediments. Although the particle edges of birnessite minerals often dominate the total reactive surface area, especially in the case of nanoscale crystallites, the metal sorption reactivity of birnessite particle edges remains elusive. In this study, we investigated the sorption selectivity of birnessite particle edges by combining Cd(ii) and Pb(ii) adsorption isotherms at pH 5.5 with surface structural characterization by differential pair distribution function (d-PDF) analysis. We compared the sorption reactivity of δ-MnO2 to that of the nanomineral, 2-line ferrihydrite, which exhibits only external surface sites. Our results show that, whereas Cd(ii) and Pb(ii) both bind to birnessite layer vacancies, only Pb(ii) binds extensively to birnessite particle edges. For ferrihydrite, significant Pb(ii) adsorption to external sites was observed (roughly 20 mol%), whereas Cd(ii) sorption was negligible. These results are supported by bond valence calculations that show comparable degrees of saturation of oxygen atoms on birnessite and ferrihydrite particle edges. Therefore, we propose that the sorption selectivity of birnessite edges follows the same order of that reported previously for ferrihydrite: Ca(ii) < Cd(ii) < Ni(ii) < Zn(ii) < Cu(ii) < Pb(ii).

Chemically modified activated carbon with 1-acylthiosemicarbazide for selective solid-phase extraction and preconcentration of trace Cu(II), Hg(II) and Pb(II) from water samples.

PubMed

Gao, Ru; Hu, Zheng; Chang, Xijun; He, Qun; Zhang, Lijun; Tu, Zhifeng; Shi, Jianping

2009-12-15

A new sorbent 1-acylthiosemicarbazide-modified activated carbon (AC-ATSC) was prepared as a solid-phase extractant and applied for removing of trace Cu(II), Hg(II) and Pb(II) prior to their determination by inductively coupled plasma optical emission spectrometry (ICP-OES). The separation/preconcentration conditions of analytes were investigated, including effects of pH, the shaking time, the sample flow rate and volume, the elution condition and the interfering ions. At pH 3, the maximum static adsorption capacity of Cu(II), Hg(II) and Pb(II) onto the AC-ATSC were 78.20, 67.80 and 48.56 mg g(-1), respectively. The adsorbed metal ions were quantitatively eluted by 3.0 mL of 2% CS(NH2)2 and 2.0 mol L(-1) HCl solution. Common coexisting ions did not interfere with the separation. According to the definition of IUPAC, the detection limits (3sigma) of this method for Cu(II), Hg(II) and Pb(II) were 0.20, 0.12 and 0.45 ng mL(-1), respectively. The relative standard deviation under optimum conditions is less than 4.0% (n=8). The prepared sorbent was applied for the preconcentration of trace Cu(II), Hg(II) and Pb(II) in certified and water samples with satisfactory results.

Evaluation of Sensitivity and Specificity Performance of Elecsys HTLV-I/II Assay in a Multicenter Study in Europe and Japan.

PubMed

Laperche, Syria; Sauleda, Silvia; Piron, Maria; Mühlbacher, Annelies; Schennach, Harald; Schottstedt, Volkmar; Queirós, Lucinda; Uno, Naoki; Yanagihara, Katsunori; Imdahl, Roland; Hey, Ariann; Klinkicht, Markus; Melchior, Walter; Muench, Peter; Watanabe, Toshiki

2017-07-01

Screening of blood for human T-cell lymphotropic virus type 1 and type 2 (HTLV-1 and -2, respectively) is important to diagnose and prevent infection and ensure the safety of blood supplies. The Elecsys HTLV-I/II assay is a newly developed, electrochemiluminescence screening assay for the detection of HTLV-1/2 infection. The sensitivity and specificity of the Elecsys HTLV-I/II assay were determined using well-characterized HTLV-1/2-positive serum and plasma samples and routine diagnostic and blood donor samples expected to be HTLV negative, respectively. These results were compared with those for at least one of the following CE-marked assays at seven independent laboratories and the Roche Diagnostics facility in Penzberg, Germany: Abbott Architect rHTLV-I/II, Ortho Avioq HTLV-I/II Microelisa system, Abbott Prism HTLV-I/HTLV-II, and DiaSorin Murex HTLV I+II. Fujirebio INNO-LIA HTLV-I/II Score was used as a confirmatory assay. The Elecsys HTLV-I/II, Abbott Architect rHTLV-I/II, and Abbott Prism HTLV-I/HTLV-II assays detected all HTLV-1/2-positive samples (sensitivity, 100%). Sensitivity for Ortho Avioq HTLV-I/II was 98.63%. The Elecsys HTLV-I/II assay had a specificity of 99.95% in blood donor samples, which was comparable to results for the other assays (range, 99.91 to 100%). In routine diagnostic samples, the specificity of the Elecsys HTLV-I/II assay was 99.83%, compared with 99.70% for Abbott Architect rHTLV-I/II. Specificity for the Elecsys HTLV-I/II assay in potentially cross-reactive samples was 100%, compared with 99.0% for Ortho Avioq HTLV-I/II and 99.2% for DiaSorin Murex HTLV I+II. The Elecsys HTLV-I/II assay has the sensitivity and specificity to support its use as a routine screening assay for detecting HTLV infection. Copyright © 2017 Laperche et al.

Evaluation of Sensitivity and Specificity Performance of Elecsys HTLV-I/II Assay in a Multicenter Study in Europe and Japan

PubMed Central

Sauleda, Silvia; Piron, Maria; Mühlbacher, Annelies; Schennach, Harald; Schottstedt, Volkmar; Queirós, Lucinda; Uno, Naoki; Yanagihara, Katsunori; Imdahl, Roland; Hey, Ariann; Klinkicht, Markus; Melchior, Walter; Muench, Peter; Watanabe, Toshiki

2017-01-01

ABSTRACT Screening of blood for human T-cell lymphotropic virus type 1 and type 2 (HTLV-1 and -2, respectively) is important to diagnose and prevent infection and ensure the safety of blood supplies. The Elecsys HTLV-I/II assay is a newly developed, electrochemiluminescence screening assay for the detection of HTLV-1/2 infection. The sensitivity and specificity of the Elecsys HTLV-I/II assay were determined using well-characterized HTLV-1/2-positive serum and plasma samples and routine diagnostic and blood donor samples expected to be HTLV negative, respectively. These results were compared with those for at least one of the following CE-marked assays at seven independent laboratories and the Roche Diagnostics facility in Penzberg, Germany: Abbott Architect rHTLV-I/II, Ortho Avioq HTLV-I/II Microelisa system, Abbott Prism HTLV-I/HTLV-II, and DiaSorin Murex HTLV I+II. Fujirebio INNO-LIA HTLV-I/II Score was used as a confirmatory assay. The Elecsys HTLV-I/II, Abbott Architect rHTLV-I/II, and Abbott Prism HTLV-I/HTLV-II assays detected all HTLV-1/2-positive samples (sensitivity, 100%). Sensitivity for Ortho Avioq HTLV-I/II was 98.63%. The Elecsys HTLV-I/II assay had a specificity of 99.95% in blood donor samples, which was comparable to results for the other assays (range, 99.91 to 100%). In routine diagnostic samples, the specificity of the Elecsys HTLV-I/II assay was 99.83%, compared with 99.70% for Abbott Architect rHTLV-I/II. Specificity for the Elecsys HTLV-I/II assay in potentially cross-reactive samples was 100%, compared with 99.0% for Ortho Avioq HTLV-I/II and 99.2% for DiaSorin Murex HTLV I+II. The Elecsys HTLV-I/II assay has the sensitivity and specificity to support its use as a routine screening assay for detecting HTLV infection. PMID:28468860

75 FR 32505 - Importer of Controlled Substances; Notice of Registration

Federal Register 2010, 2011, 2012, 2013, 2014

2010-06-08

... 55858), Johnson Matthey, Inc., Pharmaceutical Materials, 2003 Nolte Drive, West Deptford, New Jersey... Phenylacetone (8501) II Coca Leaves (9040) II Thebaine (9333) II Opium, raw (9600) II Noroxymorphone (9668) II Poppy Straw Concentrate (9670) II The company plans to import the listed controlled substances as raw...

Collaborative Research to Optimize Warfighter Nutrition II (CROWN II)

DTIC Science & Technology

2016-09-01

Award Number: W81XWH-14-1-0335 TITLE: Collaborative Research to Optimize Warfighter Nutrition II (CROWN II) PRINCIPAL INVESTIGATOR: Jennifer C...2016 4. TITLE AND SUBTITLE Collaborative Research to Optimize Warfighter Nutrition II (CROWN II) 5a. CONTRACT NUMBER 5b. GRANT NUMBER W81XWH-14-1...has been forged between USARIEM and Pennington Biomedical Research Center (PBRC) since 1988. Objective: CROWN II conducts research in nutrition

40 CFR 52.2465 - Original identification of plan section.

Code of Federal Regulations, 2010 CFR

2010-07-01

..., 2FSD, and pre-dryer 3FSD from Part IV, Rule EX-4, Section 4.41(i) until December 15, 1981, submitted on...) Appendix K (7) Appendix N (8) Appendix P (9) Appendix R I., II.B., II.D., II.E., II.F., II.G., II.H., II.I...) Amendments to Part I, Subpart 1.01 (Certain Terms Defined) and to Part IV, Section 4.52 (former Section 4.705...

Elaboration of a Highly Porous RuII,II Analogue of HKUST-1.

PubMed

Zhang, Wenhua; Freitag, Kerstin; Wannapaiboon, Suttipong; Schneider, Christian; Epp, Konstantin; Kieslich, Gregor; Fischer, Roland A

2016-12-19

When the dinuclear Ru II,II precursor [Ru 2 (OOCCH 3 ) 4 ] is employed under redox-inert conditions, a Ru II,II analogue of HKUST-1 was successfully prepared and characterized as a phase-pure microcrystalline powder. X-ray absorption near-edge spectroscopy confirms the oxidation state of the Ru centers of the paddle-wheel nodes in the framework. The porosity of 1371 m 2 /mmol of Ru II,II -HKUST-1 exceeds that of the parent compound HKUST1 (1049 m 2 / mmol).

Copper Ion Detection in Drinking Water via a Fabric Nanocomposite Sensor

NASA Astrophysics Data System (ADS)

Yu, Guoqiang

Excessive Cu(II) ions in drinking water are always a big threat to people's health. In this work, we developed a flexible amperometric sensor by a simple dip-coating method, which was able to rapidly, sensitively, and selectively detect the Cu(II) ions in the range of 0.65 to 39 ppm in real time. The prepared Cu(II) sensor consisted of three layers that were electrospun nylon-6 nanofibers, multiwalled carbon nanotubes (MWCNTs), and 2,2':5',2''-terthiophene molecules, respectively. When a voltage was applied to the Cu(II) sensor, the current was obviously impeded in the presence of Cu(II) ions. Interfering metal ions, including Cd(II), Fe(II), Pb(II), Hg(II), and Ag(I) ions, had almost no influence on the responsiveness of the Cu(II) sensor.

Spectroscopic (FT-IR, FT-Raman, 1H, 13C NMR, UV/VIS), thermogravimetric and antimicrobial studies of Ca(II), Mn(II), Cu(II), Zn(II) and Cd(II) complexes of ferulic acid

NASA Astrophysics Data System (ADS)

Kalinowska, M.; Piekut, J.; Bruss, A.; Follet, C.; Sienkiewicz-Gromiuk, J.; Świsłocka, R.; Rzączyńska, Z.; Lewandowski, W.

2014-03-01

The molecular structure of Mn(II), Cu(II), Zn(II), Cd(II) and Ca(II) ferulates (4-hydroxy-3-methoxycinnamates) was studied. The selected metal ferulates were synthesized. Their composition was established by means of elementary and thermogravimetric analysis. The following spectroscopic methods were used: infrared (FT-IR), Raman (FT-Raman), nuclear magnetic resonance (13C, 1H NMR) and ultraviolet-visible (UV/VIS). On the basis of obtained results the electronic charge distribution in studied metal complexes in comparison with ferulic acid molecule was discussed. The microbiological study of ferulic acid and ferulates toward Escherichia coli, Bacillus subtilis, Candida albicans, Pseudomonas aeruginosa, Staphylococcus aureus and Proteus vulgaris was done.

DNA methyltransferase inhibitor CDA-II inhibits myogenic differentiation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Zirong; Department of Molecular Genetics and Microbiology, Shands Cancer Center, University of Florida, Gainesville, FL 32610; Jin, Guorong

2012-06-08

Highlights: Black-Right-Pointing-Pointer CDA-II inhibits myogenic differentiation in a dose-dependent manner. Black-Right-Pointing-Pointer CDA-II repressed expression of muscle transcription factors and structural proteins. Black-Right-Pointing-Pointer CDA-II inhibited proliferation and migration of C2C12 myoblasts. -- Abstract: CDA-II (cell differentiation agent II), isolated from healthy human urine, is a DNA methyltransferase inhibitor. Previous studies indicated that CDA-II played important roles in the regulation of cell growth and certain differentiation processes. However, it has not been determined whether CDA-II affects skeletal myogenesis. In this study, we investigated effects of CDA-II treatment on skeletal muscle progenitor cell differentiation, migration and proliferation. We found that CDA-II blocked differentiationmore » of murine myoblasts C2C12 in a dose-dependent manner. CDA-II repressed expression of muscle transcription factors, such as Myogenin and Mef2c, and structural proteins, such as myosin heavy chain (Myh3), light chain (Mylpf) and MCK. Moreover, CDA-II inhibited C1C12 cell migration and proliferation. Thus, our data provide the first evidence that CDA-II inhibits growth and differentiation of muscle progenitor cells, suggesting that the use of CDA-II might affect skeletal muscle functions.« less

Simultaneous removal of heavy-metal ions in wastewater samples using nano-alumina modified with 2,4-dinitrophenylhydrazine.

PubMed

Afkhami, Abbas; Saber-Tehrani, Mohammad; Bagheri, Hasan

2010-09-15

2,4-Dinitrophenylhydrazine (DNPH) immobilized on sodium dodecyl sulfate coated nano-alumina was developed for the removal of metal cations Pb(II), Cd(II), Cr(III), Co(II), Ni(II) and Mn(II) from water samples. The research results displayed that adsorbent has the highest adsorption capacity for Pb(II), Cr(III) and Cd(II) in ions mixture system. Optimal experimental conditions including pH, adsorbent dosage and contact time have been established. Langmuir and Freundlich isotherm models were applied to analyze the experimental data. The best interpretation for the experimental data was given by the Freundlich adsorption isotherm equation for Mn(II), Pb(II), Cr(III) and Cd(II) ions and by Langmuir isotherm equation for Ni(II) and Co(II) ions. Desorption experiments by elution of the adsorbent with a mixture of nitric acid and methanol show that the modified alumina nanoparticles could be reused without significant losses of its initial properties even after three adsorption-desorption cycles. Thus, modified nano-alumina with DNPH is favorable and useful for the removal of these metal ions, and the high adsorption capacity makes it a good promising candidate material for Pb(II),Cr(III) and Cd(II) removal. Copyright 2010 Elsevier B.V. All rights reserved.

Chelation, spectroscopic characterization, biological activity and crystal structure of 2,3-butanedione isonicotinylhydrazone: Determination of Zr4+ after flotation separation

NASA Astrophysics Data System (ADS)

Al-Fulaij, O. A.; Jeragh, B.; El-Sayed, A. E. M.; El-Defrawy, M. M.; El-Asmy, A. A.

2015-02-01

New metal complexes of Co(II), Ni(II) Cu(II), Zn(II), Cd(II), Pd(II) and Hg(II) with 2,3-butanedione isonicotinylhydrazone [BINH] have been prepared and investigated. Single crystal for BINH is grown and solved as orthorhombic with P 21 21 2 space group. The formula of the ligand was assigned based on the elemental analysis, mass spectra and conductivity measurements. The complexes assigned the formulae [M(BINH-H)Cl]ṡnH2O (Mdbnd Co(II), Ni(II), Cu(II), Zn(II); n = 0 or 1); [Hg(BINH-H)(H2O)2Cl]; [Cd(BINH)Cl2]ṡ2H2O and [Pd(BINH)Cl2]ṡH2O. All complexes are nonelectrolytes. BINH acts as a tridentate ligand in [M(BINH-H)Cl]ṡnH2O and [Hg(BINH-H)(H2O)2Cl] coordinating through Cdbnd Oketonic, Csbnd Oamedic and Cdbnd Nhy and as a neutral bidentate through Cdbnd Oketonic and Cdbnd Nhy in [Cd(BINH)Cl2]ṡ2H2O and [Pd(BINH)Cl2]ṡH2O; the pyridine nitrogen has no rule in coordination. The data are supported by NMR (1H and 13C) spectra. The magnetic moments and electronic spectra provide a tetrahedral structure for the Co(II), Ni(II), Cu(II), Zn(II) and Cd(II) complexes; square-planar for the Pd(II) complex and octahedral for the Hg(II) complex. The TGA of the complexes depicted the outer and inner water molecules as well as the final residue. The cobalt and cadmium complexes ended with the metal while the Cu(II), Zn(II) and Pd(II) complexes ended with complex species. [Hg(BINH-H)(H2O)2Cl] has no residue. The ligand is inactive against all tested organisms except for Bacillus thuringiensis. The Hg(II) complex is found more active than the other complexes. The flotation technique is found applicable for the separation of micro amount (10 ppm) of Zr4+ using 10 ppm of BINH and 1 × 10-5 mol L-1 of oleic acid at pH 6 with efficiency of 98% with no interferences.

Complexation humic substances of soils with metal ions as the main way migration of matals from soil to water

NASA Astrophysics Data System (ADS)

Dinu, Marina

2013-04-01

Organic matter (OM) of natural waters can bind with the ions metals (IM) entering the system, thus reducing their toxic properties. OM in water consists predominantly (up to 80%) of humic acids (HA), represented by highmolecular, dyed, polyfunctional compounds. The natural-climatic zones feature various ratios of fulvic (FA) and humic acids. An important specific feature of metals as contamination elements is the fact that when they occur in the environment, their potential toxicity and bioavailability depend significantly on their speciation. In recent years, lakes have been continuously enriched in hazardous elements such as Pb, Cd, Al, and Cr on a global (regional) basis. The most important organic ligands are humic matter (HM) washed out from soils in water and metals occur in natural waters as free ions, simple complexes with inorganic and organic ligands, and mineral and organic particles of molecules and ions sorbed on the surface. The occurrence of soluble metal forms in natural waters depends on the presence of organic and inorganic anions. However, direct determinations are rather difficult. The goal was the calculation and analysis of the forms of metals in the system catchment basin, based on the chemical composition of the water body and the structural features of soil humic substances (HS).We used the following analytical techniques - leaching of humic substances from soil and sample preparation (Orlov DS, 1985), the functional characteristics of humic substances - spectral analysis methods, the definition of conditional stability constants of complexes - electrochemical methods of analysis. Our results show thet HAs of selected soil types are different in functions, and these differences effect substantially the complexing process. When analyzing the results obtained in the course of spectrometric investigation of HMs in selected soil types, we determined the following main HA characteristics: (1) predominance of oxygen bearing groups in HM of the northern taiga soils; (2) similar amounts of oxygen bearing fragments, hydrocarbon constituents, and nitrogen bearing components in the mixed forest zones; (3) occurrence of aromatic and aliphatic hydrocarbons in HM of steppe soils. The HM functional characteristics influence substantially the stability constants of complexes with metal ions and complex stoichiometry: Fe(III)>Cu(II)>Pb(II)>Al(III)>Co(II)>Ni(II)>Cd(II)>Zn(II)>Cr(III)>Mg(II)>Sr(II)>Ca(II)>Mn(II) - northern taiga soils; Cu(II)>Fe(III)>Al(III)>Ni(II)>Zn(II)>Pb(II)>Co(II)>Cd(II)>Sr(II)>Mn(II)>Cr(III)>Ca(II)>Mg(II) - mixed forest zones; Fe(III)>Cu(II)>Al(III)>Pb(II)>Ni(II)>Zn(II)>Co(II)>Ca(II)>Cd(II)>Sr(II)>Mg(II)>Cr(III)>Mn(II) - steppe soils. 1. T.I. Moiseenko, L.P. Kudryavtseva, and N.A. Gashkina, Scattered Element in Surface Land Waters: Technophility, Bioaccumulation, and Ecotoxicology (Nauka, Moscow, 2006) 2. G. M. Varshal, Ext. Abstr. Doct. Dis. Chem. (Inst. Geokh. Analit. Khim. RAN, Moscow, 1994).. 4. D.S. Orlov, Humic Acids (MGU, Moscow, 1986) 5. D.V. Kovalevsky, Ext. Abstr. Cand. Dis. Chem. (MGU, Moscow, 1998). 6. I.A. Linnik and B. I. Nabivanets, Metal Migration Forms in Surface Fresh Waters (Gidrometizdat, Leningrad, 1985) 7. Hartley, F., Burgess, C., and Alcoc, R., Solution Equilibria (Ellis Horwood, Chichester (UK), 1980). 8. Yu. Yu. Lur'e, Reference Book of Physicochemical Values (Nauka, Moscow, 2000)

Locations and properties of angiotensin II-responsive neurones in the circumventricular region of the duck brain.

PubMed Central

Matsumura, K; Simon, E

1990-01-01

1. In brain slice preparations from the hypothalamus of domestic ducks, single-unit activity was recorded extracellularly to investigate location and properties of angiotensin II (AngII)-responsive neurones in various periventricular regions. 2. When exposing the slice to 10(-7) M-AngII in the perfusion medium, more than 65% of the neurones recorded in the subfornical organ (SFO) were activated (49 out of 75) and none inhibited. In the magnocellular (MC) region of the paraventricular nucleus (PVN) only four out of eighty-one neurones were influenced by AngII; one was inhibited and three were activated. In the anterior third ventricle region (A3V) two out of twenty-one neurones were activated by AngII. In the dorsal periventricular (PeV) region, one out of thirty-seven neurones was activated and one inhibited. The changes in firing rate of AngII-responsive neurones at comparable doses of AngII were generally large in the SFO and A3V but were small in neurones from the MC and PeV regions. 3. Analysis of AngII-responsive SFO neurones consistently revealed a dose-dependent stimulation with a threshold at 10(-9) M-AngII. The AngII antagonist 1Sar-8Ile-AngII (4 x 10(-7) to 10(-6) M) caused reversible, complete or partial suppression of responsiveness to 10(-7) M-AngII. Synaptic blockade with a medium low in Ca2+ and high in Mg2+ did not abolish AngII responsiveness in eight out of ten SFO neurones tested. 4. Angiotensin III affected neither AngII-responsive nor AngII-insensitive neurones. When eighteen AngII-responsive neurones were exposed to hypertonic stimulation (+20 to +30 mosmol/kg) by adding NaCl to the perfusion medium, only one neurone was stimulated and two were inhibited. 5. The results indicate that: (a) the SFO is a specific target for circulating AngII; (b) although neurones in the A3V responsive to AngII are rare, the pronounced excitation of those which were found suggest that neurones in this region might serve as targets for AngII acting from the brain side; (c) neurones in the MC region do not seem to function as direct AngII targets; (d) neuronal AngII responsiveness in the duck's hypothalamus seems to be specific inasmuch as activation by AngII (i) is readily blocked by an AngII antagonist, (ii) cannot be induced by AngIII, and (iii) is not associated, as a rule, with responsiveness to hypertonic stimulation. PMID:2277348

Subtypes of the Type II Pit Pattern Reflect Distinct Molecular Subclasses in the Serrated Neoplastic Pathway.

PubMed

Aoki, Hironori; Yamamoto, Eiichiro; Yamano, Hiro-O; Sugai, Tamotsu; Kimura, Tomoaki; Tanaka, Yoshihito; Matsushita, Hiro-O; Yoshikawa, Kenjiro; Takagi, Ryo; Harada, Eiji; Nakaoka, Michiko; Yoshida, Yuko; Harada, Taku; Sudo, Gota; Eizuka, Makoto; Yorozu, Akira; Kitajima, Hiroshi; Niinuma, Takeshi; Kai, Masahiro; Nojima, Masanori; Suzuki, Hiromu; Nakase, Hiroshi

2018-03-15

Colorectal serrated lesions (SLs) are important premalignant lesions whose clinical and biological features are not fully understood. We aimed to establish accurate colonoscopic diagnosis and treatment of SLs through evaluation of associations among the morphological, pathological, and molecular characteristics of SLs. A total of 388 premalignant and 18 malignant colorectal lesions were studied. Using magnifying colonoscopy, microsurface structures were assessed based on Kudo's pit pattern classification system, and the Type II pit pattern was subcategorized into classical Type II, Type II-Open (Type II-O) and Type II-Long (Type II-L). BRAF/KRAS mutations and DNA methylation of CpG island methylator phenotype (CIMP) markers (MINT1, - 2, - 12, - 31, p16, and MLH1) were analyzed through pyrosequencing. Type II-O was tightly associated with sessile serrated adenoma/polyps (SSA/Ps) with BRAF mutation and CIMP-high. Most lesions with simple Type II or Type II-L were hyperplastic polyps, while mixtures of Type II or Type II-L plus more advanced pit patterns (III/IV) were characteristic of traditional serrated adenomas (TSAs). Type II-positive TSAs frequently exhibited BRAF mutation and CIMP-low, while Type II-L-positive TSAs were tightly associated with KRAS mutation and CIMP-low. Analysis of lesions containing both premalignant and cancerous components suggested Type II-L-positive TSAs may develop into KRAS-mutated/CIMP-low/microsatellite stable cancers, while Type II-O-positive SSA/Ps develop into BRAF-mutated/CIMP-high/microsatellite unstable cancers. These results suggest that Type II subtypes reflect distinct molecular subclasses in the serrated neoplasia pathway and that they could be useful hallmarks for identifying SLs at high risk of developing into CRC.

Biogeochemistry of Fe(II) oxidation in a photosynthetic microbial mat: Implications for Precambrian Fe(II) oxidation

NASA Astrophysics Data System (ADS)

Trouwborst, Robert E.; Johnston, Anne; Koch, Gretchen; Luther, George W.; Pierson, Beverly K.

2007-10-01

We studied the role of microbial photosynthesis in the oxidation of Fe(II) to Fe(III) in a high Fe(II) and high Mn(II) hot spring devoid of sulfide and atmospheric oxygen in the source waters. In situ light and dark microelectrode measurements of Fe(II), Mn(II) and O 2 were made in the microbial mat consisting of cyanobacteria and anoxygenic photosynthetic Chloroflexus sp. We show that Fe(II) oxidation occurred when the mat was exposed to varying intensities of sunlight but not near infrared light. We did not observe any Mn(II) oxidation under any light or dark condition over the pH range 5-7. We observed the impact of oxygenic photosynthesis on Fe(II) oxidation, distinct from the influence of atmospheric O 2 and anoxygenic photosynthesis. In situ Fe(II) oxidation rates in the mats and cell suspensions exposed to light are consistent with abiotic oxidation by O 2. The oxidation of Fe(II) to form primary Fe(III) phases contributed to banded iron-formations (BIFs) during the Precambrian. Both oxygenic photosynthesis, which produces O 2 as an oxidizing waste product, and anoxygenic photosynthesis in which Fe(II) is used to fix CO 2 have been proposed as Fe(II) oxidation mechanisms. Although we do not know the specific mechanisms responsible for all Precambrian Fe(II) oxidation, we assessed the relative importance of both mechanisms in this modern hot spring environment. In this environment, cyanobacterial oxygen production accounted for all the observed Fe(II) oxidation. The rate data indicate that a modest population of cyanobacteria could have mediated sufficient Fe(II) oxidation for some BIFs.

Synthesis, characterization and anti-microbial activity of a novel macrocyclic ligand derived from the reaction of 2,6-pyridinedicarboxylic acid with homopiperazine and its Co(II), Ni(II), Cu(II), and Zn(II) complexes

NASA Astrophysics Data System (ADS)

Soleimani, Esmaiel

2011-05-01

The preparation of a novel macrocyclic ligand ( 1), N,N'-diethylhomopiperazinyl,2,6-pyridinedicarboxylate and its Co(II), Ni(II), Cu(II), and Zn(II) complexes are described. The ligand was prepared in EtOH from the reaction of dipotassium salt of 2,6-pyridinedicarboxylic acid with 1,2-dibromoethane in the presence of homopiperazine. Reaction of macrocyclic ligand ( 1) in EtOH with CoCl 2.6H 2O, NiCl 2.6H 2O, CuCl 2.2H 2O, and ZnCl 2·2H 2O yielded the complexes with the general formula [M(L)Cl 2] {where M = Co(II) ( 2), Ni(II) ( 3), Cu(II) ( 4), Zn ( 5), respectively}. The analysis of IR, 1H and 13C NMR spectral data of macrocyclic ligand ( 1) and its Zn(II) complex ( 5) together with their molar conductivity values, and the magnetic moments of the complexes suggest that the macrocyclic ligand ( 1) is bonded to metal(II) ions through two oxygen atoms of ester moiety and the two nitrogen atoms of homopiperazine ring. The electronic spectral data of these complexes in DMSO are in good agreement with the octahedral coordination of M(II) ions. The ligand field parameters for these complexes, i.e. splitting energy and Racah parameter were calculated to be 14,945 and 673 cm -1 for the Co(II) ( 2), 16,260 and 774 cm -1 for the Ni(II) ( 3) complexes respectively. The spliting energy of 17,262 cm -1 was obtained for the Cu(II) complex ( 4).

Synthesis and characterization of new complexes of nickel (II), palladium (II) and platinum(II) with derived sulfonamide ligand: Structure, DFT study, antibacterial and cytotoxicity activities

NASA Astrophysics Data System (ADS)

Bouchoucha, Afaf; Zaater, Sihem; Bouacida, Sofiane; Merazig, Hocine; Djabbar, Safia

2018-06-01

The synthesis, characterization and biological study of new nickel (II), palladium (II), and platinum (II) complexes with sulfamethoxazole ligand used in pharmaceutical field, were reported. [MLCl2].nH2O is the general formula obtained for Pd(II) and Pt(II) complexes. These complexes have been prepared and characterized by elemental analysis, FTIR, 1HNMR spectral, magnetic measurements, UV-Visible spectra, and conductivity. The DFT calculation was applied to optimize the geometric structure of the Pd(II) and Pt(II) complexes. A new single-crystal X-ray structure of the Ni(II) complex has been determined. It crystallized in monoclinic system with P 21/c space group and Z = 8. The invitro antibacterial activity of ligand and complexes against Escherichia coli, P. aeruginosa, Klebsiella pneumoniae, S. aureus, Bacillus subtilis species has been carried out and compared using agar-diffusion method. The Pd(II) and Pt(II) complexes showed a remarkable inhibition against bacteria tested. The invitro cytotoxicity assay of the complexes against three cell lines chronic myelogenous leukaemia (K562), human colon adenocarcinoma (HT-29) and breast cancer (MCF-7) was also reported.

Composition, Characterization and Antibacterial activity of Mn(II), Co(II),Ni(II), Cu(II) Zn(II) and Cd(II) mixed ligand complexes Schiff base derived from Trimethoprim with 8-Hydroxy quinoline

NASA Astrophysics Data System (ADS)

Numan, Ahmed T.; Atiyah, Eman M.; Al-Shemary, Rehab K.; Ulrazzaq, Sahira S. Abd

2018-05-01

New Schiff base ligand 2-((4-amino-5-(3, 4, 5-trimethoxybenzyl) pyrimidin-2-ylimino) (phenyl)methyl)benzoic acid] = [HL] was synthesized using microwave irradiation trimethoprim and 2-benzoyl benzoic acid. Mixed ligand complexes of Mn((II), Co(II), Ni(II), Cu(II), Zn(II) and Cd(II) are reacted in ethanol with Schiff base ligand [HL] and 8-hydroxyquinoline [HQ] then reacted with metal salts in ethanol as a solvent in (1:1:1) ratio. The ligand [HL] is characterized by FTIR, UV-Vis, melting point, elemental microanalysis (C.H.N), 1H-NMR, 13C-NMR, and mass spectra. The mixed ligand complexes are characterized by infrared spectra, electronic spectra, (C.H.N), melting point, atomic absorption, molar conductance and magnetic moment measurements. These measurements indicate that the ligand [HL] coordinates with metal (II) ion in a tridentate manner through the oxygen and nitrogen atoms of the ligand, octahedral structures are suggested for these complexes. Antibacterial activity of the ligands [HL], [HQ] and their complexes are studied against (gram positive) and (gram negative) bacteria.

Selective adsorption of Pb (II) ions by amylopectin-g-poly (acrylamide-co-acrylic acid): A bio-degradable graft copolymer.

PubMed

Sasmal, Dinabandhu; Maity, Jayanta; Kolya, Haradhan; Tripathy, Tridib

2017-04-01

Amylopectin-g-poly (acrylamide-co-acrylic acid) [AP-g-poly (AM-co-AA)] was synthesised in water medium by using potassium perdisulphate as an initiator. The graft copolymer was characterized by molecular weight determination by size exclusion chromatography (SEC), fourier transform infrared spectroscopy (FTIR) and nuclear magnetic resonance (NMR) spectroscopy, scanning electron microscope (SEM) studies, thermal analysis, measurement of neutralisation equivalent and biodegradation studies. The graft copolymer was used for Pb (II) ion removal from aqueous solution. The Pb (II) ion removal capacity of the graft copolymer was also compared with another laboratory developed graft copolymer Amylopectin-g-poly (acrylamide) (AP-g-PAM). Both the graft copolymers were also used for the competitive metal ions removal with Pb (II)/Cd (II), Pb (II)/Zn (II), Pb (II)/Ni (II), Pb (II)/Cu (II) pairs separately under similar conditions. AP-g-poly (AM-co-AA) showed better Pb (II) ion adsorbing power over AP-g-PAM and also much selective towards Pb (II) ions. The adsorption follows a second order rate equation and Langmuir isotherm model. Copyright © 2017 Elsevier B.V. All rights reserved.

Synthesis, characterization and anti-microbial activity of phenylurea-formaldehyde resin (PUF) and its polymer metal complexes (PUF-Mn(II)

NASA Astrophysics Data System (ADS)

Ahamad, Tansir; Alshehri, Saad M.

2012-10-01

Phenylurea-formaldehyde polymer (PUF) was synthesized via polycondensation of phenylurea and formaldehyde in basic medium, its polymer-metal complexes [PUF-M(II)] were prepared with Mn(II), Co(II), Ni(II), Cu(II), and Zn(II) ions. PUF and PUF-M(II) were characterized with magnetic moment measurements, elemental and spectral (UV-visible, FTIR, 1H-NMR, 13C-NMR and ESR) analysis. The thermal behaviors of all the synthesized polymers were carried out using thermogravimetric analysis (TGA) and differential thermal analysis (DTA). The thermal data revealed that all of the PUF-M(II) showed higher thermal stabilities than the PUF and also ascribed that the PUF-Cu(II) showed better thermal stability than the other PUF-M(II). The kinetic parameters such as activation energy, pre-exponential factor etc., were evaluated for these polymer metal complexes using Coats-Redfern equation. In addition, the antimicrobial activity of the synthesized polymers was tested against several microorganisms using agar well diffusion methods. Among all of the PUF-M(II), the antimicrobial activity of the PUF-Cu(II) showed the highest zone of inhibition because of its higher stability constant and may be used in biomedical applications.

Characterization and cloning of tripeptidyl peptidase II from the fruit fly, Drosophila melanogaster.

PubMed

Renn, S C; Tomkinson, B; Taghert, P H

1998-07-24

We describe the characterization, cloning, and genetic analysis of tripeptidyl peptidase II (TPP II) from Drosophila melanogaster. Mammalian TPP II removes N-terminal tripeptides, has wide distribution, and has been identified as the cholecystokinin-degrading peptidase in rat brain. Size exclusion and ion exchange chromatography produced a 70-fold purification of dTPP II activity from Drosophila tissue extracts. The substrate specificity and the inhibitor sensitivity of dTPP II is comparable to that of the human enzyme. In particular, dTPP II is sensitive to butabindide, a specific inhibitor of the rat cholecystokinin-inactivating activity. We isolated a 4309-base pair dTPP II cDNA which predicts a 1354-amino acid protein. The deduced human and Drosophila TPP II proteins display 38% overall identity. The catalytic triad, its spacing, and the sequences that surround it are highly conserved; the C-terminal end of dTPP II contains a 100-amino acid insert not found in the mammalian proteins. Recombinant dTPP II displays the predicted activity following expression in HEK cells. TPP II maps to cytological position 49F4-7; animals deficient for this interval show reduced TPP II activity.

76 FR 73678 - Importer of Controlled Substances; Notice of Registration

Federal Register 2010, 2011, 2012, 2013, 2014

2011-11-29

...) II Alphaprodine (9010) II Anileridine (9020) II Cocaine (9041) II Codeine (9050) II Dihydrocodeine... United States obligations under international treaties, conventions, or protocols in effect on May 1...

Accumulation of metal ions by pectinates

NASA Astrophysics Data System (ADS)

Deiana, S.; Deiana, L.; Palma, A.; Premoli, A.; Senette, C.

2009-04-01

The knowledge of the mechanisms which regulate the interactions of metal ions with partially methyl esterified linear polymers of α-1,4 linked D-galacturonic acid units (pectinates), well represented in the root inner and outer apoplasm, is of great relevance to understand the processes which control their accumulation at the soil-root interface as well as their mobilization by plant metabolites. Accumulation of a metal by pectinates can be affected by the presence of other metals so that competition or distribution could be expected depending on the similar or different affinity of the metal ions towards the binding sites, mainly represented by the carboxylate groups. In order to better understand the mechanism of accumulation in the apoplasm of several metal ions, the sorption of Cd(II), Zn(II), Cu(II), Pb(II) and Cr(III) by a Ca-polygalacturonate gel, used as model of the soil-root interface, with a degree of esterification of 18% (PGAE1) and 65% (PGAE2) was studied at pH 3.0, 4.0, 5.0 and 6.0 in the presence of CaCl2 2.5 mM.. The results show that sorption increases with increasing both the initial metal concentration and pH. A similar sorption trend was evidenced for Cu(II) and Pb(II) and for Zn(II) and Cd(II), indicating that the mechanism of sorption for these two ionic couples is quite different. As an example, at pH 6.0 and an initial metal concentration equal to 2.0 mM, the amount of Cu(II) and Pb(II) sorbed was about 1.98 mg-1 of PGAE1 while that of Cd(II) and Zn(II) was about 1.2 mg-1. Cr(III) showed a rather different sorption trend and a much higher amount (2.8 mg-1of PGAE1 at pH 6.0) was recorded. The higher affinity of Cr(III) for the polysaccharidic matrix is attributable to the formation of Cr(III) polynuclear species in solution, as shown by the distribution diagrams obtained through the MEDUSA software. On the basis of these findings, the following affinity towards the PGAE1 can be assessed: Cr(III) > Cu(II) ? Pb(II) > Zn (II) ? Cd(II). Surprisingly, simultaneous sorption tests and SEM analyses indicate that a different mechanism regulates the sorption of Cu(II) and Pb(II) by PGAE1. In fact, the amount of Pb(II) sorbed (0.92 moles mg-1of PGAE1) by PGAE1 was nearly independent by the presence of Cu(II) ions, at least at the three different concentrations tested, that indicates a higher affinity of Pb(II). Such an aspect was further confirmed by exchange experiments. Samples of PGAE1 saturated with 1.96 moles mg-1of Cu(II) or 2.01 moles mg-1of Pb(II) were put in contact with 100 mL of solutions containing 97.3 moles of Pb(II) or 99.4 moles Cu(II), respectively. The exchange kinetics show that about 80% of Cu(II) was stochiometrically exchanged by Pb(II). In contrast, only about 10% of Pb(II) complexed by PGAE1 was exchanged by Cu(II). The kinetics of simultaneous sorption of all the metal ions tested indicate that Pb(II) is selectively sorbed by the PGAE1 gels. Cd(II) and Zn(II) show a similar affinity towards PGAE1. Thus, in the simultaneous presence of these ions, their selectivity towards this matrix follows the order: Pb > Cu > Cd ? Zn. Sorption of Cr(III) in the presence of the ions considered was not possible to carry out due to interference phenomena. The sorption of the same ions by 50 mg of PGAE2 evidences that the amount of Cu(II), Pb(II), and Cr(III) sorbed is markedly lower than that found for PGAE1. By considering that two carboxylic groups are involved in the complexation of a metal ion, the data show that such a stoichiometry is respected only for Pb(II). The amount of Cu(II) sorbed is about 50% lower than that of Pb(II) at all the pH values tested whereas those of Zn(II) and Cd(II) are negligible whereas that of Cr(III) is the highest. The different behaviour of Cu(II) compared to Pb(II) can be explained taking into account for both hydrophobic and steric effects of the methyl groups as well as to their different charge density. Thus, it can be concluded that the accumulation of metals at the soil-root interface strictly depends on the esterification degree of the root pectinates which, even highly esterified, do not loose the ability to accumulate metals, mainly Pb(II) and Cr(III).

Microbial Iron(II) Oxidation in Littoral Freshwater Lake Sediment: The Potential for Competition between Phototrophic vs. Nitrate-Reducing Iron(II)-Oxidizers

PubMed Central

Melton, E. D.; Schmidt, C.; Kappler, A.

2012-01-01

The distribution of neutrophilic microbial iron oxidation is mainly determined by local gradients of oxygen, light, nitrate and ferrous iron. In the anoxic top part of littoral freshwater lake sediment, nitrate-reducing and phototrophic Fe(II)-oxidizers compete for the same e− donor; reduced iron. It is not yet understood how these microbes co-exist in the sediment and what role they play in the Fe cycle. We show that both metabolic types of anaerobic Fe(II)-oxidizing microorganisms are present in the same sediment layer directly beneath the oxic-anoxic sediment interface. The photoferrotrophic most probable number counted 3.4·105 cells·g−1 and the autotrophic and mixotrophic nitrate-reducing Fe(II)-oxidizers totaled 1.8·104 and 4.5·104 cells·g−1 dry weight sediment, respectively. To distinguish between the two microbial Fe(II) oxidation processes and assess their individual contribution to the sedimentary Fe cycle, littoral lake sediment was incubated in microcosm experiments. Nitrate-reducing Fe(II)-oxidizing bacteria exhibited a higher maximum Fe(II) oxidation rate per cell, in both pure cultures and microcosms, than photoferrotrophs. In microcosms, photoferrotrophs instantly started oxidizing Fe(II), whilst nitrate-reducing Fe(II)-oxidizers showed a significant lag-phase during which they probably use organics as e− donor before initiating Fe(II) oxidation. This suggests that they will be outcompeted by phototrophic Fe(II)-oxidizers during optimal light conditions; as phototrophs deplete Fe(II) before nitrate-reducing Fe(II)-oxidizers start Fe(II) oxidation. Thus, the co-existence of the two anaerobic Fe(II)-oxidizers may be possible due to a niche space separation in time by the day-night cycle, where nitrate-reducing Fe(II)-oxidizers oxidize Fe(II) during darkness and phototrophs play a dominant role in Fe(II) oxidation during daylight. Furthermore, metabolic flexibility of Fe(II)-oxidizing microbes may play a paramount role in the conservation of the sedimentary Fe cycle. PMID:22666221

Manganese Binding Properties of Human Calprotectin Under Conditions of High and Low Calcium: X-ray Crystallographic and Advanced EPR Spectroscopic Analysis

PubMed Central

Gagnon, Derek M.; Brophy, Megan Brunjes; Bowman, Sarah E. J.; Stich, Troy A.; Drennan, Catherine L.; Britt, R. David; Nolan, Elizabeth M.

2015-01-01

The antimicrobial protein calprotectin (CP), a hetero-oligomer of the S100 family members S100A8 and S100A9, is the only identified mammalian Mn(II)-sequestering protein. Human CP uses Ca(II) ions to tune its Mn(II) affinity at a biologically unprecedented hexahistidine site that forms at the S100A8/S100A9 interface, and the molecular basis for this phenomenon requires elucidation. Herein, we investigate the remarkable Mn(II) coordination chemistry of human CP using X-ray crystallography as well as continuous wave (CW) and pulse electron paramagnetic resonance (EPR) spectroscopies. An X-ray crystallographic structure of Mn(II)-CP containing one Mn(II), two Ca(II), and two Na(I) ions per CP heterodimer is reported. The CW EPR spectrum of Ca(II)- and Mn(II)-bound CP prepared with a 10:0.9:1 Ca(II):Mn(II):CP ratio is characterized by an unusually low zero-field splitting of 485 MHz (E/D = 0.30) for the S = 5/2 Mn(II) ion, consistent with the high symmetry of the His6 binding site observed crystallographically. Results from electron spin-echo envelope modulation and electron nuclear double resonance experiments reveal that the six Mn(II)-coordinating histidine residues of Ca(II)- and Mn(II)-bound CP are spectroscopically equivalent. The observed 15N (I = 1/2) hyperfine couplings (A) arise from two distinct classes of nitrogen atoms: the coordinating ε-nitrogen of the imidazole ring of each histidine ligand (A = [3.45, 3.71, 5.91] MHz) and the distal δ-nitrogen (A = [0.11, 0.18, 0.42] MHz). In the absence of Ca(II), the binding affinity of CP for Mn(II) drops by ca. two orders of magnitude and coincides with Mn(II) binding at the His6 site as well as other sites. This study demonstrates the role of Ca(II) in enabling high-affinity and specific binding of Mn(II) to the His6 site of human calprotectin. PMID:25597447

Manganese binding properties of human calprotectin under conditions of high and low calcium: X-ray crystallographic and advanced electron paramagnetic resonance spectroscopic analysis.

PubMed

Gagnon, Derek M; Brophy, Megan Brunjes; Bowman, Sarah E J; Stich, Troy A; Drennan, Catherine L; Britt, R David; Nolan, Elizabeth M

2015-03-04

The antimicrobial protein calprotectin (CP), a hetero-oligomer of the S100 family members S100A8 and S100A9, is the only identified mammalian Mn(II)-sequestering protein. Human CP uses Ca(II) ions to tune its Mn(II) affinity at a biologically unprecedented hexahistidine site that forms at the S100A8/S100A9 interface, and the molecular basis for this phenomenon requires elucidation. Herein, we investigate the remarkable Mn(II) coordination chemistry of human CP using X-ray crystallography as well as continuous-wave (CW) and pulse electron paramagnetic resonance (EPR) spectroscopies. An X-ray crystallographic structure of Mn(II)-CP containing one Mn(II), two Ca(II), and two Na(I) ions per CP heterodimer is reported. The CW EPR spectrum of Ca(II)- and Mn(II)-bound CP prepared with a 10:0.9:1 Ca(II):Mn(II):CP ratio is characterized by an unusually low zero-field splitting of 485 MHz (E/D = 0.30) for the S = 5/2 Mn(II) ion, consistent with the high symmetry of the His6 binding site observed crystallographically. Results from electron spin-echo envelope modulation and electron-nuclear double resonance experiments reveal that the six Mn(II)-coordinating histidine residues of Ca(II)- and Mn(II)-bound CP are spectroscopically equivalent. The observed (15)N (I = 1/2) hyperfine couplings (A) arise from two distinct classes of nitrogen atoms: the coordinating ε-nitrogen of the imidazole ring of each histidine ligand (A = [3.45, 3.71, 5.91] MHz) and the distal δ-nitrogen (A = [0.11, 0.18, 0.42] MHz). In the absence of Ca(II), the binding affinity of CP for Mn(II) drops by two to three orders of magnitude and coincides with Mn(II) binding at the His6 site as well as other sites. This study demonstrates the role of Ca(II) in enabling high-affinity and specific binding of Mn(II) to the His6 site of human calprotectin.

Manganese Binding Properties of Human Calprotectin under Conditions of High and Low Calcium: X-ray Crystallographic and Advanced Electron Paramagnetic Resonance Spectroscopic Analysis

DOE PAGES

Gagnon, Derek M.; Brophy, Megan Brunjes; Bowman, Sarah E. J.; ...

2015-01-18

The antimicrobial protein calprotectin (CP), a hetero-oligomer of the S100 family members S100A8 and S100A9, is the only identified mammalian Mn(II)-sequestering protein. Human CP uses Ca(II) ions to tune its Mn(II) affinity at a biologically unprecedented hexahistidine site that forms at the S100A8/S100A9 interface, and the molecular basis for this phenomenon requires elucidation. Here in this paper, we investigate the remarkable Mn(II) coordination chemistry of human CP using X-ray crystallography as well as continuous-wave (CW) and pulse electron paramagnetic resonance (EPR) spectroscopies. An X-ray crystallographic structure of Mn(II)-CP containing one Mn(II), two Ca(II), and two Na(I) ions per CP heterodimermore » is reported. The CW EPR spectrum of Ca(II)- and Mn(II)-bound CP prepared with a 10:0.9:1 Ca(II):Mn(II):CP ratio is characterized by an unusually low zero-field splitting of 485 MHz (E/D = 0.30) for the S = 5/2 Mn(II) ion, consistent with the high symmetry of the His6 binding site observed crystallographically. Results from electron spin–echo envelope modulation and electron–nuclear double resonance experiments reveal that the six Mn(II)-coordinating histidine residues of Ca(II)- and Mn(II)-bound CP are spectroscopically equivalent. The observed 15N (I = 1/2) hyperfine couplings (A) arise from two distinct classes of nitrogen atoms: the coordinating ε-nitrogen of the imidazole ring of each histidine ligand (A = [3.45, 3.71, 5.91] MHz) and the distal δ-nitrogen (A = [0.11, 0.18, 0.42] MHz). In the absence of Ca(II), the binding affinity of CP for Mn(II) drops by two to three orders of magnitude and coincides with Mn(II) binding at the His6 site as well as other sites. This study demonstrates the role of Ca(II) in enabling high-affinity and specific binding of Mn(II) to the His 6 site of human calprotectin.« less

Application of mucilage from Dicerocaryum eriocarpum plant as biosorption medium in the removal of selected heavy metal ions.

PubMed

Jones, Bassey O; John, Odiyo O; Luke, Chimuka; Ochieng, Aoyi; Bassey, Bridget J

2016-07-15

The ability of mucilage from Dicerocaryum eriocarpum (DE) plant to act as biosorption medium in the removal of metals ions from aqueous solution was investigated. Functional groups present in the mucilage were identified using Fourier transform infrared spectroscopy (FTIR). Mucilage was modified with sodium and potassium chlorides. This was aimed at assessing the biosorption efficiency of modified mucilage: potassium mucilage (PCE) and sodium mucilage (SCE) and comparing it with non-modified deionised water mucilage (DCE) in the uptake of metal ions. FTIR results showed that the functional groups providing the active sites in PCE and SCE and DCE include: carboxyl, hydroxyl and carbonyl groups. The chloride used in the modification of the mucilage did not introduce new functional groups but increased the intensity of the already existing functional groups in the mucilage. Results from biosorption experiment showed that DE mucilage displays good binding affinity with metals ions [Zn(II), Cd(II) Ni(II), Cr(III) and Fe(II)] in the aqueous solution. Increase in the aqueous solution pH, metal ions initial concentration and mucilage concentration increased the biosorption efficiency of DE mucilage. The maximum contact time varied with each species of metal ions. Optimum pH for [Zn(II), Cd(II) Ni(II) and Fe(II)] occurred at pH 4 and pH 6 for Cr(III). Kinetic models result fitted well to pseudo-second-order with a coefficient values of R(2) = 1 for Cd(II), Ni(II), Cr(III), Fe(II) and R(2) = 0.9974 for Zn(II). Biosorption isotherms conforms best with Freundlich model for all the metal ions with correlation factors of 0.9994, 0.9987, 0.9554, 0.9621 and 0.937 for Zn(II), Ni(II), Fe(II), Cr(III) and Cd(II), respectively. Biosorption capacity of DE mucilage was 0.010, 2.387, 4.902, 0688 and 0.125 for Zn(II), Cr(III), Fe(II), Cd(II) and Ni(II) respectively. The modified mucilage was found to be highly efficient in the removal of metal ions than the unmodified mucilage. Copyright © 2016 Elsevier Ltd. All rights reserved.